38 RISCVOutgoingValueAssigner(
41 RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet) {}
51 if (RISCVAssignFn(
DL, Subtarget.
getTargetABI(), ValNo, ValVT, LocVT,
52 LocInfo, Flags, State,
Info.IsFixed, IsRet,
Info.Ty,
65 : OutgoingValueHandler(
B,
MRI), MIB(MIB),
75 SPReg = MIRBuilder.buildCopy(p0,
Register(RISCV::X2)).getReg(0);
77 auto OffsetReg = MIRBuilder.buildConstant(sXLen,
Offset);
79 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
82 return AddrReg.getReg(0);
97 MIRBuilder.buildStore(ExtReg,
Addr, *MMO);
104 ValVReg = MIRBuilder.buildAnyExt(
LLT::scalar(64), ValVReg).getReg(0);
107 MIRBuilder.buildCopy(PhysReg, ExtReg);
113 std::function<
void()> *Thunk)
override {
114 assert(VAs.
size() >= 2 &&
"Expected at least 2 VAs.");
120 "Values belong to different arguments");
124 "unexpected custom value");
128 MIRBuilder.buildUnmerge(NewRegs, Arg.
Regs[0]);
141 auto assignFunc = [=]() {
176 RISCVIncomingValueAssigner(
179 RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet) {}
192 if (RISCVAssignFn(
DL, Subtarget.
getTargetABI(), ValNo, ValVT, LocVT,
193 LocInfo, Flags, State,
true, IsRet,
Info.Ty,
205 : IncomingValueHandler(
B,
MRI),
225 MIRBuilder.buildLoad(ValVReg,
Addr, *MMO);
230 markPhysRegUsed(PhysReg);
236 std::function<
void()> *Thunk)
override {
237 assert(VAs.
size() >= 2 &&
"Expected at least 2 VAs.");
243 "Values belong to different arguments");
247 "unexpected custom value");
267 MIRBuilder.buildMergeLikeInstr(Arg.
Regs[0], NewRegs);
275 virtual void markPhysRegUsed(
MCRegister PhysReg) = 0;
281struct RISCVFormalArgHandler :
public RISCVIncomingValueHandler {
283 : RISCVIncomingValueHandler(
B,
MRI) {}
285 void markPhysRegUsed(
MCRegister PhysReg)
override {
286 MIRBuilder.getMRI()->addLiveIn(PhysReg);
287 MIRBuilder.getMBB().addLiveIn(PhysReg);
291struct RISCVCallReturnHandler :
public RISCVIncomingValueHandler {
294 : RISCVIncomingValueHandler(
B,
MRI), MIB(MIB) {}
296 void markPhysRegUsed(
MCRegister PhysReg)
override {
332 bool IsLowerArgs =
false) {
335 if (
T->isIntegerTy())
336 return T->getIntegerBitWidth() <= Subtarget.
getXLen() * 2;
337 if (
T->isFloatTy() ||
T->isDoubleTy())
339 if (
T->isPointerTy())
353 bool IsLowerRetVal =
false) {
356 if (
T->isIntegerTy())
357 return T->getIntegerBitWidth() <= Subtarget.
getXLen() * 2;
358 if (
T->isFloatTy() ||
T->isDoubleTy())
360 if (
T->isPointerTy())
366 if (
T->isStructTy()) {
367 auto StructT = cast<StructType>(
T);
368 for (
unsigned i = 0, e = StructT->getNumElements(); i != e; ++i)
405 RISCVOutgoingValueAssigner Assigner(
408 RISCVOutgoingValueHandler Handler(MIRBuilder, MF.
getRegInfo(), Ret);
410 MIRBuilder,
CC,
F.isVarArg());
416 assert(!Val == VRegs.
empty() &&
"Return value without a vreg");
419 if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
440 for (
auto &Arg :
F.args()) {
452 for (
auto &Arg :
F.args()) {
465 RISCVIncomingValueAssigner Assigner(
468 RISCVFormalArgHandler Handler(MIRBuilder, MF.
getRegInfo());
471 MIRBuilder,
CC,
F.isVarArg());
483 for (
auto &AInfo :
Info.OrigArgs) {
488 if (!
Info.OrigRet.Ty->isVoidTy() &&
493 MIRBuilder.
buildInstr(RISCV::ADJCALLSTACKDOWN);
497 for (
auto &AInfo :
Info.OrigArgs) {
505 Info.IsTailCall =
false;
508 if (!
Info.Callee.isReg())
517 Call.addRegMask(
TRI->getCallPreservedMask(MF,
Info.CallConv));
519 RISCVOutgoingValueAssigner ArgAssigner(
522 RISCVOutgoingValueHandler ArgHandler(MIRBuilder, MF.
getRegInfo(), Call);
524 MIRBuilder,
CC,
Info.IsVarArg))
531 .
addImm(ArgAssigner.StackSize)
537 if (Call->getOperand(0).isReg())
541 Call->getDesc(), Call->getOperand(0), 0);
543 if (
Info.OrigRet.Ty->isVoidTy())
549 RISCVIncomingValueAssigner RetAssigner(
552 RISCVCallReturnHandler RetHandler(MIRBuilder, MF.
getRegInfo(), Call);
554 MIRBuilder,
CC,
Info.IsVarArg))
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
This file declares the MachineIRBuilder class.
unsigned const TargetRegisterInfo * TRI
static bool isSupportedReturnType(Type *T)
static bool isSupportedArgumentType(Type *T)
static bool isLegalElementTypeForRVV(Type *EltTy, const RISCVSubtarget &Subtarget)
Return true if scalable vector with ScalarTy is legal for lowering.
This file describes how to lower LLVM calls to machine code calls.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
CCState - This class holds information needed while lowering arguments and return values.
MachineFunction & getMachineFunction() const
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
int64_t getLocMemOffset() const
unsigned getValNo() const
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
A parsed version of the target data layout string in and methods for querying it.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Wrapper class representing physical registers. Should be passed by value.
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Helper class to build MachineInstr.
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register > > VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
RISCVCallLowering(const RISCVTargetLowering &TLI)
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
RISCVABI::ABI getTargetABI() const
const RegisterBankInfo * getRegBankInfo() const override
bool hasVInstructionsI64() const
bool hasVInstructionsF64() const
bool hasVInstructionsF16() const
bool hasVInstructionsBF16() const
bool hasVInstructions() const
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
const RISCVTargetLowering * getTargetLowering() const override
bool hasVInstructionsF32() const
bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
RISCVCCAssignFn - This target-specific function extends the default CCValAssign with additional infor...
Wrapper class representing virtual and physical registers.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
bool isPointerTy() const
True if this is an instance of PointerType.
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
bool isBFloatTy() const
Return true if this is 'bfloat', a 16-bit bfloat type.
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
bool isIntegerTy() const
True if this is an instance of IntegerType.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
@ Fast
Attempts to make calls as fast as possible (e.g.
bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
This is an optimization pass for GlobalISel generic memory operations.
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Helper struct shared between Function Specialization and SCCP Solver.
SmallVector< Register, 4 > Regs
SmallVector< ISD::ArgFlagsTy, 4 > Flags
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
void assignValueToReg(Register ValVReg, Register PhysReg, const CCValAssign &VA) override
Provides a default implementation for argument handling.
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
virtual bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, const ArgInfo &Info, ISD::ArgFlagsTy Flags, CCState &State)
Wrap call to (typically tablegenerated CCAssignFn).
virtual Register getStackAddress(uint64_t MemSize, int64_t Offset, MachinePointerInfo &MPO, ISD::ArgFlagsTy Flags)=0
Materialize a VReg containing the address of the specified stack-based object.
virtual void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO, const CCValAssign &VA)=0
The specified value has been assigned to a stack location.
Register extendRegister(Register ValReg, const CCValAssign &VA, unsigned MaxSizeBits=0)
Extend a register to the location type given in VA, capped at extending to at most MaxSize bits.
virtual unsigned assignCustomValue(ArgInfo &Arg, ArrayRef< CCValAssign > VAs, std::function< void()> *Thunk=nullptr)
Handle custom values, which may be passed into one or more of VAs.
virtual void assignValueToReg(Register ValVReg, Register PhysReg, const CCValAssign &VA)=0
The specified value has been assigned to a physical register, handle the appropriate COPY (either to ...
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.