LLVM 19.0.0git
RISCVCallLowering.cpp
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1//===-- RISCVCallLowering.cpp - Call lowering -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file implements the lowering of LLVM calls to machine code calls for
11/// GlobalISel.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCVCallLowering.h"
16#include "RISCVISelLowering.h"
18#include "RISCVSubtarget.h"
22
23using namespace llvm;
24
25namespace {
26
27struct RISCVOutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
28private:
29 // The function used internally to assign args - we ignore the AssignFn stored
30 // by OutgoingValueAssigner since RISC-V implements its CC using a custom
31 // function with a different signature.
33
34 // Whether this is assigning args for a return.
35 bool IsRet;
36
37 // true if assignArg has been called for a mask argument, false otherwise.
38 bool AssignedFirstMaskArg = false;
39
40public:
41 RISCVOutgoingValueAssigner(
42 RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet)
43 : CallLowering::OutgoingValueAssigner(nullptr),
44 RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet) {}
45
46 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
48 const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
49 CCState &State) override {
51 const DataLayout &DL = MF.getDataLayout();
52 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
53
54 std::optional<unsigned> FirstMaskArgument;
55 if (Subtarget.hasVInstructions() && !AssignedFirstMaskArg &&
56 ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1) {
57 FirstMaskArgument = ValNo;
58 AssignedFirstMaskArg = true;
59 }
60
61 if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
62 LocInfo, Flags, State, Info.IsFixed, IsRet, Info.Ty,
63 *Subtarget.getTargetLowering(), FirstMaskArgument))
64 return true;
65
66 StackSize = State.getStackSize();
67 return false;
68 }
69};
70
71struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
72 RISCVOutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
74 : OutgoingValueHandler(B, MRI), MIB(MIB),
75 Subtarget(MIRBuilder.getMF().getSubtarget<RISCVSubtarget>()) {}
76 Register getStackAddress(uint64_t MemSize, int64_t Offset,
78 ISD::ArgFlagsTy Flags) override {
79 MachineFunction &MF = MIRBuilder.getMF();
80 LLT p0 = LLT::pointer(0, Subtarget.getXLen());
81 LLT sXLen = LLT::scalar(Subtarget.getXLen());
82
83 if (!SPReg)
84 SPReg = MIRBuilder.buildCopy(p0, Register(RISCV::X2)).getReg(0);
85
86 auto OffsetReg = MIRBuilder.buildConstant(sXLen, Offset);
87
88 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
89
91 return AddrReg.getReg(0);
92 }
93
94 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
95 const MachinePointerInfo &MPO,
96 const CCValAssign &VA) override {
97 MachineFunction &MF = MIRBuilder.getMF();
98 uint64_t LocMemOffset = VA.getLocMemOffset();
99
100 // TODO: Move StackAlignment to subtarget and share with FrameLowering.
101 auto MMO =
103 commonAlignment(Align(16), LocMemOffset));
104
105 Register ExtReg = extendRegister(ValVReg, VA);
106 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
107 }
108
109 void assignValueToReg(Register ValVReg, Register PhysReg,
110 const CCValAssign &VA) override {
111 // If we're passing an f32 value into an i64, anyextend before copying.
112 if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32)
113 ValVReg = MIRBuilder.buildAnyExt(LLT::scalar(64), ValVReg).getReg(0);
114
115 Register ExtReg = extendRegister(ValVReg, VA);
116 MIRBuilder.buildCopy(PhysReg, ExtReg);
117 MIB.addUse(PhysReg, RegState::Implicit);
118 }
119
122 std::function<void()> *Thunk) override {
123 assert(VAs.size() >= 2 && "Expected at least 2 VAs.");
124 const CCValAssign &VALo = VAs[0];
125 const CCValAssign &VAHi = VAs[1];
126
127 assert(VAHi.needsCustom() && "Value doesn't need custom handling");
128 assert(VALo.getValNo() == VAHi.getValNo() &&
129 "Values belong to different arguments");
130
131 assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
132 VALo.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
133 "unexpected custom value");
134
135 Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
136 MRI.createGenericVirtualRegister(LLT::scalar(32))};
137 MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
138
139 if (VAHi.isMemLoc()) {
140 LLT MemTy(VAHi.getLocVT());
141
143 Register StackAddr = getStackAddress(
144 MemTy.getSizeInBytes(), VAHi.getLocMemOffset(), MPO, Arg.Flags[0]);
145
146 assignValueToAddress(NewRegs[1], StackAddr, MemTy, MPO,
147 const_cast<CCValAssign &>(VAHi));
148 }
149
150 auto assignFunc = [=]() {
151 assignValueToReg(NewRegs[0], VALo.getLocReg(), VALo);
152 if (VAHi.isRegLoc())
153 assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi);
154 };
155
156 if (Thunk) {
157 *Thunk = assignFunc;
158 return 2;
159 }
160
161 assignFunc();
162 return 2;
163 }
164
165private:
167
168 // Cache the SP register vreg if we need it more than once in this call site.
169 Register SPReg;
170
171 const RISCVSubtarget &Subtarget;
172};
173
174struct RISCVIncomingValueAssigner : public CallLowering::IncomingValueAssigner {
175private:
176 // The function used internally to assign args - we ignore the AssignFn stored
177 // by IncomingValueAssigner since RISC-V implements its CC using a custom
178 // function with a different signature.
180
181 // Whether this is assigning args from a return.
182 bool IsRet;
183
184 // true if assignArg has been called for a mask argument, false otherwise.
185 bool AssignedFirstMaskArg = false;
186
187public:
188 RISCVIncomingValueAssigner(
189 RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet)
190 : CallLowering::IncomingValueAssigner(nullptr),
191 RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet) {}
192
193 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
194 CCValAssign::LocInfo LocInfo,
195 const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
196 CCState &State) override {
198 const DataLayout &DL = MF.getDataLayout();
199 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
200
201 if (LocVT.isScalableVector())
203
204 std::optional<unsigned> FirstMaskArgument;
205 if (Subtarget.hasVInstructions() && !AssignedFirstMaskArg &&
206 ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1) {
207 FirstMaskArgument = ValNo;
208 AssignedFirstMaskArg = true;
209 }
210
211 if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT,
212 LocInfo, Flags, State, /*IsFixed=*/true, IsRet, Info.Ty,
213 *Subtarget.getTargetLowering(), FirstMaskArgument))
214 return true;
215
216 StackSize = State.getStackSize();
217 return false;
218 }
219};
220
221struct RISCVIncomingValueHandler : public CallLowering::IncomingValueHandler {
222 RISCVIncomingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI)
223 : IncomingValueHandler(B, MRI),
224 Subtarget(MIRBuilder.getMF().getSubtarget<RISCVSubtarget>()) {}
225
226 Register getStackAddress(uint64_t MemSize, int64_t Offset,
228 ISD::ArgFlagsTy Flags) override {
229 MachineFrameInfo &MFI = MIRBuilder.getMF().getFrameInfo();
230
231 int FI = MFI.CreateFixedObject(MemSize, Offset, /*Immutable=*/true);
232 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
233 return MIRBuilder.buildFrameIndex(LLT::pointer(0, Subtarget.getXLen()), FI)
234 .getReg(0);
235 }
236
237 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
238 const MachinePointerInfo &MPO,
239 const CCValAssign &VA) override {
240 MachineFunction &MF = MIRBuilder.getMF();
241 auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
242 inferAlignFromPtrInfo(MF, MPO));
243 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
244 }
245
246 void assignValueToReg(Register ValVReg, Register PhysReg,
247 const CCValAssign &VA) override {
248 markPhysRegUsed(PhysReg);
249 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
250 }
251
254 std::function<void()> *Thunk) override {
255 assert(VAs.size() >= 2 && "Expected at least 2 VAs.");
256 const CCValAssign &VALo = VAs[0];
257 const CCValAssign &VAHi = VAs[1];
258
259 assert(VAHi.needsCustom() && "Value doesn't need custom handling");
260 assert(VALo.getValNo() == VAHi.getValNo() &&
261 "Values belong to different arguments");
262
263 assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 &&
264 VALo.getValVT() == MVT::f64 && VAHi.getValVT() == MVT::f64 &&
265 "unexpected custom value");
266
267 Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
268 MRI.createGenericVirtualRegister(LLT::scalar(32))};
269
270 if (VAHi.isMemLoc()) {
271 LLT MemTy(VAHi.getLocVT());
272
274 Register StackAddr = getStackAddress(
275 MemTy.getSizeInBytes(), VAHi.getLocMemOffset(), MPO, Arg.Flags[0]);
276
277 assignValueToAddress(NewRegs[1], StackAddr, MemTy, MPO,
278 const_cast<CCValAssign &>(VAHi));
279 }
280
281 assignValueToReg(NewRegs[0], VALo.getLocReg(), VALo);
282 if (VAHi.isRegLoc())
283 assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi);
284
285 MIRBuilder.buildMergeLikeInstr(Arg.Regs[0], NewRegs);
286
287 return 2;
288 }
289
290 /// How the physical register gets marked varies between formal
291 /// parameters (it's a basic-block live-in), and a call instruction
292 /// (it's an implicit-def of the BL).
293 virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
294
295private:
296 const RISCVSubtarget &Subtarget;
297};
298
299struct RISCVFormalArgHandler : public RISCVIncomingValueHandler {
300 RISCVFormalArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI)
301 : RISCVIncomingValueHandler(B, MRI) {}
302
303 void markPhysRegUsed(MCRegister PhysReg) override {
304 MIRBuilder.getMRI()->addLiveIn(PhysReg);
305 MIRBuilder.getMBB().addLiveIn(PhysReg);
306 }
307};
308
309struct RISCVCallReturnHandler : public RISCVIncomingValueHandler {
310 RISCVCallReturnHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
312 : RISCVIncomingValueHandler(B, MRI), MIB(MIB) {}
313
314 void markPhysRegUsed(MCRegister PhysReg) override {
315 MIB.addDef(PhysReg, RegState::Implicit);
316 }
317
319};
320
321} // namespace
322
324 : CallLowering(&TLI) {}
325
326/// Return true if scalable vector with ScalarTy is legal for lowering.
328 const RISCVSubtarget &Subtarget) {
329 if (EltTy->isPointerTy())
330 return Subtarget.is64Bit() ? Subtarget.hasVInstructionsI64() : true;
331 if (EltTy->isIntegerTy(1) || EltTy->isIntegerTy(8) ||
332 EltTy->isIntegerTy(16) || EltTy->isIntegerTy(32))
333 return true;
334 if (EltTy->isIntegerTy(64))
335 return Subtarget.hasVInstructionsI64();
336 if (EltTy->isHalfTy())
337 return Subtarget.hasVInstructionsF16();
338 if (EltTy->isBFloatTy())
339 return Subtarget.hasVInstructionsBF16();
340 if (EltTy->isFloatTy())
341 return Subtarget.hasVInstructionsF32();
342 if (EltTy->isDoubleTy())
343 return Subtarget.hasVInstructionsF64();
344 return false;
345}
346
347// TODO: Support all argument types.
348// TODO: Remove IsLowerArgs argument by adding support for vectors in lowerCall.
349static bool isSupportedArgumentType(Type *T, const RISCVSubtarget &Subtarget,
350 bool IsLowerArgs = false) {
351 // TODO: Integers larger than 2*XLen are passed indirectly which is not
352 // supported yet.
353 if (T->isIntegerTy())
354 return T->getIntegerBitWidth() <= Subtarget.getXLen() * 2;
355 if (T->isFloatTy() || T->isDoubleTy())
356 return true;
357 if (T->isPointerTy())
358 return true;
359 // TODO: Support fixed vector types.
360 if (IsLowerArgs && T->isVectorTy() && Subtarget.hasVInstructions() &&
361 T->isScalableTy() &&
362 isLegalElementTypeForRVV(T->getScalarType(), Subtarget))
363 return true;
364 return false;
365}
366
367// TODO: Only integer, pointer and aggregate types are supported now.
368// TODO: Remove IsLowerRetVal argument by adding support for vectors in
369// lowerCall.
370static bool isSupportedReturnType(Type *T, const RISCVSubtarget &Subtarget,
371 bool IsLowerRetVal = false) {
372 // TODO: Integers larger than 2*XLen are passed indirectly which is not
373 // supported yet.
374 if (T->isIntegerTy())
375 return T->getIntegerBitWidth() <= Subtarget.getXLen() * 2;
376 if (T->isFloatTy() || T->isDoubleTy())
377 return true;
378 if (T->isPointerTy())
379 return true;
380
381 if (T->isArrayTy())
382 return isSupportedReturnType(T->getArrayElementType(), Subtarget);
383
384 if (T->isStructTy()) {
385 auto StructT = cast<StructType>(T);
386 for (unsigned i = 0, e = StructT->getNumElements(); i != e; ++i)
387 if (!isSupportedReturnType(StructT->getElementType(i), Subtarget))
388 return false;
389 return true;
390 }
391
392 if (IsLowerRetVal && T->isVectorTy() && Subtarget.hasVInstructions() &&
393 T->isScalableTy() &&
394 isLegalElementTypeForRVV(T->getScalarType(), Subtarget))
395 return true;
396
397 return false;
398}
399
400bool RISCVCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
401 const Value *Val,
402 ArrayRef<Register> VRegs,
403 MachineInstrBuilder &Ret) const {
404 if (!Val)
405 return true;
406
407 const RISCVSubtarget &Subtarget =
408 MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
409 if (!isSupportedReturnType(Val->getType(), Subtarget, /*IsLowerRetVal=*/true))
410 return false;
411
412 MachineFunction &MF = MIRBuilder.getMF();
413 const DataLayout &DL = MF.getDataLayout();
414 const Function &F = MF.getFunction();
415 CallingConv::ID CC = F.getCallingConv();
416
417 ArgInfo OrigRetInfo(VRegs, Val->getType(), 0);
419
420 SmallVector<ArgInfo, 4> SplitRetInfos;
421 splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, CC);
422
423 RISCVOutgoingValueAssigner Assigner(
425 /*IsRet=*/true);
426 RISCVOutgoingValueHandler Handler(MIRBuilder, MF.getRegInfo(), Ret);
427 return determineAndHandleAssignments(Handler, Assigner, SplitRetInfos,
428 MIRBuilder, CC, F.isVarArg());
429}
430
432 const Value *Val, ArrayRef<Register> VRegs,
433 FunctionLoweringInfo &FLI) const {
434 assert(!Val == VRegs.empty() && "Return value without a vreg");
435 MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET);
436
437 if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
438 return false;
439
440 MIRBuilder.insertInstr(Ret);
441 return true;
442}
443
444/// If there are varargs that were passed in a0-a7, the data in those registers
445/// must be copied to the varargs save area on the stack.
446void RISCVCallLowering::saveVarArgRegisters(
448 IncomingValueAssigner &Assigner, CCState &CCInfo) const {
449 MachineFunction &MF = MIRBuilder.getMF();
450 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
451 unsigned XLenInBytes = Subtarget.getXLen() / 8;
454 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
455 MachineFrameInfo &MFI = MF.getFrameInfo();
457
458 // Size of the vararg save area. For now, the varargs save area is either
459 // zero or large enough to hold a0-a7.
460 int VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
461 int FI;
462
463 // If all registers are allocated, then all varargs must be passed on the
464 // stack and we don't need to save any argregs.
465 if (VarArgsSaveSize == 0) {
466 int VaArgOffset = Assigner.StackSize;
467 FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
468 } else {
469 int VaArgOffset = -VarArgsSaveSize;
470 FI = MFI.CreateFixedObject(VarArgsSaveSize, VaArgOffset, true);
471
472 // If saving an odd number of registers then create an extra stack slot to
473 // ensure that the frame pointer is 2*XLEN-aligned, which in turn ensures
474 // offsets to even-numbered registered remain 2*XLEN-aligned.
475 if (Idx % 2) {
476 MFI.CreateFixedObject(XLenInBytes,
477 VaArgOffset - static_cast<int>(XLenInBytes), true);
478 VarArgsSaveSize += XLenInBytes;
479 }
480
482 Subtarget.getXLen());
483 const LLT sXLen = LLT::scalar(Subtarget.getXLen());
484
485 auto FIN = MIRBuilder.buildFrameIndex(p0, FI);
486 auto Offset = MIRBuilder.buildConstant(
487 MRI.createGenericVirtualRegister(sXLen), XLenInBytes);
488
489 // Copy the integer registers that may have been used for passing varargs
490 // to the vararg save area.
491 const MVT XLenVT = Subtarget.getXLenVT();
492 for (unsigned I = Idx; I < ArgRegs.size(); ++I) {
493 const Register VReg = MRI.createGenericVirtualRegister(sXLen);
494 Handler.assignValueToReg(
495 VReg, ArgRegs[I],
497 ArgRegs[I], XLenVT, CCValAssign::Full));
498 auto MPO =
499 MachinePointerInfo::getFixedStack(MF, FI, (I - Idx) * XLenInBytes);
500 MIRBuilder.buildStore(VReg, FIN, MPO, inferAlignFromPtrInfo(MF, MPO));
501 FIN = MIRBuilder.buildPtrAdd(MRI.createGenericVirtualRegister(p0),
502 FIN.getReg(0), Offset);
503 }
504 }
505
506 // Record the frame index of the first variable argument which is a value
507 // necessary to G_VASTART.
508 RVFI->setVarArgsFrameIndex(FI);
509 RVFI->setVarArgsSaveSize(VarArgsSaveSize);
510}
511
513 const Function &F,
515 FunctionLoweringInfo &FLI) const {
516 // Early exit if there are no arguments. varargs are not part of F.args() but
517 // must be lowered.
518 if (F.arg_empty() && !F.isVarArg())
519 return true;
520
521 const RISCVSubtarget &Subtarget =
522 MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
523 for (auto &Arg : F.args()) {
524 if (!isSupportedArgumentType(Arg.getType(), Subtarget,
525 /*IsLowerArgs=*/true))
526 return false;
527 }
528
529 MachineFunction &MF = MIRBuilder.getMF();
530 const DataLayout &DL = MF.getDataLayout();
531 CallingConv::ID CC = F.getCallingConv();
532
533 SmallVector<ArgInfo, 32> SplitArgInfos;
534 unsigned Index = 0;
535 for (auto &Arg : F.args()) {
536 // Construct the ArgInfo object from destination register and argument type.
537 ArgInfo AInfo(VRegs[Index], Arg.getType(), Index);
539
540 // Handle any required merging from split value types from physical
541 // registers into the desired VReg. ArgInfo objects are constructed
542 // correspondingly and appended to SplitArgInfos.
543 splitToValueTypes(AInfo, SplitArgInfos, DL, CC);
544
545 ++Index;
546 }
547
548 RISCVIncomingValueAssigner Assigner(
550 /*IsRet=*/false);
551 RISCVFormalArgHandler Handler(MIRBuilder, MF.getRegInfo());
552
554 CCState CCInfo(CC, F.isVarArg(), MIRBuilder.getMF(), ArgLocs, F.getContext());
555 if (!determineAssignments(Assigner, SplitArgInfos, CCInfo) ||
556 !handleAssignments(Handler, SplitArgInfos, CCInfo, ArgLocs, MIRBuilder))
557 return false;
558
559 if (F.isVarArg())
560 saveVarArgRegisters(MIRBuilder, Handler, Assigner, CCInfo);
561
562 return true;
563}
564
566 CallLoweringInfo &Info) const {
567 MachineFunction &MF = MIRBuilder.getMF();
568 const DataLayout &DL = MF.getDataLayout();
569 const Function &F = MF.getFunction();
570 CallingConv::ID CC = F.getCallingConv();
571
572 const RISCVSubtarget &Subtarget =
573 MIRBuilder.getMF().getSubtarget<RISCVSubtarget>();
574 for (auto &AInfo : Info.OrigArgs) {
575 if (!isSupportedArgumentType(AInfo.Ty, Subtarget))
576 return false;
577 }
578
579 if (!Info.OrigRet.Ty->isVoidTy() &&
580 !isSupportedReturnType(Info.OrigRet.Ty, Subtarget))
581 return false;
582
583 MachineInstrBuilder CallSeqStart =
584 MIRBuilder.buildInstr(RISCV::ADJCALLSTACKDOWN);
585
586 SmallVector<ArgInfo, 32> SplitArgInfos;
588 for (auto &AInfo : Info.OrigArgs) {
589 // Handle any required unmerging of split value types from a given VReg into
590 // physical registers. ArgInfo objects are constructed correspondingly and
591 // appended to SplitArgInfos.
592 splitToValueTypes(AInfo, SplitArgInfos, DL, CC);
593 }
594
595 // TODO: Support tail calls.
596 Info.IsTailCall = false;
597
598 // Select the recommended relocation type R_RISCV_CALL_PLT.
599 if (!Info.Callee.isReg())
600 Info.Callee.setTargetFlags(RISCVII::MO_CALL);
601
603 MIRBuilder
604 .buildInstrNoInsert(Info.Callee.isReg() ? RISCV::PseudoCALLIndirect
605 : RISCV::PseudoCALL)
606 .add(Info.Callee);
607 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
608 Call.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
609
610 RISCVOutgoingValueAssigner ArgAssigner(
612 /*IsRet=*/false);
613 RISCVOutgoingValueHandler ArgHandler(MIRBuilder, MF.getRegInfo(), Call);
614 if (!determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgInfos,
615 MIRBuilder, CC, Info.IsVarArg))
616 return false;
617
618 MIRBuilder.insertInstr(Call);
619
620 CallSeqStart.addImm(ArgAssigner.StackSize).addImm(0);
621 MIRBuilder.buildInstr(RISCV::ADJCALLSTACKUP)
622 .addImm(ArgAssigner.StackSize)
623 .addImm(0);
624
625 // If Callee is a reg, since it is used by a target specific
626 // instruction, it must have a register class matching the
627 // constraint of that instruction.
628 if (Call->getOperand(0).isReg())
630 *Subtarget.getInstrInfo(),
631 *Subtarget.getRegBankInfo(), *Call,
632 Call->getDesc(), Call->getOperand(0), 0);
633
634 if (Info.OrigRet.Ty->isVoidTy())
635 return true;
636
637 SmallVector<ArgInfo, 4> SplitRetInfos;
638 splitToValueTypes(Info.OrigRet, SplitRetInfos, DL, CC);
639
640 RISCVIncomingValueAssigner RetAssigner(
642 /*IsRet=*/true);
643 RISCVCallReturnHandler RetHandler(MIRBuilder, MF.getRegInfo(), Call);
644 if (!determineAndHandleAssignments(RetHandler, RetAssigner, SplitRetInfos,
645 MIRBuilder, CC, Info.IsVarArg))
646 return false;
647
648 return true;
649}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Addr
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the MachineIRBuilder class.
unsigned const TargetRegisterInfo * TRI
static bool isSupportedReturnType(Type *T)
static bool isSupportedArgumentType(Type *T)
static bool isLegalElementTypeForRVV(Type *EltTy, const RISCVSubtarget &Subtarget)
Return true if scalable vector with ScalarTy is legal for lowering.
This file describes how to lower LLVM calls to machine code calls.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
CCState - This class holds information needed while lowering arguments and return values.
MachineFunction & getMachineFunction() const
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
CCValAssign - Represent assignment of one arg/retval to a location.
bool isRegLoc() const
Register getLocReg() const
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
bool needsCustom() const
bool isMemLoc() const
int64_t getLocMemOffset() const
unsigned getValNo() const
bool handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Use Handler to insert code to handle the argument/return values represented by Args.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:276
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelType.h:57
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelType.h:203
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Machine Value Type.
bool isVector() const
Return true if this is a vector value type.
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
MVT getVectorElementType() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Helper class to build MachineInstr.
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register > > VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
RISCVCallLowering(const RISCVTargetLowering &TLI)
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
RISCVABI::ABI getTargetABI() const
const RegisterBankInfo * getRegBankInfo() const override
bool hasVInstructionsI64() const
bool hasVInstructionsF64() const
unsigned getXLen() const
bool hasVInstructionsF16() const
bool hasVInstructionsBF16() const
bool hasVInstructions() const
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
const RISCVTargetLowering * getTargetLowering() const override
bool hasVInstructionsF32() const
bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
RISCVCCAssignFn - This target-specific function extends the default CCValAssign with additional infor...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:255
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:154
bool isBFloatTy() const
Return true if this is 'bfloat', a 16-bit bfloat type.
Definition: Type.h:146
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
Definition: Type.h:143
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:157
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:228
unsigned getNumOperands() const
Definition: User.h:191
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
ArrayRef< MCPhysReg > getArgGPRs(const RISCVABI::ABI ABI)
bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:54
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:212
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:865
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Helper struct shared between Function Specialization and SCCP Solver.
Definition: SCCPSolver.h:41
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:63
SmallVector< ISD::ArgFlagsTy, 4 > Flags
Definition: CallLowering.h:51
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
Definition: CallLowering.h:323
void assignValueToReg(Register ValVReg, Register PhysReg, const CCValAssign &VA) override
Provides a default implementation for argument handling.
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:339
virtual bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, const ArgInfo &Info, ISD::ArgFlagsTy Flags, CCState &State)
Wrap call to (typically tablegenerated CCAssignFn).
Definition: CallLowering.h:191
virtual Register getStackAddress(uint64_t MemSize, int64_t Offset, MachinePointerInfo &MPO, ISD::ArgFlagsTy Flags)=0
Materialize a VReg containing the address of the specified stack-based object.
virtual void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO, const CCValAssign &VA)=0
The specified value has been assigned to a stack location.
Register extendRegister(Register ValReg, const CCValAssign &VA, unsigned MaxSizeBits=0)
Extend a register to the location type given in VA, capped at extending to at most MaxSize bits.
virtual unsigned assignCustomValue(ArgInfo &Arg, ArrayRef< CCValAssign > VAs, std::function< void()> *Thunk=nullptr)
Handle custom values, which may be passed into one or more of VAs.
Definition: CallLowering.h:300
virtual void assignValueToReg(Register ValVReg, Register PhysReg, const CCValAssign &VA)=0
The specified value has been assigned to a physical register, handle the appropriate COPY (either to ...
Extended Value Type.
Definition: ValueTypes.h:34
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.