LLVM  9.0.0svn
MipsCallLowering.cpp
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1 //===- MipsCallLowering.cpp -------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsCallLowering.h"
16 #include "MipsCCState.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/CodeGen/Analysis.h"
21 
22 using namespace llvm;
23 
25  : CallLowering(&TLI) {}
26 
27 bool MipsCallLowering::MipsHandler::assign(Register VReg, const CCValAssign &VA,
28  const EVT &VT) {
29  if (VA.isRegLoc()) {
30  assignValueToReg(VReg, VA, VT);
31  } else if (VA.isMemLoc()) {
32  assignValueToAddress(VReg, VA);
33  } else {
34  return false;
35  }
36  return true;
37 }
38 
40  ArrayRef<CCValAssign> ArgLocs,
41  unsigned ArgLocsStartIndex,
42  const EVT &VT) {
43  for (unsigned i = 0; i < VRegs.size(); ++i)
44  if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT))
45  return false;
46  return true;
47 }
48 
51  if (!MIRBuilder.getMF().getDataLayout().isLittleEndian())
52  std::reverse(VRegs.begin(), VRegs.end());
53 }
54 
58  unsigned SplitLength;
59  const Function &F = MIRBuilder.getMF().getFunction();
60  const DataLayout &DL = F.getParent()->getDataLayout();
61  const MipsTargetLowering &TLI = *static_cast<const MipsTargetLowering *>(
62  MIRBuilder.getMF().getSubtarget().getTargetLowering());
63 
64  for (unsigned ArgsIndex = 0, ArgLocsIndex = 0; ArgsIndex < Args.size();
65  ++ArgsIndex, ArgLocsIndex += SplitLength) {
66  EVT VT = TLI.getValueType(DL, Args[ArgsIndex].Ty);
67  SplitLength = TLI.getNumRegistersForCallingConv(F.getContext(),
68  F.getCallingConv(), VT);
69  assert(Args[ArgsIndex].Regs.size() == 1 && "Can't handle multple regs yet");
70 
71  if (SplitLength > 1) {
72  VRegs.clear();
73  MVT RegisterVT = TLI.getRegisterTypeForCallingConv(
74  F.getContext(), F.getCallingConv(), VT);
75  for (unsigned i = 0; i < SplitLength; ++i)
76  VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT}));
77 
78  if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Regs[0],
79  VT))
80  return false;
81  } else {
82  if (!assign(Args[ArgsIndex].Regs[0], ArgLocs[ArgLocsIndex], VT))
83  return false;
84  }
85  }
86  return true;
87 }
88 
89 namespace {
90 class IncomingValueHandler : public MipsCallLowering::MipsHandler {
91 public:
92  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
93  : MipsHandler(MIRBuilder, MRI) {}
94 
95 private:
96  void assignValueToReg(Register ValVReg, const CCValAssign &VA,
97  const EVT &VT) override;
98 
99  Register getStackAddress(const CCValAssign &VA,
100  MachineMemOperand *&MMO) override;
101 
102  void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
103 
104  bool handleSplit(SmallVectorImpl<Register> &VRegs,
105  ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
106  Register ArgsReg, const EVT &VT) override;
107 
108  virtual void markPhysRegUsed(unsigned PhysReg) {
109  MIRBuilder.getMBB().addLiveIn(PhysReg);
110  }
111 
112  void buildLoad(Register Val, const CCValAssign &VA) {
113  MachineMemOperand *MMO;
114  Register Addr = getStackAddress(VA, MMO);
115  MIRBuilder.buildLoad(Val, Addr, *MMO);
116  }
117 };
118 
119 class CallReturnHandler : public IncomingValueHandler {
120 public:
121  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
122  MachineInstrBuilder &MIB)
123  : IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
124 
125 private:
126  void markPhysRegUsed(unsigned PhysReg) override {
127  MIB.addDef(PhysReg, RegState::Implicit);
128  }
129 
130  MachineInstrBuilder &MIB;
131 };
132 
133 } // end anonymous namespace
134 
135 void IncomingValueHandler::assignValueToReg(Register ValVReg,
136  const CCValAssign &VA,
137  const EVT &VT) {
138  const MipsSubtarget &STI =
139  static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
140  Register PhysReg = VA.getLocReg();
141  if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
142  const MipsSubtarget &STI =
143  static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
144 
145  MIRBuilder
146  .buildInstr(STI.isFP64bit() ? Mips::BuildPairF64_64
148  .addDef(ValVReg)
149  .addUse(PhysReg + (STI.isLittle() ? 0 : 1))
150  .addUse(PhysReg + (STI.isLittle() ? 1 : 0))
151  .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
152  *STI.getRegBankInfo());
153  markPhysRegUsed(PhysReg);
154  markPhysRegUsed(PhysReg + 1);
155  } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
156  MIRBuilder.buildInstr(Mips::MTC1)
157  .addDef(ValVReg)
158  .addUse(PhysReg)
159  .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
160  *STI.getRegBankInfo());
161  markPhysRegUsed(PhysReg);
162  } else {
163  switch (VA.getLocInfo()) {
164  case CCValAssign::LocInfo::SExt:
165  case CCValAssign::LocInfo::ZExt:
166  case CCValAssign::LocInfo::AExt: {
167  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
168  MIRBuilder.buildTrunc(ValVReg, Copy);
169  break;
170  }
171  default:
172  MIRBuilder.buildCopy(ValVReg, PhysReg);
173  break;
174  }
175  markPhysRegUsed(PhysReg);
176  }
177 }
178 
179 Register IncomingValueHandler::getStackAddress(const CCValAssign &VA,
180  MachineMemOperand *&MMO) {
181  MachineFunction &MF = MIRBuilder.getMF();
182  unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
183  unsigned Offset = VA.getLocMemOffset();
184  MachineFrameInfo &MFI = MF.getFrameInfo();
185 
186  int FI = MFI.CreateFixedObject(Size, Offset, true);
187  MachinePointerInfo MPO =
188  MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
189 
191  unsigned Align = MinAlign(TFL->getStackAlignment(), Offset);
192  MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, Align);
193 
194  Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
195  MIRBuilder.buildFrameIndex(AddrReg, FI);
196 
197  return AddrReg;
198 }
199 
200 void IncomingValueHandler::assignValueToAddress(Register ValVReg,
201  const CCValAssign &VA) {
202  if (VA.getLocInfo() == CCValAssign::SExt ||
203  VA.getLocInfo() == CCValAssign::ZExt ||
204  VA.getLocInfo() == CCValAssign::AExt) {
205  Register LoadReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
206  buildLoad(LoadReg, VA);
207  MIRBuilder.buildTrunc(ValVReg, LoadReg);
208  } else
209  buildLoad(ValVReg, VA);
210 }
211 
212 bool IncomingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
213  ArrayRef<CCValAssign> ArgLocs,
214  unsigned ArgLocsStartIndex,
215  Register ArgsReg, const EVT &VT) {
216  if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
217  return false;
218  setLeastSignificantFirst(VRegs);
219  MIRBuilder.buildMerge(ArgsReg, VRegs);
220  return true;
221 }
222 
223 namespace {
224 class OutgoingValueHandler : public MipsCallLowering::MipsHandler {
225 public:
226  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
227  MachineInstrBuilder &MIB)
228  : MipsHandler(MIRBuilder, MRI), MIB(MIB) {}
229 
230 private:
231  void assignValueToReg(Register ValVReg, const CCValAssign &VA,
232  const EVT &VT) override;
233 
234  Register getStackAddress(const CCValAssign &VA,
235  MachineMemOperand *&MMO) override;
236 
237  void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
238 
239  bool handleSplit(SmallVectorImpl<Register> &VRegs,
240  ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
241  Register ArgsReg, const EVT &VT) override;
242 
243  Register extendRegister(Register ValReg, const CCValAssign &VA);
244 
245  MachineInstrBuilder &MIB;
246 };
247 } // end anonymous namespace
248 
249 void OutgoingValueHandler::assignValueToReg(Register ValVReg,
250  const CCValAssign &VA,
251  const EVT &VT) {
252  Register PhysReg = VA.getLocReg();
253  const MipsSubtarget &STI =
254  static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
255 
256  if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
257  MIRBuilder
258  .buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64
260  .addDef(PhysReg + (STI.isLittle() ? 1 : 0))
261  .addUse(ValVReg)
262  .addImm(1)
263  .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
264  *STI.getRegBankInfo());
265  MIRBuilder
266  .buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64
268  .addDef(PhysReg + (STI.isLittle() ? 0 : 1))
269  .addUse(ValVReg)
270  .addImm(0)
271  .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
272  *STI.getRegBankInfo());
273  } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) {
274  MIRBuilder.buildInstr(Mips::MFC1)
275  .addDef(PhysReg)
276  .addUse(ValVReg)
277  .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
278  *STI.getRegBankInfo());
279  } else {
280  Register ExtReg = extendRegister(ValVReg, VA);
281  MIRBuilder.buildCopy(PhysReg, ExtReg);
282  MIB.addUse(PhysReg, RegState::Implicit);
283  }
284 }
285 
286 Register OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
287  MachineMemOperand *&MMO) {
288  MachineFunction &MF = MIRBuilder.getMF();
290 
291  LLT p0 = LLT::pointer(0, 32);
292  LLT s32 = LLT::scalar(32);
293  Register SPReg = MRI.createGenericVirtualRegister(p0);
294  MIRBuilder.buildCopy(SPReg, Register(Mips::SP));
295 
296  Register OffsetReg = MRI.createGenericVirtualRegister(s32);
297  unsigned Offset = VA.getLocMemOffset();
298  MIRBuilder.buildConstant(OffsetReg, Offset);
299 
300  Register AddrReg = MRI.createGenericVirtualRegister(p0);
301  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
302 
303  MachinePointerInfo MPO =
304  MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
305  unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
306  unsigned Align = MinAlign(TFL->getStackAlignment(), Offset);
307  MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, Size, Align);
308 
309  return AddrReg;
310 }
311 
312 void OutgoingValueHandler::assignValueToAddress(Register ValVReg,
313  const CCValAssign &VA) {
314  MachineMemOperand *MMO;
315  Register Addr = getStackAddress(VA, MMO);
316  Register ExtReg = extendRegister(ValVReg, VA);
317  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
318 }
319 
320 Register OutgoingValueHandler::extendRegister(Register ValReg,
321  const CCValAssign &VA) {
322  LLT LocTy{VA.getLocVT()};
323  switch (VA.getLocInfo()) {
324  case CCValAssign::SExt: {
325  Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
326  MIRBuilder.buildSExt(ExtReg, ValReg);
327  return ExtReg;
328  }
329  case CCValAssign::ZExt: {
330  Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
331  MIRBuilder.buildZExt(ExtReg, ValReg);
332  return ExtReg;
333  }
334  case CCValAssign::AExt: {
335  Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
336  MIRBuilder.buildAnyExt(ExtReg, ValReg);
337  return ExtReg;
338  }
339  // TODO : handle upper extends
340  case CCValAssign::Full:
341  return ValReg;
342  default:
343  break;
344  }
345  llvm_unreachable("unable to extend register");
346 }
347 
348 bool OutgoingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
349  ArrayRef<CCValAssign> ArgLocs,
350  unsigned ArgLocsStartIndex,
351  Register ArgsReg, const EVT &VT) {
352  MIRBuilder.buildUnmerge(VRegs, ArgsReg);
353  setLeastSignificantFirst(VRegs);
354  if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex, VT))
355  return false;
356 
357  return true;
358 }
359 
360 static bool isSupportedType(Type *T) {
361  if (T->isIntegerTy())
362  return true;
363  if (T->isPointerTy())
364  return true;
365  if (T->isFloatingPointTy())
366  return true;
367  return false;
368 }
369 
370 static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT,
371  const ISD::ArgFlagsTy &Flags) {
372  // > does not mean loss of information as type RegisterVT can't hold type VT,
373  // it means that type VT is split into multiple registers of type RegisterVT
374  if (VT.getSizeInBits() >= RegisterVT.getSizeInBits())
376  if (Flags.isSExt())
377  return CCValAssign::LocInfo::SExt;
378  if (Flags.isZExt())
379  return CCValAssign::LocInfo::ZExt;
380  return CCValAssign::LocInfo::AExt;
381 }
382 
383 template <typename T>
385  const SmallVectorImpl<T> &Arguments) {
386  for (unsigned i = 0; i < ArgLocs.size(); ++i) {
387  const CCValAssign &VA = ArgLocs[i];
389  Arguments[i].VT, Arguments[i].ArgVT, Arguments[i].Flags);
390  if (VA.isMemLoc())
391  ArgLocs[i] =
393  VA.getLocMemOffset(), VA.getLocVT(), LocInfo);
394  else
395  ArgLocs[i] = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
396  VA.getLocReg(), VA.getLocVT(), LocInfo);
397  }
398 }
399 
401  const Value *Val,
402  ArrayRef<Register> VRegs) const {
403 
404  MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
405 
406  if (Val != nullptr && !isSupportedType(Val->getType()))
407  return false;
408 
409  if (!VRegs.empty()) {
410  MachineFunction &MF = MIRBuilder.getMF();
411  const Function &F = MF.getFunction();
412  const DataLayout &DL = MF.getDataLayout();
413  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
414  LLVMContext &Ctx = Val->getType()->getContext();
415 
416  SmallVector<EVT, 4> SplitEVTs;
417  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
418  assert(VRegs.size() == SplitEVTs.size() &&
419  "For each split Type there should be exactly one VReg.");
420 
421  SmallVector<ArgInfo, 8> RetInfos;
422  SmallVector<unsigned, 8> OrigArgIndices;
423 
424  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
425  ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
426  setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
427  splitToValueTypes(CurArgInfo, 0, RetInfos, OrigArgIndices);
428  }
429 
431  subTargetRegTypeForCallingConv(F, RetInfos, OrigArgIndices, Outs);
432 
434  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
435  F.getContext());
436  CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn());
437  setLocInfo(ArgLocs, Outs);
438 
439  OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
440  if (!RetHandler.handle(ArgLocs, RetInfos)) {
441  return false;
442  }
443  }
444  MIRBuilder.insertInstr(Ret);
445  return true;
446 }
447 
449  MachineIRBuilder &MIRBuilder, const Function &F,
450  ArrayRef<ArrayRef<Register>> VRegs) const {
451 
452  // Quick exit if there aren't any args.
453  if (F.arg_empty())
454  return true;
455 
456  if (F.isVarArg()) {
457  return false;
458  }
459 
460  for (auto &Arg : F.args()) {
461  if (!isSupportedType(Arg.getType()))
462  return false;
463  }
464 
465  MachineFunction &MF = MIRBuilder.getMF();
466  const DataLayout &DL = MF.getDataLayout();
467  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
468 
469  SmallVector<ArgInfo, 8> ArgInfos;
470  SmallVector<unsigned, 8> OrigArgIndices;
471  unsigned i = 0;
472  for (auto &Arg : F.args()) {
473  ArgInfo AInfo(VRegs[i], Arg.getType());
474  setArgFlags(AInfo, i + AttributeList::FirstArgIndex, DL, F);
475  splitToValueTypes(AInfo, i, ArgInfos, OrigArgIndices);
476  ++i;
477  }
478 
480  subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Ins);
481 
483  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
484  F.getContext());
485 
486  const MipsTargetMachine &TM =
487  static_cast<const MipsTargetMachine &>(MF.getTarget());
488  const MipsABIInfo &ABI = TM.getABI();
489  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()),
490  1);
491  CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall());
492  setLocInfo(ArgLocs, Ins);
493 
494  IncomingValueHandler Handler(MIRBuilder, MF.getRegInfo());
495  if (!Handler.handle(ArgLocs, ArgInfos))
496  return false;
497 
498  return true;
499 }
500 
502  CallingConv::ID CallConv,
503  const MachineOperand &Callee,
504  const ArgInfo &OrigRet,
505  ArrayRef<ArgInfo> OrigArgs) const {
506 
507  if (CallConv != CallingConv::C)
508  return false;
509 
510  for (auto &Arg : OrigArgs) {
511  if (!isSupportedType(Arg.Ty))
512  return false;
513  if (Arg.Flags.isByVal() || Arg.Flags.isSRet())
514  return false;
515  }
516 
517  if (OrigRet.Regs[0] && !isSupportedType(OrigRet.Ty))
518  return false;
519 
520  MachineFunction &MF = MIRBuilder.getMF();
521  const Function &F = MF.getFunction();
522  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
523  const MipsTargetMachine &TM =
524  static_cast<const MipsTargetMachine &>(MF.getTarget());
525  const MipsABIInfo &ABI = TM.getABI();
526 
527  MachineInstrBuilder CallSeqStart =
528  MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
529 
530  const bool IsCalleeGlobalPIC =
531  Callee.isGlobal() && TM.isPositionIndependent();
532 
533  MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(
534  Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL);
535  MIB.addDef(Mips::SP, RegState::Implicit);
536  if (IsCalleeGlobalPIC) {
537  Register CalleeReg =
539  MachineInstr *CalleeGlobalValue =
540  MIRBuilder.buildGlobalValue(CalleeReg, Callee.getGlobal());
541  if (!Callee.getGlobal()->hasLocalLinkage())
542  CalleeGlobalValue->getOperand(1).setTargetFlags(MipsII::MO_GOT_CALL);
543  MIB.addUse(CalleeReg);
544  } else
545  MIB.add(Callee);
548 
549  TargetLowering::ArgListTy FuncOrigArgs;
550  FuncOrigArgs.reserve(OrigArgs.size());
551 
552  SmallVector<ArgInfo, 8> ArgInfos;
553  SmallVector<unsigned, 8> OrigArgIndices;
554  unsigned i = 0;
555  for (auto &Arg : OrigArgs) {
556 
558  Entry.Ty = Arg.Ty;
559  FuncOrigArgs.push_back(Entry);
560 
561  splitToValueTypes(Arg, i, ArgInfos, OrigArgIndices);
562  ++i;
563  }
564 
566  subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Outs);
567 
569  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
570  F.getContext());
571 
572  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
573  const char *Call = Callee.isSymbol() ? Callee.getSymbolName() : nullptr;
574  CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call);
575  setLocInfo(ArgLocs, Outs);
576 
577  OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
578  if (!RetHandler.handle(ArgLocs, ArgInfos)) {
579  return false;
580  }
581 
582  unsigned NextStackOffset = CCInfo.getNextStackOffset();
584  unsigned StackAlignment = TFL->getStackAlignment();
585  NextStackOffset = alignTo(NextStackOffset, StackAlignment);
586  CallSeqStart.addImm(NextStackOffset).addImm(0);
587 
588  if (IsCalleeGlobalPIC) {
589  MIRBuilder.buildCopy(
590  Register(Mips::GP),
592  MIB.addDef(Mips::GP, RegState::Implicit);
593  }
594  MIRBuilder.insertInstr(MIB);
595  if (MIB->getOpcode() == Mips::JALRPseudo) {
596  const MipsSubtarget &STI =
597  static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
598  MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
599  *STI.getRegBankInfo());
600  }
601 
602  if (OrigRet.Regs[0]) {
603  ArgInfos.clear();
604  SmallVector<unsigned, 8> OrigRetIndices;
605 
606  splitToValueTypes(OrigRet, 0, ArgInfos, OrigRetIndices);
607 
609  subTargetRegTypeForCallingConv(F, ArgInfos, OrigRetIndices, Ins);
610 
612  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
613  F.getContext());
614 
615  CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), OrigRet.Ty, Call);
616  setLocInfo(ArgLocs, Ins);
617 
618  CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);
619  if (!Handler.handle(ArgLocs, ArgInfos))
620  return false;
621  }
622 
623  MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);
624 
625  return true;
626 }
627 
628 template <typename T>
629 void MipsCallLowering::subTargetRegTypeForCallingConv(
631  ArrayRef<unsigned> OrigArgIndices, SmallVectorImpl<T> &ISDArgs) const {
632  const DataLayout &DL = F.getParent()->getDataLayout();
633  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
634 
635  unsigned ArgNo = 0;
636  for (auto &Arg : Args) {
637 
638  EVT VT = TLI.getValueType(DL, Arg.Ty);
639  MVT RegisterVT = TLI.getRegisterTypeForCallingConv(F.getContext(),
640  F.getCallingConv(), VT);
641  unsigned NumRegs = TLI.getNumRegistersForCallingConv(
642  F.getContext(), F.getCallingConv(), VT);
643 
644  for (unsigned i = 0; i < NumRegs; ++i) {
645  ISD::ArgFlagsTy Flags = Arg.Flags;
646 
647  if (i == 0)
649  else
650  Flags.setOrigAlign(1);
651 
652  ISDArgs.emplace_back(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo],
653  0);
654  }
655  ++ArgNo;
656  }
657 }
658 
659 void MipsCallLowering::splitToValueTypes(
660  const ArgInfo &OrigArg, unsigned OriginalIndex,
661  SmallVectorImpl<ArgInfo> &SplitArgs,
662  SmallVectorImpl<unsigned> &SplitArgsOrigIndices) const {
663 
664  // TODO : perform structure and array split. For now we only deal with
665  // types that pass isSupportedType check.
666  SplitArgs.push_back(OrigArg);
667  SplitArgsOrigIndices.push_back(OriginalIndex);
668 }
const RegisterBankInfo * getRegBankInfo() const override
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:641
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
bool hasLocalLinkage() const
Definition: GlobalValue.h:445
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register getLocReg() const
void setTargetFlags(unsigned F)
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool assignVRegs(ArrayRef< Register > VRegs, ArrayRef< CCValAssign > ArgLocs, unsigned ArgLocsStartIndex, const EVT &VT)
unsigned getValNo() const
unsigned const TargetRegisterInfo * TRI
F(f)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:684
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
bool isMemLoc() const
A description of a memory reference used in the backend.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:161
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
CCAssignFn * CCAssignFnForCall() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:196
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const
Obtain the size of the area allocated by the callee for arguments.
Definition: MipsABIInfo.cpp:48
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
const char * getSymbolName() const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
unsigned getSizeInBits() const
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:273
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
bool arg_empty() const
Definition: Function.h:723
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn, const Type *RetTy, const char *Func)
Definition: MipsCCState.h:119
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
MipsCallLowering(const MipsTargetLowering &TLI)
void setOrigAlign(unsigned A)
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:119
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:609
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:43
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs...
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:223
const GlobalValue * getGlobal() const
Helper class to build MachineInstr.
AMDGPU Lower Kernel Arguments
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static void setLocInfo(SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< T > &Arguments)
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:33
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
This class contains a discriminated union of information about pointers in memory operands...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
The memory access writes data.
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
bool isLittle() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
const MipsRegisterInfo * getRegisterInfo() const override
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
CCValAssign - Represent assignment of one arg/retval to a location.
Information about stack frame layout on the target.
Promote Memory to Register
Definition: Mem2Reg.cpp:109
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
const TargetInstrInfo & getTII()
const Function & getFunction() const
Return the LLVM function that this machine code represents.
void setLeastSignificantFirst(SmallVectorImpl< Register > &VRegs)
This file declares the MachineIRBuilder class.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:64
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
Definition: MipsCCState.h:130
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
virtual const TargetFrameLowering * getFrameLowering() const
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
uint32_t Size
Definition: Profile.cpp:46
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
This file describes how to lower LLVM calls to machine code calls.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isSupportedType(Type *T)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:72
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, const MachineOperand &Callee, const ArgInfo &OrigRet, ArrayRef< ArgInfo > OrigArgs) const override
This hook behaves as the extended lowerCall function, but for targets that do not support swifterror ...
CCAssignFn * CCAssignFnForReturn() const
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:46
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT, const ISD::ArgFlagsTy &Flags)
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
bool isFP64bit() const
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
bool handle(ArrayRef< CCValAssign > ArgLocs, ArrayRef< CallLowering::ArgInfo > Args)
iterator_range< arg_iterator > args()
Definition: Function.h:713
bool constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:18
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143