LLVM  10.0.0svn
MipsMachineFunction.cpp
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1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MipsMachineFunction.h"
11 #include "MipsSubtarget.h"
12 #include "MipsTargetMachine.h"
18 
19 using namespace llvm;
20 
21 static cl::opt<bool>
22 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
23  cl::desc("Always use $gp as the global base register."));
24 
26 
28  return GlobalBaseReg;
29 }
30 
32  auto &STI = static_cast<const MipsSubtarget &>(MF.getSubtarget());
33  auto &TM = static_cast<const MipsTargetMachine &>(MF.getTarget());
34 
35  if (STI.inMips16Mode())
36  return Mips::CPU16RegsRegClass;
37 
38  if (STI.inMicroMipsMode())
39  return Mips::GPRMM16RegClass;
40 
41  if (TM.getABI().IsN64())
42  return Mips::GPR64RegClass;
43 
44  return Mips::GPR32RegClass;
45 }
46 
48  if (!GlobalBaseReg)
49  GlobalBaseReg =
51  return GlobalBaseReg;
52 }
53 
55  if (!GlobalBaseReg) {
58  }
59  return GlobalBaseReg;
60 }
61 
63  if (!GlobalBaseReg)
64  return;
65 
66  MachineBasicBlock &MBB = MF.front();
68  MachineRegisterInfo &RegInfo = MF.getRegInfo();
70  DebugLoc DL;
71  unsigned V0, V1;
72  const TargetRegisterClass *RC;
73  const MipsABIInfo &ABI =
74  static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
75  RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
76 
77  V0 = RegInfo.createVirtualRegister(RC);
78  V1 = RegInfo.createVirtualRegister(RC);
79 
80  if (ABI.IsN64()) {
81  MF.getRegInfo().addLiveIn(Mips::T9_64);
82  MBB.addLiveIn(Mips::T9_64);
83 
84  // lui $v0, %hi(%neg(%gp_rel(fname)))
85  // daddu $v1, $v0, $t9
86  // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
87  const GlobalValue *FName = &MF.getFunction();
88  BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
89  .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
90  BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
91  .addReg(Mips::T9_64);
92  BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
94  return;
95  }
96 
97  if (!MF.getTarget().isPositionIndependent()) {
98  // Set global register to __gnu_local_gp.
99  //
100  // lui $v0, %hi(__gnu_local_gp)
101  // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
102  BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
103  .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
104  BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
105  .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
106  return;
107  }
108 
109  MF.getRegInfo().addLiveIn(Mips::T9);
110  MBB.addLiveIn(Mips::T9);
111 
112  if (ABI.IsN32()) {
113  // lui $v0, %hi(%neg(%gp_rel(fname)))
114  // addu $v1, $v0, $t9
115  // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
116  const GlobalValue *FName = &MF.getFunction();
117  BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
118  .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
119  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
120  BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
122  return;
123  }
124 
125  assert(ABI.IsO32());
126 
127  // For O32 ABI, the following instruction sequence is emitted to initialize
128  // the global base register:
129  //
130  // 0. lui $2, %hi(_gp_disp)
131  // 1. addiu $2, $2, %lo(_gp_disp)
132  // 2. addu $globalbasereg, $2, $t9
133  //
134  // We emit only the last instruction here.
135  //
136  // GNU linker requires that the first two instructions appear at the beginning
137  // of a function and no instructions be inserted before or between them.
138  // The two instructions are emitted during lowering to MC layer in order to
139  // avoid any reordering.
140  //
141  // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
142  // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
143  // reads it.
144  MF.getRegInfo().addLiveIn(Mips::V0);
145  MBB.addLiveIn(Mips::V0);
146  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
147  .addReg(Mips::V0).addReg(Mips::T9);
148 }
149 
152  for (int I = 0; I < 4; ++I) {
153  const TargetRegisterClass &RC =
154  static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
155  ? Mips::GPR64RegClass
156  : Mips::GPR32RegClass;
157 
158  EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC),
159  TRI.getSpillAlignment(RC), false);
160  }
161 }
162 
164  // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
165  // The current implementation only supports Mips32r2+ not Mips64rX. Status
166  // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture,
167  // however Mips32r2+ is the supported architecture.
168  const TargetRegisterClass &RC = Mips::GPR32RegClass;
170 
171  for (int I = 0; I < 2; ++I)
172  ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
173  TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false);
174 }
175 
177  return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
178  || FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
179 }
180 
181 bool MipsFunctionInfo::isISRRegFI(int FI) const {
182  return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
183 }
186 }
187 
190 }
191 
194  if (MoveF64ViaSpillFI == -1) {
195  MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject(
196  TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false);
197  }
198  return MoveF64ViaSpillFI;
199 }
200 
201 void MipsFunctionInfo::anchor() {}
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
MachinePointerInfo callPtrInfo(const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
const HexagonInstrInfo * TII
bool IsN32() const
Definition: MipsABIInfo.h:42
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:51
bool IsN64() const
Definition: MipsABIInfo.h:43
PseudoSourceValueManager & getPSVManager() const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
virtual const TargetInstrInfo * getInstrInfo() const
TargetInstrInfo - Interface to description of machine instruction set.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
static const TargetRegisterClass & getGlobalBaseRegClass(MachineFunction &MF)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
const PseudoSourceValue * getExternalSymbolCallEntry(const char *ES)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool IsO32() const
Definition: MipsABIInfo.h:41
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MachineBasicBlock & front() const
This class contains a discriminated union of information about pointers in memory operands...
int CreateStackObject(uint64_t Size, llvm::Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const PseudoSourceValue * getGlobalValueCallEntry(const GlobalValue *GV)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isPositionIndependent() const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
#define I(x, y, z)
Definition: MD5.cpp:58
int getMoveF64ViaSpillFI(const TargetRegisterClass *RC)
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static cl::opt< bool > FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true), cl::desc("Always use $gp as the global base register."))
bool isEhDataRegFI(int FI) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isISRRegFI(int FI) const
~MipsFunctionInfo() override