LLVM  14.0.0git
MipsMachineFunction.cpp
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1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MipsMachineFunction.h"
11 #include "MipsSubtarget.h"
12 #include "MipsTargetMachine.h"
18 
19 using namespace llvm;
20 
21 static cl::opt<bool>
22 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
23  cl::desc("Always use $gp as the global base register."));
24 
26 
28  return GlobalBaseReg;
29 }
30 
32  auto &STI = static_cast<const MipsSubtarget &>(MF.getSubtarget());
33  auto &TM = static_cast<const MipsTargetMachine &>(MF.getTarget());
34 
35  if (STI.inMips16Mode())
36  return Mips::CPU16RegsRegClass;
37 
38  if (STI.inMicroMipsMode())
39  return Mips::GPRMM16RegClass;
40 
41  if (TM.getABI().IsN64())
42  return Mips::GPR64RegClass;
43 
44  return Mips::GPR32RegClass;
45 }
46 
48  if (!GlobalBaseReg)
49  GlobalBaseReg =
51  return GlobalBaseReg;
52 }
53 
55  if (!GlobalBaseReg) {
56  getGlobalBaseReg(MF);
58  }
59  return GlobalBaseReg;
60 }
61 
63  if (!GlobalBaseReg)
64  return;
65 
66  MachineBasicBlock &MBB = MF.front();
68  MachineRegisterInfo &RegInfo = MF.getRegInfo();
70  DebugLoc DL;
71  const TargetRegisterClass *RC;
72  const MipsABIInfo &ABI =
73  static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
74  RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
75 
76  Register V0 = RegInfo.createVirtualRegister(RC);
77  Register V1 = RegInfo.createVirtualRegister(RC);
78 
79  if (ABI.IsN64()) {
80  MF.getRegInfo().addLiveIn(Mips::T9_64);
81  MBB.addLiveIn(Mips::T9_64);
82 
83  // lui $v0, %hi(%neg(%gp_rel(fname)))
84  // daddu $v1, $v0, $t9
85  // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
86  const GlobalValue *FName = &MF.getFunction();
87  BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
89  BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
90  .addReg(Mips::T9_64);
91  BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
93  return;
94  }
95 
96  if (!MF.getTarget().isPositionIndependent()) {
97  // Set global register to __gnu_local_gp.
98  //
99  // lui $v0, %hi(__gnu_local_gp)
100  // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
101  BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
102  .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
103  BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
104  .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
105  return;
106  }
107 
108  MF.getRegInfo().addLiveIn(Mips::T9);
109  MBB.addLiveIn(Mips::T9);
110 
111  if (ABI.IsN32()) {
112  // lui $v0, %hi(%neg(%gp_rel(fname)))
113  // addu $v1, $v0, $t9
114  // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
115  const GlobalValue *FName = &MF.getFunction();
116  BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
118  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
119  BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
121  return;
122  }
123 
124  assert(ABI.IsO32());
125 
126  // For O32 ABI, the following instruction sequence is emitted to initialize
127  // the global base register:
128  //
129  // 0. lui $2, %hi(_gp_disp)
130  // 1. addiu $2, $2, %lo(_gp_disp)
131  // 2. addu $globalbasereg, $2, $t9
132  //
133  // We emit only the last instruction here.
134  //
135  // GNU linker requires that the first two instructions appear at the beginning
136  // of a function and no instructions be inserted before or between them.
137  // The two instructions are emitted during lowering to MC layer in order to
138  // avoid any reordering.
139  //
140  // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
141  // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
142  // reads it.
143  MF.getRegInfo().addLiveIn(Mips::V0);
144  MBB.addLiveIn(Mips::V0);
145  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
146  .addReg(Mips::V0).addReg(Mips::T9);
147 }
148 
151  for (int I = 0; I < 4; ++I) {
152  const TargetRegisterClass &RC =
153  static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
154  ? Mips::GPR64RegClass
155  : Mips::GPR32RegClass;
156 
157  EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
158  TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false);
159  }
160 }
161 
163  // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
164  // The current implementation only supports Mips32r2+ not Mips64rX. Status
165  // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture,
166  // however Mips32r2+ is the supported architecture.
167  const TargetRegisterClass &RC = Mips::GPR32RegClass;
169 
170  for (int I = 0; I < 2; ++I)
171  ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
172  TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false);
173 }
174 
176  return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
177  || FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
178 }
179 
180 bool MipsFunctionInfo::isISRRegFI(int FI) const {
181  return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
182 }
184  const char *ES) {
186 }
187 
189  const GlobalValue *GV) {
191 }
192 
194  const TargetRegisterClass *RC) {
196  if (MoveF64ViaSpillFI == -1) {
197  MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject(
198  TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC), false);
199  }
200  return MoveF64ViaSpillFI;
201 }
202 
203 void MipsFunctionInfo::anchor() {}
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:957
ABI
Generic address nodes are lowered to some combination of target independent and machine specific ABI
Definition: Relocation.txt:34
llvm::MipsTargetMachine
Definition: MipsTargetMachine.h:27
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::MipsABIInfo
Definition: MipsABIInfo.h:22
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::MipsFunctionInfo::createISRRegFI
void createISRRegFI(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:162
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::MachineFunction::getPSVManager
PseudoSourceValueManager & getPSVManager() const
Definition: MachineFunction.h:601
MipsTargetMachine.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
MachineRegisterInfo.h
CommandLine.h
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:835
llvm::MipsFunctionInfo::~MipsFunctionInfo
~MipsFunctionInfo() override
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MipsFunctionInfo::initGlobalBaseReg
void initGlobalBaseReg(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:62
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
getGlobalBaseRegClass
static const TargetRegisterClass & getGlobalBaseRegClass(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:31
llvm::MipsII::MO_ABS_LO
@ MO_ABS_LO
Definition: MipsBaseInfo.h:53
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:44
llvm::MipsFunctionInfo::isEhDataRegFI
bool isEhDataRegFI(int FI) const
Definition: MipsMachineFunction.cpp:175
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:288
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::cl::opt< bool >
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:282
llvm::MipsFunctionInfo::createEhDataRegsFI
void createEhDataRegsFI(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:149
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
I
#define I(x, y, z)
Definition: MD5.cpp:59
MipsMachineFunction.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:657
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MipsFunctionInfo::getGlobalBaseRegForGlobalISel
Register getGlobalBaseRegForGlobalISel(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:54
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::MipsFunctionInfo::getGlobalBaseReg
Register getGlobalBaseReg(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:47
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::MipsFunctionInfo::isISRRegFI
bool isISRRegFI(int FI) const
Definition: MipsMachineFunction.cpp:180
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::PseudoSourceValueManager::getGlobalValueCallEntry
const PseudoSourceValue * getGlobalValueCallEntry(const GlobalValue *GV)
Definition: PseudoSourceValue.cpp:137
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MipsII::MO_GPOFF_LO
@ MO_GPOFF_LO
Definition: MipsBaseInfo.h:78
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:637
MachineFrameInfo.h
MipsABIInfo.h
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:177
llvm::MipsII::MO_ABS_HI
@ MO_ABS_HI
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
llvm::MipsII::MO_GPOFF_HI
@ MO_GPOFF_HI
Definition: MipsBaseInfo.h:77
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
MipsSubtarget.h
FixGlobalBaseReg
static cl::opt< bool > FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true), cl::desc("Always use $gp as the global base register."))
llvm::MipsFunctionInfo::getMoveF64ViaSpillFI
int getMoveF64ViaSpillFI(MachineFunction &MF, const TargetRegisterClass *RC)
Definition: MipsMachineFunction.cpp:193
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:412
llvm::MipsFunctionInfo::globalBaseRegSet
bool globalBaseRegSet() const
Definition: MipsMachineFunction.cpp:27
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::PseudoSourceValueManager::getExternalSymbolCallEntry
const PseudoSourceValue * getExternalSymbolCallEntry(const char *ES)
Definition: PseudoSourceValue.cpp:146
TargetRegisterInfo.h
llvm::MipsFunctionInfo::callPtrInfo
MachinePointerInfo callPtrInfo(MachineFunction &MF, const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
Definition: MipsMachineFunction.cpp:183