LLVM  16.0.0git
MipsMachineFunction.cpp
Go to the documentation of this file.
1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MipsMachineFunction.h"
11 #include "MipsSubtarget.h"
12 #include "MipsTargetMachine.h"
18 
19 using namespace llvm;
20 
21 static cl::opt<bool>
22 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
23  cl::desc("Always use $gp as the global base register."));
24 
28  &Src2DstMBB) const {
29  return DestMF.cloneInfo<MipsFunctionInfo>(*this);
30 }
31 
33 
35  return GlobalBaseReg;
36 }
37 
39  auto &STI = MF.getSubtarget<MipsSubtarget>();
40  auto &TM = static_cast<const MipsTargetMachine &>(MF.getTarget());
41 
42  if (STI.inMips16Mode())
43  return Mips::CPU16RegsRegClass;
44 
45  if (STI.inMicroMipsMode())
46  return Mips::GPRMM16RegClass;
47 
48  if (TM.getABI().IsN64())
49  return Mips::GPR64RegClass;
50 
51  return Mips::GPR32RegClass;
52 }
53 
55  if (!GlobalBaseReg)
56  GlobalBaseReg =
58  return GlobalBaseReg;
59 }
60 
62  if (!GlobalBaseReg) {
63  getGlobalBaseReg(MF);
65  }
66  return GlobalBaseReg;
67 }
68 
70  if (!GlobalBaseReg)
71  return;
72 
73  MachineBasicBlock &MBB = MF.front();
75  MachineRegisterInfo &RegInfo = MF.getRegInfo();
77  DebugLoc DL;
78  const TargetRegisterClass *RC;
79  const MipsABIInfo &ABI =
80  static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
81  RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
82 
83  Register V0 = RegInfo.createVirtualRegister(RC);
84  Register V1 = RegInfo.createVirtualRegister(RC);
85 
86  if (ABI.IsN64()) {
87  MF.getRegInfo().addLiveIn(Mips::T9_64);
88  MBB.addLiveIn(Mips::T9_64);
89 
90  // lui $v0, %hi(%neg(%gp_rel(fname)))
91  // daddu $v1, $v0, $t9
92  // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
93  const GlobalValue *FName = &MF.getFunction();
94  BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
96  BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
97  .addReg(Mips::T9_64);
98  BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
100  return;
101  }
102 
103  if (!MF.getTarget().isPositionIndependent()) {
104  // Set global register to __gnu_local_gp.
105  //
106  // lui $v0, %hi(__gnu_local_gp)
107  // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
108  BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
109  .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
110  BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
111  .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
112  return;
113  }
114 
115  MF.getRegInfo().addLiveIn(Mips::T9);
116  MBB.addLiveIn(Mips::T9);
117 
118  if (ABI.IsN32()) {
119  // lui $v0, %hi(%neg(%gp_rel(fname)))
120  // addu $v1, $v0, $t9
121  // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
122  const GlobalValue *FName = &MF.getFunction();
123  BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
125  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
126  BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
128  return;
129  }
130 
131  assert(ABI.IsO32());
132 
133  // For O32 ABI, the following instruction sequence is emitted to initialize
134  // the global base register:
135  //
136  // 0. lui $2, %hi(_gp_disp)
137  // 1. addiu $2, $2, %lo(_gp_disp)
138  // 2. addu $globalbasereg, $2, $t9
139  //
140  // We emit only the last instruction here.
141  //
142  // GNU linker requires that the first two instructions appear at the beginning
143  // of a function and no instructions be inserted before or between them.
144  // The two instructions are emitted during lowering to MC layer in order to
145  // avoid any reordering.
146  //
147  // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
148  // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
149  // reads it.
150  MF.getRegInfo().addLiveIn(Mips::V0);
151  MBB.addLiveIn(Mips::V0);
152  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
153  .addReg(Mips::V0).addReg(Mips::T9);
154 }
155 
158  for (int &I : EhDataRegFI) {
159  const TargetRegisterClass &RC =
160  static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
161  ? Mips::GPR64RegClass
162  : Mips::GPR32RegClass;
163 
165  TRI.getSpillAlign(RC), false);
166  }
167 }
168 
170  // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
171  // The current implementation only supports Mips32r2+ not Mips64rX. Status
172  // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture,
173  // however Mips32r2+ is the supported architecture.
174  const TargetRegisterClass &RC = Mips::GPR32RegClass;
176 
177  for (int &I : ISRDataRegFI)
179  TRI.getSpillAlign(RC), false);
180 }
181 
183  return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
184  || FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
185 }
186 
187 bool MipsFunctionInfo::isISRRegFI(int FI) const {
188  return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
189 }
191  const char *ES) {
193 }
194 
196  const GlobalValue *GV) {
198 }
199 
201  const TargetRegisterClass *RC) {
203  if (MoveF64ViaSpillFI == -1) {
204  MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject(
205  TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC), false);
206  }
207  return MoveF64ViaSpillFI;
208 }
209 
210 void MipsFunctionInfo::anchor() {}
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:959
ABI
Generic address nodes are lowered to some combination of target independent and machine specific ABI
Definition: Relocation.txt:34
llvm::MipsTargetMachine
Definition: MipsTargetMachine.h:27
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MipsABIInfo
Definition: MipsABIInfo.h:22
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:95
llvm::MipsFunctionInfo::createISRRegFI
void createISRRegFI(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:169
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:127
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::MachineFunction::getPSVManager
PseudoSourceValueManager & getPSVManager() const
Definition: MachineFunction.h:617
MipsTargetMachine.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MipsFunctionInfo
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Definition: MipsMachineFunction.h:25
MachineRegisterInfo.h
CommandLine.h
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:866
llvm::MipsFunctionInfo::~MipsFunctionInfo
~MipsFunctionInfo() override
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MipsFunctionInfo::initGlobalBaseReg
void initGlobalBaseReg(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:69
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
getGlobalBaseRegClass
static const TargetRegisterClass & getGlobalBaseRegClass(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:38
llvm::MipsII::MO_ABS_LO
@ MO_ABS_LO
Definition: MipsBaseInfo.h:53
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:41
llvm::MipsFunctionInfo::isEhDataRegFI
bool isEhDataRegFI(int FI) const
Definition: MipsMachineFunction.cpp:182
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:292
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::cl::opt< bool >
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:286
llvm::MipsFunctionInfo::createEhDataRegsFI
void createEhDataRegsFI(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:156
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:63
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::DenseMap
Definition: DenseMap.h:714
I
#define I(x, y, z)
Definition: MD5.cpp:58
MipsMachineFunction.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MipsFunctionInfo::clone
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
Definition: MipsMachineFunction.cpp:26
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MipsFunctionInfo::getGlobalBaseRegForGlobalISel
Register getGlobalBaseRegForGlobalISel(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:61
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::MipsFunctionInfo::getGlobalBaseReg
Register getGlobalBaseReg(MachineFunction &MF)
Definition: MipsMachineFunction.cpp:54
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::MipsFunctionInfo::isISRRegFI
bool isISRRegFI(int FI) const
Definition: MipsMachineFunction.cpp:187
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:404
llvm::MachineFunction::cloneInfo
Ty * cloneInfo(const Ty &Old)
Definition: MachineFunction.h:766
llvm::PseudoSourceValueManager::getGlobalValueCallEntry
const PseudoSourceValue * getGlobalValueCallEntry(const GlobalValue *GV)
Definition: PseudoSourceValue.cpp:131
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MipsII::MO_GPOFF_LO
@ MO_GPOFF_LO
Definition: MipsBaseInfo.h:78
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:653
MachineFrameInfo.h
MipsABIInfo.h
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:177
llvm::MipsII::MO_ABS_HI
@ MO_ABS_HI
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
llvm::MipsII::MO_GPOFF_HI
@ MO_GPOFF_HI
Definition: MipsBaseInfo.h:77
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:143
MipsSubtarget.h
FixGlobalBaseReg
static cl::opt< bool > FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true), cl::desc("Always use $gp as the global base register."))
llvm::MipsFunctionInfo::getMoveF64ViaSpillFI
int getMoveF64ViaSpillFI(MachineFunction &MF, const TargetRegisterClass *RC)
Definition: MipsMachineFunction.cpp:200
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:413
llvm::MipsFunctionInfo::globalBaseRegSet
bool globalBaseRegSet() const
Definition: MipsMachineFunction.cpp:34
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MachineFunctionInfo
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Definition: MachineFunction.h:95
llvm::PseudoSourceValueManager::getExternalSymbolCallEntry
const PseudoSourceValue * getExternalSymbolCallEntry(const char *ES)
Definition: PseudoSourceValue.cpp:140
TargetRegisterInfo.h
llvm::MipsFunctionInfo::callPtrInfo
MachinePointerInfo callPtrInfo(MachineFunction &MF, const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
Definition: MipsMachineFunction.cpp:190