LLVM 18.0.0git
llvm::RISCVSubtarget Member List

This is the complete list of members for llvm::RISCVSubtarget, including all inherited members.

CallLoweringInfollvm::RISCVSubtargetprotected
enableMachineScheduler() const overridellvm::RISCVSubtargetinline
enableSubRegLiveness() const overridellvm::RISCVSubtarget
getCallLowering() const overridellvm::RISCVSubtarget
getDLenFactor() constllvm::RISCVSubtargetinline
getELen() constllvm::RISCVSubtargetinline
getFLen() constllvm::RISCVSubtargetinline
getFrameLowering() const overridellvm::RISCVSubtargetinline
getInstrInfo() const overridellvm::RISCVSubtargetinline
getInstructionSelector() const overridellvm::RISCVSubtarget
getLegalizerInfo() const overridellvm::RISCVSubtarget
getMaxBuildIntsCost() constllvm::RISCVSubtarget
getMaxInterleaveFactor() constllvm::RISCVSubtargetinline
getMaxLMULForFixedLengthVectors() constllvm::RISCVSubtarget
getMaxRVVVectorSizeInBits() constllvm::RISCVSubtargetprotected
getMinRVVVectorSizeInBits() constllvm::RISCVSubtargetprotected
getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const overridellvm::RISCVSubtarget
getPrefFunctionAlignment() constllvm::RISCVSubtargetinline
getPrefLoopAlignment() constllvm::RISCVSubtargetinline
getProcFamily() constllvm::RISCVSubtargetinline
getRealMaxVLen() constllvm::RISCVSubtargetinline
getRealMinVLen() constllvm::RISCVSubtargetinline
getRegBankInfo() const overridellvm::RISCVSubtarget
getRegisterInfo() const overridellvm::RISCVSubtargetinline
getSelectionDAGInfo() const overridellvm::RISCVSubtargetinline
getTargetABI() constllvm::RISCVSubtargetinline
getTargetLowering() const overridellvm::RISCVSubtargetinline
getXLen() constllvm::RISCVSubtargetinline
getXLenVT() constllvm::RISCVSubtargetinline
hasHalfFPLoadStoreMove() constllvm::RISCVSubtargetinline
hasMacroFusion() constllvm::RISCVSubtargetinline
hasStdExtCOrZca() constllvm::RISCVSubtargetinline
hasStdExtDOrZdinx() constllvm::RISCVSubtargetinline
hasStdExtFOrZfinx() constllvm::RISCVSubtargetinline
hasStdExtZfhOrZfhmin() constllvm::RISCVSubtargetinline
hasStdExtZfhOrZfhminOrZhinxOrZhinxmin() constllvm::RISCVSubtargetinline
hasStdExtZfhOrZhinx() constllvm::RISCVSubtargetinline
hasStdExtZhinxOrZhinxmin() constllvm::RISCVSubtargetinline
hasStdExtZvl() constllvm::RISCVSubtargetinline
hasVInstructions() constllvm::RISCVSubtargetinline
hasVInstructionsAnyF() constllvm::RISCVSubtargetinline
hasVInstructionsBF16() constllvm::RISCVSubtargetinline
hasVInstructionsF16() constllvm::RISCVSubtargetinline
hasVInstructionsF16Minimal() constllvm::RISCVSubtargetinline
hasVInstructionsF32() constllvm::RISCVSubtargetinline
hasVInstructionsF64() constllvm::RISCVSubtargetinline
hasVInstructionsFullMultiply() constllvm::RISCVSubtargetinline
hasVInstructionsI64() constllvm::RISCVSubtargetinline
InstSelectorllvm::RISCVSubtargetprotected
is64Bit() constllvm::RISCVSubtargetinline
isRegisterReservedByUser(Register i) constllvm::RISCVSubtargetinline
isSoftFPABI() constllvm::RISCVSubtargetinline
isTargetFuchsia() constllvm::RISCVSubtargetinline
Legalizerllvm::RISCVSubtargetprotected
Others enum valuellvm::RISCVSubtarget
ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)llvm::RISCVSubtarget
RegBankInfollvm::RISCVSubtargetprotected
RISCVProcFamilyEnum enum namellvm::RISCVSubtarget
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)llvm::RISCVSubtarget
SiFive7 enum valuellvm::RISCVSubtarget
useAA() const overridellvm::RISCVSubtarget
useConstantPoolForLargeInts() constllvm::RISCVSubtarget
useRVVForFixedLengthVectors() constllvm::RISCVSubtarget