LLVM
18.0.0git
llvm
RISCVSubtarget
llvm::RISCVSubtarget Member List
This is the complete list of members for
llvm::RISCVSubtarget
, including all inherited members.
CallLoweringInfo
llvm::RISCVSubtarget
protected
enableMachineScheduler
() const override
llvm::RISCVSubtarget
inline
enableSubRegLiveness
() const override
llvm::RISCVSubtarget
getCallLowering
() const override
llvm::RISCVSubtarget
getDLenFactor
() const
llvm::RISCVSubtarget
inline
getELen
() const
llvm::RISCVSubtarget
inline
getFLen
() const
llvm::RISCVSubtarget
inline
getFrameLowering
() const override
llvm::RISCVSubtarget
inline
getInstrInfo
() const override
llvm::RISCVSubtarget
inline
getInstructionSelector
() const override
llvm::RISCVSubtarget
getLegalizerInfo
() const override
llvm::RISCVSubtarget
getMaxBuildIntsCost
() const
llvm::RISCVSubtarget
getMaxInterleaveFactor
() const
llvm::RISCVSubtarget
inline
getMaxLMULForFixedLengthVectors
() const
llvm::RISCVSubtarget
getMaxRVVVectorSizeInBits
() const
llvm::RISCVSubtarget
protected
getMinRVVVectorSizeInBits
() const
llvm::RISCVSubtarget
protected
getPostRAMutations
(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
llvm::RISCVSubtarget
getPrefFunctionAlignment
() const
llvm::RISCVSubtarget
inline
getPrefLoopAlignment
() const
llvm::RISCVSubtarget
inline
getProcFamily
() const
llvm::RISCVSubtarget
inline
getRealMaxVLen
() const
llvm::RISCVSubtarget
inline
getRealMinVLen
() const
llvm::RISCVSubtarget
inline
getRegBankInfo
() const override
llvm::RISCVSubtarget
getRegisterInfo
() const override
llvm::RISCVSubtarget
inline
getSelectionDAGInfo
() const override
llvm::RISCVSubtarget
inline
getTargetABI
() const
llvm::RISCVSubtarget
inline
getTargetLowering
() const override
llvm::RISCVSubtarget
inline
getXLen
() const
llvm::RISCVSubtarget
inline
getXLenVT
() const
llvm::RISCVSubtarget
inline
hasHalfFPLoadStoreMove
() const
llvm::RISCVSubtarget
inline
hasMacroFusion
() const
llvm::RISCVSubtarget
inline
hasStdExtCOrZca
() const
llvm::RISCVSubtarget
inline
hasStdExtDOrZdinx
() const
llvm::RISCVSubtarget
inline
hasStdExtFOrZfinx
() const
llvm::RISCVSubtarget
inline
hasStdExtZfhOrZfhmin
() const
llvm::RISCVSubtarget
inline
hasStdExtZfhOrZfhminOrZhinxOrZhinxmin
() const
llvm::RISCVSubtarget
inline
hasStdExtZfhOrZhinx
() const
llvm::RISCVSubtarget
inline
hasStdExtZhinxOrZhinxmin
() const
llvm::RISCVSubtarget
inline
hasStdExtZvl
() const
llvm::RISCVSubtarget
inline
hasVInstructions
() const
llvm::RISCVSubtarget
inline
hasVInstructionsAnyF
() const
llvm::RISCVSubtarget
inline
hasVInstructionsBF16
() const
llvm::RISCVSubtarget
inline
hasVInstructionsF16
() const
llvm::RISCVSubtarget
inline
hasVInstructionsF16Minimal
() const
llvm::RISCVSubtarget
inline
hasVInstructionsF32
() const
llvm::RISCVSubtarget
inline
hasVInstructionsF64
() const
llvm::RISCVSubtarget
inline
hasVInstructionsFullMultiply
() const
llvm::RISCVSubtarget
inline
hasVInstructionsI64
() const
llvm::RISCVSubtarget
inline
InstSelector
llvm::RISCVSubtarget
protected
is64Bit
() const
llvm::RISCVSubtarget
inline
isRegisterReservedByUser
(Register i) const
llvm::RISCVSubtarget
inline
isSoftFPABI
() const
llvm::RISCVSubtarget
inline
isTargetFuchsia
() const
llvm::RISCVSubtarget
inline
Legalizer
llvm::RISCVSubtarget
protected
Others
enum value
llvm::RISCVSubtarget
ParseSubtargetFeatures
(StringRef CPU, StringRef TuneCPU, StringRef FS)
llvm::RISCVSubtarget
RegBankInfo
llvm::RISCVSubtarget
protected
RISCVProcFamilyEnum
enum name
llvm::RISCVSubtarget
RISCVSubtarget
(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)
llvm::RISCVSubtarget
SiFive7
enum value
llvm::RISCVSubtarget
useAA
() const override
llvm::RISCVSubtarget
useConstantPoolForLargeInts
() const
llvm::RISCVSubtarget
useRVVForFixedLengthVectors
() const
llvm::RISCVSubtarget
Generated on Tue Sep 26 2023 11:22:32 for LLVM by
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