LLVM  14.0.0git
RISCVTargetTransformInfo.cpp
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1 //===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
14 using namespace llvm;
15 
16 #define DEBUG_TYPE "riscvtti"
17 
19  "riscv-v-register-bit-width-lmul",
20  cl::desc(
21  "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used "
22  "by autovectorized code. Fractional LMULs are not supported."),
23  cl::init(1), cl::Hidden);
24 
27  assert(Ty->isIntegerTy() &&
28  "getIntImmCost can only estimate cost of materialising integers");
29 
30  // We have a Zero register, so 0 is always free.
31  if (Imm == 0)
32  return TTI::TCC_Free;
33 
34  // Otherwise, we check how many instructions it will take to materialise.
35  const DataLayout &DL = getDataLayout();
37  getST()->getFeatureBits());
38 }
39 
40 InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
41  const APInt &Imm, Type *Ty,
43  Instruction *Inst) {
44  assert(Ty->isIntegerTy() &&
45  "getIntImmCost can only estimate cost of materialising integers");
46 
47  // We have a Zero register, so 0 is always free.
48  if (Imm == 0)
49  return TTI::TCC_Free;
50 
51  // Some instructions in RISC-V can take a 12-bit immediate. Some of these are
52  // commutative, in others the immediate comes from a specific argument index.
53  bool Takes12BitImm = false;
54  unsigned ImmArgIdx = ~0U;
55 
56  switch (Opcode) {
57  case Instruction::GetElementPtr:
58  // Never hoist any arguments to a GetElementPtr. CodeGenPrepare will
59  // split up large offsets in GEP into better parts than ConstantHoisting
60  // can.
61  return TTI::TCC_Free;
62  case Instruction::And:
63  // zext.h
64  if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb())
65  return TTI::TCC_Free;
66  // zext.w
67  if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZbb())
68  return TTI::TCC_Free;
70  case Instruction::Add:
71  case Instruction::Or:
72  case Instruction::Xor:
73  case Instruction::Mul:
74  Takes12BitImm = true;
75  break;
76  case Instruction::Sub:
77  case Instruction::Shl:
78  case Instruction::LShr:
79  case Instruction::AShr:
80  Takes12BitImm = true;
81  ImmArgIdx = 1;
82  break;
83  default:
84  break;
85  }
86 
87  if (Takes12BitImm) {
88  // Check immediate is the correct argument...
89  if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) {
90  // ... and fits into the 12-bit immediate.
91  if (Imm.getMinSignedBits() <= 64 &&
92  getTLI()->isLegalAddImmediate(Imm.getSExtValue())) {
93  return TTI::TCC_Free;
94  }
95  }
96 
97  // Otherwise, use the full materialisation cost.
98  return getIntImmCost(Imm, Ty, CostKind);
99  }
100 
101  // By default, prevent hoisting.
102  return TTI::TCC_Free;
103 }
104 
107  const APInt &Imm, Type *Ty,
109  // Prevent hoisting in unknown cases.
110  return TTI::TCC_Free;
111 }
112 
115  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
117 }
118 
120  // Currently, the ExpandReductions pass can't expand scalable-vector
121  // reductions, but we still request expansion as RVV doesn't support certain
122  // reductions and the SelectionDAG can't legalize them either.
123  switch (II->getIntrinsicID()) {
124  default:
125  return false;
126  // These reductions have no equivalent in RVV
127  case Intrinsic::vector_reduce_mul:
128  case Intrinsic::vector_reduce_fmul:
129  return true;
130  }
131 }
132 
134  // There is no assumption of the maximum vector length in V specification.
135  // We use the value specified by users as the maximum vector length.
136  // This function will use the assumed maximum vector length to get the
137  // maximum vscale for LoopVectorizer.
138  // If users do not specify the maximum vector length, we have no way to
139  // know whether the LoopVectorizer is safe to do or not.
140  // We only consider to use single vector register (LMUL = 1) to vectorize.
141  unsigned MaxVectorSizeInBits = ST->getMaxRVVVectorSizeInBits();
142  if (ST->hasVInstructions() && MaxVectorSizeInBits != 0)
143  return MaxVectorSizeInBits / RISCV::RVVBitsPerBlock;
144  return BaseT::getMaxVScale();
145 }
146 
147 TypeSize
149  unsigned LMUL = PowerOf2Floor(
150  std::max<unsigned>(std::min<unsigned>(RVVRegisterWidthLMUL, 8), 1));
151  switch (K) {
153  return TypeSize::getFixed(ST->getXLen());
155  return TypeSize::getFixed(
156  ST->hasVInstructions() ? LMUL * ST->getMinRVVVectorSizeInBits() : 0);
158  return TypeSize::getScalable(
160  }
161 
162  llvm_unreachable("Unsupported register kind");
163 }
164 
166  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
167  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) {
169  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
170  Alignment, CostKind, I);
171 
172  if ((Opcode == Instruction::Load &&
173  !isLegalMaskedGather(DataTy, Align(Alignment))) ||
174  (Opcode == Instruction::Store &&
175  !isLegalMaskedScatter(DataTy, Align(Alignment))))
176  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
177  Alignment, CostKind, I);
178 
179  // FIXME: Only supporting fixed vectors for now.
180  if (!isa<FixedVectorType>(DataTy))
181  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
182  Alignment, CostKind, I);
183 
184  auto *VTy = cast<FixedVectorType>(DataTy);
185  unsigned NumLoads = VTy->getNumElements();
186  InstructionCost MemOpCost =
187  getMemoryOpCost(Opcode, VTy->getElementType(), Alignment, 0, CostKind, I);
188  return NumLoads * MemOpCost;
189 }
190 
194  // TODO: More tuning on benchmarks and metrics with changes as needed
195  // would apply to all settings below to enable performance.
196 
197  // Support explicit targets enabled for SiFive with the unrolling preferences
198  // below
199  bool UseDefaultPreferences = true;
201  UseDefaultPreferences = false;
202 
203  if (UseDefaultPreferences)
204  return BasicTTIImplBase::getUnrollingPreferences(L, SE, UP, ORE);
205 
206  // Enable Upper bound unrolling universally, not dependant upon the conditions
207  // below.
208  UP.UpperBound = true;
209 
210  // Disable loop unrolling for Oz and Os.
211  UP.OptSizeThreshold = 0;
213  if (L->getHeader()->getParent()->hasOptSize())
214  return;
215 
216  SmallVector<BasicBlock *, 4> ExitingBlocks;
217  L->getExitingBlocks(ExitingBlocks);
218  LLVM_DEBUG(dbgs() << "Loop has:\n"
219  << "Blocks: " << L->getNumBlocks() << "\n"
220  << "Exit blocks: " << ExitingBlocks.size() << "\n");
221 
222  // Only allow another exit other than the latch. This acts as an early exit
223  // as it mirrors the profitability calculation of the runtime unroller.
224  if (ExitingBlocks.size() > 2)
225  return;
226 
227  // Limit the CFG of the loop body for targets with a branch predictor.
228  // Allowing 4 blocks permits if-then-else diamonds in the body.
229  if (L->getNumBlocks() > 4)
230  return;
231 
232  // Don't unroll vectorized loops, including the remainder loop
233  if (getBooleanLoopAttribute(L, "llvm.loop.isvectorized"))
234  return;
235 
236  // Scan the loop: don't unroll loops with calls as this could prevent
237  // inlining.
238  InstructionCost Cost = 0;
239  for (auto *BB : L->getBlocks()) {
240  for (auto &I : *BB) {
241  // Initial setting - Don't unroll loops containing vectorized
242  // instructions.
243  if (I.getType()->isVectorTy())
244  return;
245 
246  if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
247  if (const Function *F = cast<CallBase>(I).getCalledFunction()) {
248  if (!isLoweredToCall(F))
249  continue;
250  }
251  return;
252  }
253 
254  SmallVector<const Value *> Operands(I.operand_values());
255  Cost +=
257  }
258  }
259 
260  LLVM_DEBUG(dbgs() << "Cost of loop: " << Cost << "\n");
261 
262  UP.Partial = true;
263  UP.Runtime = true;
264  UP.UnrollRemainder = true;
265  UP.UnrollAndJam = true;
267 
268  // Force unrolling small loops can be very useful because of the branch
269  // taken cost of the backedge.
270  if (Cost < 12)
271  UP.Force = true;
272 }
273 
276  BaseT::getPeelingPreferences(L, SE, PP);
277 }
278 
281  if (Ty->isVectorTy()) {
282  if (Size.isScalable() && ST->hasVInstructions())
283  return divideCeil(Size.getKnownMinValue(), RISCV::RVVBitsPerBlock);
284 
285  if (ST->useRVVForFixedLengthVectors())
287  }
288 
289  return BaseT::getRegUsageForType(Ty);
290 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::PSK_FastHardware
@ PSK_FastHardware
Definition: TargetTransformInfo.h:595
llvm::TargetTransformInfo::UnrollingPreferences::PartialOptSizeThreshold
unsigned PartialOptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size, like OptSizeThreshold,...
Definition: TargetTransformInfo.h:460
llvm::RISCVTTIImpl::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: RISCVTargetTransformInfo.cpp:133
llvm::RISCVMatInt::getIntMatCost
int getIntMatCost(const APInt &Val, unsigned Size, const FeatureBitset &ActiveFeatures, bool CompressionCost)
Definition: RISCVMatInt.cpp:348
llvm::BasicTTIImplBase< RISCVTTIImpl >::DL
const DataLayout & DL
Definition: TargetTransformInfoImpl.h:39
llvm::TargetTransformInfo::UnrollingPreferences::Runtime
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
Definition: TargetTransformInfo.h:488
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm::RISCVTTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: RISCVTargetTransformInfo.cpp:119
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::RISCVTTIImpl::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:106
llvm::RISCVTTIImpl::getPopcntSupport
TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: RISCVTargetTransformInfo.cpp:114
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::RISCVSubtarget::useRVVForFixedLengthVectors
bool useRVVForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:206
llvm::BasicBlock::getParent
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:107
llvm::Function
Definition: Function.h:62
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:595
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:52
llvm::TargetTransformInfoImplCRTPBase< RISCVTTIImpl >::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:961
llvm::DataLayout::getTypeSizeInBits
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:673
llvm::APInt::getMinSignedBits
unsigned getMinSignedBits() const
NOTE: This is soft-deprecated. Please use getSignificantBits() instead.
Definition: APInt.h:1460
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1479
llvm::RISCVSubtarget::hasVInstructions
bool hasVInstructions() const
Definition: RISCVSubtarget.h:180
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:460
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:916
llvm::TargetTransformInfo::UnrollingPreferences::UnrollAndJamInnerLoopThreshold
unsigned UnrollAndJamInnerLoopThreshold
Threshold for unroll and jam, for inner loop size.
Definition: TargetTransformInfo.h:507
llvm::RISCVTTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:134
llvm::TargetTransformInfo::UnrollingPreferences::UnrollRemainder
bool UnrollRemainder
Allow unrolling of all the iterations of the runtime loop remainder.
Definition: TargetTransformInfo.h:500
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::TargetTransformInfo::UnrollingPreferences::Partial
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
Definition: TargetTransformInfo.h:484
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:538
llvm::RISCVTTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:131
llvm::Optional< unsigned >
llvm::RISCVTTIImpl::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:25
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
RISCVMatInt.h
llvm::LoopBase::getNumBlocks
unsigned getNumBlocks() const
Get the number of blocks in this loop in constant time.
Definition: LoopInfo.h:185
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:49
TargetLowering.h
llvm::RISCVTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: RISCVTargetTransformInfo.cpp:274
llvm::BasicTTIImplBase::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: BasicTTIImpl.h:493
llvm::RISCVTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: RISCVTargetTransformInfo.cpp:148
llvm::PowerOf2Floor
uint64_t PowerOf2Floor(uint64_t A)
Returns the power of two which is less than or equal to the given value.
Definition: MathExtras.h:695
llvm::TargetTransformInfo::UnrollingPreferences::Force
bool Force
Apply loop unroll on any kind of loop (mainly to loops that fail runtime unrolling).
Definition: TargetTransformInfo.h:496
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:226
llvm::TargetTransformInfo::UnrollingPreferences::UnrollAndJam
bool UnrollAndJam
Allow unroll and jam. Used to enable unroll and jam for the target.
Definition: TargetTransformInfo.h:502
llvm::LoopBase::getBlocks
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
Definition: LoopInfo.h:171
llvm::Instruction
Definition: Instruction.h:45
llvm::LoopBase::getExitingBlocks
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Definition: LoopInfoImpl.h:34
llvm::RISCVTTIImpl::getRegUsageForType
InstructionCost getRegUsageForType(Type *Ty)
Definition: RISCVTargetTransformInfo.cpp:279
llvm::RISCVSubtarget::hasStdExtZbb
bool hasStdExtZbb() const
Definition: RISCVSubtarget.h:143
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:916
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::Instruction::isCommutative
bool isCommutative() const LLVM_READONLY
Return true if the instruction is commutative:
Definition: Instruction.cpp:768
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:595
llvm::RISCVTTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Definition: RISCVTargetTransformInfo.cpp:165
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:190
llvm::RISCV::RVVBitsPerBlock
static constexpr unsigned RVVBitsPerBlock
Definition: RISCVISelLowering.h:665
llvm::cl::opt
Definition: CommandLine.h:1432
llvm::RISCVSubtarget::getMaxRVVVectorSizeInBits
unsigned getMaxRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:139
llvm::divideCeil
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:742
llvm::RISCVSubtarget::getProcFamily
RISCVProcFamilyEnum getProcFamily() const
Returns RISCV processor family.
Definition: RISCVSubtarget.h:135
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:431
I
#define I(x, y, z)
Definition: MD5.cpp:58
getCalledFunction
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
Definition: MemoryBuiltins.cpp:117
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::RISCVTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: RISCVTargetTransformInfo.cpp:191
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RVVRegisterWidthLMUL
static cl::opt< unsigned > RVVRegisterWidthLMUL("riscv-v-register-bit-width-lmul", cl::desc("The LMUL to use for getRegisterBitWidth queries. Affects LMUL used " "by autovectorized code. Fractional LMULs are not supported."), cl::init(1), cl::Hidden)
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: BasicTTIImpl.h:672
llvm::TargetTransformInfoImplBase::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Definition: TargetTransformInfoImpl.h:124
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:262
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:68
llvm::TargetTransformInfo::TCK_SizeAndLatency
@ TCK_SizeAndLatency
The weighted sum of size and latency.
Definition: TargetTransformInfo.h:215
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::BasicTTIImplBase< RISCVTTIImpl >::getRegUsageForType
InstructionCost getRegUsageForType(Type *Ty)
Definition: BasicTTIImpl.h:365
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BasicTTIImplBase< RISCVTTIImpl >::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: BasicTTIImpl.h:565
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:290
llvm::Function::hasOptSize
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:661
llvm::TargetTransformInfo::UnrollingPreferences::UpperBound
bool UpperBound
Allow using trip count upper bound to unroll loops.
Definition: TargetTransformInfo.h:498
llvm::TypeSize
Definition: TypeSize.h:416
llvm::LoopBase::getHeader
BlockT * getHeader() const
Definition: LoopInfo.h:104
llvm::LinearPolySize< TypeSize >::getScalable
static TypeSize getScalable(ScalarTy MinVal)
Definition: TypeSize.h:286
llvm::BasicTTIImplBase< RISCVTTIImpl >::isLegalAddImmediate
bool isLegalAddImmediate(int64_t imm)
Definition: BasicTTIImpl.h:296
llvm::RISCVSubtarget::getXLen
unsigned getXLen() const
Definition: RISCVSubtarget.h:163
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:183
llvm::XCoreISD::LMUL
@ LMUL
Definition: XCoreISelLowering.h:59
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:916
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::BasicTTIImplBase< RISCVTTIImpl >::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1210
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:916
llvm::getBooleanLoopAttribute
bool getBooleanLoopAttribute(const Loop *TheLoop, StringRef Name)
Returns true if Name is applied to TheLoop and enabled.
Definition: LoopInfo.cpp:1088
TargetTransformInfo.h
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1159
llvm::TargetTransformInfo::UnrollingPreferences::OptSizeThreshold
unsigned OptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size (set to UINT_MAX to disable).
Definition: TargetTransformInfo.h:453
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::RISCVSubtarget::getMinRVVVectorSizeInBits
unsigned getMinRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:163
llvm::RISCVSubtarget::SiFive7
@ SiFive7
Definition: RISCVSubtarget.h:55
BasicTTIImpl.h
llvm::cl::desc
Definition: CommandLine.h:412
RISCVTargetTransformInfo.h
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::RISCVTTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: RISCVTargetTransformInfo.cpp:40
llvm::Type::getPrimitiveSizeInBits
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:166
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38