21#define DEBUG_TYPE "riscvtti"
24 "riscv-v-register-bit-width-lmul",
26 "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used "
27 "by autovectorized code. Fractional LMULs are not supported."),
33 "Overrides result used for getMaximumVF query which is used "
34 "exclusively by SLP vectorizer."),
43 size_t NumInstr = OpCodes.
size();
48 return LMULCost * NumInstr;
50 for (
auto Op : OpCodes) {
52 case RISCV::VRGATHER_VI:
55 case RISCV::VRGATHER_VV:
58 case RISCV::VSLIDEUP_VI:
59 case RISCV::VSLIDEDOWN_VI:
62 case RISCV::VSLIDEUP_VX:
63 case RISCV::VSLIDEDOWN_VX:
66 case RISCV::VREDMAX_VS:
67 case RISCV::VREDMIN_VS:
68 case RISCV::VREDMAXU_VS:
69 case RISCV::VREDMINU_VS:
70 case RISCV::VREDSUM_VS:
71 case RISCV::VREDAND_VS:
72 case RISCV::VREDOR_VS:
73 case RISCV::VREDXOR_VS:
74 case RISCV::VFREDMAX_VS:
75 case RISCV::VFREDMIN_VS:
76 case RISCV::VFREDUSUM_VS: {
83 case RISCV::VFREDOSUM_VS: {
97 case RISCV::VMANDN_MM:
98 case RISCV::VMNAND_MM:
112 "getIntImmCost can only estimate cost of materialising integers");
128 auto *BO = dyn_cast<BinaryOperator>(Inst->
getOperand(0));
129 if (!BO || !BO->hasOneUse())
132 if (BO->getOpcode() != Instruction::Shl)
135 if (!isa<ConstantInt>(BO->getOperand(1)))
138 unsigned ShAmt = cast<ConstantInt>(BO->getOperand(1))->getZExtValue();
143 if (ShAmt == Trailing)
155 "getIntImmCost can only estimate cost of materialising integers");
163 bool Takes12BitImm =
false;
164 unsigned ImmArgIdx = ~0U;
167 case Instruction::GetElementPtr:
172 case Instruction::Store:
177 case Instruction::Load:
180 case Instruction::And:
182 if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb())
185 if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZba())
188 if (ST->hasStdExtZbs() && (~Imm).isPowerOf2())
190 if (Inst &&
Idx == 1 && Imm.getBitWidth() <= ST->
getXLen() &&
193 Takes12BitImm =
true;
195 case Instruction::Add:
196 Takes12BitImm =
true;
198 case Instruction::Or:
199 case Instruction::Xor:
201 if (ST->hasStdExtZbs() && Imm.isPowerOf2())
203 Takes12BitImm =
true;
205 case Instruction::Mul:
207 if (Imm.isPowerOf2() || Imm.isNegatedPowerOf2())
210 if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2())
213 Takes12BitImm =
true;
215 case Instruction::Sub:
216 case Instruction::Shl:
217 case Instruction::LShr:
218 case Instruction::AShr:
219 Takes12BitImm =
true;
230 if (Imm.getSignificantBits() <= 64 &&
259 return ST->hasStdExtZbb() || ST->hasVendorXCVbitmanip()
272 case Intrinsic::vector_reduce_mul:
273 case Intrinsic::vector_reduce_fmul:
329 return cast<VectorType>(
EVT(IndexVT).getTypeForEVT(
C));
345 if (isa<FixedVectorType>(Tp)) {
350 if (Mask.size() >= 2 && LT.second.isFixedLengthVector()) {
351 MVT EltTp = LT.second.getVectorElementType();
364 if (Mask[0] == 0 || Mask[0] == 1) {
368 if (
equal(DeinterleaveMask, Mask))
369 return LT.first * getRISCVInstructionCost(RISCV::VNSRL_WI,
376 if (LT.second.isFixedLengthVector() && LT.first == 1 &&
377 (LT.second.getScalarSizeInBits() != 8 ||
378 LT.second.getVectorNumElements() <= 256)) {
382 getRISCVInstructionCost(RISCV::VRGATHER_VV, LT.second,
CostKind);
391 if (LT.second.isFixedLengthVector() && LT.first == 1 &&
392 (LT.second.getScalarSizeInBits() != 8 ||
393 LT.second.getVectorNumElements() <= 256)) {
400 return 2 * IndexCost +
401 getRISCVInstructionCost({RISCV::VRGATHER_VV, RISCV::VRGATHER_VV},
411 if (!Mask.empty() && LT.first.isValid() && LT.first != 1 &&
412 LT.second.isFixedLengthVector() &&
413 LT.second.getVectorElementType().getSizeInBits() ==
415 LT.second.getVectorNumElements() <
416 cast<FixedVectorType>(Tp)->getNumElements() &&
418 cast<FixedVectorType>(Tp)->getNumElements()) ==
419 static_cast<unsigned>(*LT.first.getValue())) {
420 unsigned NumRegs = *LT.first.getValue();
421 unsigned VF = cast<FixedVectorType>(Tp)->getNumElements();
426 for (
unsigned I = 0;
I < NumRegs; ++
I) {
427 bool IsSingleVector =
true;
430 I == NumRegs - 1 ? Mask.size() % SubVF : SubVF),
431 SubMask.
begin(), [&](
int I) {
432 bool SingleSubVector = I / VF == 0;
433 IsSingleVector &= SingleSubVector;
434 return (SingleSubVector ? 0 : 1) * SubVF + I % VF;
438 SubVecTy, SubMask,
CostKind, 0,
nullptr);
466 SubLT.second.isValid() && SubLT.second.isFixedLengthVector()) {
469 if (MinVLen == MaxVLen &&
470 SubLT.second.getScalarSizeInBits() *
Index % MinVLen == 0 &&
471 SubLT.second.getSizeInBits() <= MinVLen)
479 getRISCVInstructionCost(RISCV::VSLIDEDOWN_VI, LT.second,
CostKind);
485 getRISCVInstructionCost(RISCV::VSLIDEUP_VI, LT.second,
CostKind);
497 (1 + getRISCVInstructionCost({RISCV::VMV_S_X, RISCV::VMERGE_VVM},
502 Instruction::InsertElement);
503 if (LT.second.getScalarSizeInBits() == 1) {
511 (1 + getRISCVInstructionCost({RISCV::VMV_V_X, RISCV::VMSNE_VI},
524 (1 + getRISCVInstructionCost({RISCV::VMV_V_I, RISCV::VMERGE_VIM,
525 RISCV::VMV_X_S, RISCV::VMV_V_X,
534 getRISCVInstructionCost(RISCV::VMV_V_X, LT.second,
CostKind);
540 getRISCVInstructionCost(RISCV::VRGATHER_VI, LT.second,
CostKind);
546 unsigned Opcodes[2] = {RISCV::VSLIDEDOWN_VX, RISCV::VSLIDEUP_VX};
548 Opcodes[0] = RISCV::VSLIDEDOWN_VI;
549 else if (Index < 0 && Index > -32)
550 Opcodes[1] = RISCV::VSLIDEUP_VI;
551 return LT.first * getRISCVInstructionCost(Opcodes, LT.second,
CostKind);
569 if (LT.second.isFixedLengthVector())
571 LenCost = isInt<5>(LT.second.getVectorNumElements() - 1) ? 0 : 1;
572 unsigned Opcodes[] = {RISCV::VID_V, RISCV::VRSUB_VX, RISCV::VRGATHER_VV};
573 if (LT.second.isFixedLengthVector() &&
574 isInt<5>(LT.second.getVectorNumElements() - 1))
575 Opcodes[1] = RISCV::VRSUB_VI;
577 getRISCVInstructionCost(Opcodes, LT.second,
CostKind);
580 return LT.first * (LenCost + GatherCost + ExtendCost);
601 bool UseMaskForCond,
bool UseMaskForGaps) {
602 if (isa<ScalableVectorType>(VecTy))
604 auto *FVTy = cast<FixedVectorType>(VecTy);
607 unsigned VF = FVTy->getNumElements() / Factor;
613 if (!UseMaskForCond && !UseMaskForGaps &&
614 Factor <= TLI->getMaxSupportedInterleaveFactor()) {
617 if (LT.second.isFixedLengthVector()) {
619 LT.second.getVectorNumElements());
628 return LT.first + LegalMemCost;
638 if (Opcode == Instruction::Load) {
640 for (
unsigned Index : Indices) {
665 UseMaskForCond, UseMaskForGaps);
667 assert(Opcode == Instruction::Store &&
"Opcode must be a store");
674 return MemCost + ShuffleCost;
678 unsigned Opcode,
Type *DataTy,
const Value *
Ptr,
bool VariableMask,
684 if ((Opcode == Instruction::Load &&
686 (Opcode == Instruction::Store &&
694 auto &VTy = *cast<VectorType>(DataTy);
697 {TTI::OK_AnyValue, TTI::OP_None},
I);
698 unsigned NumLoads = getEstimatedVLFor(&VTy);
699 return NumLoads * MemOpCost;
703 unsigned Opcode,
Type *DataTy,
const Value *
Ptr,
bool VariableMask,
705 if (((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
707 (Opcode != Instruction::Load && Opcode != Instruction::Store))
717 auto &VTy = *cast<VectorType>(DataTy);
720 {TTI::OK_AnyValue, TTI::OP_None},
I);
721 unsigned NumLoads = getEstimatedVLFor(&VTy);
722 return NumLoads * MemOpCost;
730 {Intrinsic::floor, MVT::f32, 9},
731 {Intrinsic::floor, MVT::f64, 9},
732 {Intrinsic::ceil, MVT::f32, 9},
733 {Intrinsic::ceil, MVT::f64, 9},
734 {Intrinsic::trunc, MVT::f32, 7},
735 {Intrinsic::trunc, MVT::f64, 7},
736 {Intrinsic::round, MVT::f32, 9},
737 {Intrinsic::round, MVT::f64, 9},
738 {Intrinsic::roundeven, MVT::f32, 9},
739 {Intrinsic::roundeven, MVT::f64, 9},
740 {Intrinsic::rint, MVT::f32, 7},
741 {Intrinsic::rint, MVT::f64, 7},
742 {Intrinsic::lrint, MVT::i32, 1},
743 {Intrinsic::lrint, MVT::i64, 1},
744 {Intrinsic::llrint, MVT::i64, 1},
745 {Intrinsic::nearbyint, MVT::f32, 9},
746 {Intrinsic::nearbyint, MVT::f64, 9},
747 {Intrinsic::bswap, MVT::i16, 3},
748 {Intrinsic::bswap, MVT::i32, 12},
749 {Intrinsic::bswap, MVT::i64, 31},
750 {Intrinsic::vp_bswap, MVT::i16, 3},
751 {Intrinsic::vp_bswap, MVT::i32, 12},
752 {Intrinsic::vp_bswap, MVT::i64, 31},
753 {Intrinsic::vp_fshl, MVT::i8, 7},
754 {Intrinsic::vp_fshl, MVT::i16, 7},
755 {Intrinsic::vp_fshl, MVT::i32, 7},
756 {Intrinsic::vp_fshl, MVT::i64, 7},
757 {Intrinsic::vp_fshr, MVT::i8, 7},
758 {Intrinsic::vp_fshr, MVT::i16, 7},
759 {Intrinsic::vp_fshr, MVT::i32, 7},
760 {Intrinsic::vp_fshr, MVT::i64, 7},
761 {Intrinsic::bitreverse, MVT::i8, 17},
762 {Intrinsic::bitreverse, MVT::i16, 24},
763 {Intrinsic::bitreverse, MVT::i32, 33},
764 {Intrinsic::bitreverse, MVT::i64, 52},
765 {Intrinsic::vp_bitreverse, MVT::i8, 17},
766 {Intrinsic::vp_bitreverse, MVT::i16, 24},
767 {Intrinsic::vp_bitreverse, MVT::i32, 33},
768 {Intrinsic::vp_bitreverse, MVT::i64, 52},
769 {Intrinsic::ctpop, MVT::i8, 12},
770 {Intrinsic::ctpop, MVT::i16, 19},
771 {Intrinsic::ctpop, MVT::i32, 20},
772 {Intrinsic::ctpop, MVT::i64, 21},
773 {Intrinsic::vp_ctpop, MVT::i8, 12},
774 {Intrinsic::vp_ctpop, MVT::i16, 19},
775 {Intrinsic::vp_ctpop, MVT::i32, 20},
776 {Intrinsic::vp_ctpop, MVT::i64, 21},
777 {Intrinsic::vp_ctlz, MVT::i8, 19},
778 {Intrinsic::vp_ctlz, MVT::i16, 28},
779 {Intrinsic::vp_ctlz, MVT::i32, 31},
780 {Intrinsic::vp_ctlz, MVT::i64, 35},
781 {Intrinsic::vp_cttz, MVT::i8, 16},
782 {Intrinsic::vp_cttz, MVT::i16, 23},
783 {Intrinsic::vp_cttz, MVT::i32, 24},
784 {Intrinsic::vp_cttz, MVT::i64, 25},
789#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \
790 case Intrinsic::VPID: \
792#include "llvm/IR/VPIntrinsics.def"
793#undef HELPER_MAP_VPID_TO_VPSD
802 switch (ICA.
getID()) {
803 case Intrinsic::ceil:
804 case Intrinsic::floor:
805 case Intrinsic::trunc:
806 case Intrinsic::rint:
807 case Intrinsic::lrint:
808 case Intrinsic::llrint:
809 case Intrinsic::round:
810 case Intrinsic::roundeven: {
817 case Intrinsic::umin:
818 case Intrinsic::umax:
819 case Intrinsic::smin:
820 case Intrinsic::smax: {
822 if (LT.second.isScalarInteger() && ST->hasStdExtZbb())
827 switch (ICA.
getID()) {
828 case Intrinsic::umin:
829 Op = RISCV::VMINU_VV;
831 case Intrinsic::umax:
832 Op = RISCV::VMAXU_VV;
834 case Intrinsic::smin:
837 case Intrinsic::smax:
841 return LT.first * getRISCVInstructionCost(
Op, LT.second,
CostKind);
845 case Intrinsic::sadd_sat:
846 case Intrinsic::ssub_sat:
847 case Intrinsic::uadd_sat:
848 case Intrinsic::usub_sat:
849 case Intrinsic::fabs:
850 case Intrinsic::sqrt: {
856 case Intrinsic::ctpop: {
862 case Intrinsic::abs: {
871 case Intrinsic::get_active_lane_mask: {
881 getRISCVInstructionCost({RISCV::VSADDU_VX, RISCV::VMSLTU_VX},
887 case Intrinsic::experimental_stepvector: {
892 return getRISCVInstructionCost(RISCV::VID_V, LT.second,
CostKind) +
894 getRISCVInstructionCost(RISCV::VADD_VX, LT.second,
CostKind);
895 return 1 + (LT.first - 1);
897 case Intrinsic::vp_rint: {
902 return Cost * LT.first;
905 case Intrinsic::vp_nearbyint: {
910 return Cost * LT.first;
913 case Intrinsic::vp_ceil:
914 case Intrinsic::vp_floor:
915 case Intrinsic::vp_round:
916 case Intrinsic::vp_roundeven:
917 case Intrinsic::vp_roundtozero: {
924 return Cost * LT.first;
931 LT.second.isVector()) {
932 MVT EltTy = LT.second.getVectorElementType();
935 return LT.first * Entry->Cost;
947 bool IsVectorType = isa<VectorType>(Dst) && isa<VectorType>(Src);
952 (Src->getScalarSizeInBits() <= ST->
getELen()) &&
953 (Dst->getScalarSizeInBits() <= ST->
getELen());
963 assert(ISD &&
"Invalid opcode");
965 int PowDiff = (int)
Log2_32(Dst->getScalarSizeInBits()) -
966 (
int)
Log2_32(Src->getScalarSizeInBits());
970 const unsigned SrcEltSize = Src->getScalarSizeInBits();
971 if (SrcEltSize == 1) {
976 return getRISCVInstructionCost({RISCV::VMV_V_I, RISCV::VMERGE_VIM},
979 if ((PowDiff < 1) || (PowDiff > 3))
981 unsigned SExtOp[] = {RISCV::VSEXT_VF2, RISCV::VSEXT_VF4, RISCV::VSEXT_VF8};
982 unsigned ZExtOp[] = {RISCV::VZEXT_VF2, RISCV::VZEXT_VF4, RISCV::VZEXT_VF8};
985 return getRISCVInstructionCost(
Op, DstLT.second,
CostKind);
988 if (Dst->getScalarSizeInBits() == 1) {
994 return getRISCVInstructionCost({RISCV::VAND_VI, RISCV::VMSNE_VI},
1001 unsigned SrcEltSize = Src->getScalarSizeInBits();
1002 unsigned DstEltSize = Dst->getScalarSizeInBits();
1006 : RISCV::VFNCVT_F_F_W;
1008 for (; SrcEltSize != DstEltSize;) {
1014 (DstEltSize > SrcEltSize) ? DstEltSize >> 1 : DstEltSize << 1;
1023 if (Src->getScalarSizeInBits() == 1 || Dst->getScalarSizeInBits() == 1) {
1037 if (std::abs(PowDiff) <= 1)
1041 if (Src->isIntOrIntVectorTy())
1044 return std::abs(PowDiff);
1049unsigned RISCVTTIImpl::getEstimatedVLFor(
VectorType *Ty) {
1050 if (isa<ScalableVectorType>(Ty)) {
1056 return cast<FixedVectorType>(Ty)->getNumElements();
1075 if (IID == Intrinsic::umax || IID == Intrinsic::smin)
1081 if (IID == Intrinsic::maximum || IID == Intrinsic::minimum) {
1085 case Intrinsic::maximum:
1087 Opcodes = {RISCV::VFREDMAX_VS, RISCV::VFMV_F_S};
1089 Opcodes = {RISCV::VMFNE_VV, RISCV::VCPOP_M, RISCV::VFREDMAX_VS,
1104 case Intrinsic::minimum:
1106 Opcodes = {RISCV::VFREDMIN_VS, RISCV::VFMV_F_S};
1108 Opcodes = {RISCV::VMFNE_VV, RISCV::VCPOP_M, RISCV::VFREDMIN_VS,
1123 return ExtraCost + getRISCVInstructionCost(Opcodes, LT.second,
CostKind);
1132 case Intrinsic::smax:
1133 SplitOp = RISCV::VMAX_VV;
1134 Opcodes = {RISCV::VMV_S_X, RISCV::VREDMAX_VS, RISCV::VMV_X_S};
1136 case Intrinsic::smin:
1137 SplitOp = RISCV::VMIN_VV;
1138 Opcodes = {RISCV::VMV_S_X, RISCV::VREDMIN_VS, RISCV::VMV_X_S};
1140 case Intrinsic::umax:
1141 SplitOp = RISCV::VMAXU_VV;
1142 Opcodes = {RISCV::VMV_S_X, RISCV::VREDMAXU_VS, RISCV::VMV_X_S};
1144 case Intrinsic::umin:
1145 SplitOp = RISCV::VMINU_VV;
1146 Opcodes = {RISCV::VMV_S_X, RISCV::VREDMINU_VS, RISCV::VMV_X_S};
1148 case Intrinsic::maxnum:
1149 SplitOp = RISCV::VFMAX_VV;
1150 Opcodes = {RISCV::VFMV_S_F, RISCV::VFREDMAX_VS, RISCV::VFMV_F_S};
1152 case Intrinsic::minnum:
1153 SplitOp = RISCV::VFMIN_VV;
1154 Opcodes = {RISCV::VFMV_S_F, RISCV::VFREDMIN_VS, RISCV::VFMV_F_S};
1159 (LT.first > 1) ? (LT.first - 1) *
1160 getRISCVInstructionCost(SplitOp, LT.second,
CostKind)
1162 return SplitCost + getRISCVInstructionCost(Opcodes, LT.second,
CostKind);
1167 std::optional<FastMathFlags> FMF,
1177 assert(ISD &&
"Invalid opcode");
1193 Opcodes = {RISCV::VMNAND_MM, RISCV::VCPOP_M};
1194 return (LT.first - 1) +
1195 getRISCVInstructionCost(Opcodes, LT.second,
CostKind) +
1203 Opcodes = {RISCV::VCPOP_M};
1204 return (LT.first - 1) +
1205 getRISCVInstructionCost(Opcodes, LT.second,
CostKind) +
1214 for (
unsigned i = 0; i < LT.first.getValue(); i++)
1217 return getRISCVInstructionCost(Opcodes, LT.second,
CostKind);
1222 SplitOp = RISCV::VADD_VV;
1223 Opcodes = {RISCV::VMV_S_X, RISCV::VREDSUM_VS, RISCV::VMV_X_S};
1226 SplitOp = RISCV::VOR_VV;
1227 Opcodes = {RISCV::VMV_S_X, RISCV::VREDOR_VS, RISCV::VMV_X_S};
1230 SplitOp = RISCV::VXOR_VV;
1231 Opcodes = {RISCV::VMV_S_X, RISCV::VREDXOR_VS, RISCV::VMV_X_S};
1234 SplitOp = RISCV::VAND_VV;
1235 Opcodes = {RISCV::VMV_S_X, RISCV::VREDAND_VS, RISCV::VMV_X_S};
1238 SplitOp = RISCV::VFADD_VV;
1239 Opcodes = {RISCV::VFMV_S_F, RISCV::VFREDUSUM_VS, RISCV::VFMV_F_S};
1244 (LT.first > 1) ? (LT.first - 1) *
1245 getRISCVInstructionCost(SplitOp, LT.second,
CostKind)
1247 return SplitCost + getRISCVInstructionCost(Opcodes, LT.second,
CostKind);
1251 unsigned Opcode,
bool IsUnsigned,
Type *ResTy,
VectorType *ValTy,
1262 if (Opcode != Instruction::Add && Opcode != Instruction::FAdd)
1272 return (LT.first - 1) +
1280 if (!isa<VectorType>(Ty))
1292 return getConstantPoolLoadCost(Ty,
CostKind);
1304 if (VT == MVT::Other)
1309 if (Opcode == Instruction::Store && OpInfo.
isConstant())
1320 return Cost + BaseCost;
1343 if (Opcode == Instruction::Select && ValTy->
isVectorTy()) {
1350 getRISCVInstructionCost(
1351 {RISCV::VMANDN_MM, RISCV::VMAND_MM, RISCV::VMOR_MM},
1356 getRISCVInstructionCost(RISCV::VMERGE_VVM, LT.second,
CostKind);
1365 MVT InterimVT = LT.second.changeVectorElementType(MVT::i8);
1367 getRISCVInstructionCost({RISCV::VMV_V_X, RISCV::VMSNE_VI},
1369 LT.first * getRISCVInstructionCost(
1370 {RISCV::VMANDN_MM, RISCV::VMAND_MM, RISCV::VMOR_MM},
1377 return LT.first * getRISCVInstructionCost(
1378 {RISCV::VMV_V_X, RISCV::VMSNE_VI, RISCV::VMERGE_VVM},
1382 if ((Opcode == Instruction::ICmp) && ValTy->
isVectorTy() &&
1387 getRISCVInstructionCost(RISCV::VMSLT_VV, LT.second,
CostKind);
1390 if ((Opcode == Instruction::FCmp) && ValTy->
isVectorTy() &&
1395 return getRISCVInstructionCost(RISCV::VMXOR_MM, LT.second,
CostKind);
1414 return LT.first * getRISCVInstructionCost(
1415 {RISCV::VMFLT_VV, RISCV::VMFLT_VV, RISCV::VMOR_MM},
1423 getRISCVInstructionCost({RISCV::VMFLT_VV, RISCV::VMNAND_MM},
1433 getRISCVInstructionCost(RISCV::VMFLT_VV, LT.second,
CostKind);
1448 return Opcode == Instruction::PHI ? 0 : 1;
1459 if (Opcode != Instruction::ExtractElement &&
1460 Opcode != Instruction::InsertElement)
1467 if (!LT.second.isVector()) {
1468 auto *FixedVecTy = cast<FixedVectorType>(Val);
1476 Type *ElemTy = FixedVecTy->getElementType();
1477 auto NumElems = FixedVecTy->getNumElements();
1483 return Opcode == Instruction::ExtractElement
1484 ? StoreCost * NumElems + LoadCost
1485 : (StoreCost + LoadCost) * NumElems + StoreCost;
1489 if (LT.second.isScalableVector() && !LT.first.isValid())
1499 cast<VectorType>(Val)->getElementCount());
1500 if (Opcode == Instruction::ExtractElement) {
1506 return ExtendCost + ExtractCost;
1516 return ExtendCost + InsertCost + TruncCost;
1522 unsigned BaseCost = 1;
1524 unsigned SlideCost = Opcode == Instruction::InsertElement ? 2 : 1;
1529 if (LT.second.isFixedLengthVector()) {
1530 unsigned Width = LT.second.getVectorNumElements();
1537 else if (Opcode == Instruction::InsertElement)
1562 BaseCost = Opcode == Instruction::InsertElement ? 3 : 4;
1564 return BaseCost + SlideCost;
1590 if (!LT.second.isVector())
1595 auto getConstantMatCost =
1605 return getConstantPoolLoadCost(Ty,
CostKind);
1611 ConstantMatCost += getConstantMatCost(0, Op1Info);
1613 ConstantMatCost += getConstantMatCost(1, Op2Info);
1631 return ConstantMatCost + TLI->
getLMULCost(LT.second) * LT.first * 1;
1634 return ConstantMatCost +
1657 const auto *
GEP = dyn_cast<GetElementPtrInst>(V);
1660 if (
Info.isSameBase() && V !=
Base) {
1661 if (
GEP->hasAllConstantIndices())
1668 if (
Info.isUnitStride() &&
1674 GEP->getType()->getPointerAddressSpace()))
1677 {TTI::OK_AnyValue, TTI::OP_None},
1678 {TTI::OK_AnyValue, TTI::OP_None},
1696 if (ST->enableDefaultUnroll())
1706 if (L->getHeader()->getParent()->hasOptSize())
1710 L->getExitingBlocks(ExitingBlocks);
1712 <<
"Blocks: " << L->getNumBlocks() <<
"\n"
1713 <<
"Exit blocks: " << ExitingBlocks.
size() <<
"\n");
1717 if (ExitingBlocks.
size() > 2)
1722 if (L->getNumBlocks() > 4)
1732 for (
auto *BB : L->getBlocks()) {
1733 for (
auto &
I : *BB) {
1736 if (
I.getType()->isVectorTy())
1739 if (isa<CallInst>(
I) || isa<InvokeInst>(
I)) {
1798 return std::max<unsigned>(1U, RegWidth.
getFixedValue() / ElemWidth);
1813 auto *VTy = dyn_cast<VectorType>(DataTy);
1814 if (!VTy || VTy->isScalableTy())
1827 TM.getSubtargetImpl(*Caller)->getFeatureBits();
1829 TM.getSubtargetImpl(*Callee)->getFeatureBits();
1833 return (CallerBits & CalleeBits) == CalleeBits;
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
Analysis containing CSE Info
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
Cost tables and simple lookup functions.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
mir Rename Register Operands
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool isTypeLegal(Type *Ty)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Get intrinsic cost based on arguments.
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
std::optional< unsigned > getVScaleForTuning() const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
std::optional< unsigned > getMaxVScale() const
TTI::ShuffleKind improveShuffleKindFromMask(TTI::ShuffleKind Kind, ArrayRef< int > Mask, VectorType *Ty, int &Index, VectorType *&SubTy) const
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
unsigned getRegUsageForType(Type *Ty)
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
Try to calculate op costs for min/max reduction operations.
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt, const Instruction *CxtI=nullptr)
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind)
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=std::nullopt, const Instruction *CxtI=nullptr)
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
std::pair< InstructionCost, MVT > getTypeLegalizationCost(Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
bool isLegalAddImmediate(int64_t imm)
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr, int64_t ScalableOffset=0)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ FCMP_ULT
1 1 0 0 True if unordered or less than
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
bool isFPPredicate() const
bool isIntPredicate() const
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
Convenience struct for specifying and reasoning about fast-math flags.
Container class for subtarget features.
Class to represent fixed width SIMD vectors.
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
static InstructionCost getInvalid(CostType Val=0)
bool isCommutative() const LLVM_READONLY
Return true if the instruction is commutative:
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
const SmallVectorImpl< Type * > & getArgTypes() const
Type * getReturnType() const
Intrinsic::ID getID() const
A wrapper class for inspecting calls to intrinsic functions.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
This is an important class for using LLVM in a threaded context.
Represents a single loop in the control flow graph.
static MVT getFloatingPointVT(unsigned BitWidth)
unsigned getVectorMinNumElements() const
Given a vector type, return the minimum number of elements it contains.
uint64_t getScalarSizeInBits() const
MVT changeVectorElementType(MVT EltVT) const
Return a VT for a vector type whose attributes match ourselves with the exception of the element type...
unsigned getVectorNumElements() const
bool isVector() const
Return true if this is a vector value type.
MVT changeTypeToInteger()
Return the type converted to an equivalently sized integer or vector with integer element type.
bool bitsGT(MVT VT) const
Return true if this has more bits than VT.
bool isFixedLengthVector() const
static MVT getIntegerVT(unsigned BitWidth)
MVT getScalarType() const
If this is a vector, return the element type, otherwise return this.
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
bool hasVInstructionsF64() const
unsigned getRealMinVLen() const
bool useRVVForFixedLengthVectors() const
bool hasVInstructionsF16() const
bool hasVInstructions() const
unsigned getRealMaxVLen() const
bool hasVInstructionsF32() const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt, const Instruction *CxtI=nullptr)
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2)
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
bool isLegalMaskedLoadStore(Type *DataType, Align Alignment)
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=std::nullopt, const Instruction *CxtI=nullptr)
InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
std::optional< unsigned > getVScaleForTuning() const
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *ValTy, FastMathFlags FMF, TTI::TargetCostKind CostKind)
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
std::optional< unsigned > getMaxVScale() const
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const TTI::PointersChainInfo &Info, Type *AccessTy, TTI::TargetCostKind CostKind)
TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
bool shouldExpandReduction(const IntrinsicInst *II) const
InstructionCost getStoreImmCost(Type *VecTy, TTI::OperandValueInfo OpInfo, TTI::TargetCostKind CostKind)
Return the cost of materializing an immediate for a value operand of a store instruction.
bool isLegalMaskedCompressStore(Type *DataTy, Align Alignment)
bool isLegalStridedLoadStore(Type *DataType, Align Alignment)
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
unsigned getRegUsageForType(Type *Ty)
bool isLegalMaskedGather(Type *DataType, Align Alignment)
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpdInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
InstructionCost getVRGatherVVCost(MVT VT) const
Return the cost of a vrgather.vv instruction for the type VT.
bool canSplatOperand(Instruction *I, int Operand) const
Return true if the (vector) instruction I will be lowered to an instruction with a scalar splat opera...
InstructionCost getVRGatherVICost(MVT VT) const
Return the cost of a vrgather.vi (or vx) instruction for the type VT.
static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)
InstructionCost getLMULCost(MVT VT) const
Return the cost of LMUL for linear operations.
InstructionCost getVSlideVICost(MVT VT) const
Return the cost of a vslidedown.vi or vslideup.vi instruction for the type VT.
InstructionCost getVSlideVXCost(MVT VT) const
Return the cost of a vslidedown.vx or vslideup.vx instruction for the type VT.
bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace, const DataLayout &) const
Returns whether or not generating a interleaved load/store intrinsic for this type will be legal.
The main scalar evolution driver.
static bool isInterleaveMask(ArrayRef< int > Mask, unsigned Factor, unsigned NumInputElts, SmallVectorImpl< unsigned > &StartIndexes)
Return true if the mask interleaves one or more input vectors together.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
const TargetMachine & getTargetMachine() const
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not.
Primary interface to the complete machine description for the target machine.
static constexpr TypeSize getFixed(ScalarTy ExactSize)
static constexpr TypeSize getScalable(ScalarTy MinimumSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
static IntegerType * getInt1Ty(LLVMContext &C)
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Value * getOperand(unsigned i) const
LLVM Value Representation.
Base class of all SIMD vector types.
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
static VectorType * get(Type *ElementType, ElementCount EC)
This static method is the primary way to construct an VectorType.
Type * getElementType() const
constexpr ScalarTy getFixedValue() const
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ ADD
Simple integer binary arithmetic operators.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ FADD
Simple binary floating point operators.
@ SIGN_EXTEND
Conversion operators.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
int getIntMatCost(const APInt &Val, unsigned Size, const MCSubtargetInfo &STI, bool CompressionCost)
static constexpr unsigned RVVBitsPerBlock
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
const CostTblEntryT< CostType > * CostTableLookup(ArrayRef< CostTblEntryT< CostType > > Tbl, int ISD, MVT Ty)
Find in cost table.
bool getBooleanLoopAttribute(const Loop *TheLoop, StringRef Name)
Returns true if Name is applied to TheLoop and enabled.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
OutputIt transform(R &&Range, OutputIt d_first, UnaryFunction F)
Wrapper function around std::transform to apply a function to a range and store the result elsewhere.
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
llvm::SmallVector< int, 16 > createStrideMask(unsigned Start, unsigned Stride, unsigned VF)
Create a stride shuffle mask.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
constexpr int PoisonMaskElem
llvm::SmallVector< int, 16 > createInterleaveMask(unsigned VF, unsigned NumVecs)
Create an interleave shuffle mask.
DWARFExpression::Operation Op
bool equal(L &&LRange, R &&RRange)
Wrapper function around std::equal to detect if pair-wise elements between two ranges are the same.
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
This struct is a compact representation of a valid (non-zero power of two) alignment.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.