LLVM  14.0.0git
RISCVTargetTransformInfo.cpp
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1 //===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
14 using namespace llvm;
15 
16 #define DEBUG_TYPE "riscvtti"
17 
20  assert(Ty->isIntegerTy() &&
21  "getIntImmCost can only estimate cost of materialising integers");
22 
23  // We have a Zero register, so 0 is always free.
24  if (Imm == 0)
25  return TTI::TCC_Free;
26 
27  // Otherwise, we check how many instructions it will take to materialise.
28  const DataLayout &DL = getDataLayout();
30  getST()->getFeatureBits());
31 }
32 
33 InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
34  const APInt &Imm, Type *Ty,
36  Instruction *Inst) {
37  assert(Ty->isIntegerTy() &&
38  "getIntImmCost can only estimate cost of materialising integers");
39 
40  // We have a Zero register, so 0 is always free.
41  if (Imm == 0)
42  return TTI::TCC_Free;
43 
44  // Some instructions in RISC-V can take a 12-bit immediate. Some of these are
45  // commutative, in others the immediate comes from a specific argument index.
46  bool Takes12BitImm = false;
47  unsigned ImmArgIdx = ~0U;
48 
49  switch (Opcode) {
50  case Instruction::GetElementPtr:
51  // Never hoist any arguments to a GetElementPtr. CodeGenPrepare will
52  // split up large offsets in GEP into better parts than ConstantHoisting
53  // can.
54  return TTI::TCC_Free;
55  case Instruction::And:
56  // zext.h
57  if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb())
58  return TTI::TCC_Free;
59  // zext.w
60  if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZbb())
61  return TTI::TCC_Free;
63  case Instruction::Add:
64  case Instruction::Or:
65  case Instruction::Xor:
66  case Instruction::Mul:
67  Takes12BitImm = true;
68  break;
69  case Instruction::Sub:
70  case Instruction::Shl:
71  case Instruction::LShr:
72  case Instruction::AShr:
73  Takes12BitImm = true;
74  ImmArgIdx = 1;
75  break;
76  default:
77  break;
78  }
79 
80  if (Takes12BitImm) {
81  // Check immediate is the correct argument...
82  if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) {
83  // ... and fits into the 12-bit immediate.
84  if (Imm.getMinSignedBits() <= 64 &&
85  getTLI()->isLegalAddImmediate(Imm.getSExtValue())) {
86  return TTI::TCC_Free;
87  }
88  }
89 
90  // Otherwise, use the full materialisation cost.
91  return getIntImmCost(Imm, Ty, CostKind);
92  }
93 
94  // By default, prevent hoisting.
95  return TTI::TCC_Free;
96 }
97 
100  const APInt &Imm, Type *Ty,
102  // Prevent hoisting in unknown cases.
103  return TTI::TCC_Free;
104 }
105 
108  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
110 }
111 
113  // Currently, the ExpandReductions pass can't expand scalable-vector
114  // reductions, but we still request expansion as RVV doesn't support certain
115  // reductions and the SelectionDAG can't legalize them either.
116  switch (II->getIntrinsicID()) {
117  default:
118  return false;
119  // These reductions have no equivalent in RVV
120  case Intrinsic::vector_reduce_mul:
121  case Intrinsic::vector_reduce_fmul:
122  return true;
123  }
124 }
125 
127  // There is no assumption of the maximum vector length in V specification.
128  // We use the value specified by users as the maximum vector length.
129  // This function will use the assumed maximum vector length to get the
130  // maximum vscale for LoopVectorizer.
131  // If users do not specify the maximum vector length, we have no way to
132  // know whether the LoopVectorizer is safe to do or not.
133  // We only consider to use single vector register (LMUL = 1) to vectorize.
134  unsigned MaxVectorSizeInBits = ST->getMaxRVVVectorSizeInBits();
135  if (ST->hasStdExtV() && MaxVectorSizeInBits != 0)
136  return MaxVectorSizeInBits / RISCV::RVVBitsPerBlock;
137  return BaseT::getMaxVScale();
138 }
139 
141  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
142  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) {
144  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
145  Alignment, CostKind, I);
146 
147  if ((Opcode == Instruction::Load &&
148  !isLegalMaskedGather(DataTy, Align(Alignment))) ||
149  (Opcode == Instruction::Store &&
150  !isLegalMaskedScatter(DataTy, Align(Alignment))))
151  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
152  Alignment, CostKind, I);
153 
154  // FIXME: Only supporting fixed vectors for now.
155  if (!isa<FixedVectorType>(DataTy))
156  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
157  Alignment, CostKind, I);
158 
159  auto *VTy = cast<FixedVectorType>(DataTy);
160  unsigned NumLoads = VTy->getNumElements();
161  InstructionCost MemOpCost =
162  getMemoryOpCost(Opcode, VTy->getElementType(), Alignment, 0, CostKind, I);
163  return NumLoads * MemOpCost;
164 }
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::PSK_FastHardware
@ PSK_FastHardware
Definition: TargetTransformInfo.h:592
llvm::RISCVTTIImpl::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: RISCVTargetTransformInfo.cpp:126
llvm::RISCVMatInt::getIntMatCost
int getIntMatCost(const APInt &Val, unsigned Size, const FeatureBitset &ActiveFeatures, bool CompressionCost)
Definition: RISCVMatInt.cpp:283
llvm::BasicTTIImplBase< RISCVTTIImpl >::DL
const DataLayout & DL
Definition: TargetTransformInfoImpl.h:38
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm::RISCVTTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: RISCVTargetTransformInfo.cpp:112
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::RISCVTTIImpl::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:99
llvm::RISCVTTIImpl::getPopcntSupport
TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: RISCVTargetTransformInfo.cpp:107
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:592
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:52
llvm::DataLayout::getTypeSizeInBits
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:664
llvm::APInt::getMinSignedBits
unsigned getMinSignedBits() const
Get the minimum bit size for this signed APInt.
Definition: APInt.h:1442
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1463
llvm::RISCVTTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:138
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RISCVTTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:135
llvm::Optional< unsigned >
llvm::RISCVTTIImpl::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:18
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
RISCVMatInt.h
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
TargetLowering.h
llvm::Instruction
Definition: Instruction.h:45
llvm::RISCVSubtarget::hasStdExtZbb
bool hasStdExtZbb() const
Definition: RISCVSubtarget.h:109
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::Instruction::isCommutative
bool isCommutative() const LLVM_READONLY
Return true if the instruction is commutative:
Definition: Instruction.cpp:758
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:592
llvm::RISCVTTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Definition: RISCVTargetTransformInfo.cpp:140
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:190
llvm::RISCV::RVVBitsPerBlock
static constexpr unsigned RVVBitsPerBlock
Definition: RISCVISelLowering.h:626
llvm::RISCVSubtarget::getMaxRVVVectorSizeInBits
unsigned getMaxRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:113
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: BasicTTIImpl.h:667
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:262
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
llvm::BasicTTIImplBase< RISCVTTIImpl >::isLegalAddImmediate
bool isLegalAddImmediate(int64_t imm)
Definition: BasicTTIImpl.h:291
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:183
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::BasicTTIImplBase< RISCVTTIImpl >::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1167
TargetTransformInfo.h
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1116
BasicTTIImpl.h
RISCVTargetTransformInfo.h
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::RISCVTTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: RISCVTargetTransformInfo.cpp:33
llvm::RISCVSubtarget::hasStdExtV
bool hasStdExtV() const
Definition: RISCVSubtarget.h:118
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37