21#define DEBUG_TYPE "riscvtti"
24 "riscv-v-register-bit-width-lmul",
26 "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used "
27 "by autovectorized code. Fractional LMULs are not supported."),
33 "Result used for getMaximumVF query which is used exclusively by "
34 "SLP vectorizer. Defaults to 1 which disables SLP."),
46 std::tie(LMul, Fractional) =
48 Cost = Fractional ? 1 : LMul;
58 "getIntImmCost can only estimate cost of materialising integers");
67 getST()->getFeatureBits());
75 auto *BO = dyn_cast<BinaryOperator>(Inst->
getOperand(0));
76 if (!BO || !BO->hasOneUse())
79 if (BO->getOpcode() != Instruction::Shl)
82 if (!isa<ConstantInt>(BO->getOperand(1)))
85 unsigned ShAmt = cast<ConstantInt>(BO->getOperand(1))->getZExtValue();
90 if (ShAmt == Trailing)
102 "getIntImmCost can only estimate cost of materialising integers");
110 bool Takes12BitImm =
false;
111 unsigned ImmArgIdx = ~0U;
114 case Instruction::GetElementPtr:
119 case Instruction::And:
121 if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb())
124 if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZba())
127 if (ST->hasStdExtZbs() && (~Imm).isPowerOf2())
129 if (Inst &&
Idx == 1 && Imm.getBitWidth() <= ST->
getXLen() &&
132 Takes12BitImm =
true;
134 case Instruction::Add:
135 Takes12BitImm =
true;
137 case Instruction::Or:
138 case Instruction::Xor:
140 if (ST->hasStdExtZbs() && Imm.isPowerOf2())
142 Takes12BitImm =
true;
144 case Instruction::Mul:
146 if (Imm.isPowerOf2() || Imm.isNegatedPowerOf2())
149 Takes12BitImm =
true;
151 case Instruction::Sub:
152 case Instruction::Shl:
153 case Instruction::LShr:
154 case Instruction::AShr:
155 Takes12BitImm =
true;
166 if (Imm.getSignificantBits() <= 64 &&
202 case Intrinsic::vector_reduce_mul:
203 case Intrinsic::vector_reduce_fmul:
259 return cast<VectorType>(
EVT(IndexVT).getTypeForEVT(
C));
275 if (isa<FixedVectorType>(Tp)) {
280 if (Mask.size() >= 2 && LT.second.isFixedLengthVector()) {
281 MVT EltTp = LT.second.getVectorElementType();
292 return 2 * LT.first * getLMULCost(LT.second);
294 if (Mask[0] == 0 || Mask[0] == 1) {
298 if (
equal(DeinterleaveMask, Mask))
299 return LT.first * getLMULCost(LT.second);
306 (LT.second.getScalarSizeInBits() != 8 ||
307 LT.second.getVectorNumElements() <= 256)) {
310 return IndexCost + getLMULCost(LT.second);
317 if (Mask.size() >= 2 && LT.second.isFixedLengthVector()) {
322 (LT.second.getScalarSizeInBits() != 8 ||
323 LT.second.getVectorNumElements() <= 256)) {
330 return 2 * IndexCost + 2 * getLMULCost(LT.second) + MaskCost;
349 return LT.first * getLMULCost(LT.second);
354 return LT.first * getLMULCost(LT.second);
361 return LT.first * 3 * getLMULCost(LT.second);
365 Instruction::InsertElement);
366 if (LT.second.getScalarSizeInBits() == 1) {
373 return LT.first * getLMULCost(LT.second) * 3;
384 return LT.first * getLMULCost(LT.second) * 6;
390 return LT.first * getLMULCost(LT.second);
397 return LT.first * getLMULCost(LT.second);
403 return 2 * LT.first * getLMULCost(LT.second);
419 unsigned LenCost = 3;
420 if (LT.second.isFixedLengthVector())
422 LenCost = isInt<5>(LT.second.getVectorNumElements() - 1) ? 0 : 1;
425 return LT.first * (LenCost + 6);
426 return LT.first * (LenCost + 3);
447 bool UseMaskForCond,
bool UseMaskForGaps) {
448 auto *FVTy = cast<FixedVectorType>(VecTy);
451 unsigned VF = FVTy->getNumElements() / Factor;
457 if (!UseMaskForCond && !UseMaskForGaps &&
458 Factor <= TLI->getMaxSupportedInterleaveFactor()) {
461 if (LT.second.isFixedLengthVector()) {
463 LT.second.getVectorNumElements());
471 return LT.first + LegalMemCost;
481 if (Opcode == Instruction::Load) {
483 for (
unsigned Index : Indices) {
508 UseMaskForCond, UseMaskForGaps);
510 assert(Opcode == Instruction::Store &&
"Opcode must be a store");
517 return MemCost + ShuffleCost;
521 unsigned Opcode,
Type *DataTy,
const Value *
Ptr,
bool VariableMask,
527 if ((Opcode == Instruction::Load &&
529 (Opcode == Instruction::Store &&
537 auto &VTy = *cast<VectorType>(DataTy);
540 {TTI::OK_AnyValue, TTI::OP_None},
I);
541 unsigned NumLoads = getEstimatedVLFor(&VTy);
542 return NumLoads * MemOpCost;
550 {Intrinsic::floor, MVT::v2f32, 9},
551 {Intrinsic::floor, MVT::v4f32, 9},
552 {Intrinsic::floor, MVT::v8f32, 9},
553 {Intrinsic::floor, MVT::v16f32, 9},
554 {Intrinsic::floor, MVT::nxv1f32, 9},
555 {Intrinsic::floor, MVT::nxv2f32, 9},
556 {Intrinsic::floor, MVT::nxv4f32, 9},
557 {Intrinsic::floor, MVT::nxv8f32, 9},
558 {Intrinsic::floor, MVT::nxv16f32, 9},
559 {Intrinsic::floor, MVT::v2f64, 9},
560 {Intrinsic::floor, MVT::v4f64, 9},
561 {Intrinsic::floor, MVT::v8f64, 9},
562 {Intrinsic::floor, MVT::v16f64, 9},
563 {Intrinsic::floor, MVT::nxv1f64, 9},
564 {Intrinsic::floor, MVT::nxv2f64, 9},
565 {Intrinsic::floor, MVT::nxv4f64, 9},
566 {Intrinsic::floor, MVT::nxv8f64, 9},
567 {Intrinsic::ceil, MVT::v2f32, 9},
568 {Intrinsic::ceil, MVT::v4f32, 9},
569 {Intrinsic::ceil, MVT::v8f32, 9},
570 {Intrinsic::ceil, MVT::v16f32, 9},
571 {Intrinsic::ceil, MVT::nxv1f32, 9},
572 {Intrinsic::ceil, MVT::nxv2f32, 9},
573 {Intrinsic::ceil, MVT::nxv4f32, 9},
574 {Intrinsic::ceil, MVT::nxv8f32, 9},
575 {Intrinsic::ceil, MVT::nxv16f32, 9},
576 {Intrinsic::ceil, MVT::v2f64, 9},
577 {Intrinsic::ceil, MVT::v4f64, 9},
578 {Intrinsic::ceil, MVT::v8f64, 9},
579 {Intrinsic::ceil, MVT::v16f64, 9},
580 {Intrinsic::ceil, MVT::nxv1f64, 9},
581 {Intrinsic::ceil, MVT::nxv2f64, 9},
582 {Intrinsic::ceil, MVT::nxv4f64, 9},
583 {Intrinsic::ceil, MVT::nxv8f64, 9},
584 {Intrinsic::trunc, MVT::v2f32, 7},
585 {Intrinsic::trunc, MVT::v4f32, 7},
586 {Intrinsic::trunc, MVT::v8f32, 7},
587 {Intrinsic::trunc, MVT::v16f32, 7},
588 {Intrinsic::trunc, MVT::nxv1f32, 7},
589 {Intrinsic::trunc, MVT::nxv2f32, 7},
590 {Intrinsic::trunc, MVT::nxv4f32, 7},
591 {Intrinsic::trunc, MVT::nxv8f32, 7},
592 {Intrinsic::trunc, MVT::nxv16f32, 7},
593 {Intrinsic::trunc, MVT::v2f64, 7},
594 {Intrinsic::trunc, MVT::v4f64, 7},
595 {Intrinsic::trunc, MVT::v8f64, 7},
596 {Intrinsic::trunc, MVT::v16f64, 7},
597 {Intrinsic::trunc, MVT::nxv1f64, 7},
598 {Intrinsic::trunc, MVT::nxv2f64, 7},
599 {Intrinsic::trunc, MVT::nxv4f64, 7},
600 {Intrinsic::trunc, MVT::nxv8f64, 7},
601 {Intrinsic::round, MVT::v2f32, 9},
602 {Intrinsic::round, MVT::v4f32, 9},
603 {Intrinsic::round, MVT::v8f32, 9},
604 {Intrinsic::round, MVT::v16f32, 9},
605 {Intrinsic::round, MVT::nxv1f32, 9},
606 {Intrinsic::round, MVT::nxv2f32, 9},
607 {Intrinsic::round, MVT::nxv4f32, 9},
608 {Intrinsic::round, MVT::nxv8f32, 9},
609 {Intrinsic::round, MVT::nxv16f32, 9},
610 {Intrinsic::round, MVT::v2f64, 9},
611 {Intrinsic::round, MVT::v4f64, 9},
612 {Intrinsic::round, MVT::v8f64, 9},
613 {Intrinsic::round, MVT::v16f64, 9},
614 {Intrinsic::round, MVT::nxv1f64, 9},
615 {Intrinsic::round, MVT::nxv2f64, 9},
616 {Intrinsic::round, MVT::nxv4f64, 9},
617 {Intrinsic::round, MVT::nxv8f64, 9},
618 {Intrinsic::roundeven, MVT::v2f32, 9},
619 {Intrinsic::roundeven, MVT::v4f32, 9},
620 {Intrinsic::roundeven, MVT::v8f32, 9},
621 {Intrinsic::roundeven, MVT::v16f32, 9},
622 {Intrinsic::roundeven, MVT::nxv1f32, 9},
623 {Intrinsic::roundeven, MVT::nxv2f32, 9},
624 {Intrinsic::roundeven, MVT::nxv4f32, 9},
625 {Intrinsic::roundeven, MVT::nxv8f32, 9},
626 {Intrinsic::roundeven, MVT::nxv16f32, 9},
627 {Intrinsic::roundeven, MVT::v2f64, 9},
628 {Intrinsic::roundeven, MVT::v4f64, 9},
629 {Intrinsic::roundeven, MVT::v8f64, 9},
630 {Intrinsic::roundeven, MVT::v16f64, 9},
631 {Intrinsic::roundeven, MVT::nxv1f64, 9},
632 {Intrinsic::roundeven, MVT::nxv2f64, 9},
633 {Intrinsic::roundeven, MVT::nxv4f64, 9},
634 {Intrinsic::roundeven, MVT::nxv8f64, 9},
635 {Intrinsic::rint, MVT::v2f32, 7},
636 {Intrinsic::rint, MVT::v4f32, 7},
637 {Intrinsic::rint, MVT::v8f32, 7},
638 {Intrinsic::rint, MVT::v16f32, 7},
639 {Intrinsic::rint, MVT::nxv1f32, 7},
640 {Intrinsic::rint, MVT::nxv2f32, 7},
641 {Intrinsic::rint, MVT::nxv4f32, 7},
642 {Intrinsic::rint, MVT::nxv8f32, 7},
643 {Intrinsic::rint, MVT::nxv16f32, 7},
644 {Intrinsic::rint, MVT::v2f64, 7},
645 {Intrinsic::rint, MVT::v4f64, 7},
646 {Intrinsic::rint, MVT::v8f64, 7},
647 {Intrinsic::rint, MVT::v16f64, 7},
648 {Intrinsic::rint, MVT::nxv1f64, 7},
649 {Intrinsic::rint, MVT::nxv2f64, 7},
650 {Intrinsic::rint, MVT::nxv4f64, 7},
651 {Intrinsic::rint, MVT::nxv8f64, 7},
652 {Intrinsic::nearbyint, MVT::v2f32, 9},
653 {Intrinsic::nearbyint, MVT::v4f32, 9},
654 {Intrinsic::nearbyint, MVT::v8f32, 9},
655 {Intrinsic::nearbyint, MVT::v16f32, 9},
656 {Intrinsic::nearbyint, MVT::nxv1f32, 9},
657 {Intrinsic::nearbyint, MVT::nxv2f32, 9},
658 {Intrinsic::nearbyint, MVT::nxv4f32, 9},
659 {Intrinsic::nearbyint, MVT::nxv8f32, 9},
660 {Intrinsic::nearbyint, MVT::nxv16f32, 9},
661 {Intrinsic::nearbyint, MVT::v2f64, 9},
662 {Intrinsic::nearbyint, MVT::v4f64, 9},
663 {Intrinsic::nearbyint, MVT::v8f64, 9},
664 {Intrinsic::nearbyint, MVT::v16f64, 9},
665 {Intrinsic::nearbyint, MVT::nxv1f64, 9},
666 {Intrinsic::nearbyint, MVT::nxv2f64, 9},
667 {Intrinsic::nearbyint, MVT::nxv4f64, 9},
668 {Intrinsic::nearbyint, MVT::nxv8f64, 9},
669 {Intrinsic::bswap, MVT::v2i16, 3},
670 {Intrinsic::bswap, MVT::v4i16, 3},
671 {Intrinsic::bswap, MVT::v8i16, 3},
672 {Intrinsic::bswap, MVT::v16i16, 3},
673 {Intrinsic::bswap, MVT::nxv1i16, 3},
674 {Intrinsic::bswap, MVT::nxv2i16, 3},
675 {Intrinsic::bswap, MVT::nxv4i16, 3},
676 {Intrinsic::bswap, MVT::nxv8i16, 3},
677 {Intrinsic::bswap, MVT::nxv16i16, 3},
678 {Intrinsic::bswap, MVT::v2i32, 12},
679 {Intrinsic::bswap, MVT::v4i32, 12},
680 {Intrinsic::bswap, MVT::v8i32, 12},
681 {Intrinsic::bswap, MVT::v16i32, 12},
682 {Intrinsic::bswap, MVT::nxv1i32, 12},
683 {Intrinsic::bswap, MVT::nxv2i32, 12},
684 {Intrinsic::bswap, MVT::nxv4i32, 12},
685 {Intrinsic::bswap, MVT::nxv8i32, 12},
686 {Intrinsic::bswap, MVT::nxv16i32, 12},
687 {Intrinsic::bswap, MVT::v2i64, 31},
688 {Intrinsic::bswap, MVT::v4i64, 31},
689 {Intrinsic::bswap, MVT::v8i64, 31},
690 {Intrinsic::bswap, MVT::v16i64, 31},
691 {Intrinsic::bswap, MVT::nxv1i64, 31},
692 {Intrinsic::bswap, MVT::nxv2i64, 31},
693 {Intrinsic::bswap, MVT::nxv4i64, 31},
694 {Intrinsic::bswap, MVT::nxv8i64, 31},
695 {Intrinsic::vp_bswap, MVT::v2i16, 3},
696 {Intrinsic::vp_bswap, MVT::v4i16, 3},
697 {Intrinsic::vp_bswap, MVT::v8i16, 3},
698 {Intrinsic::vp_bswap, MVT::v16i16, 3},
699 {Intrinsic::vp_bswap, MVT::nxv1i16, 3},
700 {Intrinsic::vp_bswap, MVT::nxv2i16, 3},
701 {Intrinsic::vp_bswap, MVT::nxv4i16, 3},
702 {Intrinsic::vp_bswap, MVT::nxv8i16, 3},
703 {Intrinsic::vp_bswap, MVT::nxv16i16, 3},
704 {Intrinsic::vp_bswap, MVT::v2i32, 12},
705 {Intrinsic::vp_bswap, MVT::v4i32, 12},
706 {Intrinsic::vp_bswap, MVT::v8i32, 12},
707 {Intrinsic::vp_bswap, MVT::v16i32, 12},
708 {Intrinsic::vp_bswap, MVT::nxv1i32, 12},
709 {Intrinsic::vp_bswap, MVT::nxv2i32, 12},
710 {Intrinsic::vp_bswap, MVT::nxv4i32, 12},
711 {Intrinsic::vp_bswap, MVT::nxv8i32, 12},
712 {Intrinsic::vp_bswap, MVT::nxv16i32, 12},
713 {Intrinsic::vp_bswap, MVT::v2i64, 31},
714 {Intrinsic::vp_bswap, MVT::v4i64, 31},
715 {Intrinsic::vp_bswap, MVT::v8i64, 31},
716 {Intrinsic::vp_bswap, MVT::v16i64, 31},
717 {Intrinsic::vp_bswap, MVT::nxv1i64, 31},
718 {Intrinsic::vp_bswap, MVT::nxv2i64, 31},
719 {Intrinsic::vp_bswap, MVT::nxv4i64, 31},
720 {Intrinsic::vp_bswap, MVT::nxv8i64, 31},
721 {Intrinsic::vp_fshl, MVT::v2i8, 7},
722 {Intrinsic::vp_fshl, MVT::v4i8, 7},
723 {Intrinsic::vp_fshl, MVT::v8i8, 7},
724 {Intrinsic::vp_fshl, MVT::v16i8, 7},
725 {Intrinsic::vp_fshl, MVT::nxv1i8, 7},
726 {Intrinsic::vp_fshl, MVT::nxv2i8, 7},
727 {Intrinsic::vp_fshl, MVT::nxv4i8, 7},
728 {Intrinsic::vp_fshl, MVT::nxv8i8, 7},
729 {Intrinsic::vp_fshl, MVT::nxv16i8, 7},
730 {Intrinsic::vp_fshl, MVT::nxv32i8, 7},
731 {Intrinsic::vp_fshl, MVT::nxv64i8, 7},
732 {Intrinsic::vp_fshl, MVT::v2i16, 7},
733 {Intrinsic::vp_fshl, MVT::v4i16, 7},
734 {Intrinsic::vp_fshl, MVT::v8i16, 7},
735 {Intrinsic::vp_fshl, MVT::v16i16, 7},
736 {Intrinsic::vp_fshl, MVT::nxv1i16, 7},
737 {Intrinsic::vp_fshl, MVT::nxv2i16, 7},
738 {Intrinsic::vp_fshl, MVT::nxv4i16, 7},
739 {Intrinsic::vp_fshl, MVT::nxv8i16, 7},
740 {Intrinsic::vp_fshl, MVT::nxv16i16, 7},
741 {Intrinsic::vp_fshl, MVT::nxv32i16, 7},
742 {Intrinsic::vp_fshl, MVT::v2i32, 7},
743 {Intrinsic::vp_fshl, MVT::v4i32, 7},
744 {Intrinsic::vp_fshl, MVT::v8i32, 7},
745 {Intrinsic::vp_fshl, MVT::v16i32, 7},
746 {Intrinsic::vp_fshl, MVT::nxv1i32, 7},
747 {Intrinsic::vp_fshl, MVT::nxv2i32, 7},
748 {Intrinsic::vp_fshl, MVT::nxv4i32, 7},
749 {Intrinsic::vp_fshl, MVT::nxv8i32, 7},
750 {Intrinsic::vp_fshl, MVT::nxv16i32, 7},
751 {Intrinsic::vp_fshl, MVT::v2i64, 7},
752 {Intrinsic::vp_fshl, MVT::v4i64, 7},
753 {Intrinsic::vp_fshl, MVT::v8i64, 7},
754 {Intrinsic::vp_fshl, MVT::v16i64, 7},
755 {Intrinsic::vp_fshl, MVT::nxv1i64, 7},
756 {Intrinsic::vp_fshl, MVT::nxv2i64, 7},
757 {Intrinsic::vp_fshl, MVT::nxv4i64, 7},
758 {Intrinsic::vp_fshl, MVT::nxv8i64, 7},
759 {Intrinsic::vp_fshr, MVT::v2i8, 7},
760 {Intrinsic::vp_fshr, MVT::v4i8, 7},
761 {Intrinsic::vp_fshr, MVT::v8i8, 7},
762 {Intrinsic::vp_fshr, MVT::v16i8, 7},
763 {Intrinsic::vp_fshr, MVT::nxv1i8, 7},
764 {Intrinsic::vp_fshr, MVT::nxv2i8, 7},
765 {Intrinsic::vp_fshr, MVT::nxv4i8, 7},
766 {Intrinsic::vp_fshr, MVT::nxv8i8, 7},
767 {Intrinsic::vp_fshr, MVT::nxv16i8, 7},
768 {Intrinsic::vp_fshr, MVT::nxv32i8, 7},
769 {Intrinsic::vp_fshr, MVT::nxv64i8, 7},
770 {Intrinsic::vp_fshr, MVT::v2i16, 7},
771 {Intrinsic::vp_fshr, MVT::v4i16, 7},
772 {Intrinsic::vp_fshr, MVT::v8i16, 7},
773 {Intrinsic::vp_fshr, MVT::v16i16, 7},
774 {Intrinsic::vp_fshr, MVT::nxv1i16, 7},
775 {Intrinsic::vp_fshr, MVT::nxv2i16, 7},
776 {Intrinsic::vp_fshr, MVT::nxv4i16, 7},
777 {Intrinsic::vp_fshr, MVT::nxv8i16, 7},
778 {Intrinsic::vp_fshr, MVT::nxv16i16, 7},
779 {Intrinsic::vp_fshr, MVT::nxv32i16, 7},
780 {Intrinsic::vp_fshr, MVT::v2i32, 7},
781 {Intrinsic::vp_fshr, MVT::v4i32, 7},
782 {Intrinsic::vp_fshr, MVT::v8i32, 7},
783 {Intrinsic::vp_fshr, MVT::v16i32, 7},
784 {Intrinsic::vp_fshr, MVT::nxv1i32, 7},
785 {Intrinsic::vp_fshr, MVT::nxv2i32, 7},
786 {Intrinsic::vp_fshr, MVT::nxv4i32, 7},
787 {Intrinsic::vp_fshr, MVT::nxv8i32, 7},
788 {Intrinsic::vp_fshr, MVT::nxv16i32, 7},
789 {Intrinsic::vp_fshr, MVT::v2i64, 7},
790 {Intrinsic::vp_fshr, MVT::v4i64, 7},
791 {Intrinsic::vp_fshr, MVT::v8i64, 7},
792 {Intrinsic::vp_fshr, MVT::v16i64, 7},
793 {Intrinsic::vp_fshr, MVT::nxv1i64, 7},
794 {Intrinsic::vp_fshr, MVT::nxv2i64, 7},
795 {Intrinsic::vp_fshr, MVT::nxv4i64, 7},
796 {Intrinsic::vp_fshr, MVT::nxv8i64, 7},
797 {Intrinsic::bitreverse, MVT::v2i8, 17},
798 {Intrinsic::bitreverse, MVT::v4i8, 17},
799 {Intrinsic::bitreverse, MVT::v8i8, 17},
800 {Intrinsic::bitreverse, MVT::v16i8, 17},
801 {Intrinsic::bitreverse, MVT::nxv1i8, 17},
802 {Intrinsic::bitreverse, MVT::nxv2i8, 17},
803 {Intrinsic::bitreverse, MVT::nxv4i8, 17},
804 {Intrinsic::bitreverse, MVT::nxv8i8, 17},
805 {Intrinsic::bitreverse, MVT::nxv16i8, 17},
806 {Intrinsic::bitreverse, MVT::v2i16, 24},
807 {Intrinsic::bitreverse, MVT::v4i16, 24},
808 {Intrinsic::bitreverse, MVT::v8i16, 24},
809 {Intrinsic::bitreverse, MVT::v16i16, 24},
810 {Intrinsic::bitreverse, MVT::nxv1i16, 24},
811 {Intrinsic::bitreverse, MVT::nxv2i16, 24},
812 {Intrinsic::bitreverse, MVT::nxv4i16, 24},
813 {Intrinsic::bitreverse, MVT::nxv8i16, 24},
814 {Intrinsic::bitreverse, MVT::nxv16i16, 24},
815 {Intrinsic::bitreverse, MVT::v2i32, 33},
816 {Intrinsic::bitreverse, MVT::v4i32, 33},
817 {Intrinsic::bitreverse, MVT::v8i32, 33},
818 {Intrinsic::bitreverse, MVT::v16i32, 33},
819 {Intrinsic::bitreverse, MVT::nxv1i32, 33},
820 {Intrinsic::bitreverse, MVT::nxv2i32, 33},
821 {Intrinsic::bitreverse, MVT::nxv4i32, 33},
822 {Intrinsic::bitreverse, MVT::nxv8i32, 33},
823 {Intrinsic::bitreverse, MVT::nxv16i32, 33},
824 {Intrinsic::bitreverse, MVT::v2i64, 52},
825 {Intrinsic::bitreverse, MVT::v4i64, 52},
826 {Intrinsic::bitreverse, MVT::v8i64, 52},
827 {Intrinsic::bitreverse, MVT::v16i64, 52},
828 {Intrinsic::bitreverse, MVT::nxv1i64, 52},
829 {Intrinsic::bitreverse, MVT::nxv2i64, 52},
830 {Intrinsic::bitreverse, MVT::nxv4i64, 52},
831 {Intrinsic::bitreverse, MVT::nxv8i64, 52},
832 {Intrinsic::vp_bitreverse, MVT::v2i8, 17},
833 {Intrinsic::vp_bitreverse, MVT::v4i8, 17},
834 {Intrinsic::vp_bitreverse, MVT::v8i8, 17},
835 {Intrinsic::vp_bitreverse, MVT::v16i8, 17},
836 {Intrinsic::vp_bitreverse, MVT::nxv1i8, 17},
837 {Intrinsic::vp_bitreverse, MVT::nxv2i8, 17},
838 {Intrinsic::vp_bitreverse, MVT::nxv4i8, 17},
839 {Intrinsic::vp_bitreverse, MVT::nxv8i8, 17},
840 {Intrinsic::vp_bitreverse, MVT::nxv16i8, 17},
841 {Intrinsic::vp_bitreverse, MVT::v2i16, 24},
842 {Intrinsic::vp_bitreverse, MVT::v4i16, 24},
843 {Intrinsic::vp_bitreverse, MVT::v8i16, 24},
844 {Intrinsic::vp_bitreverse, MVT::v16i16, 24},
845 {Intrinsic::vp_bitreverse, MVT::nxv1i16, 24},
846 {Intrinsic::vp_bitreverse, MVT::nxv2i16, 24},
847 {Intrinsic::vp_bitreverse, MVT::nxv4i16, 24},
848 {Intrinsic::vp_bitreverse, MVT::nxv8i16, 24},
849 {Intrinsic::vp_bitreverse, MVT::nxv16i16, 24},
850 {Intrinsic::vp_bitreverse, MVT::v2i32, 33},
851 {Intrinsic::vp_bitreverse, MVT::v4i32, 33},
852 {Intrinsic::vp_bitreverse, MVT::v8i32, 33},
853 {Intrinsic::vp_bitreverse, MVT::v16i32, 33},
854 {Intrinsic::vp_bitreverse, MVT::nxv1i32, 33},
855 {Intrinsic::vp_bitreverse, MVT::nxv2i32, 33},
856 {Intrinsic::vp_bitreverse, MVT::nxv4i32, 33},
857 {Intrinsic::vp_bitreverse, MVT::nxv8i32, 33},
858 {Intrinsic::vp_bitreverse, MVT::nxv16i32, 33},
859 {Intrinsic::vp_bitreverse, MVT::v2i64, 52},
860 {Intrinsic::vp_bitreverse, MVT::v4i64, 52},
861 {Intrinsic::vp_bitreverse, MVT::v8i64, 52},
862 {Intrinsic::vp_bitreverse, MVT::v16i64, 52},
863 {Intrinsic::vp_bitreverse, MVT::nxv1i64, 52},
864 {Intrinsic::vp_bitreverse, MVT::nxv2i64, 52},
865 {Intrinsic::vp_bitreverse, MVT::nxv4i64, 52},
866 {Intrinsic::vp_bitreverse, MVT::nxv8i64, 52},
867 {Intrinsic::ctpop, MVT::v2i8, 12},
868 {Intrinsic::ctpop, MVT::v4i8, 12},
869 {Intrinsic::ctpop, MVT::v8i8, 12},
870 {Intrinsic::ctpop, MVT::v16i8, 12},
871 {Intrinsic::ctpop, MVT::nxv1i8, 12},
872 {Intrinsic::ctpop, MVT::nxv2i8, 12},
873 {Intrinsic::ctpop, MVT::nxv4i8, 12},
874 {Intrinsic::ctpop, MVT::nxv8i8, 12},
875 {Intrinsic::ctpop, MVT::nxv16i8, 12},
876 {Intrinsic::ctpop, MVT::v2i16, 19},
877 {Intrinsic::ctpop, MVT::v4i16, 19},
878 {Intrinsic::ctpop, MVT::v8i16, 19},
879 {Intrinsic::ctpop, MVT::v16i16, 19},
880 {Intrinsic::ctpop, MVT::nxv1i16, 19},
881 {Intrinsic::ctpop, MVT::nxv2i16, 19},
882 {Intrinsic::ctpop, MVT::nxv4i16, 19},
883 {Intrinsic::ctpop, MVT::nxv8i16, 19},
884 {Intrinsic::ctpop, MVT::nxv16i16, 19},
885 {Intrinsic::ctpop, MVT::v2i32, 20},
886 {Intrinsic::ctpop, MVT::v4i32, 20},
887 {Intrinsic::ctpop, MVT::v8i32, 20},
888 {Intrinsic::ctpop, MVT::v16i32, 20},
889 {Intrinsic::ctpop, MVT::nxv1i32, 20},
890 {Intrinsic::ctpop, MVT::nxv2i32, 20},
891 {Intrinsic::ctpop, MVT::nxv4i32, 20},
892 {Intrinsic::ctpop, MVT::nxv8i32, 20},
893 {Intrinsic::ctpop, MVT::nxv16i32, 20},
894 {Intrinsic::ctpop, MVT::v2i64, 21},
895 {Intrinsic::ctpop, MVT::v4i64, 21},
896 {Intrinsic::ctpop, MVT::v8i64, 21},
897 {Intrinsic::ctpop, MVT::v16i64, 21},
898 {Intrinsic::ctpop, MVT::nxv1i64, 21},
899 {Intrinsic::ctpop, MVT::nxv2i64, 21},
900 {Intrinsic::ctpop, MVT::nxv4i64, 21},
901 {Intrinsic::ctpop, MVT::nxv8i64, 21},
902 {Intrinsic::vp_ctpop, MVT::v2i8, 12},
903 {Intrinsic::vp_ctpop, MVT::v4i8, 12},
904 {Intrinsic::vp_ctpop, MVT::v8i8, 12},
905 {Intrinsic::vp_ctpop, MVT::v16i8, 12},
906 {Intrinsic::vp_ctpop, MVT::nxv1i8, 12},
907 {Intrinsic::vp_ctpop, MVT::nxv2i8, 12},
908 {Intrinsic::vp_ctpop, MVT::nxv4i8, 12},
909 {Intrinsic::vp_ctpop, MVT::nxv8i8, 12},
910 {Intrinsic::vp_ctpop, MVT::nxv16i8, 12},
911 {Intrinsic::vp_ctpop, MVT::v2i16, 19},
912 {Intrinsic::vp_ctpop, MVT::v4i16, 19},
913 {Intrinsic::vp_ctpop, MVT::v8i16, 19},
914 {Intrinsic::vp_ctpop, MVT::v16i16, 19},
915 {Intrinsic::vp_ctpop, MVT::nxv1i16, 19},
916 {Intrinsic::vp_ctpop, MVT::nxv2i16, 19},
917 {Intrinsic::vp_ctpop, MVT::nxv4i16, 19},
918 {Intrinsic::vp_ctpop, MVT::nxv8i16, 19},
919 {Intrinsic::vp_ctpop, MVT::nxv16i16, 19},
920 {Intrinsic::vp_ctpop, MVT::v2i32, 20},
921 {Intrinsic::vp_ctpop, MVT::v4i32, 20},
922 {Intrinsic::vp_ctpop, MVT::v8i32, 20},
923 {Intrinsic::vp_ctpop, MVT::v16i32, 20},
924 {Intrinsic::vp_ctpop, MVT::nxv1i32, 20},
925 {Intrinsic::vp_ctpop, MVT::nxv2i32, 20},
926 {Intrinsic::vp_ctpop, MVT::nxv4i32, 20},
927 {Intrinsic::vp_ctpop, MVT::nxv8i32, 20},
928 {Intrinsic::vp_ctpop, MVT::nxv16i32, 20},
929 {Intrinsic::vp_ctpop, MVT::v2i64, 21},
930 {Intrinsic::vp_ctpop, MVT::v4i64, 21},
931 {Intrinsic::vp_ctpop, MVT::v8i64, 21},
932 {Intrinsic::vp_ctpop, MVT::v16i64, 21},
933 {Intrinsic::vp_ctpop, MVT::nxv1i64, 21},
934 {Intrinsic::vp_ctpop, MVT::nxv2i64, 21},
935 {Intrinsic::vp_ctpop, MVT::nxv4i64, 21},
936 {Intrinsic::vp_ctpop, MVT::nxv8i64, 21},
937 {Intrinsic::vp_ctlz, MVT::v2i8, 19},
938 {Intrinsic::vp_ctlz, MVT::v4i8, 19},
939 {Intrinsic::vp_ctlz, MVT::v8i8, 19},
940 {Intrinsic::vp_ctlz, MVT::v16i8, 19},
941 {Intrinsic::vp_ctlz, MVT::nxv1i8, 19},
942 {Intrinsic::vp_ctlz, MVT::nxv2i8, 19},
943 {Intrinsic::vp_ctlz, MVT::nxv4i8, 19},
944 {Intrinsic::vp_ctlz, MVT::nxv8i8, 19},
945 {Intrinsic::vp_ctlz, MVT::nxv16i8, 19},
946 {Intrinsic::vp_ctlz, MVT::nxv32i8, 19},
947 {Intrinsic::vp_ctlz, MVT::nxv64i8, 19},
948 {Intrinsic::vp_ctlz, MVT::v2i16, 28},
949 {Intrinsic::vp_ctlz, MVT::v4i16, 28},
950 {Intrinsic::vp_ctlz, MVT::v8i16, 28},
951 {Intrinsic::vp_ctlz, MVT::v16i16, 28},
952 {Intrinsic::vp_ctlz, MVT::nxv1i16, 28},
953 {Intrinsic::vp_ctlz, MVT::nxv2i16, 28},
954 {Intrinsic::vp_ctlz, MVT::nxv4i16, 28},
955 {Intrinsic::vp_ctlz, MVT::nxv8i16, 28},
956 {Intrinsic::vp_ctlz, MVT::nxv16i16, 28},
957 {Intrinsic::vp_ctlz, MVT::nxv32i16, 28},
958 {Intrinsic::vp_ctlz, MVT::v2i32, 31},
959 {Intrinsic::vp_ctlz, MVT::v4i32, 31},
960 {Intrinsic::vp_ctlz, MVT::v8i32, 31},
961 {Intrinsic::vp_ctlz, MVT::v16i32, 31},
962 {Intrinsic::vp_ctlz, MVT::nxv1i32, 31},
963 {Intrinsic::vp_ctlz, MVT::nxv2i32, 31},
964 {Intrinsic::vp_ctlz, MVT::nxv4i32, 31},
965 {Intrinsic::vp_ctlz, MVT::nxv8i32, 31},
966 {Intrinsic::vp_ctlz, MVT::nxv16i32, 31},
967 {Intrinsic::vp_ctlz, MVT::v2i64, 35},
968 {Intrinsic::vp_ctlz, MVT::v4i64, 35},
969 {Intrinsic::vp_ctlz, MVT::v8i64, 35},
970 {Intrinsic::vp_ctlz, MVT::v16i64, 35},
971 {Intrinsic::vp_ctlz, MVT::nxv1i64, 35},
972 {Intrinsic::vp_ctlz, MVT::nxv2i64, 35},
973 {Intrinsic::vp_ctlz, MVT::nxv4i64, 35},
974 {Intrinsic::vp_ctlz, MVT::nxv8i64, 35},
975 {Intrinsic::vp_cttz, MVT::v2i8, 16},
976 {Intrinsic::vp_cttz, MVT::v4i8, 16},
977 {Intrinsic::vp_cttz, MVT::v8i8, 16},
978 {Intrinsic::vp_cttz, MVT::v16i8, 16},
979 {Intrinsic::vp_cttz, MVT::nxv1i8, 16},
980 {Intrinsic::vp_cttz, MVT::nxv2i8, 16},
981 {Intrinsic::vp_cttz, MVT::nxv4i8, 16},
982 {Intrinsic::vp_cttz, MVT::nxv8i8, 16},
983 {Intrinsic::vp_cttz, MVT::nxv16i8, 16},
984 {Intrinsic::vp_cttz, MVT::nxv32i8, 16},
985 {Intrinsic::vp_cttz, MVT::nxv64i8, 16},
986 {Intrinsic::vp_cttz, MVT::v2i16, 23},
987 {Intrinsic::vp_cttz, MVT::v4i16, 23},
988 {Intrinsic::vp_cttz, MVT::v8i16, 23},
989 {Intrinsic::vp_cttz, MVT::v16i16, 23},
990 {Intrinsic::vp_cttz, MVT::nxv1i16, 23},
991 {Intrinsic::vp_cttz, MVT::nxv2i16, 23},
992 {Intrinsic::vp_cttz, MVT::nxv4i16, 23},
993 {Intrinsic::vp_cttz, MVT::nxv8i16, 23},
994 {Intrinsic::vp_cttz, MVT::nxv16i16, 23},
995 {Intrinsic::vp_cttz, MVT::nxv32i16, 23},
996 {Intrinsic::vp_cttz, MVT::v2i32, 24},
997 {Intrinsic::vp_cttz, MVT::v4i32, 24},
998 {Intrinsic::vp_cttz, MVT::v8i32, 24},
999 {Intrinsic::vp_cttz, MVT::v16i32, 24},
1000 {Intrinsic::vp_cttz, MVT::nxv1i32, 24},
1001 {Intrinsic::vp_cttz, MVT::nxv2i32, 24},
1002 {Intrinsic::vp_cttz, MVT::nxv4i32, 24},
1003 {Intrinsic::vp_cttz, MVT::nxv8i32, 24},
1004 {Intrinsic::vp_cttz, MVT::nxv16i32, 24},
1005 {Intrinsic::vp_cttz, MVT::v2i64, 25},
1006 {Intrinsic::vp_cttz, MVT::v4i64, 25},
1007 {Intrinsic::vp_cttz, MVT::v8i64, 25},
1008 {Intrinsic::vp_cttz, MVT::v16i64, 25},
1009 {Intrinsic::vp_cttz, MVT::nxv1i64, 25},
1010 {Intrinsic::vp_cttz, MVT::nxv2i64, 25},
1011 {Intrinsic::vp_cttz, MVT::nxv4i64, 25},
1012 {Intrinsic::vp_cttz, MVT::nxv8i64, 25},
1017#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \
1018 case Intrinsic::VPID: \
1020#include "llvm/IR/VPIntrinsics.def"
1021#undef HELPER_MAP_VPID_TO_VPSD
1030 switch (ICA.
getID()) {
1031 case Intrinsic::ceil:
1032 case Intrinsic::floor:
1033 case Intrinsic::trunc:
1034 case Intrinsic::rint:
1035 case Intrinsic::round:
1036 case Intrinsic::roundeven: {
1040 return LT.first * 8;
1043 case Intrinsic::umin:
1044 case Intrinsic::umax:
1045 case Intrinsic::smin:
1046 case Intrinsic::smax: {
1049 (LT.second.isScalarInteger() && ST->hasStdExtZbb()))
1053 case Intrinsic::sadd_sat:
1054 case Intrinsic::ssub_sat:
1055 case Intrinsic::uadd_sat:
1056 case Intrinsic::usub_sat:
1057 case Intrinsic::fabs:
1058 case Intrinsic::sqrt: {
1064 case Intrinsic::abs: {
1069 return LT.first * 2;
1074 case Intrinsic::experimental_stepvector: {
1077 return Cost + (LT.first - 1);
1079 case Intrinsic::vp_rint: {
1084 return Cost * LT.first;
1087 case Intrinsic::vp_nearbyint: {
1092 return Cost * LT.first;
1095 case Intrinsic::vp_ceil:
1096 case Intrinsic::vp_floor:
1097 case Intrinsic::vp_round:
1098 case Intrinsic::vp_roundeven:
1099 case Intrinsic::vp_roundtozero: {
1106 return Cost * LT.first;
1114 ICA.
getID(), LT.second))
1115 return LT.first * Entry->Cost;
1126 if (isa<VectorType>(Dst) && isa<VectorType>(Src)) {
1132 if (Src->getScalarSizeInBits() > ST->
getELEN() ||
1133 Dst->getScalarSizeInBits() > ST->
getELEN())
1137 assert(ISD &&
"Invalid opcode");
1140 int PowDiff = (int)
Log2_32(Dst->getScalarSizeInBits()) -
1141 (
int)
Log2_32(Src->getScalarSizeInBits());
1145 if (Src->getScalarSizeInBits() == 1) {
1154 if (Dst->getScalarSizeInBits() == 1) {
1166 return std::abs(PowDiff);
1171 if (Src->getScalarSizeInBits() == 1 || Dst->getScalarSizeInBits() == 1) {
1185 if (std::abs(PowDiff) <= 1)
1189 if (Src->isIntOrIntVectorTy())
1192 return std::abs(PowDiff);
1198unsigned RISCVTTIImpl::getEstimatedVLFor(
VectorType *Ty) {
1199 if (isa<ScalableVectorType>(Ty)) {
1205 return cast<FixedVectorType>(Ty)->getNumElements();
1223 return (LT.first - 1) + 3;
1229 return (LT.first - 1) + BaseCost;
1231 unsigned VL = getEstimatedVLFor(Ty);
1237 std::optional<FastMathFlags> FMF,
1247 assert(ISD &&
"Invalid opcode");
1256 return (LT.first - 1) + (ISD ==
ISD::AND ? 3 : 2);
1262 return (LT.first - 1) + BaseCost;
1264 unsigned VL = getEstimatedVLFor(Ty);
1266 return (LT.first - 1) + BaseCost + VL;
1271 unsigned Opcode,
bool IsUnsigned,
Type *ResTy,
VectorType *ValTy,
1282 if (Opcode != Instruction::Add && Opcode != Instruction::FAdd)
1292 return (LT.first - 1) +
1300 if (!isa<VectorType>(Ty))
1312 return getConstantPoolLoadCost(Ty,
CostKind);
1324 if (VT == MVT::Other)
1329 if (Opcode == Instruction::Store && OpInfo.
isConstant())
1338 LT.second.isVector())
1339 BaseCost *= getLMULCost(LT.second);
1340 return Cost + BaseCost;
1362 if (Opcode == Instruction::Select && ValTy->
isVectorTy()) {
1369 return LT.first * 3;
1372 return LT.first * 1;
1381 return LT.first * 5;
1387 return LT.first * 3;
1390 if ((Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) &&
1396 return LT.first * 1;
1415 return LT.first * 1;
1433 if (Opcode != Instruction::ExtractElement &&
1434 Opcode != Instruction::InsertElement)
1441 if (!LT.second.isVector())
1445 if (LT.second.isScalableVector() && !LT.first.isValid())
1453 unsigned BaseCost = 1;
1455 unsigned SlideCost = Opcode == Instruction::InsertElement ? 2 : 1;
1460 if (LT.second.isFixedLengthVector()) {
1461 unsigned Width = LT.second.getVectorNumElements();
1468 else if (Opcode == Instruction::InsertElement)
1494 BaseCost = Opcode == Instruction::InsertElement ? 5 : 3;
1517 BaseCost = Opcode == Instruction::InsertElement ? 3 : 4;
1519 return BaseCost + SlideCost;
1545 if (!LT.second.isVector())
1550 auto getConstantMatCost =
1560 return getConstantPoolLoadCost(Ty,
CostKind);
1566 ConstantMatCost += getConstantMatCost(0, Op1Info);
1568 ConstantMatCost += getConstantMatCost(1, Op2Info);
1586 return ConstantMatCost + getLMULCost(LT.second) * LT.first * 1;
1589 return ConstantMatCost +
1612 const auto *
GEP = dyn_cast<GetElementPtrInst>(V);
1615 if (
Info.isSameBase() && V !=
Base) {
1616 if (
GEP->hasAllConstantIndices())
1623 if (
Info.isUnitStride() &&
1629 GEP->getType()->getPointerAddressSpace()))
1632 {TTI::OK_AnyValue, TTI::OP_None},
1633 {TTI::OK_AnyValue, TTI::OP_None},
1651 if (ST->enableDefaultUnroll())
1661 if (L->getHeader()->getParent()->hasOptSize())
1665 L->getExitingBlocks(ExitingBlocks);
1667 <<
"Blocks: " << L->getNumBlocks() <<
"\n"
1668 <<
"Exit blocks: " << ExitingBlocks.
size() <<
"\n");
1672 if (ExitingBlocks.
size() > 2)
1677 if (L->getNumBlocks() > 4)
1687 for (
auto *BB : L->getBlocks()) {
1688 for (
auto &
I : *BB) {
1691 if (
I.getType()->isVectorTy())
1694 if (isa<CallInst>(
I) || isa<InvokeInst>(
I)) {
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
Analysis containing CSE Info
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
Cost tables and simple lookup functions.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
mir Rename Register Operands
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool isTypeLegal(Type *Ty)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Get intrinsic cost based on arguments.
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
std::optional< unsigned > getVScaleForTuning() const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
std::optional< unsigned > getMaxVScale() const
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
unsigned getRegUsageForType(Type *Ty)
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, FastMathFlags FMF, TTI::TargetCostKind CostKind)
Try to calculate op costs for min/max reduction operations.
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr)
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
std::pair< InstructionCost, MVT > getTypeLegalizationCost(Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
TTI::ShuffleKind improveShuffleKindFromMask(TTI::ShuffleKind Kind, ArrayRef< int > Mask) const
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
bool isLegalAddImmediate(int64_t imm)
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
bool isIntPredicate() const
A parsed version of the target data layout string in and methods for querying it.
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Convenience struct for specifying and reasoning about fast-math flags.
Class to represent fixed width SIMD vectors.
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
static InstructionCost getInvalid(CostType Val=0)
bool isCommutative() const LLVM_READONLY
Return true if the instruction is commutative:
Type * getReturnType() const
Intrinsic::ID getID() const
A wrapper class for inspecting calls to intrinsic functions.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
This is an important class for using LLVM in a threaded context.
Represents a single loop in the control flow graph.
uint64_t getScalarSizeInBits() const
MVT changeVectorElementType(MVT EltVT) const
Return a VT for a vector type whose attributes match ourselves with the exception of the element type...
unsigned getVectorNumElements() const
bool isVector() const
Return true if this is a vector value type.
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
MVT changeTypeToInteger()
Return the type converted to an equivalently sized integer or vector with integer element type.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
bool bitsGT(MVT VT) const
Return true if this has more bits than VT.
MVT getScalarType() const
If this is a vector, return the element type, otherwise return this.
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
bool hasVInstructionsF64() const
unsigned getRealMinVLen() const
bool useRVVForFixedLengthVectors() const
bool hasVInstructionsF16() const
bool hasVInstructions() const
unsigned getRealMaxVLen() const
bool hasVInstructionsF32() const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2)
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
bool isLegalMaskedLoadStore(Type *DataType, Align Alignment)
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
std::optional< unsigned > getVScaleForTuning() const
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *ValTy, FastMathFlags FMF, TTI::TargetCostKind CostKind)
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
std::optional< unsigned > getMaxVScale() const
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const TTI::PointersChainInfo &Info, Type *AccessTy, TTI::TargetCostKind CostKind)
TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, FastMathFlags FMF, TTI::TargetCostKind CostKind)
bool shouldExpandReduction(const IntrinsicInst *II) const
InstructionCost getStoreImmCost(Type *VecTy, TTI::OperandValueInfo OpInfo, TTI::TargetCostKind CostKind)
Return the cost of materializing an immediate for a value operand of a store instruction.
unsigned getRegUsageForType(Type *Ty)
bool isLegalMaskedGather(Type *DataType, Align Alignment)
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpdInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
bool isLegalInterleavedAccessType(FixedVectorType *, unsigned Factor, const DataLayout &) const
Returns whether or not generating a fixed length interleaved load/store intrinsic for this type will ...
bool canSplatOperand(Instruction *I, int Operand) const
Return true if the (vector) instruction I will be lowered to an instruction with a scalar splat opera...
static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)
static RISCVII::VLMUL getLMUL(MVT VT)
The main scalar evolution driver.
static bool isInterleaveMask(ArrayRef< int > Mask, unsigned Factor, unsigned NumInputElts, SmallVectorImpl< unsigned > &StartIndexes)
Return true if the mask interleaves one or more input vectors together.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not.
static constexpr TypeSize getFixed(ScalarTy ExactSize)
static constexpr TypeSize getScalable(ScalarTy MinimumSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
static IntegerType * getInt1Ty(LLVMContext &C)
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
bool isIntegerTy() const
True if this is an instance of IntegerType.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Value * getOperand(unsigned i) const
LLVM Value Representation.
Base class of all SIMD vector types.
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
static VectorType * get(Type *ElementType, ElementCount EC)
This static method is the primary way to construct an VectorType.
Type * getElementType() const
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ ADD
Simple integer binary arithmetic operators.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ FADD
Simple binary floating point operators.
@ SIGN_EXTEND
Conversion operators.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
int getIntMatCost(const APInt &Val, unsigned Size, const FeatureBitset &ActiveFeatures, bool CompressionCost)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
static constexpr unsigned RVVBitsPerBlock
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
const CostTblEntryT< CostType > * CostTableLookup(ArrayRef< CostTblEntryT< CostType > > Tbl, int ISD, MVT Ty)
Find in cost table.
bool getBooleanLoopAttribute(const Loop *TheLoop, StringRef Name)
Returns true if Name is applied to TheLoop and enabled.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
llvm::SmallVector< int, 16 > createStrideMask(unsigned Start, unsigned Stride, unsigned VF)
Create a stride shuffle mask.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
llvm::SmallVector< int, 16 > createInterleaveMask(unsigned VF, unsigned NumVecs)
Create an interleave shuffle mask.
bool equal(L &&LRange, R &&RRange)
Wrapper function around std::equal to detect if pair-wise elements between two ranges are the same.
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
This struct is a compact representation of a valid (non-zero power of two) alignment.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.