LLVM  15.0.0git
RISCVTargetTransformInfo.cpp
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1 //===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
14 #include <cmath>
15 using namespace llvm;
16 
17 #define DEBUG_TYPE "riscvtti"
18 
20  "riscv-v-register-bit-width-lmul",
21  cl::desc(
22  "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used "
23  "by autovectorized code. Fractional LMULs are not supported."),
24  cl::init(1), cl::Hidden);
25 
28  assert(Ty->isIntegerTy() &&
29  "getIntImmCost can only estimate cost of materialising integers");
30 
31  // We have a Zero register, so 0 is always free.
32  if (Imm == 0)
33  return TTI::TCC_Free;
34 
35  // Otherwise, we check how many instructions it will take to materialise.
36  const DataLayout &DL = getDataLayout();
38  getST()->getFeatureBits());
39 }
40 
41 InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
42  const APInt &Imm, Type *Ty,
44  Instruction *Inst) {
45  assert(Ty->isIntegerTy() &&
46  "getIntImmCost can only estimate cost of materialising integers");
47 
48  // We have a Zero register, so 0 is always free.
49  if (Imm == 0)
50  return TTI::TCC_Free;
51 
52  // Some instructions in RISC-V can take a 12-bit immediate. Some of these are
53  // commutative, in others the immediate comes from a specific argument index.
54  bool Takes12BitImm = false;
55  unsigned ImmArgIdx = ~0U;
56 
57  switch (Opcode) {
58  case Instruction::GetElementPtr:
59  // Never hoist any arguments to a GetElementPtr. CodeGenPrepare will
60  // split up large offsets in GEP into better parts than ConstantHoisting
61  // can.
62  return TTI::TCC_Free;
63  case Instruction::And:
64  // zext.h
65  if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb())
66  return TTI::TCC_Free;
67  // zext.w
68  if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZbb())
69  return TTI::TCC_Free;
71  case Instruction::Add:
72  case Instruction::Or:
73  case Instruction::Xor:
74  case Instruction::Mul:
75  Takes12BitImm = true;
76  break;
77  case Instruction::Sub:
78  case Instruction::Shl:
79  case Instruction::LShr:
80  case Instruction::AShr:
81  Takes12BitImm = true;
82  ImmArgIdx = 1;
83  break;
84  default:
85  break;
86  }
87 
88  if (Takes12BitImm) {
89  // Check immediate is the correct argument...
90  if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) {
91  // ... and fits into the 12-bit immediate.
92  if (Imm.getMinSignedBits() <= 64 &&
93  getTLI()->isLegalAddImmediate(Imm.getSExtValue())) {
94  return TTI::TCC_Free;
95  }
96  }
97 
98  // Otherwise, use the full materialisation cost.
99  return getIntImmCost(Imm, Ty, CostKind);
100  }
101 
102  // By default, prevent hoisting.
103  return TTI::TCC_Free;
104 }
105 
108  const APInt &Imm, Type *Ty,
110  // Prevent hoisting in unknown cases.
111  return TTI::TCC_Free;
112 }
113 
116  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
118 }
119 
121  // Currently, the ExpandReductions pass can't expand scalable-vector
122  // reductions, but we still request expansion as RVV doesn't support certain
123  // reductions and the SelectionDAG can't legalize them either.
124  switch (II->getIntrinsicID()) {
125  default:
126  return false;
127  // These reductions have no equivalent in RVV
128  case Intrinsic::vector_reduce_mul:
129  case Intrinsic::vector_reduce_fmul:
130  return true;
131  }
132 }
133 
135  if (ST->hasVInstructions())
136  return ST->getRealMaxVLen() / RISCV::RVVBitsPerBlock;
137  return BaseT::getMaxVScale();
138 }
139 
141  if (ST->hasVInstructions())
142  return ST->getRealMinVLen() / RISCV::RVVBitsPerBlock;
143  return BaseT::getVScaleForTuning();
144 }
145 
146 TypeSize
148  unsigned LMUL = PowerOf2Floor(
149  std::max<unsigned>(std::min<unsigned>(RVVRegisterWidthLMUL, 8), 1));
150  switch (K) {
152  return TypeSize::getFixed(ST->getXLen());
154  return TypeSize::getFixed(
155  ST->useRVVForFixedLengthVectors() ? LMUL * ST->getRealMinVLen() : 0);
157  return TypeSize::getScalable(
159  }
160 
161  llvm_unreachable("Unsupported register kind");
162 }
163 
165  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
166 
167  unsigned Cost = 2; // vslidedown+vslideup.
168  // TODO: LMUL should increase cost.
169  // TODO: Multiplying by LT.first implies this legalizes into multiple copies
170  // of similar code, but I think we expand through memory.
171  return Cost * LT.first;
172 }
173 
176  int Index, VectorType *SubTp,
178  if (isa<ScalableVectorType>(Tp)) {
179  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
180  switch (Kind) {
181  default:
182  // Fallthrough to generic handling.
183  // TODO: Most of these cases will return getInvalid in generic code, and
184  // must be implemented here.
185  break;
186  case TTI::SK_Broadcast: {
187  return LT.first * 1;
188  }
189  case TTI::SK_Splice:
190  return getSpliceCost(Tp, Index);
191  case TTI::SK_Reverse:
192  // Most of the cost here is producing the vrgather index register
193  // Example sequence:
194  // csrr a0, vlenb
195  // srli a0, a0, 3
196  // addi a0, a0, -1
197  // vsetvli a1, zero, e8, mf8, ta, mu (ignored)
198  // vid.v v9
199  // vrsub.vx v10, v9, a0
200  // vrgather.vv v9, v8, v10
201  return LT.first * 6;
202  }
203  }
204 
205  return BaseT::getShuffleCost(Kind, Tp, Mask, Index, SubTp);
206 }
207 
209 RISCVTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
210  unsigned AddressSpace,
212  if (!isa<ScalableVectorType>(Src))
213  return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
214  CostKind);
215 
216  return getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind);
217 }
218 
220  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
221  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) {
223  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
224  Alignment, CostKind, I);
225 
226  if ((Opcode == Instruction::Load &&
227  !isLegalMaskedGather(DataTy, Align(Alignment))) ||
228  (Opcode == Instruction::Store &&
229  !isLegalMaskedScatter(DataTy, Align(Alignment))))
230  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
231  Alignment, CostKind, I);
232 
233  // Cost is proportional to the number of memory operations implied. For
234  // scalable vectors, we use an upper bound on that number since we don't
235  // know exactly what VL will be.
236  auto &VTy = *cast<VectorType>(DataTy);
237  InstructionCost MemOpCost = getMemoryOpCost(Opcode, VTy.getElementType(),
238  Alignment, 0, CostKind, I);
239  unsigned NumLoads = getMaxVLFor(&VTy);
240  return NumLoads * MemOpCost;
241 }
242 
246  auto *RetTy = ICA.getReturnType();
247  switch (ICA.getID()) {
248  // TODO: add more intrinsic
249  case Intrinsic::experimental_stepvector: {
250  unsigned Cost = 1; // vid
251  auto LT = TLI->getTypeLegalizationCost(DL, RetTy);
252  return Cost + (LT.first - 1);
253  }
254  default:
255  break;
256  }
258 }
259 
261  Type *Src,
264  const Instruction *I) {
265  if (isa<VectorType>(Dst) && isa<VectorType>(Src)) {
266  // FIXME: Need to compute legalizing cost for illegal types.
267  if (!isTypeLegal(Src) || !isTypeLegal(Dst))
268  return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
269 
270  // Skip if element size of Dst or Src is bigger than ELEN.
271  if (Src->getScalarSizeInBits() > ST->getELEN() ||
272  Dst->getScalarSizeInBits() > ST->getELEN())
273  return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
274 
275  int ISD = TLI->InstructionOpcodeToISD(Opcode);
276  assert(ISD && "Invalid opcode");
277 
278  // FIXME: Need to consider vsetvli and lmul.
279  int PowDiff = (int)Log2_32(Dst->getScalarSizeInBits()) -
280  (int)Log2_32(Src->getScalarSizeInBits());
281  switch (ISD) {
282  case ISD::SIGN_EXTEND:
283  case ISD::ZERO_EXTEND:
284  return 1;
285  case ISD::TRUNCATE:
286  case ISD::FP_EXTEND:
287  case ISD::FP_ROUND:
288  // Counts of narrow/widen instructions.
289  return std::abs(PowDiff);
290  case ISD::FP_TO_SINT:
291  case ISD::FP_TO_UINT:
292  case ISD::SINT_TO_FP:
293  case ISD::UINT_TO_FP:
294  if (std::abs(PowDiff) <= 1)
295  return 1;
296  // Backend could lower (v[sz]ext i8 to double) to vfcvt(v[sz]ext.f8 i8),
297  // so it only need two conversion.
298  if (Src->isIntOrIntVectorTy())
299  return 2;
300  // Counts of narrow/widen instructions.
301  return std::abs(PowDiff);
302  }
303  }
304  return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
305 }
306 
307 unsigned RISCVTTIImpl::getMaxVLFor(VectorType *Ty) {
308  if (isa<ScalableVectorType>(Ty)) {
309  const unsigned EltSize = DL.getTypeSizeInBits(Ty->getElementType());
310  const unsigned MinSize = DL.getTypeSizeInBits(Ty).getKnownMinValue();
311  const unsigned VectorBitsMax = ST->getRealMaxVLen();
312  return RISCVTargetLowering::computeVLMAX(VectorBitsMax, EltSize, MinSize);
313  }
314  return cast<FixedVectorType>(Ty)->getNumElements();
315 }
316 
319  bool IsUnsigned,
321  if (isa<FixedVectorType>(Ty) && !ST->useRVVForFixedLengthVectors())
322  return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
323 
324  // Skip if scalar size of Ty is bigger than ELEN.
325  if (Ty->getScalarSizeInBits() > ST->getELEN())
326  return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
327 
328  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
329  if (Ty->getElementType()->isIntegerTy(1))
330  // vcpop sequences, see vreduction-mask.ll. umax, smin actually only
331  // cost 2, but we don't have enough info here so we slightly over cost.
332  return (LT.first - 1) + 3;
333 
334  // IR Reduction is composed by two vmv and one rvv reduction instruction.
335  InstructionCost BaseCost = 2;
336  unsigned VL = getMaxVLFor(Ty);
337  return (LT.first - 1) + BaseCost + Log2_32_Ceil(VL);
338 }
339 
344  if (isa<FixedVectorType>(Ty) && !ST->useRVVForFixedLengthVectors())
345  return BaseT::getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
346 
347  // Skip if scalar size of Ty is bigger than ELEN.
348  if (Ty->getScalarSizeInBits() > ST->getELEN())
349  return BaseT::getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
350 
351  int ISD = TLI->InstructionOpcodeToISD(Opcode);
352  assert(ISD && "Invalid opcode");
353 
354  if (ISD != ISD::ADD && ISD != ISD::OR && ISD != ISD::XOR && ISD != ISD::AND &&
355  ISD != ISD::FADD)
356  return BaseT::getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
357 
358  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
359  if (Ty->getElementType()->isIntegerTy(1))
360  // vcpop sequences, see vreduction-mask.ll
361  return (LT.first - 1) + (ISD == ISD::AND ? 3 : 2);
362 
363  // IR Reduction is composed by two vmv and one rvv reduction instruction.
364  InstructionCost BaseCost = 2;
365  unsigned VL = getMaxVLFor(Ty);
367  return (LT.first - 1) + BaseCost + VL;
368  return (LT.first - 1) + BaseCost + Log2_32_Ceil(VL);
369 }
370 
374  // TODO: More tuning on benchmarks and metrics with changes as needed
375  // would apply to all settings below to enable performance.
376 
377 
378  if (ST->enableDefaultUnroll())
379  return BasicTTIImplBase::getUnrollingPreferences(L, SE, UP, ORE);
380 
381  // Enable Upper bound unrolling universally, not dependant upon the conditions
382  // below.
383  UP.UpperBound = true;
384 
385  // Disable loop unrolling for Oz and Os.
386  UP.OptSizeThreshold = 0;
388  if (L->getHeader()->getParent()->hasOptSize())
389  return;
390 
391  SmallVector<BasicBlock *, 4> ExitingBlocks;
392  L->getExitingBlocks(ExitingBlocks);
393  LLVM_DEBUG(dbgs() << "Loop has:\n"
394  << "Blocks: " << L->getNumBlocks() << "\n"
395  << "Exit blocks: " << ExitingBlocks.size() << "\n");
396 
397  // Only allow another exit other than the latch. This acts as an early exit
398  // as it mirrors the profitability calculation of the runtime unroller.
399  if (ExitingBlocks.size() > 2)
400  return;
401 
402  // Limit the CFG of the loop body for targets with a branch predictor.
403  // Allowing 4 blocks permits if-then-else diamonds in the body.
404  if (L->getNumBlocks() > 4)
405  return;
406 
407  // Don't unroll vectorized loops, including the remainder loop
408  if (getBooleanLoopAttribute(L, "llvm.loop.isvectorized"))
409  return;
410 
411  // Scan the loop: don't unroll loops with calls as this could prevent
412  // inlining.
413  InstructionCost Cost = 0;
414  for (auto *BB : L->getBlocks()) {
415  for (auto &I : *BB) {
416  // Initial setting - Don't unroll loops containing vectorized
417  // instructions.
418  if (I.getType()->isVectorTy())
419  return;
420 
421  if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
422  if (const Function *F = cast<CallBase>(I).getCalledFunction()) {
423  if (!isLoweredToCall(F))
424  continue;
425  }
426  return;
427  }
428 
429  SmallVector<const Value *> Operands(I.operand_values());
430  Cost +=
432  }
433  }
434 
435  LLVM_DEBUG(dbgs() << "Cost of loop: " << Cost << "\n");
436 
437  UP.Partial = true;
438  UP.Runtime = true;
439  UP.UnrollRemainder = true;
440  UP.UnrollAndJam = true;
442 
443  // Force unrolling small loops can be very useful because of the branch
444  // taken cost of the backedge.
445  if (Cost < 12)
446  UP.Force = true;
447 }
448 
451  BaseT::getPeelingPreferences(L, SE, PP);
452 }
453 
455  TypeSize Size = Ty->getPrimitiveSizeInBits();
456  if (Ty->isVectorTy()) {
457  if (Size.isScalable() && ST->hasVInstructions())
458  return divideCeil(Size.getKnownMinValue(), RISCV::RVVBitsPerBlock);
459 
460  if (ST->useRVVForFixedLengthVectors())
461  return divideCeil(Size, ST->getRealMinVLen());
462  }
463 
464  return BaseT::getRegUsageForType(Ty);
465 }
llvm::RISCVTTIImpl::getRegUsageForType
unsigned getRegUsageForType(Type *Ty)
Definition: RISCVTargetTransformInfo.cpp:454
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::PSK_FastHardware
@ PSK_FastHardware
Definition: TargetTransformInfo.h:595
llvm::TargetTransformInfo::UnrollingPreferences::PartialOptSizeThreshold
unsigned PartialOptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size, like OptSizeThreshold,...
Definition: TargetTransformInfo.h:460
llvm::RISCVTTIImpl::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: RISCVTargetTransformInfo.cpp:134
llvm::RISCVMatInt::getIntMatCost
int getIntMatCost(const APInt &Val, unsigned Size, const FeatureBitset &ActiveFeatures, bool CompressionCost)
Definition: RISCVMatInt.cpp:381
llvm::BasicTTIImplBase< RISCVTTIImpl >::DL
const DataLayout & DL
Definition: TargetTransformInfoImpl.h:37
llvm::TargetTransformInfo::UnrollingPreferences::Runtime
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
Definition: TargetTransformInfo.h:488
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm::RISCVTTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: RISCVTargetTransformInfo.cpp:120
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::RISCVTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:244
llvm::RISCVTTIImpl::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:107
llvm::RISCVTTIImpl::getPopcntSupport
TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: RISCVTargetTransformInfo.cpp:115
llvm::RISCVTTIImpl::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:318
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::RISCVSubtarget::useRVVForFixedLengthVectors
bool useRVVForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:200
llvm::BasicBlock::getParent
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:104
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:546
llvm::RISCVTTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:209
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:595
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:53
llvm::TargetTransformInfoImplCRTPBase< RISCVTTIImpl >::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:978
llvm::DataLayout::getTypeSizeInBits
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:673
llvm::BasicTTIImplBase< RISCVTTIImpl >::isTypeLegal
bool isTypeLegal(Type *Ty)
Definition: BasicTTIImpl.h:384
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::RISCVSubtarget::hasVInstructions
bool hasVInstructions() const
Definition: RISCVSubtarget.h:223
llvm::RISCVSubtarget::getRealMaxVLen
unsigned getRealMaxVLen() const
Definition: RISCVSubtarget.h:210
llvm::IntrinsicCostAttributes::getReturnType
Type * getReturnType() const
Definition: TargetTransformInfo.h:150
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:930
llvm::TargetTransformInfo::UnrollingPreferences::UnrollAndJamInnerLoopThreshold
unsigned UnrollAndJamInnerLoopThreshold
Threshold for unroll and jam, for inner loop size.
Definition: TargetTransformInfo.h:507
llvm::RISCVTTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:166
llvm::TargetTransformInfo::UnrollingPreferences::UnrollRemainder
bool UnrollRemainder
Allow unrolling of all the iterations of the runtime loop remainder.
Definition: TargetTransformInfo.h:500
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@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:819
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::RISCVTTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:341
llvm::TargetTransformInfo::UnrollingPreferences::Partial
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
Definition: TargetTransformInfo.h:484
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:538
llvm::RISCVTTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:163
llvm::Optional< unsigned >
llvm::RISCVTTIImpl::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:26
llvm::TargetLoweringBase::getTypeLegalizationCost
std::pair< InstructionCost, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
Definition: TargetLoweringBase.cpp:1847
llvm::VectorType::getElementType
Type * getElementType() const
Definition: DerivedTypes.h:422
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
RISCVMatInt.h
llvm::LoopBase::getNumBlocks
unsigned getNumBlocks() const
Get the number of blocks in this loop in constant time.
Definition: LoopInfo.h:201
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::TargetTransformInfo::SK_Broadcast
@ SK_Broadcast
Broadcast element 0 to all other elements.
Definition: TargetTransformInfo.h:883
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::RISCVTargetLowering::computeVLMAX
static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)
Definition: RISCVISelLowering.h:568
llvm::TargetTransformInfo::requiresOrderedReduction
static bool requiresOrderedReduction(Optional< FastMathFlags > FMF)
A helper function to determine the type of reduction algorithm used for a given Opcode and set of Fas...
Definition: TargetTransformInfo.h:1218
llvm::AArch64CC::LT
@ LT
Definition: AArch64BaseInfo.h:266
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:46
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
TargetLowering.h
llvm::RISCVTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: RISCVTargetTransformInfo.cpp:449
llvm::BasicTTIImplBase::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: BasicTTIImpl.h:516
llvm::RISCVTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: RISCVTargetTransformInfo.cpp:147
llvm::PowerOf2Floor
uint64_t PowerOf2Floor(uint64_t A)
Returns the power of two which is less than or equal to the given value.
Definition: MathExtras.h:722
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:882
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1103
llvm::TargetTransformInfo::UnrollingPreferences::Force
bool Force
Apply loop unroll on any kind of loop (mainly to loops that fail runtime unrolling).
Definition: TargetTransformInfo.h:496
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::RISCVTTIImpl::getSpliceCost
InstructionCost getSpliceCost(VectorType *Tp, int Index)
Definition: RISCVTargetTransformInfo.cpp:164
llvm::BasicTTIImplBase< RISCVTTIImpl >::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: BasicTTIImpl.h:2244
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
llvm::RISCVSubtarget::getELEN
unsigned getELEN() const
Definition: RISCVSubtarget.h:200
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:623
llvm::TargetTransformInfo::UnrollingPreferences::UnrollAndJam
bool UnrollAndJam
Allow unroll and jam. Used to enable unroll and jam for the target.
Definition: TargetTransformInfo.h:502
llvm::LoopBase::getBlocks
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
Definition: LoopInfo.h:187
llvm::BasicTTIImplBase< RISCVTTIImpl >::getRegUsageForType
unsigned getRegUsageForType(Type *Ty)
Definition: BasicTTIImpl.h:389
llvm::Instruction
Definition: Instruction.h:42
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:189
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:773
llvm::LoopBase::getExitingBlocks
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Definition: LoopInfoImpl.h:33
llvm::RISCVSubtarget::hasStdExtZbb
bool hasStdExtZbb() const
Definition: RISCVSubtarget.h:155
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::RISCVSubtarget::enableDefaultUnroll
bool enableDefaultUnroll() const
Definition: RISCVSubtarget.h:185
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:930
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::RISCVSubtarget::getRealMinVLen
unsigned getRealMinVLen() const
Definition: RISCVSubtarget.h:206
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::BasicTTIImplBase< RISCVTTIImpl >::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:928
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:118
llvm::Log2_32_Ceil
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
Definition: MathExtras.h:636
llvm::Instruction::isCommutative
bool isCommutative() const LLVM_READONLY
Return true if the instruction is commutative:
Definition: Instruction.cpp:770
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:595
llvm::RISCVTTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Definition: RISCVTargetTransformInfo.cpp:219
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:191
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:390
llvm::TargetTransformInfo::SK_Reverse
@ SK_Reverse
Reverse the order of the vector.
Definition: TargetTransformInfo.h:884
llvm::RISCV::RVVBitsPerBlock
static constexpr unsigned RVVBitsPerBlock
Definition: RISCVISelLowering.h:344
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::cl::opt
Definition: CommandLine.h:1392
llvm::RISCVTTIImpl::getVScaleForTuning
Optional< unsigned > getVScaleForTuning() const
Definition: RISCVTargetTransformInfo.cpp:140
llvm::divideCeil
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:776
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:820
llvm::BasicTTIImplBase< RISCVTTIImpl >::getVScaleForTuning
Optional< unsigned > getVScaleForTuning() const
Definition: BasicTTIImpl.h:696
llvm::RISCVTTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None)
Definition: RISCVTargetTransformInfo.cpp:174
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:431
I
#define I(x, y, z)
Definition: MD5.cpp:58
getCalledFunction
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
Definition: MemoryBuiltins.cpp:160
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::RISCVTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: RISCVTargetTransformInfo.cpp:371
llvm::RISCVTTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: RISCVTargetTransformInfo.cpp:260
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RVVRegisterWidthLMUL
static cl::opt< unsigned > RVVRegisterWidthLMUL("riscv-v-register-bit-width-lmul", cl::desc("The LMUL to use for getRegisterBitWidth queries. Affects LMUL used " "by autovectorized code. Fractional LMULs are not supported."), cl::init(1), cl::Hidden)
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: BasicTTIImpl.h:695
llvm::TargetTransformInfoImplBase::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Definition: TargetTransformInfoImpl.h:121
llvm::TargetTransformInfo::SK_Splice
@ SK_Splice
Concatenates elements from the first input vector with elements of the second input vector.
Definition: TargetTransformInfo.h:895
llvm::LinearPolySize::getKnownMinValue
ScalarTy getKnownMinValue() const
Returns the minimum value this size can represent.
Definition: TypeSize.h:296
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:262
llvm::ArrayRef< int >
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:70
llvm::TargetTransformInfo::TCK_SizeAndLatency
@ TCK_SizeAndLatency
The weighted sum of size and latency.
Definition: TargetTransformInfo.h:215
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::TargetLoweringBase::InstructionOpcodeToISD
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Definition: TargetLoweringBase.cpp:1767
llvm::BasicTTIImplBase< RISCVTTIImpl >::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: BasicTTIImpl.h:588
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::Function::hasOptSize
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:664
llvm::TargetTransformInfo::UnrollingPreferences::UpperBound
bool UpperBound
Allow using trip count upper bound to unroll loops.
Definition: TargetTransformInfo.h:498
llvm::TypeSize
Definition: TypeSize.h:435
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: BasicTTIImpl.h:1235
llvm::LoopBase::getHeader
BlockT * getHeader() const
Definition: LoopInfo.h:104
llvm::LinearPolySize< TypeSize >::getScalable
static TypeSize getScalable(ScalarTy MinVal)
Definition: TypeSize.h:286
llvm::BasicTTIImplBase< RISCVTTIImpl >::isLegalAddImmediate
bool isLegalAddImmediate(int64_t imm)
Definition: BasicTTIImpl.h:300
llvm::RISCVSubtarget::getXLen
unsigned getXLen() const
Definition: RISCVSubtarget.h:190
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:185
llvm::XCoreISD::LMUL
@ LMUL
Definition: XCoreISelLowering.h:59
llvm::ISD::UINT_TO_FP
@ UINT_TO_FP
Definition: ISDOpcodes.h:774
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:930
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
Try to calculate op costs for min/max reduction operations.
Definition: BasicTTIImpl.h:2254
llvm::ISD::FP_EXTEND
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:871
llvm::BasicTTIImplBase< RISCVTTIImpl >::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1242
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:148
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:930
llvm::BasicTTIImplBase< RISCVTTIImpl >::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Get intrinsic cost based on arguments.
Definition: BasicTTIImpl.h:1395
llvm::getBooleanLoopAttribute
bool getBooleanLoopAttribute(const Loop *TheLoop, StringRef Name)
Returns true if Name is applied to TheLoop and enabled.
Definition: LoopInfo.cpp:1084
TargetTransformInfo.h
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1190
llvm::TargetTransformInfo::UnrollingPreferences::OptSizeThreshold
unsigned OptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size (set to UINT_MAX to disable).
Definition: TargetTransformInfo.h:453
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
BasicTTIImpl.h
llvm::cl::desc
Definition: CommandLine.h:405
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
RISCVTargetTransformInfo.h
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1282
llvm::ISD::FP_ROUND
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:852
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::RISCVTTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: RISCVTargetTransformInfo.cpp:41
llvm::Type::getPrimitiveSizeInBits
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:164
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::BasicTTIImplBase< RISCVTTIImpl >::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None)
Definition: BasicTTIImpl.h:899