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RISCVTargetTransformInfo.h
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1 //===- RISCVTargetTransformInfo.h - RISC-V specific TTI ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file defines a TargetTransformInfo::Concept conforming object specific
10 /// to the RISC-V target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
18 
19 #include "RISCVSubtarget.h"
20 #include "RISCVTargetMachine.h"
24 #include "llvm/IR/Function.h"
25 
26 namespace llvm {
27 
28 class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
30  using TTI = TargetTransformInfo;
31 
32  friend BaseT;
33 
34  const RISCVSubtarget *ST;
35  const RISCVTargetLowering *TLI;
36 
37  const RISCVSubtarget *getST() const { return ST; }
38  const RISCVTargetLowering *getTLI() const { return TLI; }
39 
40  /// This function returns an estimate for VL to be used in VL based terms
41  /// of the cost model. For fixed length vectors, this is simply the
42  /// vector length. For scalable vectors, we return results consistent
43  /// with getVScaleForTuning under the assumption that clients are also
44  /// using that when comparing costs between scalar and vector representation.
45  /// This does unfortunately mean that we can both undershoot and overshot
46  /// the true cost significantly if getVScaleForTuning is wildly off for the
47  /// actual target hardware.
48  unsigned getEstimatedVLFor(VectorType *Ty);
49 
50  /// Return the cost of LMUL. The larger the LMUL, the higher the cost.
51  InstructionCost getLMULCost(MVT VT);
52 
53 public:
54  explicit RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F)
55  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
56  TLI(ST->getTargetLowering()) {}
57 
58  /// Return the cost of materializing an immediate for a value operand of
59  /// a store instruction.
62 
65  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
66  const APInt &Imm, Type *Ty,
68  Instruction *Inst = nullptr);
70  const APInt &Imm, Type *Ty,
72 
74 
75  bool shouldExpandReduction(const IntrinsicInst *II) const;
76  bool supportsScalableVectors() const { return ST->hasVInstructions(); }
77  bool enableScalableVectorization() const { return ST->hasVInstructions(); }
79  return ST->hasVInstructions() ? PredicationStyle::Data
81  }
84 
86 
87  unsigned getRegUsageForType(Type *Ty);
88 
89  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
90 
92  // Epilogue vectorization is usually unprofitable - tail folding or
93  // a smaller VF would have been better. This a blunt hammer - we
94  // should re-examine this once vectorization is better tuned.
95  return false;
96  }
97 
98  InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
99  Align Alignment, unsigned AddressSpace,
101 
105 
108 
109  unsigned getMinVectorRegisterBitWidth() const {
110  return ST->useRVVForFixedLengthVectors() ? 16 : 0;
111  }
112 
117  VectorType *SubTp,
119 
122 
123  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
124  const Value *Ptr, bool VariableMask,
125  Align Alignment,
127  const Instruction *I);
128 
129  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
132  const Instruction *I = nullptr);
133 
135  bool IsUnsigned,
137 
141 
142  InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned,
143  Type *ResTy, VectorType *ValTy,
146 
148  getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
151  const Instruction *I = nullptr);
152 
153  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
154  CmpInst::Predicate VecPred,
156  const Instruction *I = nullptr);
157 
159  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
160  unsigned Index);
161 
162  InstructionCost getArithmeticInstrCost(
163  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
164  TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
165  TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
166  ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
167  const Instruction *CxtI = nullptr);
168 
170  return TLI->isLegalElementTypeForRVV(Ty);
171  }
172 
173  bool isLegalMaskedLoadStore(Type *DataType, Align Alignment) {
174  if (!ST->hasVInstructions())
175  return false;
176 
177  // Only support fixed vectors if we know the minimum vector size.
178  if (isa<FixedVectorType>(DataType) && !ST->useRVVForFixedLengthVectors())
179  return false;
180 
181  // Don't allow elements larger than the ELEN.
182  // FIXME: How to limit for scalable vectors?
183  if (isa<FixedVectorType>(DataType) &&
184  DataType->getScalarSizeInBits() > ST->getELEN())
185  return false;
186 
187  if (Alignment <
189  return false;
190 
191  return TLI->isLegalElementTypeForRVV(DataType->getScalarType());
192  }
193 
194  bool isLegalMaskedLoad(Type *DataType, Align Alignment) {
195  return isLegalMaskedLoadStore(DataType, Alignment);
196  }
197  bool isLegalMaskedStore(Type *DataType, Align Alignment) {
198  return isLegalMaskedLoadStore(DataType, Alignment);
199  }
200 
201  bool isLegalMaskedGatherScatter(Type *DataType, Align Alignment) {
202  if (!ST->hasVInstructions())
203  return false;
204 
205  // Only support fixed vectors if we know the minimum vector size.
206  if (isa<FixedVectorType>(DataType) && !ST->useRVVForFixedLengthVectors())
207  return false;
208 
209  // Don't allow elements larger than the ELEN.
210  // FIXME: How to limit for scalable vectors?
211  if (isa<FixedVectorType>(DataType) &&
212  DataType->getScalarSizeInBits() > ST->getELEN())
213  return false;
214 
215  if (Alignment <
217  return false;
218 
219  return TLI->isLegalElementTypeForRVV(DataType->getScalarType());
220  }
221 
222  bool isLegalMaskedGather(Type *DataType, Align Alignment) {
223  return isLegalMaskedGatherScatter(DataType, Alignment);
224  }
225  bool isLegalMaskedScatter(Type *DataType, Align Alignment) {
226  return isLegalMaskedGatherScatter(DataType, Alignment);
227  }
228 
230  // Scalarize masked gather for RV64 if EEW=64 indices aren't supported.
231  return ST->is64Bit() && !ST->hasVInstructionsI64();
232  }
233 
235  // Scalarize masked scatter for RV64 if EEW=64 indices aren't supported.
236  return ST->is64Bit() && !ST->hasVInstructionsI64();
237  }
238 
239  /// \returns How the target needs this vector-predicated operation to be
240  /// transformed.
245  }
246 
248  ElementCount VF) const {
249  if (!VF.isScalable())
250  return true;
251 
252  Type *Ty = RdxDesc.getRecurrenceType();
253  if (!TLI->isLegalElementTypeForRVV(Ty))
254  return false;
255 
256  switch (RdxDesc.getRecurrenceKind()) {
257  case RecurKind::Add:
258  case RecurKind::FAdd:
259  case RecurKind::And:
260  case RecurKind::Or:
261  case RecurKind::Xor:
262  case RecurKind::SMin:
263  case RecurKind::SMax:
264  case RecurKind::UMin:
265  case RecurKind::UMax:
266  case RecurKind::FMin:
267  case RecurKind::FMax:
270  case RecurKind::FMulAdd:
271  return true;
272  default:
273  return false;
274  }
275  }
276 
277  unsigned getMaxInterleaveFactor(unsigned VF) {
278  // If the loop will not be vectorized, don't interleave the loop.
279  // Let regular unroll to unroll the loop.
280  return VF == 1 ? 1 : ST->getMaxInterleaveFactor();
281  }
282 
284  unsigned getNumberOfRegisters(unsigned ClassID) const {
285  switch (ClassID) {
286  case RISCVRegisterClass::GPRRC:
287  // 31 = 32 GPR - x0 (zero register)
288  // FIXME: Should we exclude fixed registers like SP, TP or GP?
289  return 31;
290  case RISCVRegisterClass::FPRRC:
291  if (ST->hasStdExtF())
292  return 32;
293  return 0;
294  case RISCVRegisterClass::VRRC:
295  // Although there are 32 vector registers, v0 is special in that it is the
296  // only register that can be used to hold a mask.
297  // FIXME: Should we conservatively return 31 as the number of usable
298  // vector registers?
299  return ST->hasVInstructions() ? 32 : 0;
300  }
301  llvm_unreachable("unknown register class");
302  }
303 
304  unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
305  if (Vector)
306  return RISCVRegisterClass::VRRC;
307  if (!Ty)
308  return RISCVRegisterClass::GPRRC;
309 
310  Type *ScalarTy = Ty->getScalarType();
311  if ((ScalarTy->isHalfTy() && ST->hasStdExtZfh()) ||
312  (ScalarTy->isFloatTy() && ST->hasStdExtF()) ||
313  (ScalarTy->isDoubleTy() && ST->hasStdExtD())) {
314  return RISCVRegisterClass::FPRRC;
315  }
316 
317  return RISCVRegisterClass::GPRRC;
318  }
319 
320  const char *getRegisterClassName(unsigned ClassID) const {
321  switch (ClassID) {
322  case RISCVRegisterClass::GPRRC:
323  return "RISCV::GPRRC";
324  case RISCVRegisterClass::FPRRC:
325  return "RISCV::FPRRC";
326  case RISCVRegisterClass::VRRC:
327  return "RISCV::VRRC";
328  }
329  llvm_unreachable("unknown register class");
330  }
331 };
332 
333 } // end namespace llvm
334 
335 #endif // LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
llvm::RISCVTTIImpl::getRegUsageForType
unsigned getRegUsageForType(Type *Ty)
Definition: RISCVTargetTransformInfo.cpp:1192
llvm::InstructionCost
Definition: InstructionCost.h:30
llvm::RISCVTTIImpl::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: RISCVTargetTransformInfo.cpp:199
llvm::BasicTTIImplBase< RISCVTTIImpl >::DL
const DataLayout & DL
Definition: TargetTransformInfoImpl.h:37
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:218
llvm::RISCVTTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: RISCVTargetTransformInfo.cpp:185
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::RISCVTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:606
llvm::RISCVTTIImpl::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:172
llvm::RISCVTTIImpl::getPopcntSupport
TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: RISCVTargetTransformInfo.cpp:180
llvm::RecurKind::Or
@ Or
Bitwise or logical OR of integers.
llvm::RISCVTTIImpl::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:763
llvm::RISCVTTIImpl
Definition: RISCVTargetTransformInfo.h:28
llvm::RISCVTTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: RISCVTargetTransformInfo.cpp:1055
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::RISCVTTIImpl::RISCVTTIImpl
RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F)
Definition: RISCVTargetTransformInfo.h:54
llvm::ElementCount
Definition: TypeSize.h:404
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:444
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
llvm::RISCVTTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:321
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:586
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:328
llvm::DataLayout::getTypeStoreSize
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Definition: DataLayout.h:474
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:173
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::RISCVTTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: RISCVTargetTransformInfo.cpp:962
llvm::RISCVTTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:225
llvm::RISCVTargetMachine
Definition: RISCVTargetMachine.h:23
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1513
llvm::RISCVTTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:786
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:529
llvm::RISCVTTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:222
llvm::RISCVTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: RISCVTargetTransformInfo.h:284
llvm::Optional< unsigned >
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::RecurKind::SelectFCmp
@ SelectFCmp
Integer select(fcmp(),x,y) where one of (x,y) is loop invariant.
llvm::RISCVTTIImpl::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: RISCVTargetTransformInfo.h:169
llvm::RISCVTTIImpl::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:55
llvm::RecurKind::SMin
@ SMin
Signed integer min implemented in terms of select(cmp()).
llvm::TargetTransformInfo::OperandValueInfo
Definition: TargetTransformInfo.h:924
llvm::RISCVTTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpdInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
Definition: RISCVTargetTransformInfo.cpp:866
llvm::RISCVTTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: RISCVTargetTransformInfo.h:109
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:298
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::RISCVTTIImpl::preferEpilogueVectorization
bool preferEpilogueVectorization() const
Definition: RISCVTargetTransformInfo.h:91
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:46
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::RISCVTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: RISCVTargetTransformInfo.cpp:1187
llvm::RISCVTargetLowering::isLegalElementTypeForRVV
bool isLegalElementTypeForRVV(Type *ScalarTy) const
Definition: RISCVISelLowering.cpp:1666
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
llvm::RISCVTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: RISCVTargetTransformInfo.cpp:214
llvm::BasicTTIImplBase< RISCVTTIImpl >::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: BasicTTIImpl.h:1187
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:916
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:887
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1139
llvm::RISCVTTIImpl::getSpliceCost
InstructionCost getSpliceCost(VectorType *Tp, int Index)
Definition: RISCVTargetTransformInfo.cpp:234
llvm::RecurrenceDescriptor::getRecurrenceType
Type * getRecurrenceType() const
Returns the type of the recurrence.
Definition: IVDescriptors.h:245
llvm::RISCVTTIImpl::supportsScalableVectors
bool supportsScalableVectors() const
Definition: RISCVTargetTransformInfo.h:76
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
llvm::Instruction
Definition: Instruction.h:42
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:189
llvm::RecurrenceDescriptor::getRecurrenceKind
RecurKind getRecurrenceKind() const
Definition: IVDescriptors.h:198
llvm::RISCVTTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None)
Definition: RISCVTargetTransformInfo.cpp:244
llvm::RISCVTTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: RISCVTargetTransformInfo.h:277
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
IVDescriptors.h
llvm::RISCVTTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:197
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:120
llvm::RecurKind::UMin
@ UMin
Unisgned integer min implemented in terms of select(cmp()).
llvm::RISCVTTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Definition: RISCVTargetTransformInfo.cpp:332
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::RISCVTTIImpl::getVScaleForTuning
Optional< unsigned > getVScaleForTuning() const
Definition: RISCVTargetTransformInfo.cpp:205
llvm::RISCVTTIImpl::forceScalarizeMaskedGather
bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment)
Definition: RISCVTargetTransformInfo.h:229
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::RISCVTTIImpl::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: RISCVTargetTransformInfo.h:247
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:417
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::RecurKind::Add
@ Add
Sum of integers.
llvm::RISCVTTIImpl::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: RISCVTargetTransformInfo.h:320
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:78
llvm::RISCVTTIImpl::isLegalMaskedLoadStore
bool isLegalMaskedLoadStore(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:173
llvm::RISCVTTIImpl::getVPLegalizationStrategy
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: RISCVTargetTransformInfo.h:242
llvm::Type::isHalfTy
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
Definition: Type.h:142
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::RISCVTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: RISCVTargetTransformInfo.cpp:1109
llvm::RISCVTTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: RISCVTargetTransformInfo.cpp:675
llvm::RISCVTTIImpl::emitGetActiveLaneMask
PredicationStyle emitGetActiveLaneMask() const
Definition: RISCVTargetTransformInfo.h:78
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::RISCVTTIImpl::isLegalMaskedGatherScatter
bool isLegalMaskedGatherScatter(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:201
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::RecurKind::UMax
@ UMax
Unsigned integer max implemented in terms of select(cmp()).
llvm::RISCVTTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: RISCVTargetTransformInfo.cpp:879
llvm::ArrayRef< int >
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
llvm::RISCVTTIImpl::getExtendedReductionCost
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *ValTy, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:816
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:805
llvm::RISCVTTIImpl::RISCVRegisterClass
RISCVRegisterClass
Definition: RISCVTargetTransformInfo.h:283
llvm::RecurKind::FMax
@ FMax
FP max implemented in terms of select(cmp()).
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:908
llvm::RISCVTTIImpl::VRRC
@ VRRC
Definition: RISCVTargetTransformInfo.h:283
llvm::RISCVTTIImpl::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: RISCVTargetTransformInfo.h:304
llvm::RecurKind::FMulAdd
@ FMulAdd
Fused multiply-add of floats (a * b + c).
llvm::Type::isFloatTy
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:153
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:475
VPLegalization
TargetTransformInfo::VPLegalization VPLegalization
Definition: ExpandVectorPredication.cpp:35
llvm::TypeSize
Definition: TypeSize.h:435
Function.h
llvm::Type::isDoubleTy
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:156
llvm::RISCVTTIImpl::enableScalableVectorization
bool enableScalableVectorization() const
Definition: RISCVTargetTransformInfo.h:77
llvm::RISCVTargetLowering
Definition: RISCVISelLowering.h:334
llvm::PredicationStyle
PredicationStyle
Definition: TargetTransformInfo.h:166
llvm::RISCVTTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:194
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
RISCVSubtarget.h
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:69
llvm::RISCVTTIImpl::getStoreImmCost
InstructionCost getStoreImmCost(Type *VecTy, TTI::OperandValueInfo OpInfo, TTI::TargetCostKind CostKind)
Return the cost of materializing an immediate for a value operand of a store instruction.
Definition: RISCVTargetTransformInfo.cpp:842
llvm::RecurKind::SelectICmp
@ SelectICmp
Integer select(icmp(),x,y) where one of (x,y) is loop invariant.
llvm::RecurKind::FAdd
@ FAdd
Sum of floats.
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:965
llvm::TargetTransformInfo::VPLegalization::Legal
@ Legal
Definition: TargetTransformInfo.h:1516
TargetTransformInfo.h
llvm::RISCVTTIImpl::GPRRC
@ GPRRC
Definition: RISCVTargetTransformInfo.h:283
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RecurKind::FMin
@ FMin
FP min implemented in terms of select(cmp()).
llvm::RISCVTTIImpl::forceScalarizeMaskedScatter
bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment)
Definition: RISCVTargetTransformInfo.h:234
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
BasicTTIImpl.h
llvm::RISCVTTIImpl::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: RISCVTargetTransformInfo.cpp:1205
llvm::RecurKind::SMax
@ SMax
Signed integer max implemented in terms of select(cmp()).
llvm::PredicationStyle::None
@ None
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::RISCVTTIImpl::FPRRC
@ FPRRC
Definition: RISCVTargetTransformInfo.h:283
llvm::Data
@ Data
llvm::RISCVTTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: RISCVTargetTransformInfo.cpp:97
llvm::RecurKind::Xor
@ Xor
Bitwise or logical XOR of integers.
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:39
RISCVTargetMachine.h