46#define DEBUG_TYPE "asm-printer"
49 "Number of RISC-V Compressed instructions emitted");
61 std::unique_ptr<MCStreamer> Streamer)
86 bool emitPseudoExpansionLowering(
MCStreamer &OutStreamer,
89 typedef std::tuple<unsigned, uint32_t> HwasanMemaccessTuple;
90 std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
93 void EmitHwasanMemaccessSymbols(
Module &M);
102 bool emitDirectiveOptionArch();
115 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
119 MCSymbol *MILabel = Ctx.createTempSymbol();
123 assert(NumNOPBytes % NOPBytes == 0 &&
124 "Invalid number of NOP bytes requested!");
130 while (NumNOPBytes > 0) {
131 if (MII ==
MBB.
end() || MII->isCall() ||
132 MII->getOpcode() == RISCV::DBG_VALUE ||
133 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
134 MII->getOpcode() == TargetOpcode::STACKMAP)
141 emitNops(NumNOPBytes / NOPBytes);
148 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
151 MCSymbol *MILabel = Ctx.createTempSymbol();
158 unsigned EncodedBytes = 0;
160 if (CalleeMO.
isImm()) {
163 assert((CallTarget & 0xFFFF'FFFF'FFFF) == CallTarget &&
164 "High 16 bits of call target should be zero.");
168 for (
MCInst &Inst : Seq) {
169 bool Compressed = EmitToStreamer(OutStreamer, Inst);
170 EncodedBytes += Compressed ? 2 : 4;
172 bool Compressed = EmitToStreamer(OutStreamer,
MCInstBuilder(RISCV::JALR)
176 EncodedBytes += Compressed ? 2 : 4;
180 lowerOperand(CalleeMO, CallTargetMCOp);
181 EmitToStreamer(OutStreamer,
187 unsigned NumBytes = Opers.getNumPatchBytes();
188 assert(NumBytes >= EncodedBytes &&
189 "Patchpoint can't request size less than the length of a call.");
190 assert((NumBytes - EncodedBytes) % NOPBytes == 0 &&
191 "Invalid number of NOP bytes requested!");
192 emitNops((NumBytes - EncodedBytes) / NOPBytes);
197 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
200 if (
unsigned PatchBytes = SOpers.getNumPatchBytes()) {
201 assert(PatchBytes % NOPBytes == 0 &&
202 "Invalid number of NOP bytes requested!");
203 emitNops(PatchBytes / NOPBytes);
208 switch (CallTarget.
getType()) {
211 lowerOperand(CallTarget, CallTargetMCOp);
236 MCSymbol *MILabel = Ctx.createTempSymbol();
245 ++RISCVNumInstrsCompressed;
252#include "RISCVGenMCPseudoLowering.inc"
257 if (!STI->hasStdExtZihintntl())
260 if (
MI->memoperands_empty())
267 unsigned NontemporalMode = 0;
269 NontemporalMode += 0b1;
271 NontemporalMode += 0b10;
274 if (STI->hasStdExtCOrZca() && STI->enableRVCHintInstrs())
283 EmitToStreamer(*OutStreamer, Hint);
287 RISCV_MC::verifyInstructionPredicates(
MI->getOpcode(),
288 getSubtargetInfo().getFeatureBits());
293 if (emitPseudoExpansionLowering(*OutStreamer,
MI))
297 switch (
MI->getOpcode()) {
298 case RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
299 LowerHWASAN_CHECK_MEMACCESS(*
MI);
301 case RISCV::KCFI_CHECK:
302 LowerKCFI_CHECK(*
MI);
304 case RISCV::PseudoRVVInitUndefM1:
305 case RISCV::PseudoRVVInitUndefM2:
306 case RISCV::PseudoRVVInitUndefM4:
307 case RISCV::PseudoRVVInitUndefM8:
309 case TargetOpcode::STACKMAP:
310 return LowerSTACKMAP(*OutStreamer, SM, *
MI);
311 case TargetOpcode::PATCHPOINT:
312 return LowerPATCHPOINT(*OutStreamer, SM, *
MI);
313 case TargetOpcode::STATEPOINT:
314 return LowerSTATEPOINT(*OutStreamer, SM, *
MI);
318 if (!lowerToMCInst(
MI, OutInst))
319 EmitToStreamer(*OutStreamer, OutInst);
322bool RISCVAsmPrinter::PrintAsmOperand(
const MachineInstr *
MI,
unsigned OpNo,
329 if (ExtraCode && ExtraCode[0]) {
330 if (ExtraCode[1] != 0)
333 switch (ExtraCode[0]) {
357 PrintSymbolOperand(MO,
OS);
371bool RISCVAsmPrinter::PrintAsmMemoryOperand(
const MachineInstr *
MI,
373 const char *ExtraCode,
379 assert(
MI->getNumOperands() > OpNo + 1 &&
"Expected additional operand");
383 if (!AddrReg.
isReg())
390 if (!lowerOperand(
Offset, MCO))
401bool RISCVAsmPrinter::emitDirectiveOptionArch() {
407 if (STI->hasFeature(Feature.Value) == MCSTI.
hasFeature(Feature.Value))
413 auto Delta = STI->hasFeature(Feature.Value) ? RISCVOptionArchArgType::Plus
414 : RISCVOptionArchArgType::Minus;
417 if (!NeedEmitStdOptionArgs.
empty()) {
431 bool EmittedOptionArch = emitDirectiveOptionArch();
433 SetupMachineFunction(MF);
436 if (EmittedOptionArch)
437 RTS.emitDirectiveOptionPop();
441void RISCVAsmPrinter::emitStartOfAsmFile(
Module &M) {
444 if (
const MDString *ModuleTargetABI =
445 dyn_cast_or_null<MDString>(
M.getModuleFlag(
"target-abi")))
451 if (
auto *MD = dyn_cast_or_null<MDNode>(
M.getModuleFlag(
"riscv-isa"))) {
452 for (
auto &ISA : MD->operands()) {
453 if (
auto *ISAString = dyn_cast_or_null<MDString>(ISA)) {
455 ISAString->getString(),
true,
458 auto &ISAInfo = *ParseResult;
460 if (ISAInfo->hasExtension(Feature.Key) &&
471 if (
TM.getTargetTriple().isOSBinFormatELF())
472 emitAttributes(SubtargetInfo);
475void RISCVAsmPrinter::emitEndOfAsmFile(
Module &M) {
479 if (
TM.getTargetTriple().isOSBinFormatELF())
481 EmitHwasanMemaccessSymbols(M);
484void RISCVAsmPrinter::emitAttributes(
const MCSubtargetInfo &SubtargetInfo) {
493void RISCVAsmPrinter::emitFunctionEntryLabel() {
495 if (RMFI->isVectorCall()) {
509void RISCVAsmPrinter::LowerHWASAN_CHECK_MEMACCESS(
const MachineInstr &
MI) {
511 uint32_t AccessInfo =
MI.getOperand(1).getImm();
513 HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, AccessInfo)];
516 if (!
TM.getTargetTriple().isOSBinFormatELF())
519 std::string SymName =
"__hwasan_check_x" + utostr(Reg - RISCV::X0) +
"_" +
520 utostr(AccessInfo) +
"_short";
521 Sym = OutContext.getOrCreateSymbol(SymName);
526 EmitToStreamer(*OutStreamer,
MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr));
531 assert(std::next(
MI.getIterator())->isCall() &&
532 "KCFI_CHECK not followed by a call instruction");
533 assert(std::next(
MI.getIterator())->getOperand(0).getReg() == AddrReg &&
534 "KCFI_CHECK call target doesn't match call operand");
541 unsigned ScratchRegs[] = {RISCV::X6, RISCV::X7};
542 unsigned NextReg = RISCV::X28;
543 auto isRegAvailable = [&](
unsigned Reg) {
544 return Reg != AddrReg && !STI->isRegisterReservedByUser(Reg);
546 for (
auto &Reg : ScratchRegs) {
547 if (isRegAvailable(Reg))
549 while (!isRegAvailable(NextReg))
552 if (Reg > RISCV::X31)
556 if (AddrReg == RISCV::X0) {
560 .addReg(ScratchRegs[0])
566 int NopSize = STI->hasStdExtCOrZca() ? 2 : 4;
567 int64_t PrefixNops = 0;
570 .getFnAttribute(
"patchable-function-prefix")
572 .getAsInteger(10, PrefixNops);
576 .addReg(ScratchRegs[0])
578 .addImm(-(PrefixNops * NopSize + 4)));
582 const int64_t
Type =
MI.getOperand(1).getImm();
583 const int64_t Hi20 = ((
Type + 0x800) >> 12) & 0xFFFFF;
584 const int64_t Lo12 = SignExtend64<12>(
Type);
588 MCInstBuilder(RISCV::LUI).addReg(ScratchRegs[1]).addImm(Hi20));
590 if (Lo12 || Hi20 == 0) {
591 EmitToStreamer(*OutStreamer,
602 EmitToStreamer(*OutStreamer,
604 .addReg(ScratchRegs[0])
605 .addReg(ScratchRegs[1])
611 emitKCFITrapEntry(*
MI.getMF(),
Trap);
615void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(
Module &M) {
616 if (HwasanMemaccessSymbols.empty())
619 assert(
TM.getTargetTriple().isOSBinFormatELF());
626 OutContext.getOrCreateSymbol(
"__hwasan_tag_mismatch_v2");
638 for (
auto &
P : HwasanMemaccessSymbols) {
639 unsigned Reg = std::get<0>(
P.first);
640 uint32_t AccessInfo = std::get<1>(
P.first);
677 MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
686 MCSymbol *ReturnSym = OutContext.createTempSymbol();
693 OutStreamer->
emitLabel(HandleMismatchOrPartialSym);
700 MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
738 OutStreamer->
emitLabel(HandleMismatchSym);
804 if (Reg != RISCV::X10)
939 RISCVVPseudosTable::getPseudoInfo(
MI->getOpcode());
946 assert(
MBB &&
"MI expected to be in a basic block");
948 assert(MF &&
"MBB expected to be in a machine function");
953 assert(
TRI &&
"TargetRegisterInfo expected");
957 unsigned NumOps =
MI->getNumExplicitOperands();
971 for (
unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
974 if (hasVLOutput && OpNo == 1)
978 if (OpNo ==
MI->getNumExplicitDefs() && MO.
isReg() && MO.
isTied()) {
980 "Expected tied to first def.");
997 if (RISCV::VRM2RegClass.
contains(Reg) ||
998 RISCV::VRM4RegClass.
contains(Reg) ||
999 RISCV::VRM8RegClass.
contains(Reg)) {
1000 Reg =
TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
1001 assert(Reg &&
"Subregister does not exist");
1002 }
else if (RISCV::FPR16RegClass.
contains(Reg)) {
1004 TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
1005 assert(Reg &&
"Subregister does not exist");
1006 }
else if (RISCV::FPR64RegClass.
contains(Reg)) {
1007 Reg =
TRI->getSubReg(Reg, RISCV::sub_32);
1008 assert(Reg &&
"Superregister does not exist");
1009 }
else if (RISCV::VRN2M1RegClass.
contains(Reg) ||
1010 RISCV::VRN2M2RegClass.
contains(Reg) ||
1011 RISCV::VRN2M4RegClass.
contains(Reg) ||
1012 RISCV::VRN3M1RegClass.
contains(Reg) ||
1013 RISCV::VRN3M2RegClass.
contains(Reg) ||
1014 RISCV::VRN4M1RegClass.
contains(Reg) ||
1015 RISCV::VRN4M2RegClass.
contains(Reg) ||
1016 RISCV::VRN5M1RegClass.
contains(Reg) ||
1017 RISCV::VRN6M1RegClass.
contains(Reg) ||
1018 RISCV::VRN7M1RegClass.
contains(Reg) ||
1019 RISCV::VRN8M1RegClass.
contains(Reg)) {
1020 Reg =
TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
1021 assert(Reg &&
"Subregister does not exist");
1039 RISCV::VMV0RegClassID &&
1040 "Expected only mask operand to be missing");
1056 if (lowerOperand(MO, MCOp))
1061 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
1062 const Function &
F =
MI->getParent()->getParent()->getFunction();
1063 if (
F.hasFnAttribute(
"patchable-function-entry")) {
1065 if (
F.getFnAttribute(
"patchable-function-entry")
1067 .getAsInteger(10, Num))
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
This file implements a class to represent arbitrary precision integral constant values and operations...
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter()
static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, const AsmPrinter &AP)
static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This class is intended to be used as a driving class for all asm writers.
virtual void emitInstruction(const MachineInstr *)
Targets should implement this to emit instructions.
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
virtual void emitStartOfAsmFile(Module &)
This virtual method can be overridden by targets that want to emit something at the start of their fi...
virtual void emitEndOfAsmFile(Module &)
This virtual method can be overridden by targets that want to emit something at the end of their file...
MCContext & OutContext
This is the context for the output file that we are streaming.
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
virtual void emitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
const MCExpr * getExpr() const
Streaming machine code generation interface.
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
virtual bool emitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
MCContext & getContext() const
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
MCTargetStreamer * getTargetStreamer()
virtual void switchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
Represent a reference to a symbol from inside an expression.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Representation of each machine instruction.
A description of a memory reference used in the backend.
bool isNonTemporal() const
Flags getFlags() const
Return the raw flags of the source value,.
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
const BlockAddress * getBlockAddress() const
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
MCSymbol * getMCSymbol() const
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
int64_t getOffset() const
Return the offset from the symbol in this operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
A Module instance is used to store all the information related to an LLVM module.
Pass interface - Implemented by all 'passes'.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
MI-level patchpoint operands.
static bool isSupportedExtensionFeature(StringRef Ext)
static llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseArchString(StringRef Arch, bool EnableExperimentalExtension, bool ExperimentalExtensionVersionCheck=true, bool IgnoreUnknown=false)
Parse RISC-V ISA info from arch string.
static const char * getRegisterName(MCRegister Reg)
static const RISCVMCExpr * create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx)
@ VK_RISCV_TLSDESC_ADD_LO
@ VK_RISCV_TLSDESC_LOAD_LO
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
virtual void emitDirectiveVariantCC(MCSymbol &Symbol)
void emitTargetAttributes(const MCSubtargetInfo &STI, bool EmitStackAlign)
void setFlagsFromFeatures(const MCSubtargetInfo &STI)
void setTargetABI(RISCVABI::ABI ABI)
virtual void emitDirectiveOptionArch(ArrayRef< RISCVOptionArchArg > Args)
virtual void finishAttributeSection()
virtual void emitDirectiveOptionPush()
Wrapper class representing virtual and physical registers.
reference emplace_back(ArgTypes &&... Args)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MI-level stackmap operands.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
void recordStatepoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ABI getTargetABI(StringRef ABIName)
static bool hasRoundModeOp(uint64_t TSFlags)
static bool isTiedPseudo(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static bool hasVecPolicyOp(uint64_t TSFlags)
static bool hasSEWOp(uint64_t TSFlags)
void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI, MCRegister DestReg, SmallVectorImpl< MCInst > &Insts)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool isFaultFirstLoad(const MachineInstr &MI)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
bool errorToBool(Error Err)
Helper for converting an Error to a bool.
static const MachineMemOperand::Flags MONontemporalBit1
Target & getTheRISCV32Target()
static const MachineMemOperand::Flags MONontemporalBit0
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Target & getTheRISCV64Target()
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]
@ MCSA_ELF_TypeFunction
.type _foo, STT_FUNC # aka @function
@ MCSA_Hidden
.hidden (ELF)
Implement std::hash so that hash_code can be used in STL containers.
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...
Used to provide key value pairs for feature and CPU bit flags.