28#define DEBUG_TYPE "asm-printer"
31#define PRINT_ALIAS_INSTR
32#include "RISCVGenAsmWriter.inc"
36 cl::desc(
"Disable the emission of assembler pseudo instructions"),
51 if (Opt ==
"no-aliases") {
55 if (Opt ==
"numeric") {
72 NewMI =
const_cast<MCInst *
>(&UncompressedMI);
84 const char *Modifier) {
85 assert((Modifier ==
nullptr || Modifier[0] == 0) &&
"No modifiers supported");
98 assert(MO.
isExpr() &&
"Unknown operand kind in printOperand");
123 unsigned Imm =
MI->getOperand(OpNo).getImm();
124 auto SiFiveReg = RISCVSysReg::lookupSiFiveRegByEncoding(Imm);
125 auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
126 if (SiFiveReg && SiFiveReg->haveVendorRequiredFeatures(STI.
getFeatureBits()))
128 else if (SysReg && SysReg->haveRequiredFeatures(STI.
getFeatureBits()))
137 unsigned FenceArg =
MI->getOperand(OpNo).getImm();
138 assert (((FenceArg >> 4) == 0) &&
"Invalid immediate in printFenceArg");
164 unsigned Imm =
MI->getOperand(OpNo).getImm();
167 }
else if (Imm == 30) {
169 }
else if (Imm == 31) {
177 if (FPVal == (
int)(FPVal))
189 assert(MO.
isReg() &&
"printZeroOffsetMemOp can only print register operands");
197 unsigned Imm =
MI->getOperand(OpNo).getImm();
211 unsigned Imm =
MI->getOperand(OpNo).getImm();
271 int64_t Imm =
MI->getOperand(OpNo).getImm();
272 unsigned Opcode =
MI->getOpcode();
273 bool IsRV64 = STI.
hasFeature(RISCV::Feature64Bit);
274 bool IsEABI = STI.
hasFeature(RISCV::FeatureRVE);
276 auto RlistVal =
MI->getOperand(0).getImm();
277 assert(RlistVal != 16 &&
"Incorrect rlist.");
280 assert((Spimm >=
Base && Spimm <=
Base + 48) &&
"Incorrect spimm");
281 if (Opcode == RISCV::CM_PUSH)
294 assert(MO.
isReg() &&
"printVMaskReg can only print register operands");
295 if (MO.
getReg() == RISCV::NoRegister)
304 : RISCV::ABIRegAltName);
static cl::opt< bool > NoAliases("csky-no-aliases", cl::desc("Disable the emission of assembler pseudo instructions"), cl::init(false), cl::Hidden)
static cl::opt< bool > ArchRegNames("csky-arch-reg-names", cl::desc("Print architectural register names rather than the " "ABI names (such as r14 instead of sp)"), cl::init(false), cl::Hidden)
static cl::opt< bool > NoAliases("riscv-no-aliases", cl::desc("Disable the emission of assembler pseudo instructions"), cl::init(false), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
format_object< int64_t > formatHex(int64_t Value) const
WithMarkup markup(raw_ostream &OS, Markup M) const
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
bool PrintAliases
True if we prefer aliases (e.g. nop) to raw mnemonics.
Instances of this class represent a single low-level machine instruction.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
static const char * getRegisterName(MCRegister Reg)
void printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &O, MCRegister Reg) const override
Print the assembler register name.
void printFenceArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printVMaskReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
bool applyTargetSpecificCLOption(StringRef Opt) override
Customize the printer according to a command line option.
bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printSpimm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printFPImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier=nullptr)
void printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printRlist(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
StringRef - Represent a constant reference to a string, i.e.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static StringRef roundingModeToString(RoundingMode RndMode)
float getFPImm(unsigned Imm)
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
static RISCVII::VLMUL getVLMUL(unsigned VType)
void printVType(unsigned VType, raw_ostream &OS)
static unsigned getSEW(unsigned VType)
static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64, bool IsEABI)
void printSpimm(int64_t Spimm, raw_ostream &OS)
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.