LLVM 20.0.0git
RISCVInstPrinter.cpp
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1//===-- RISCVInstPrinter.cpp - Convert RISC-V MCInst to asm syntax --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class prints an RISC-V MCInst to a .s file.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVInstPrinter.h"
14#include "RISCVBaseInfo.h"
15#include "RISCVMCExpr.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCSymbol.h"
24using namespace llvm;
25
26#define DEBUG_TYPE "asm-printer"
27
28// Include the auto-generated portion of the assembly writer.
29#define PRINT_ALIAS_INSTR
30#include "RISCVGenAsmWriter.inc"
31
32static cl::opt<bool>
33 NoAliases("riscv-no-aliases",
34 cl::desc("Disable the emission of assembler pseudo instructions"),
35 cl::init(false), cl::Hidden);
36
37// Print architectural register names rather than the ABI names (such as x2
38// instead of sp).
39// TODO: Make RISCVInstPrinter::getRegisterName non-static so that this can a
40// member.
41static bool ArchRegNames;
42
43// The command-line flags above are used by llvm-mc and llc. They can be used by
44// `llvm-objdump`, but we override their values here to handle options passed to
45// `llvm-objdump` with `-M` (which matches GNU objdump). There did not seem to
46// be an easier way to allow these options in all these tools, without doing it
47// this way.
49 if (Opt == "no-aliases") {
50 PrintAliases = false;
51 return true;
52 }
53 if (Opt == "numeric") {
54 ArchRegNames = true;
55 return true;
56 }
57
58 return false;
59}
60
62 StringRef Annot, const MCSubtargetInfo &STI,
63 raw_ostream &O) {
64 bool Res = false;
65 const MCInst *NewMI = MI;
66 MCInst UncompressedMI;
67 if (PrintAliases && !NoAliases)
68 Res = RISCVRVC::uncompress(UncompressedMI, *MI, STI);
69 if (Res)
70 NewMI = const_cast<MCInst *>(&UncompressedMI);
71 if (!PrintAliases || NoAliases || !printAliasInstr(NewMI, Address, STI, O))
72 printInstruction(NewMI, Address, STI, O);
73 printAnnotation(O, Annot);
74}
75
78}
79
80void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
81 const MCSubtargetInfo &STI, raw_ostream &O,
82 const char *Modifier) {
83 assert((Modifier == nullptr || Modifier[0] == 0) && "No modifiers supported");
84 const MCOperand &MO = MI->getOperand(OpNo);
85
86 if (MO.isReg()) {
87 printRegName(O, MO.getReg());
88 return;
89 }
90
91 if (MO.isImm()) {
93 return;
94 }
95
96 assert(MO.isExpr() && "Unknown operand kind in printOperand");
97 MO.getExpr()->print(O, &MAI);
98}
99
101 unsigned OpNo,
102 const MCSubtargetInfo &STI,
103 raw_ostream &O) {
104 const MCOperand &MO = MI->getOperand(OpNo);
105 if (!MO.isImm())
106 return printOperand(MI, OpNo, STI, O);
107
109 uint64_t Target = Address + MO.getImm();
110 if (!STI.hasFeature(RISCV::Feature64Bit))
111 Target &= 0xffffffff;
113 } else {
115 }
116}
117
119 const MCSubtargetInfo &STI,
120 raw_ostream &O) {
121 unsigned Imm = MI->getOperand(OpNo).getImm();
122 auto Range = RISCVSysReg::lookupSysRegByEncoding(Imm);
123 for (auto &Reg : Range) {
124 if (Reg.haveRequiredFeatures(STI.getFeatureBits())) {
125 markup(O, Markup::Register) << Reg.Name;
126 return;
127 }
128 }
130}
131
132void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
133 const MCSubtargetInfo &STI,
134 raw_ostream &O) {
135 unsigned FenceArg = MI->getOperand(OpNo).getImm();
136 assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
137
138 if ((FenceArg & RISCVFenceField::I) != 0)
139 O << 'i';
140 if ((FenceArg & RISCVFenceField::O) != 0)
141 O << 'o';
142 if ((FenceArg & RISCVFenceField::R) != 0)
143 O << 'r';
144 if ((FenceArg & RISCVFenceField::W) != 0)
145 O << 'w';
146 if (FenceArg == 0)
147 O << "0";
148}
149
150void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
151 const MCSubtargetInfo &STI, raw_ostream &O) {
152 auto FRMArg =
153 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
155 return;
156 O << ", " << RISCVFPRndMode::roundingModeToString(FRMArg);
157}
158
160 const MCSubtargetInfo &STI,
161 raw_ostream &O) {
162 auto FRMArg =
163 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
164 // Never print rounding mode if it's the default 'rne'. This ensures the
165 // output can still be parsed by older tools that erroneously failed to
166 // accept a rounding mode.
168 return;
169 O << ", " << RISCVFPRndMode::roundingModeToString(FRMArg);
170}
171
173 const MCSubtargetInfo &STI,
174 raw_ostream &O) {
175 unsigned Imm = MI->getOperand(OpNo).getImm();
176 if (Imm == 1) {
177 markup(O, Markup::Immediate) << "min";
178 } else if (Imm == 30) {
179 markup(O, Markup::Immediate) << "inf";
180 } else if (Imm == 31) {
181 markup(O, Markup::Immediate) << "nan";
182 } else {
183 float FPVal = RISCVLoadFPImm::getFPImm(Imm);
184 // If the value is an integer, print a .0 fraction. Otherwise, use %g to
185 // which will not print trailing zeros and will use scientific notation
186 // if it is shorter than printing as a decimal. The smallest value requires
187 // 12 digits of precision including the decimal.
188 if (FPVal == (int)(FPVal))
189 markup(O, Markup::Immediate) << format("%.1f", FPVal);
190 else
191 markup(O, Markup::Immediate) << format("%.12g", FPVal);
192 }
193}
194
196 const MCSubtargetInfo &STI,
197 raw_ostream &O) {
198 const MCOperand &MO = MI->getOperand(OpNo);
199
200 assert(MO.isReg() && "printZeroOffsetMemOp can only print register operands");
201 O << "(";
202 printRegName(O, MO.getReg());
203 O << ")";
204}
205
206void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
207 const MCSubtargetInfo &STI, raw_ostream &O) {
208 unsigned Imm = MI->getOperand(OpNo).getImm();
209 // Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx,
210 // or non-zero in bits 8 and above.
212 RISCVVType::getSEW(Imm) > 64 || (Imm >> 8) != 0) {
213 O << formatImm(Imm);
214 return;
215 }
216 // Print the text form.
218}
219
220// Print a Zcmp RList. If we are printing architectural register names rather
221// than ABI register names, we need to print "{x1, x8-x9, x18-x27}" for all
222// registers. Otherwise, we print "{ra, s0-s11}".
223void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
224 const MCSubtargetInfo &STI, raw_ostream &O) {
225 unsigned Imm = MI->getOperand(OpNo).getImm();
226 O << "{";
227 printRegName(O, RISCV::X1);
228
229 if (Imm >= RISCVZC::RLISTENCODE::RA_S0) {
230 O << ", ";
231 printRegName(O, RISCV::X8);
232 }
233
235 O << '-';
237 printRegName(O, RISCV::X9);
238 }
239
241 if (ArchRegNames)
242 O << ", ";
244 printRegName(O, RISCV::X18);
245 }
246
248 if (ArchRegNames)
249 O << '-';
250 unsigned Offset = (Imm - RISCVZC::RLISTENCODE::RA_S0_S3);
251 // Encodings for S3-S9 are contiguous. There is no encoding for S10, so we
252 // must skip to S11(X27).
254 ++Offset;
255 printRegName(O, RISCV::X19 + Offset);
256 }
257
258 O << "}";
259}
260
261void RISCVInstPrinter::printRegReg(const MCInst *MI, unsigned OpNo,
262 const MCSubtargetInfo &STI, raw_ostream &O) {
263 const MCOperand &MO = MI->getOperand(OpNo);
264
265 assert(MO.isReg() && "printRegReg can only print register operands");
266 printRegName(O, MO.getReg());
267
268 O << "(";
269 const MCOperand &MO1 = MI->getOperand(OpNo + 1);
270 assert(MO1.isReg() && "printRegReg can only print register operands");
271 printRegName(O, MO1.getReg());
272 O << ")";
273}
274
275void RISCVInstPrinter::printStackAdj(const MCInst *MI, unsigned OpNo,
276 const MCSubtargetInfo &STI, raw_ostream &O,
277 bool Negate) {
278 int64_t Imm = MI->getOperand(OpNo).getImm();
279 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
280 int64_t StackAdj = 0;
281 auto RlistVal = MI->getOperand(0).getImm();
282 assert(RlistVal != 16 && "Incorrect rlist.");
283 auto Base = RISCVZC::getStackAdjBase(RlistVal, IsRV64);
284 StackAdj = Imm + Base;
285 assert((StackAdj >= Base && StackAdj <= Base + 48) &&
286 "Incorrect stack adjust");
287 if (Negate)
288 StackAdj = -StackAdj;
289
290 // RAII guard for ANSI color escape sequences
291 WithMarkup ScopedMarkup = markup(O, Markup::Immediate);
292 O << StackAdj;
293}
294
295void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
296 const MCSubtargetInfo &STI,
297 raw_ostream &O) {
298 const MCOperand &MO = MI->getOperand(OpNo);
299
300 assert(MO.isReg() && "printVMaskReg can only print register operands");
301 if (MO.getReg() == RISCV::NoRegister)
302 return;
303 O << ", ";
304 printRegName(O, MO.getReg());
305 O << ".t";
306}
307
309 return getRegisterName(Reg, ArchRegNames ? RISCV::NoRegAltName
310 : RISCV::ABIRegAltName);
311}
static cl::opt< bool > NoAliases("csky-no-aliases", cl::desc("Disable the emission of assembler pseudo instructions"), cl::init(false), cl::Hidden)
static cl::opt< bool > ArchRegNames("csky-arch-reg-names", cl::desc("Print architectural register names rather than the " "ABI names (such as r14 instead of sp)"), cl::init(false), cl::Hidden)
IRTranslator LLVM IR MI
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
static bool ArchRegNames
static cl::opt< bool > NoAliases("riscv-no-aliases", cl::desc("Disable the emission of assembler pseudo instructions"), cl::init(false), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:40
WithMarkup markup(raw_ostream &OS, Markup M)
format_object< int64_t > formatHex(int64_t Value) const
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:52
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Definition: MCInstPrinter.h:75
bool PrintAliases
True if we prefer aliases (e.g. nop) to raw mnemonics.
Definition: MCInstPrinter.h:64
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:37
int64_t getImm() const
Definition: MCInst.h:81
bool isImm() const
Definition: MCInst.h:63
bool isReg() const
Definition: MCInst.h:62
MCRegister getReg() const
Returns the register number.
Definition: MCInst.h:70
const MCExpr * getExpr() const
Definition: MCInst.h:115
bool isExpr() const
Definition: MCInst.h:66
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
static const char * getRegisterName(MCRegister Reg)
void printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printFenceArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printVMaskReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
bool applyTargetSpecificCLOption(StringRef Opt) override
Customize the printer according to a command line option.
void printFRMArgLegacy(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printFPImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier=nullptr)
void printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &O, MCRegister Reg) override
Print the assembler register name.
void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printRlist(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printStackAdj(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, bool Negate=false)
void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
static StringRef roundingModeToString(RoundingMode RndMode)
float getFPImm(unsigned Imm)
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
static RISCVII::VLMUL getVLMUL(unsigned VType)
void printVType(unsigned VType, raw_ostream &OS)
static unsigned getSEW(unsigned VType)
static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:125