LLVM  14.0.0git
X86Operand.h
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1 //===- X86Operand.h - Parsed X86 machine instruction ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
10 #define LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
11 
14 #include "X86AsmParserCommon.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
20 #include "llvm/Support/Casting.h"
21 #include "llvm/Support/SMLoc.h"
22 #include <cassert>
23 #include <memory>
24 
25 namespace llvm {
26 
27 /// X86Operand - Instances of this class represent a parsed X86 machine
28 /// instruction.
29 struct X86Operand final : public MCParsedAsmOperand {
31 
35  void *OpDecl;
36  bool AddressOf;
37 
38  struct TokOp {
39  const char *Data;
40  unsigned Length;
41  };
42 
43  struct RegOp {
44  unsigned RegNo;
45  };
46 
47  struct PrefOp {
48  unsigned Prefixes;
49  };
50 
51  struct ImmOp {
52  const MCExpr *Val;
53  bool LocalRef;
54  };
55 
56  struct MemOp {
57  unsigned SegReg;
58  const MCExpr *Disp;
59  unsigned BaseReg;
60  unsigned DefaultBaseReg;
61  unsigned IndexReg;
62  unsigned Scale;
63  unsigned Size;
64  unsigned ModeSize;
65 
66  /// If the memory operand is unsized and there are multiple instruction
67  /// matches, prefer the one with this size.
68  unsigned FrontendSize;
69  };
70 
71  union {
72  struct TokOp Tok;
73  struct RegOp Reg;
74  struct ImmOp Imm;
75  struct MemOp Mem;
76  struct PrefOp Pref;
77  };
78 
79  X86Operand(KindTy K, SMLoc Start, SMLoc End)
80  : Kind(K), StartLoc(Start), EndLoc(End), OpDecl(nullptr),
81  AddressOf(false) {}
82 
83  StringRef getSymName() override { return SymName; }
84  void *getOpDecl() override { return OpDecl; }
85 
86  /// getStartLoc - Get the location of the first token of this operand.
87  SMLoc getStartLoc() const override { return StartLoc; }
88 
89  /// getEndLoc - Get the location of the last token of this operand.
90  SMLoc getEndLoc() const override { return EndLoc; }
91 
92  /// getLocRange - Get the range between the first and last token of this
93  /// operand.
94  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
95 
96  /// getOffsetOfLoc - Get the location of the offset operator.
97  SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }
98 
99  void print(raw_ostream &OS) const override {
100 
101  auto PrintImmValue = [&](const MCExpr *Val, const char *VName) {
102  if (Val->getKind() == MCExpr::Constant) {
103  if (auto Imm = cast<MCConstantExpr>(Val)->getValue())
104  OS << VName << Imm;
105  } else if (Val->getKind() == MCExpr::SymbolRef) {
106  if (auto *SRE = dyn_cast<MCSymbolRefExpr>(Val)) {
107  const MCSymbol &Sym = SRE->getSymbol();
108  if (const char *SymNameStr = Sym.getName().data())
109  OS << VName << SymNameStr;
110  }
111  }
112  };
113 
114  switch (Kind) {
115  case Token:
116  OS << Tok.Data;
117  break;
118  case Register:
120  break;
121  case DXRegister:
122  OS << "DXReg";
123  break;
124  case Immediate:
125  PrintImmValue(Imm.Val, "Imm:");
126  break;
127  case Prefix:
128  OS << "Prefix:" << Pref.Prefixes;
129  break;
130  case Memory:
131  OS << "Memory: ModeSize=" << Mem.ModeSize;
132  if (Mem.Size)
133  OS << ",Size=" << Mem.Size;
134  if (Mem.BaseReg)
135  OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg);
136  if (Mem.IndexReg)
137  OS << ",IndexReg="
139  if (Mem.Scale)
140  OS << ",Scale=" << Mem.Scale;
141  if (Mem.Disp)
142  PrintImmValue(Mem.Disp, ",Disp=");
143  if (Mem.SegReg)
144  OS << ",SegReg=" << X86IntelInstPrinter::getRegisterName(Mem.SegReg);
145  break;
146  }
147  }
148 
149  StringRef getToken() const {
150  assert(Kind == Token && "Invalid access!");
151  return StringRef(Tok.Data, Tok.Length);
152  }
154  assert(Kind == Token && "Invalid access!");
155  Tok.Data = Value.data();
156  Tok.Length = Value.size();
157  }
158 
159  unsigned getReg() const override {
160  assert(Kind == Register && "Invalid access!");
161  return Reg.RegNo;
162  }
163 
164  unsigned getPrefix() const {
165  assert(Kind == Prefix && "Invalid access!");
166  return Pref.Prefixes;
167  }
168 
169  const MCExpr *getImm() const {
170  assert(Kind == Immediate && "Invalid access!");
171  return Imm.Val;
172  }
173 
174  const MCExpr *getMemDisp() const {
175  assert(Kind == Memory && "Invalid access!");
176  return Mem.Disp;
177  }
178  unsigned getMemSegReg() const {
179  assert(Kind == Memory && "Invalid access!");
180  return Mem.SegReg;
181  }
182  unsigned getMemBaseReg() const {
183  assert(Kind == Memory && "Invalid access!");
184  return Mem.BaseReg;
185  }
186  unsigned getMemDefaultBaseReg() const {
187  assert(Kind == Memory && "Invalid access!");
188  return Mem.DefaultBaseReg;
189  }
190  unsigned getMemIndexReg() const {
191  assert(Kind == Memory && "Invalid access!");
192  return Mem.IndexReg;
193  }
194  unsigned getMemScale() const {
195  assert(Kind == Memory && "Invalid access!");
196  return Mem.Scale;
197  }
198  unsigned getMemModeSize() const {
199  assert(Kind == Memory && "Invalid access!");
200  return Mem.ModeSize;
201  }
202  unsigned getMemFrontendSize() const {
203  assert(Kind == Memory && "Invalid access!");
204  return Mem.FrontendSize;
205  }
206 
207  bool isToken() const override {return Kind == Token; }
208 
209  bool isImm() const override { return Kind == Immediate; }
210 
211  bool isImmSExti16i8() const {
212  if (!isImm())
213  return false;
214 
215  // If this isn't a constant expr, just assume it fits and let relaxation
216  // handle it.
217  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
218  if (!CE)
219  return true;
220 
221  // Otherwise, check the value is in a range that makes sense for this
222  // extension.
223  return isImmSExti16i8Value(CE->getValue());
224  }
225  bool isImmSExti32i8() const {
226  if (!isImm())
227  return false;
228 
229  // If this isn't a constant expr, just assume it fits and let relaxation
230  // handle it.
231  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
232  if (!CE)
233  return true;
234 
235  // Otherwise, check the value is in a range that makes sense for this
236  // extension.
237  return isImmSExti32i8Value(CE->getValue());
238  }
239  bool isImmSExti64i8() const {
240  if (!isImm())
241  return false;
242 
243  // If this isn't a constant expr, just assume it fits and let relaxation
244  // handle it.
245  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
246  if (!CE)
247  return true;
248 
249  // Otherwise, check the value is in a range that makes sense for this
250  // extension.
251  return isImmSExti64i8Value(CE->getValue());
252  }
253  bool isImmSExti64i32() const {
254  if (!isImm())
255  return false;
256 
257  // If this isn't a constant expr, just assume it fits and let relaxation
258  // handle it.
259  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
260  if (!CE)
261  return true;
262 
263  // Otherwise, check the value is in a range that makes sense for this
264  // extension.
265  return isImmSExti64i32Value(CE->getValue());
266  }
267 
268  bool isImmUnsignedi4() const {
269  if (!isImm()) return false;
270  // If this isn't a constant expr, reject it. The immediate byte is shared
271  // with a register encoding. We can't have it affected by a relocation.
272  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
273  if (!CE) return false;
274  return isImmUnsignedi4Value(CE->getValue());
275  }
276 
277  bool isImmUnsignedi8() const {
278  if (!isImm()) return false;
279  // If this isn't a constant expr, just assume it fits and let relaxation
280  // handle it.
281  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
282  if (!CE) return true;
283  return isImmUnsignedi8Value(CE->getValue());
284  }
285 
286  bool isOffsetOfLocal() const override { return isImm() && Imm.LocalRef; }
287 
288  bool isMemPlaceholder(const MCInstrDesc &Desc) const override {
289  // Only MS InlineAsm uses global variables with registers rather than
290  // rip/eip.
291  return isMem() && !Mem.DefaultBaseReg && Mem.FrontendSize;
292  }
293 
294  bool needAddressOf() const override { return AddressOf; }
295 
296  bool isMem() const override { return Kind == Memory; }
297  bool isMemUnsized() const {
298  return Kind == Memory && Mem.Size == 0;
299  }
300  bool isMem8() const {
301  return Kind == Memory && (!Mem.Size || Mem.Size == 8);
302  }
303  bool isMem16() const {
304  return Kind == Memory && (!Mem.Size || Mem.Size == 16);
305  }
306  bool isMem32() const {
307  return Kind == Memory && (!Mem.Size || Mem.Size == 32);
308  }
309  bool isMem64() const {
310  return Kind == Memory && (!Mem.Size || Mem.Size == 64);
311  }
312  bool isMem80() const {
313  return Kind == Memory && (!Mem.Size || Mem.Size == 80);
314  }
315  bool isMem128() const {
316  return Kind == Memory && (!Mem.Size || Mem.Size == 128);
317  }
318  bool isMem256() const {
319  return Kind == Memory && (!Mem.Size || Mem.Size == 256);
320  }
321  bool isMem512() const {
322  return Kind == Memory && (!Mem.Size || Mem.Size == 512);
323  }
324 
325  bool isSibMem() const {
326  return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP;
327  }
328 
329  bool isMemIndexReg(unsigned LowR, unsigned HighR) const {
330  assert(Kind == Memory && "Invalid access!");
331  return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR;
332  }
333 
334  bool isMem64_RC128() const {
335  return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM15);
336  }
337  bool isMem128_RC128() const {
338  return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM15);
339  }
340  bool isMem128_RC256() const {
341  return isMem128() && isMemIndexReg(X86::YMM0, X86::YMM15);
342  }
343  bool isMem256_RC128() const {
344  return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM15);
345  }
346  bool isMem256_RC256() const {
347  return isMem256() && isMemIndexReg(X86::YMM0, X86::YMM15);
348  }
349 
350  bool isMem64_RC128X() const {
351  return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM31);
352  }
353  bool isMem128_RC128X() const {
354  return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM31);
355  }
356  bool isMem128_RC256X() const {
357  return isMem128() && isMemIndexReg(X86::YMM0, X86::YMM31);
358  }
359  bool isMem256_RC128X() const {
360  return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM31);
361  }
362  bool isMem256_RC256X() const {
363  return isMem256() && isMemIndexReg(X86::YMM0, X86::YMM31);
364  }
365  bool isMem256_RC512() const {
366  return isMem256() && isMemIndexReg(X86::ZMM0, X86::ZMM31);
367  }
368  bool isMem512_RC256X() const {
369  return isMem512() && isMemIndexReg(X86::YMM0, X86::YMM31);
370  }
371  bool isMem512_RC512() const {
372  return isMem512() && isMemIndexReg(X86::ZMM0, X86::ZMM31);
373  }
374 
375  bool isAbsMem() const {
376  return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
377  !getMemIndexReg() && getMemScale() == 1;
378  }
379  bool isAVX512RC() const{
380  return isImm();
381  }
382 
383  bool isAbsMem16() const {
384  return isAbsMem() && Mem.ModeSize == 16;
385  }
386 
387  bool isSrcIdx() const {
388  return !getMemIndexReg() && getMemScale() == 1 &&
389  (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
390  getMemBaseReg() == X86::SI) && isa<MCConstantExpr>(getMemDisp()) &&
391  cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
392  }
393  bool isSrcIdx8() const {
394  return isMem8() && isSrcIdx();
395  }
396  bool isSrcIdx16() const {
397  return isMem16() && isSrcIdx();
398  }
399  bool isSrcIdx32() const {
400  return isMem32() && isSrcIdx();
401  }
402  bool isSrcIdx64() const {
403  return isMem64() && isSrcIdx();
404  }
405 
406  bool isDstIdx() const {
407  return !getMemIndexReg() && getMemScale() == 1 &&
408  (getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
409  (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
410  getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
411  cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
412  }
413  bool isDstIdx8() const {
414  return isMem8() && isDstIdx();
415  }
416  bool isDstIdx16() const {
417  return isMem16() && isDstIdx();
418  }
419  bool isDstIdx32() const {
420  return isMem32() && isDstIdx();
421  }
422  bool isDstIdx64() const {
423  return isMem64() && isDstIdx();
424  }
425 
426  bool isMemOffs() const {
427  return Kind == Memory && !getMemBaseReg() && !getMemIndexReg() &&
428  getMemScale() == 1;
429  }
430 
431  bool isMemOffs16_8() const {
432  return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 8);
433  }
434  bool isMemOffs16_16() const {
435  return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 16);
436  }
437  bool isMemOffs16_32() const {
438  return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 32);
439  }
440  bool isMemOffs32_8() const {
441  return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 8);
442  }
443  bool isMemOffs32_16() const {
444  return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 16);
445  }
446  bool isMemOffs32_32() const {
447  return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 32);
448  }
449  bool isMemOffs32_64() const {
450  return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 64);
451  }
452  bool isMemOffs64_8() const {
453  return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 8);
454  }
455  bool isMemOffs64_16() const {
456  return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 16);
457  }
458  bool isMemOffs64_32() const {
459  return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 32);
460  }
461  bool isMemOffs64_64() const {
462  return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 64);
463  }
464 
465  bool isPrefix() const { return Kind == Prefix; }
466  bool isReg() const override { return Kind == Register; }
467  bool isDXReg() const { return Kind == DXRegister; }
468 
469  bool isGR32orGR64() const {
470  return Kind == Register &&
471  (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
472  X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
473  }
474 
475  bool isGR16orGR32orGR64() const {
476  return Kind == Register &&
477  (X86MCRegisterClasses[X86::GR16RegClassID].contains(getReg()) ||
478  X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
479  X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
480  }
481 
482  bool isVectorReg() const {
483  return Kind == Register &&
484  (X86MCRegisterClasses[X86::VR64RegClassID].contains(getReg()) ||
485  X86MCRegisterClasses[X86::VR128XRegClassID].contains(getReg()) ||
486  X86MCRegisterClasses[X86::VR256XRegClassID].contains(getReg()) ||
487  X86MCRegisterClasses[X86::VR512RegClassID].contains(getReg()));
488  }
489 
490  bool isVK1Pair() const {
491  return Kind == Register &&
492  X86MCRegisterClasses[X86::VK1RegClassID].contains(getReg());
493  }
494 
495  bool isVK2Pair() const {
496  return Kind == Register &&
497  X86MCRegisterClasses[X86::VK2RegClassID].contains(getReg());
498  }
499 
500  bool isVK4Pair() const {
501  return Kind == Register &&
502  X86MCRegisterClasses[X86::VK4RegClassID].contains(getReg());
503  }
504 
505  bool isVK8Pair() const {
506  return Kind == Register &&
507  X86MCRegisterClasses[X86::VK8RegClassID].contains(getReg());
508  }
509 
510  bool isVK16Pair() const {
511  return Kind == Register &&
512  X86MCRegisterClasses[X86::VK16RegClassID].contains(getReg());
513  }
514 
515  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
516  // Add as immediates when possible.
517  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
518  Inst.addOperand(MCOperand::createImm(CE->getValue()));
519  else
520  Inst.addOperand(MCOperand::createExpr(Expr));
521  }
522 
523  void addRegOperands(MCInst &Inst, unsigned N) const {
524  assert(N == 1 && "Invalid number of operands!");
526  }
527 
528  void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
529  assert(N == 1 && "Invalid number of operands!");
530  MCRegister RegNo = getReg();
531  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
532  RegNo = getX86SubSuperRegister(RegNo, 32);
533  Inst.addOperand(MCOperand::createReg(RegNo));
534  }
535 
536  void addGR16orGR32orGR64Operands(MCInst &Inst, unsigned N) const {
537  assert(N == 1 && "Invalid number of operands!");
538  MCRegister RegNo = getReg();
539  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(RegNo) ||
540  X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
541  RegNo = getX86SubSuperRegister(RegNo, 16);
542  Inst.addOperand(MCOperand::createReg(RegNo));
543  }
544 
545  void addAVX512RCOperands(MCInst &Inst, unsigned N) const {
546  assert(N == 1 && "Invalid number of operands!");
547  addExpr(Inst, getImm());
548  }
549 
550  void addImmOperands(MCInst &Inst, unsigned N) const {
551  assert(N == 1 && "Invalid number of operands!");
552  addExpr(Inst, getImm());
553  }
554 
555  void addMaskPairOperands(MCInst &Inst, unsigned N) const {
556  assert(N == 1 && "Invalid number of operands!");
557  unsigned Reg = getReg();
558  switch (Reg) {
559  case X86::K0:
560  case X86::K1:
561  Reg = X86::K0_K1;
562  break;
563  case X86::K2:
564  case X86::K3:
565  Reg = X86::K2_K3;
566  break;
567  case X86::K4:
568  case X86::K5:
569  Reg = X86::K4_K5;
570  break;
571  case X86::K6:
572  case X86::K7:
573  Reg = X86::K6_K7;
574  break;
575  }
577  }
578 
579  void addMemOperands(MCInst &Inst, unsigned N) const {
580  assert((N == 5) && "Invalid number of operands!");
581  if (getMemBaseReg())
583  else
587  addExpr(Inst, getMemDisp());
589  }
590 
591  void addAbsMemOperands(MCInst &Inst, unsigned N) const {
592  assert((N == 1) && "Invalid number of operands!");
593  // Add as immediates when possible.
594  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
595  Inst.addOperand(MCOperand::createImm(CE->getValue()));
596  else
598  }
599 
600  void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
601  assert((N == 2) && "Invalid number of operands!");
604  }
605 
606  void addDstIdxOperands(MCInst &Inst, unsigned N) const {
607  assert((N == 1) && "Invalid number of operands!");
609  }
610 
611  void addMemOffsOperands(MCInst &Inst, unsigned N) const {
612  assert((N == 2) && "Invalid number of operands!");
613  // Add as immediates when possible.
614  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
615  Inst.addOperand(MCOperand::createImm(CE->getValue()));
616  else
619  }
620 
621  static std::unique_ptr<X86Operand> CreateToken(StringRef Str, SMLoc Loc) {
622  SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
623  auto Res = std::make_unique<X86Operand>(Token, Loc, EndLoc);
624  Res->Tok.Data = Str.data();
625  Res->Tok.Length = Str.size();
626  return Res;
627  }
628 
629  static std::unique_ptr<X86Operand>
630  CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
631  bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),
632  StringRef SymName = StringRef(), void *OpDecl = nullptr) {
633  auto Res = std::make_unique<X86Operand>(Register, StartLoc, EndLoc);
634  Res->Reg.RegNo = RegNo;
635  Res->AddressOf = AddressOf;
636  Res->OffsetOfLoc = OffsetOfLoc;
637  Res->SymName = SymName;
638  Res->OpDecl = OpDecl;
639  return Res;
640  }
641 
642  static std::unique_ptr<X86Operand>
644  return std::make_unique<X86Operand>(DXRegister, StartLoc, EndLoc);
645  }
646 
647  static std::unique_ptr<X86Operand>
648  CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc) {
649  auto Res = std::make_unique<X86Operand>(Prefix, StartLoc, EndLoc);
650  Res->Pref.Prefixes = Prefixes;
651  return Res;
652  }
653 
654  static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val,
657  void *OpDecl = nullptr,
658  bool GlobalRef = true) {
659  auto Res = std::make_unique<X86Operand>(Immediate, StartLoc, EndLoc);
660  Res->Imm.Val = Val;
661  Res->Imm.LocalRef = !GlobalRef;
662  Res->SymName = SymName;
663  Res->OpDecl = OpDecl;
664  Res->AddressOf = true;
665  return Res;
666  }
667 
668  /// Create an absolute memory operand.
669  static std::unique_ptr<X86Operand>
670  CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
671  unsigned Size = 0, StringRef SymName = StringRef(),
672  void *OpDecl = nullptr, unsigned FrontendSize = 0) {
673  auto Res = std::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
674  Res->Mem.SegReg = 0;
675  Res->Mem.Disp = Disp;
676  Res->Mem.BaseReg = 0;
677  Res->Mem.DefaultBaseReg = 0;
678  Res->Mem.IndexReg = 0;
679  Res->Mem.Scale = 1;
680  Res->Mem.Size = Size;
681  Res->Mem.ModeSize = ModeSize;
682  Res->Mem.FrontendSize = FrontendSize;
683  Res->SymName = SymName;
684  Res->OpDecl = OpDecl;
685  Res->AddressOf = false;
686  return Res;
687  }
688 
689  /// Create a generalized memory operand.
690  static std::unique_ptr<X86Operand>
691  CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
692  unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
693  SMLoc EndLoc, unsigned Size = 0,
694  unsigned DefaultBaseReg = X86::NoRegister,
695  StringRef SymName = StringRef(), void *OpDecl = nullptr,
696  unsigned FrontendSize = 0) {
697  // We should never just have a displacement, that should be parsed as an
698  // absolute memory operand.
699  assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
700  "Invalid memory operand!");
701 
702  // The scale should always be one of {1,2,4,8}.
703  assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
704  "Invalid scale!");
705  auto Res = std::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
706  Res->Mem.SegReg = SegReg;
707  Res->Mem.Disp = Disp;
708  Res->Mem.BaseReg = BaseReg;
709  Res->Mem.DefaultBaseReg = DefaultBaseReg;
710  Res->Mem.IndexReg = IndexReg;
711  Res->Mem.Scale = Scale;
712  Res->Mem.Size = Size;
713  Res->Mem.ModeSize = ModeSize;
714  Res->Mem.FrontendSize = FrontendSize;
715  Res->SymName = SymName;
716  Res->OpDecl = OpDecl;
717  Res->AddressOf = false;
718  return Res;
719  }
720 };
721 
722 } // end namespace llvm
723 
724 #endif // LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
llvm::X86Operand::OffsetOfLoc
SMLoc OffsetOfLoc
Definition: X86Operand.h:33
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::N86::ESI
@ ESI
Definition: X86MCTargetDesc.h:51
llvm::X86Operand::isDstIdx
bool isDstIdx() const
Definition: X86Operand.h:406
llvm::X86Operand::addAVX512RCOperands
void addAVX512RCOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:545
llvm::X86Operand::MemOp::IndexReg
unsigned IndexReg
Definition: X86Operand.h:61
llvm::X86Operand::isSrcIdx
bool isSrcIdx() const
Definition: X86Operand.h:387
llvm::X86Operand::getEndLoc
SMLoc getEndLoc() const override
getEndLoc - Get the location of the last token of this operand.
Definition: X86Operand.h:90
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:22
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::X86Operand::isSrcIdx32
bool isSrcIdx32() const
Definition: X86Operand.h:399
llvm::X86Operand::Mem
struct MemOp Mem
Definition: X86Operand.h:75
llvm::X86Operand::getMemScale
unsigned getMemScale() const
Definition: X86Operand.h:194
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::MCParsedAsmOperand
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Definition: MCParsedAsmOperand.h:25
llvm::X86Operand::isMem128_RC256X
bool isMem128_RC256X() const
Definition: X86Operand.h:356
llvm::X86Operand::isMemIndexReg
bool isMemIndexReg(unsigned LowR, unsigned HighR) const
Definition: X86Operand.h:329
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
StringRef.h
llvm::X86Operand::addImmOperands
void addImmOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:550
llvm::X86Operand::isMem8
bool isMem8() const
Definition: X86Operand.h:300
llvm::X86Operand::isMem256_RC128X
bool isMem256_RC128X() const
Definition: X86Operand.h:359
llvm::isImmUnsignedi4Value
bool isImmUnsignedi4Value(uint64_t Value)
Definition: X86AsmParserCommon.h:38
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::X86Operand::isDXReg
bool isDXReg() const
Definition: X86Operand.h:467
llvm::X86Operand::isAVX512RC
bool isAVX512RC() const
Definition: X86Operand.h:379
llvm::N86::EDI
@ EDI
Definition: X86MCTargetDesc.h:51
MCParsedAsmOperand.h
llvm::X86Operand::isMem256_RC256X
bool isMem256_RC256X() const
Definition: X86Operand.h:362
llvm::isImmSExti32i8Value
bool isImmSExti32i8Value(uint64_t Value)
Definition: X86AsmParserCommon.h:21
llvm::X86Operand::isImmSExti32i8
bool isImmSExti32i8() const
Definition: X86Operand.h:225
llvm::X86Operand::Imm
struct ImmOp Imm
Definition: X86Operand.h:74
llvm::X86Operand::getMemIndexReg
unsigned getMemIndexReg() const
Definition: X86Operand.h:190
llvm::X86Operand::isMemPlaceholder
bool isMemPlaceholder(const MCInstrDesc &Desc) const override
isMemPlaceholder - Do we need to ignore the constraint, rather than emit code? Only valid when parsin...
Definition: X86Operand.h:288
llvm::X86Operand::StartLoc
SMLoc StartLoc
Definition: X86Operand.h:32
llvm::X86Operand::isMem
bool isMem() const override
isMem - Is this a memory operand?
Definition: X86Operand.h:296
llvm::X86Operand::getPrefix
unsigned getPrefix() const
Definition: X86Operand.h:164
llvm::X86Operand::isSrcIdx8
bool isSrcIdx8() const
Definition: X86Operand.h:393
llvm::X86Operand::isMem64
bool isMem64() const
Definition: X86Operand.h:309
STLExtras.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::X86Operand::isMemOffs32_8
bool isMemOffs32_8() const
Definition: X86Operand.h:440
llvm::X86Operand::isReg
bool isReg() const override
isReg - Is this a register operand?
Definition: X86Operand.h:466
llvm::X86Operand::isMem256_RC128
bool isMem256_RC128() const
Definition: X86Operand.h:343
llvm::X86Operand::isImmSExti64i32
bool isImmSExti64i32() const
Definition: X86Operand.h:253
llvm::X86Operand::isMem256_RC512
bool isMem256_RC512() const
Definition: X86Operand.h:365
llvm::X86Operand::CreatePrefix
static std::unique_ptr< X86Operand > CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:648
llvm::X86Operand::RegOp::RegNo
unsigned RegNo
Definition: X86Operand.h:44
llvm::X86Operand::isMem16
bool isMem16() const
Definition: X86Operand.h:303
llvm::X86Operand::isMem32
bool isMem32() const
Definition: X86Operand.h:306
llvm::X86Operand::isMemOffs64_16
bool isMemOffs64_16() const
Definition: X86Operand.h:455
llvm::X86Operand::addMaskPairOperands
void addMaskPairOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:555
llvm::X86Operand::addAbsMemOperands
void addAbsMemOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:591
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::X86Operand::addMemOffsOperands
void addMemOffsOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:611
llvm::X86Operand::isDstIdx16
bool isDstIdx16() const
Definition: X86Operand.h:416
llvm::X86Operand::MemOp::ModeSize
unsigned ModeSize
Definition: X86Operand.h:64
llvm::X86Operand::OpDecl
void * OpDecl
Definition: X86Operand.h:35
llvm::X86Operand::isMem64_RC128X
bool isMem64_RC128X() const
Definition: X86Operand.h:350
llvm::X86Operand::addDstIdxOperands
void addDstIdxOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:606
MCInst.h
false
Definition: StackSlotColoring.cpp:142
llvm::X86Operand::Kind
enum llvm::X86Operand::KindTy Kind
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
SMLoc.h
llvm::X86Operand::TokOp::Data
const char * Data
Definition: X86Operand.h:39
llvm::isImmSExti64i8Value
bool isImmSExti64i8Value(uint64_t Value)
Definition: X86AsmParserCommon.h:26
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::X86Operand::isImm
bool isImm() const override
isImm - Is this an immediate operand?
Definition: X86Operand.h:209
llvm::X86Operand::SymName
StringRef SymName
Definition: X86Operand.h:34
llvm::X86Operand::CreateMem
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, StringRef SymName=StringRef(), void *OpDecl=nullptr, unsigned FrontendSize=0)
Create an absolute memory operand.
Definition: X86Operand.h:670
llvm::MCSymbol::getName
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:198
llvm::isImmUnsignedi8Value
bool isImmUnsignedi8Value(uint64_t Value)
Definition: X86AsmParserCommon.h:34
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:81
llvm::X86Operand::isVK1Pair
bool isVK1Pair() const
Definition: X86Operand.h:490
llvm::X86Operand::isDstIdx32
bool isDstIdx32() const
Definition: X86Operand.h:419
llvm::X86Operand::isImmSExti16i8
bool isImmSExti16i8() const
Definition: X86Operand.h:211
llvm::X86Operand::addGR16orGR32orGR64Operands
void addGR16orGR32orGR64Operands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:536
llvm::X86Operand::getLocRange
SMRange getLocRange() const
getLocRange - Get the range between the first and last token of this operand.
Definition: X86Operand.h:94
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::X86Operand::isSrcIdx64
bool isSrcIdx64() const
Definition: X86Operand.h:402
llvm::MCConstantExpr
Definition: MCExpr.h:144
llvm::X86Operand::isGR16orGR32orGR64
bool isGR16orGR32orGR64() const
Definition: X86Operand.h:475
llvm::X86Operand::ImmOp::LocalRef
bool LocalRef
Definition: X86Operand.h:53
llvm::X86Operand::Memory
@ Memory
Definition: X86Operand.h:30
llvm::X86Operand::isMemOffs64_32
bool isMemOffs64_32() const
Definition: X86Operand.h:458
llvm::X86Operand::MemOp::Disp
const MCExpr * Disp
Definition: X86Operand.h:58
llvm::X86Operand::isMem128_RC128
bool isMem128_RC128() const
Definition: X86Operand.h:337
llvm::X86Operand::isVK2Pair
bool isVK2Pair() const
Definition: X86Operand.h:495
llvm::X86Operand::isImmSExti64i8
bool isImmSExti64i8() const
Definition: X86Operand.h:239
llvm::isImmSExti16i8Value
bool isImmSExti16i8Value(uint64_t Value)
Definition: X86AsmParserCommon.h:16
llvm::X86Operand::getOpDecl
void * getOpDecl() override
Definition: X86Operand.h:84
llvm::X86Operand::ImmOp::Val
const MCExpr * Val
Definition: X86Operand.h:52
llvm::X86Operand::TokOp::Length
unsigned Length
Definition: X86Operand.h:40
llvm::X86Operand::getMemDefaultBaseReg
unsigned getMemDefaultBaseReg() const
Definition: X86Operand.h:186
X86MCTargetDesc.h
llvm::X86Operand::getMemDisp
const MCExpr * getMemDisp() const
Definition: X86Operand.h:174
llvm::X86Operand::Pref
struct PrefOp Pref
Definition: X86Operand.h:76
llvm::X86Operand::isMemOffs64_64
bool isMemOffs64_64() const
Definition: X86Operand.h:461
llvm::X86Operand::isAbsMem16
bool isAbsMem16() const
Definition: X86Operand.h:383
llvm::X86Operand::isVectorReg
bool isVectorReg() const
Definition: X86Operand.h:482
llvm::X86Operand
X86Operand - Instances of this class represent a parsed X86 machine instruction.
Definition: X86Operand.h:29
llvm::getX86SubSuperRegister
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:822
llvm::X86Operand::PrefOp::Prefixes
unsigned Prefixes
Definition: X86Operand.h:48
llvm::X86Operand::CreateImm
static std::unique_ptr< X86Operand > CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc, StringRef SymName=StringRef(), void *OpDecl=nullptr, bool GlobalRef=true)
Definition: X86Operand.h:654
llvm::X86Operand::KindTy
KindTy
Definition: X86Operand.h:30
llvm::X86Operand::isDstIdx64
bool isDstIdx64() const
Definition: X86Operand.h:422
llvm::X86Operand::isMemOffs16_16
bool isMemOffs16_16() const
Definition: X86Operand.h:434
llvm::X86Operand::TokOp
Definition: X86Operand.h:38
llvm::X86Operand::addSrcIdxOperands
void addSrcIdxOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:600
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::X86Operand::CreateDXReg
static std::unique_ptr< X86Operand > CreateDXReg(SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:643
llvm::X86Operand::isImmUnsignedi8
bool isImmUnsignedi8() const
Definition: X86Operand.h:277
llvm::X86Operand::isMem128_RC128X
bool isMem128_RC128X() const
Definition: X86Operand.h:353
llvm::X86Operand::isGR32orGR64
bool isGR32orGR64() const
Definition: X86Operand.h:469
llvm::X86Operand::Prefix
@ Prefix
Definition: X86Operand.h:30
llvm::X86Operand::MemOp::Size
unsigned Size
Definition: X86Operand.h:63
llvm::X86IntelInstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo)
llvm::X86Operand::getImm
const MCExpr * getImm() const
Definition: X86Operand.h:169
llvm::X86Operand::Tok
struct TokOp Tok
Definition: X86Operand.h:72
llvm::X86Operand::addExpr
void addExpr(MCInst &Inst, const MCExpr *Expr) const
Definition: X86Operand.h:515
llvm::X86Operand::isMem512_RC512
bool isMem512_RC512() const
Definition: X86Operand.h:371
llvm::X86Operand::MemOp::Scale
unsigned Scale
Definition: X86Operand.h:62
llvm::sys::Memory
This class provides various memory handling functions that manipulate MemoryBlock instances.
Definition: Memory.h:52
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::X86Operand::addRegOperands
void addRegOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:523
llvm::X86Operand::isVK16Pair
bool isVK16Pair() const
Definition: X86Operand.h:510
X86IntelInstPrinter.h
llvm::X86Operand::isSibMem
bool isSibMem() const
Definition: X86Operand.h:325
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::X86Operand::isMem64_RC128
bool isMem64_RC128() const
Definition: X86Operand.h:334
llvm::X86Operand::getReg
unsigned getReg() const override
Definition: X86Operand.h:159
llvm::X86Operand::isMem256_RC256
bool isMem256_RC256() const
Definition: X86Operand.h:346
llvm::X86Operand::addMemOperands
void addMemOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:579
llvm::X86Operand::Register
@ Register
Definition: X86Operand.h:30
llvm::X86Operand::isMem80
bool isMem80() const
Definition: X86Operand.h:312
llvm::X86Operand::X86Operand
X86Operand(KindTy K, SMLoc Start, SMLoc End)
Definition: X86Operand.h:79
llvm::X86Operand::getStartLoc
SMLoc getStartLoc() const override
getStartLoc - Get the location of the first token of this operand.
Definition: X86Operand.h:87
llvm::SMLoc::getPointer
const char * getPointer() const
Definition: SMLoc.h:34
llvm::X86Operand::DXRegister
@ DXRegister
Definition: X86Operand.h:30
llvm::X86Operand::getMemModeSize
unsigned getMemModeSize() const
Definition: X86Operand.h:198
Casting.h
llvm::X86Operand::isMemOffs64_8
bool isMemOffs64_8() const
Definition: X86Operand.h:452
llvm::X86Operand::isMem128
bool isMem128() const
Definition: X86Operand.h:315
llvm::X86Operand::MemOp::FrontendSize
unsigned FrontendSize
If the memory operand is unsized and there are multiple instruction matches, prefer the one with this...
Definition: X86Operand.h:68
llvm::X86Operand::addGR32orGR64Operands
void addGR32orGR64Operands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:528
llvm::X86Operand::isMem512
bool isMem512() const
Definition: X86Operand.h:321
llvm::X86Operand::isMemOffs16_8
bool isMemOffs16_8() const
Definition: X86Operand.h:431
llvm::X86Operand::isSrcIdx16
bool isSrcIdx16() const
Definition: X86Operand.h:396
llvm::X86Operand::AddressOf
bool AddressOf
Definition: X86Operand.h:36
llvm::X86Operand::CreateToken
static std::unique_ptr< X86Operand > CreateToken(StringRef Str, SMLoc Loc)
Definition: X86Operand.h:621
llvm::X86Operand::getToken
StringRef getToken() const
Definition: X86Operand.h:149
llvm::X86Operand::isDstIdx8
bool isDstIdx8() const
Definition: X86Operand.h:413
llvm::X86Operand::getMemBaseReg
unsigned getMemBaseReg() const
Definition: X86Operand.h:182
llvm::X86Operand::Immediate
@ Immediate
Definition: X86Operand.h:30
llvm::X86Operand::isMem256
bool isMem256() const
Definition: X86Operand.h:318
llvm::X86Operand::MemOp::DefaultBaseReg
unsigned DefaultBaseReg
Definition: X86Operand.h:60
llvm::X86Operand::MemOp::SegReg
unsigned SegReg
Definition: X86Operand.h:57
llvm::X86Operand::getMemFrontendSize
unsigned getMemFrontendSize() const
Definition: X86Operand.h:202
llvm::X86Operand::PrefOp
Definition: X86Operand.h:47
llvm::X86Operand::print
void print(raw_ostream &OS) const override
print - Print a debug representation of the operand to the given stream.
Definition: X86Operand.h:99
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
llvm::X86Operand::MemOp
Definition: X86Operand.h:56
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::X86Operand::EndLoc
SMLoc EndLoc
Definition: X86Operand.h:32
N
#define N
llvm::X86Operand::needAddressOf
bool needAddressOf() const override
needAddressOf - Do we need to emit code to get the address of the variable/label? Only valid when par...
Definition: X86Operand.h:294
llvm::MCExpr::Constant
@ Constant
Constant expressions.
Definition: MCExpr.h:39
llvm::X86Operand::isVK4Pair
bool isVK4Pair() const
Definition: X86Operand.h:500
llvm::X86Operand::CreateReg
static std::unique_ptr< X86Operand > CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc, bool AddressOf=false, SMLoc OffsetOfLoc=SMLoc(), StringRef SymName=StringRef(), void *OpDecl=nullptr)
Definition: X86Operand.h:630
llvm::X86Operand::isMemOffs
bool isMemOffs() const
Definition: X86Operand.h:426
llvm::X86Operand::ImmOp
Definition: X86Operand.h:51
llvm::X86Operand::CreateMem
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, unsigned DefaultBaseReg=X86::NoRegister, StringRef SymName=StringRef(), void *OpDecl=nullptr, unsigned FrontendSize=0)
Create a generalized memory operand.
Definition: X86Operand.h:691
llvm::StringRef::data
const LLVM_NODISCARD char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:149
llvm::X86Operand::isMemOffs32_16
bool isMemOffs32_16() const
Definition: X86Operand.h:443
llvm::SMLoc::getFromPointer
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
llvm::X86Operand::isPrefix
bool isPrefix() const
Definition: X86Operand.h:465
llvm::isImmSExti64i32Value
bool isImmSExti64i32Value(uint64_t Value)
Definition: X86AsmParserCommon.h:30
llvm::X86Operand::isMem512_RC256X
bool isMem512_RC256X() const
Definition: X86Operand.h:368
llvm::X86Operand::getSymName
StringRef getSymName() override
Definition: X86Operand.h:83
llvm::X86Operand::MemOp::BaseReg
unsigned BaseReg
Definition: X86Operand.h:59
llvm::X86Operand::isMemUnsized
bool isMemUnsized() const
Definition: X86Operand.h:297
llvm::X86Operand::Token
@ Token
Definition: X86Operand.h:30
llvm::X86Operand::getOffsetOfLoc
SMLoc getOffsetOfLoc() const override
getOffsetOfLoc - Get the location of the offset operator.
Definition: X86Operand.h:97
llvm::X86Operand::isMem128_RC256
bool isMem128_RC256() const
Definition: X86Operand.h:340
llvm::X86Operand::isMemOffs16_32
bool isMemOffs16_32() const
Definition: X86Operand.h:437
MCExpr.h
X86AsmParserCommon.h
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::X86Operand::getMemSegReg
unsigned getMemSegReg() const
Definition: X86Operand.h:178
llvm::X86Operand::isImmUnsignedi4
bool isImmUnsignedi4() const
Definition: X86Operand.h:268
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::X86Operand::RegOp
Definition: X86Operand.h:43
llvm::X86Operand::Reg
struct RegOp Reg
Definition: X86Operand.h:73
llvm::X86Operand::isMemOffs32_64
bool isMemOffs32_64() const
Definition: X86Operand.h:449
llvm::X86Operand::isMemOffs32_32
bool isMemOffs32_32() const
Definition: X86Operand.h:446
llvm::X86Operand::isToken
bool isToken() const override
isToken - Is this a token operand?
Definition: X86Operand.h:207
llvm::X86Operand::setTokenValue
void setTokenValue(StringRef Value)
Definition: X86Operand.h:153
llvm::X86Operand::isVK8Pair
bool isVK8Pair() const
Definition: X86Operand.h:505
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::X86Operand::isOffsetOfLocal
bool isOffsetOfLocal() const override
isOffsetOfLocal - Do we need to emit code to get the offset of the local variable,...
Definition: X86Operand.h:286
llvm::X86Operand::isAbsMem
bool isAbsMem() const
Definition: X86Operand.h:375