WebAssemblyISelLowering.cpp File Reference

This file implements the WebAssemblyTargetLowering class. More...

#include "WebAssemblyISelLowering.h"
#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
#include "Utils/WebAssemblyTypeUtilities.h"
#include "WebAssemblyMachineFunctionInfo.h"
#include "WebAssemblySubtarget.h"
#include "WebAssemblyTargetMachine.h"
#include "WebAssemblyUtilities.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SDPatternMatch.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsWebAssembly.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetOptions.h"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "wasm-lower"

Functions
static MachineBasicBlock *	LowerFPToInt (MachineInstr &MI, DebugLoc DL, MachineBasicBlock *BB, const TargetInstrInfo &TII, bool IsUnsigned, bool Int64, bool Float64, unsigned LoweredOpcode)
static MachineBasicBlock *	LowerMemcpy (MachineInstr &MI, DebugLoc DL, MachineBasicBlock *BB, const TargetInstrInfo &TII, bool Int64)
static MachineBasicBlock *	LowerMemset (MachineInstr &MI, DebugLoc DL, MachineBasicBlock *BB, const TargetInstrInfo &TII, bool Int64)
static MachineBasicBlock *	LowerCallResults (MachineInstr &CallResults, DebugLoc DL, MachineBasicBlock *BB, const WebAssemblySubtarget *Subtarget, const TargetInstrInfo &TII)
static void	fail (const SDLoc &DL, SelectionDAG &DAG, const char *Msg)
static bool	callingConvSupported (CallingConv::ID CallConv)
static bool	IsWebAssemblyGlobal (SDValue Op)
static std::optional< unsigned >	IsWebAssemblyLocal (SDValue Op, SelectionDAG &DAG)
static SDValue	GetExtendHigh (SDValue Op, unsigned UserOpc, EVT VT, SelectionDAG &DAG)
static SDValue	LowerConvertLow (SDValue Op, SelectionDAG &DAG)
static SDValue	unrollVectorShift (SDValue Op, SelectionDAG &DAG)
static bool	HasNoSignedZerosOrNaNs (SDValue Op, SelectionDAG &DAG)
static SDValue	performVECTOR_SHUFFLECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performVectorExtendToFPCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	Convert ({u,s}itofp vec) --> ({u,s}itofp ({s,z}ext vec)) so it doesn't get split up into scalar instructions during legalization, and the vector extending instructions are selected in performVectorExtendCombine below.
static SDValue	performVectorNonNegToFPCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performVectorExtendCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performVectorTruncZeroCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	extractSubVector (SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, const SDLoc &DL, unsigned VectorWidth)
static SDValue	truncateVectorWithNARROW (EVT DstVT, SDValue In, const SDLoc &DL, SelectionDAG &DAG)
static SDValue	performTruncateCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performBitcastCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performBitmaskCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performAnyAllCombine (SDNode *N, SelectionDAG &DAG)
template<int MatchRHS, ISD::CondCode MatchCond, bool RequiresNegate, Intrinsic::ID Intrin>
static SDValue	TryMatchTrue (SDNode *N, EVT VecVT, SelectionDAG &DAG)
static SDValue	combineVectorSizedSetCCEquality (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const WebAssemblySubtarget *Subtarget)
	Try to convert a i128 comparison to a v16i8 comparison before type legalization splits it up into chunks.
static SDValue	performSETCCCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const WebAssemblySubtarget *Subtarget)
static SDValue	TryWideExtMulCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performMulCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
SDValue	DoubleVectorWidth (SDValue In, unsigned RequiredNumElems, SelectionDAG &DAG)
SDValue	performConvertFPCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performShiftCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)

Detailed Description

This file implements the WebAssemblyTargetLowering class.

Definition in file WebAssemblyISelLowering.cpp.

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "wasm-lower"

Definition at line 42 of file WebAssemblyISelLowering.cpp.

Function Documentation

callingConvSupported()

bool callingConvSupported ( CallingConv::ID CallConv )

static

Definition at line 1264 of file WebAssemblyISelLowering.cpp.

References llvm::CallingConv::C, llvm::CallingConv::Cold, llvm::CallingConv::CXX_FAST_TLS, llvm::CallingConv::Fast, llvm::CallingConv::PreserveAll, llvm::CallingConv::PreserveMost, llvm::CallingConv::Swift, and llvm::CallingConv::WASM_EmscriptenInvoke.

combineVectorSizedSetCCEquality()

SDValue combineVectorSizedSetCCEquality ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const WebAssemblySubtarget * Subtarget )

static

Try to convert a i128 comparison to a v16i8 comparison before type legalization splits it up into chunks.

Definition at line 3437 of file WebAssemblyISelLowering.cpp.

References llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::Function::hasFnAttribute(), llvm::WebAssemblySubtarget::hasSIMD128(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), llvm::EVT::isByteSized(), llvm::EVT::isScalarInteger(), llvm::ISD::LOAD, N, llvm::peekThroughBitcasts(), SDValue(), llvm::ISD::SETEQ, llvm::ISD::SETNE, X, and Y.

DoubleVectorWidth()

SDValue DoubleVectorWidth	(	SDValue	In,
		unsigned	RequiredNumElems,
		SelectionDAG &	DAG )

Definition at line 3683 of file WebAssemblyISelLowering.cpp.

References Concat, llvm::ISD::CONCAT_VECTORS, DL, DoubleVectorWidth(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getPOISON(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::EVT::getVectorVT().

Referenced by DoubleVectorWidth(), and performConvertFPCombine().

extractSubVector()

SDValue extractSubVector ( SDValue Vec, unsigned IdxVal, SelectionDAG & DAG, const SDLoc & DL, unsigned VectorWidth )

static

Definition at line 3158 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::isPowerOf2_32(), and llvm::SDNode::ops().

Referenced by combineBROADCAST_LOAD(), combineConcatVectorOps(), combineConstantPoolLoads(), combineEXTRACT_SUBVECTOR(), combineLoad(), combineOr(), combineSCALAR_TO_VECTOR(), combineSelect(), combineTargetShuffle(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), createVariablePermute(), extract128BitVector(), extract256BitVector(), getAVX512Node(), getAVX512TruncNode(), getEXTEND_VECTOR_INREG(), getHopForBuildVector(), lowerBuildVectorAsBroadcast(), LowerEXTEND_VECTOR_INREG(), lowerShuffleAsBroadcast(), lowerShuffleWithPERMV(), performBitcastCombine(), performConvertFPCombine(), performMulCombine(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), SplitOpsAndApply(), splitVector(), truncateVectorWithNARROW(), and truncateVectorWithPACK().

fail()

void fail ( const SDLoc & DL, SelectionDAG & DAG, const char * Msg )

static

Definition at line 1257 of file WebAssemblyISelLowering.cpp.

References llvm::LLVMContext::diagnose(), DL, llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFunction(), and llvm::SelectionDAG::getMachineFunction().

GetExtendHigh()

SDValue GetExtendHigh ( SDValue Op, unsigned UserOpc, EVT VT, SelectionDAG & DAG )

static

Definition at line 2307 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::cast(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), Opc, llvm::peekThroughBitcasts(), SDValue(), and llvm::ISD::VECTOR_SHUFFLE.

Referenced by TryWideExtMulCombine().

HasNoSignedZerosOrNaNs()

bool HasNoSignedZerosOrNaNs ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 2889 of file WebAssemblyISelLowering.cpp.

References llvm::SelectionDAG::isKnownNeverNaN(), and llvm::SelectionDAG::isKnownNeverZeroFloat().

IsWebAssemblyGlobal()

bool IsWebAssemblyGlobal ( SDValue Op )

static

Definition at line 1792 of file WebAssemblyISelLowering.cpp.

References llvm::dyn_cast(), llvm::GlobalAddressSDNode::getAddressSpace(), and llvm::WebAssembly::isWasmVarAddressSpace().

IsWebAssemblyLocal()

std::optional< unsigned > IsWebAssemblyLocal ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 1799 of file WebAssemblyISelLowering.cpp.

References llvm::dyn_cast(), llvm::FrameIndexSDNode::getIndex(), llvm::WebAssemblyFrameLowering::getLocalForStackObject(), and llvm::SelectionDAG::getMachineFunction().

LowerCallResults()

MachineBasicBlock * LowerCallResults ( MachineInstr & CallResults, DebugLoc DL, MachineBasicBlock * BB, const WebAssemblySubtarget * Subtarget, const TargetInstrInfo & TII )

static

Definition at line 788 of file WebAssemblyISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addSym(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::defs(), DL, llvm::MachineInstr::eraseFromParent(), llvm::MachineFunction::getContext(), llvm::MachineInstrBuilder::getInstr(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::WebAssembly::getOrCreateFuncrefCallTableSymbol(), llvm::WebAssembly::getOrCreateFunctionTableSymbol(), llvm::MachineBasicBlock::getParent(), llvm::ilist_node_with_parent< NodeTy, ParentTy, Options >::getPrevNode(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::WebAssemblySubtarget::hasCallIndirectOverlong(), llvm::WebAssemblySubtarget::hasReferenceTypes(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::insertAfter(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isReg(), Reg, llvm::MachineInstr::removeOperand(), llvm::MCSymbolWasm::setNoStrip(), TII, and llvm::MachineInstr::uses().

LowerConvertLow()

SDValue LowerConvertLow ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 2389 of file WebAssemblyISelLowering.cpp.

References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::isa(), SDValue(), llvm::ISD::SINT_TO_FP, and llvm::ISD::UINT_TO_FP.

LowerFPToInt()

MachineBasicBlock * LowerFPToInt ( MachineInstr & MI, DebugLoc DL, MachineBasicBlock * BB, const TargetInstrInfo & TII, bool IsUnsigned, bool Int64, bool Float64, unsigned LoweredOpcode )

static

Definition at line 517 of file WebAssemblyISelLowering.cpp.

References llvm::MachineInstrBuilder::addFPImm(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::cast(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::MachineBasicBlock::end(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::Function::getContext(), llvm::Type::getDoubleTy(), llvm::Type::getFloatTy(), llvm::MachineFunction::getFunction(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), INT64_MIN, MI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

LowerMemcpy()

MachineBasicBlock * LowerMemcpy ( MachineInstr & MI, DebugLoc DL, MachineBasicBlock * BB, const TargetInstrInfo & TII, bool Int64 )

static

Definition at line 612 of file WebAssemblyISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::MachineBasicBlock::end(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getVRegDef(), MI, llvm::MachineOperand::setIsKill(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

LowerMemset()

MachineBasicBlock * LowerMemset ( MachineInstr & MI, DebugLoc DL, MachineBasicBlock * BB, const TargetInstrInfo & TII, bool Int64 )

static

Definition at line 704 of file WebAssemblyISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::MachineBasicBlock::end(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getVRegDef(), MI, llvm::MachineOperand::setIsKill(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

performAnyAllCombine()

SDValue performAnyAllCombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 3358 of file WebAssemblyISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::ISD::INTRINSIC_WO_CHAIN, LHS, llvm::SDPatternMatch::m_c_SetCC(), llvm::SDPatternMatch::m_CondCode(), llvm::SDPatternMatch::m_SpecificCondCode(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SETEQ, llvm::ISD::SETNE, and llvm::ISD::XOR.

performBitcastCombine()

SDValue performBitcastCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 3265 of file WebAssemblyISelLowering.cpp.

References llvm::ISD::ADD, Concat, llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, extractSubVector(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::EVT::getFixedSizeInBits(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), I, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isScalarInteger(), llvm::PatternMatch::m_BitCast(), llvm::SDPatternMatch::m_c_SetCC(), llvm::SDPatternMatch::m_CondCode(), llvm::PatternMatch::m_Value(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SHL, llvm::size(), and llvm::SmallVectorTemplateCommon< T, typename >::size().

performBitmaskCombine()

SDValue performBitmaskCombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 3339 of file WebAssemblyISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, LHS, llvm::SDPatternMatch::m_c_SetCC(), llvm::SDPatternMatch::m_SpecificCondCode(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), N, llvm::SDPatternMatch::sd_match(), SDValue(), and llvm::ISD::SETLT.

performConvertFPCombine()

SDValue performConvertFPCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

Definition at line 3698 of file WebAssemblyISelLowering.cpp.

References llvm::ISD::AND, DL, DoubleVectorWidth(), extractSubVector(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::isPowerOf2_32(), llvm::EVT::isVector(), llvm::Masked, N, SDValue(), and truncateVectorWithNARROW().

performMulCombine()

SDValue performMulCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 3625 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, extractSubVector(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::isVector(), LHS, llvm::ISD::MUL, N, RHS, SDValue(), and TryWideExtMulCombine().

performSETCCCombine()

SDValue performSETCCCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const WebAssemblySubtarget * Subtarget )

static

Definition at line 3481 of file WebAssemblyISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::cast(), llvm::EVT::changeVectorElementType(), combineVectorSizedSetCCEquality(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getContext(), llvm::MVT::getIntegerVT(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isScalarInteger(), LHS, N, SDValue(), and TryMatchTrue().

performShiftCombine()

SDValue performShiftCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 3753 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::BitWidth, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), I, LHS, llvm::ISD::MUL, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), RHS, SDValue(), llvm::ISD::SHL, llvm::APInt::shl(), llvm::ISD::SIGN_EXTEND, llvm::APInt::uge(), and llvm::ISD::ZERO_EXTEND.

performTruncateCombine()

SDValue performTruncateCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 3238 of file WebAssemblyISelLowering.cpp.

References llvm::ISD::AND, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::is128BitVector(), llvm::EVT::isSimple(), llvm::EVT::isVector(), N, SDValue(), and truncateVectorWithNARROW().

performVECTOR_SHUFFLECombine()

SDValue performVECTOR_SHUFFLECombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 2920 of file WebAssemblyISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), N, and SDValue().

performVectorExtendCombine()

SDValue performVectorExtendCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 2990 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), N, SDValue(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

performVectorExtendToFPCombine()

SDValue performVectorExtendToFPCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Convert ({u,s}itofp vec) --> ({u,s}itofp ({s,z}ext vec)) so it doesn't get split up into scalar instructions during legalization, and the vector extending instructions are selected in performVectorExtendCombine below.

Definition at line 2948 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), N, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, and llvm::ISD::ZERO_EXTEND.

performVectorNonNegToFPCombine()

SDValue performVectorNonNegToFPCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 2971 of file WebAssemblyISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::EVT::isVector(), N, SDValue(), llvm::SelectionDAG::SignBitIsZero(), and llvm::ISD::SINT_TO_FP.

performVectorTruncZeroCombine()

SDValue performVectorTruncZeroCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 3037 of file WebAssemblyISelLowering.cpp.

References Concat, llvm::ISD::CONCAT_VECTORS, Conversion, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT_SAT, llvm::ISD::FP_TO_UINT_SAT, llvm::SelectionDAG::getNode(), llvm_unreachable, N, SDValue(), and llvm::Splat.

truncateVectorWithNARROW()

SDValue truncateVectorWithNARROW ( EVT DstVT, SDValue In, const SDLoc & DL, SelectionDAG & DAG )

static

Definition at line 3187 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::ISD::CONCAT_VECTORS, DL, extractSubVector(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::Hi, llvm::EVT::is128BitVector(), llvm::EVT::is256BitVector(), llvm::isPowerOf2_32(), llvm::Lo, SDValue(), and truncateVectorWithNARROW().

Referenced by performConvertFPCombine(), performTruncateCombine(), and truncateVectorWithNARROW().

TryMatchTrue()

template<int MatchRHS, ISD::CondCode MatchCond, bool RequiresNegate, Intrinsic::ID Intrin>

SDValue TryMatchTrue ( SDNode * N, EVT VecVT, SelectionDAG & DAG )

static

Definition at line 3413 of file WebAssemblyISelLowering.cpp.

References llvm::cast(), Cond, DL, llvm::get(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::ISD::INTRINSIC_WO_CHAIN, LHS, N, RHS, SDValue(), and llvm::ISD::XOR.

Referenced by performSETCCCombine().

TryWideExtMulCombine()

SDValue TryWideExtMulCombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 3539 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::ISD::CONCAT_VECTORS, DL, GetExtendHigh(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::Hi, LHS, llvm::Lo, llvm::ISD::MUL, N, RHS, SDValue(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by performMulCombine().

unrollVectorShift()

SDValue unrollVectorShift ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 2779 of file WebAssemblyISelLowering.cpp.

References llvm::ISD::AND, llvm::EVT::bitsGE(), DL, llvm::SelectionDAG::ExtractVectorElements(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getValueType(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, and llvm::SelectionDAG::UnrollVectorOp().