LLVM 19.0.0git
WebAssemblyISelLowering.h
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1//- WebAssemblyISelLowering.h - WebAssembly DAG Lowering Interface -*- C++ -*-//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file defines the interfaces that WebAssembly uses to lower LLVM
11/// code into a selection DAG.
12///
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
16#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
17
19
20namespace llvm {
21
22namespace WebAssemblyISD {
23
24enum NodeType : unsigned {
26#define HANDLE_NODETYPE(NODE) NODE,
27#define HANDLE_MEM_NODETYPE(NODE)
28#include "WebAssemblyISD.def"
30#undef HANDLE_NODETYPE
31#undef HANDLE_MEM_NODETYPE
32#define HANDLE_NODETYPE(NODE)
33#define HANDLE_MEM_NODETYPE(NODE) NODE,
34#include "WebAssemblyISD.def"
35#undef HANDLE_NODETYPE
36#undef HANDLE_MEM_NODETYPE
37};
38
39} // end namespace WebAssemblyISD
40
41class WebAssemblySubtarget;
42
44public:
46 const WebAssemblySubtarget &STI);
47
48 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override;
49 MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const override;
50
51private:
52 /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
53 /// right decision when generating code for different targets.
54 const WebAssemblySubtarget *Subtarget;
55
56 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
57 bool shouldScalarizeBinop(SDValue VecOp) const override;
58 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
59 const TargetLibraryInfo *LibInfo) const override;
60 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
62 EmitInstrWithCustomInserter(MachineInstr &MI,
63 MachineBasicBlock *MBB) const override;
64 const char *getTargetNodeName(unsigned Opcode) const override;
65 std::pair<unsigned, const TargetRegisterClass *>
66 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
67 StringRef Constraint, MVT VT) const override;
68 bool isCheapToSpeculateCttz(Type *Ty) const override;
69 bool isCheapToSpeculateCtlz(Type *Ty) const override;
70 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
71 unsigned AS,
72 Instruction *I = nullptr) const override;
73 bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, Align Alignment,
75 unsigned *Fast) const override;
76 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
77 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
78 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
79 bool shouldSinkOperands(Instruction *I,
80 SmallVectorImpl<Use *> &Ops) const override;
81 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
82 EVT VT) const override;
83 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
85 unsigned Intrinsic) const override;
86
87 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
88 const APInt &DemandedElts,
89 const SelectionDAG &DAG,
90 unsigned Depth) const override;
91
93 getPreferredVectorAction(MVT VT) const override;
94
95 SDValue LowerCall(CallLoweringInfo &CLI,
96 SmallVectorImpl<SDValue> &InVals) const override;
97 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
98 bool isVarArg,
100 LLVMContext &Context) const override;
101 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
103 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
104 SelectionDAG &DAG) const override;
105 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
106 bool IsVarArg,
108 const SDLoc &DL, SelectionDAG &DAG,
109 SmallVectorImpl<SDValue> &InVals) const override;
110
111 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
112 SelectionDAG &DAG) const override;
113
114 bool
115 shouldSimplifyDemandedVectorElts(SDValue Op,
116 const TargetLoweringOpt &TLO) const override;
117
118 // Custom lowering hooks.
119 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
120 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerIntrinsic(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerEXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerAccessVectorElement(SDValue Op, SelectionDAG &DAG) const;
137 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
141
142 // Custom DAG combine hooks
143 SDValue
144 PerformDAGCombine(SDNode *N,
145 TargetLowering::DAGCombinerInfo &DCI) const override;
146};
147
148namespace WebAssembly {
150 const TargetLibraryInfo *libInfo);
151} // end namespace WebAssembly
152
153} // end namespace llvm
154
155#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
Definition: APInt.h:78
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:696
This class represents a function call, abstracting a target machine's calling convention.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:69
Flags
Flags values. These may be or'd together.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:227
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Provides information about what library functions are available for the current target.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const override
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1443
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1455
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...
This structure contains all information that is necessary for lowering calls.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...