LLVM  10.0.0svn
WebAssemblyISelLowering.h
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1 //- WebAssemblyISelLowering.h - WebAssembly DAG Lowering Interface -*- C++ -*-//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the interfaces that WebAssembly uses to lower LLVM
11 /// code into a selection DAG.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
16 #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
17 
19 
20 namespace llvm {
21 
22 namespace WebAssemblyISD {
23 
24 enum NodeType : unsigned {
26 #define HANDLE_NODETYPE(NODE) NODE,
27 #include "WebAssemblyISD.def"
28 #undef HANDLE_NODETYPE
29 };
30 
31 } // end namespace WebAssemblyISD
32 
33 class WebAssemblySubtarget;
34 class WebAssemblyTargetMachine;
35 
37 public:
39  const WebAssemblySubtarget &STI);
40 
41 private:
42  /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
43  /// right decision when generating code for different targets.
44  const WebAssemblySubtarget *Subtarget;
45 
46  AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
48  const TargetLibraryInfo *LibInfo) const override;
49  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
51  EmitInstrWithCustomInserter(MachineInstr &MI,
52  MachineBasicBlock *MBB) const override;
53  const char *getTargetNodeName(unsigned Opcode) const override;
54  std::pair<unsigned, const TargetRegisterClass *>
55  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
56  StringRef Constraint, MVT VT) const override;
57  bool isCheapToSpeculateCttz() const override;
58  bool isCheapToSpeculateCtlz() const override;
59  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
60  unsigned AS,
61  Instruction *I = nullptr) const override;
62  bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, unsigned Align,
64  bool *Fast) const override;
65  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
66 
67  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
68  EVT VT) const override;
69  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
70  MachineFunction &MF,
71  unsigned Intrinsic) const override;
72 
73  SDValue LowerCall(CallLoweringInfo &CLI,
74  SmallVectorImpl<SDValue> &InVals) const override;
75  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
76  bool isVarArg,
78  LLVMContext &Context) const override;
79  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
81  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
82  SelectionDAG &DAG) const override;
83  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
84  bool IsVarArg,
86  const SDLoc &DL, SelectionDAG &DAG,
87  SmallVectorImpl<SDValue> &InVals) const override;
88 
89  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
90  SelectionDAG &DAG) const override;
91 
92  const char *getClearCacheBuiltinName() const override {
93  report_fatal_error("llvm.clear_cache is not supported on wasm");
94  }
95 
96  // Custom lowering hooks.
97  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
98  SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
100  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
101  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
102  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
103  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
104  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
105  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
106  SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
107  SDValue LowerIntrinsic(SDValue Op, SelectionDAG &DAG) const;
108  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
109  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
111  SDValue LowerAccessVectorElement(SDValue Op, SelectionDAG &DAG) const;
112  SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
113 };
114 
115 namespace WebAssembly {
117  const TargetLibraryInfo *libInfo);
118 } // end namespace WebAssembly
119 
120 } // end namespace llvm
121 
122 #endif
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:913
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
This class represents a function call, abstracting a target machine&#39;s calling convention.
Function Alias Analysis Results
unsigned const TargetRegisterInfo * TRI
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:693
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
Provides information about what library functions are available for the current target.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Flags
Flags values. These may be or&#39;d together.
Representation of each machine instruction.
Definition: MachineInstr.h:64
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.