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WebAssemblyISelLowering.h
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1 //- WebAssemblyISelLowering.h - WebAssembly DAG Lowering Interface -*- C++ -*-//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the interfaces that WebAssembly uses to lower LLVM
11 /// code into a selection DAG.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
16 #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
17 
18 #include "llvm/CodeGen/TargetLowering.h"
19 
20 namespace llvm {
21 
22 namespace WebAssemblyISD {
23 
24 enum NodeType : unsigned {
25  FIRST_NUMBER = ISD::BUILTIN_OP_END,
26 #define HANDLE_NODETYPE(NODE) NODE,
27 #define HANDLE_MEM_NODETYPE(NODE)
28 #include "WebAssemblyISD.def"
29  FIRST_MEM_OPCODE = ISD::FIRST_TARGET_MEMORY_OPCODE,
30 #undef HANDLE_NODETYPE
31 #undef HANDLE_MEM_NODETYPE
32 #define HANDLE_NODETYPE(NODE)
33 #define HANDLE_MEM_NODETYPE(NODE) NODE,
34 #include "WebAssemblyISD.def"
35 #undef HANDLE_NODETYPE
36 #undef HANDLE_MEM_NODETYPE
37 };
38 
39 } // end namespace WebAssemblyISD
40 
41 class WebAssemblySubtarget;
42 
43 class WebAssemblyTargetLowering final : public TargetLowering {
44 public:
45  WebAssemblyTargetLowering(const TargetMachine &TM,
46  const WebAssemblySubtarget &STI);
47 
48  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override;
49  MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const override;
50 
51 private:
52  /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
53  /// right decision when generating code for different targets.
54  const WebAssemblySubtarget *Subtarget;
55 
56  AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
57  bool shouldScalarizeBinop(SDValue VecOp) const override;
58  FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
59  const TargetLibraryInfo *LibInfo) const override;
60  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
61  MachineBasicBlock *
62  EmitInstrWithCustomInserter(MachineInstr &MI,
63  MachineBasicBlock *MBB) const override;
64  const char *getTargetNodeName(unsigned Opcode) const override;
65  std::pair<unsigned, const TargetRegisterClass *>
66  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
67  StringRef Constraint, MVT VT) const override;
68  bool isCheapToSpeculateCttz(Type *Ty) const override;
69  bool isCheapToSpeculateCtlz(Type *Ty) const override;
70  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
71  unsigned AS,
72  Instruction *I = nullptr) const override;
73  bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, Align Alignment,
74  MachineMemOperand::Flags Flags,
75  unsigned *Fast) const override;
76  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
77  bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
78  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
79  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
80  EVT VT) const override;
81  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
82  MachineFunction &MF,
83  unsigned Intrinsic) const override;
84 
85  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
86  const APInt &DemandedElts,
87  const SelectionDAG &DAG,
88  unsigned Depth) const override;
89 
90  TargetLoweringBase::LegalizeTypeAction
91  getPreferredVectorAction(MVT VT) const override;
92 
93  SDValue LowerCall(CallLoweringInfo &CLI,
94  SmallVectorImpl<SDValue> &InVals) const override;
95  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
96  bool isVarArg,
97  const SmallVectorImpl<ISD::OutputArg> &Outs,
98  LLVMContext &Context) const override;
99  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
100  const SmallVectorImpl<ISD::OutputArg> &Outs,
101  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
102  SelectionDAG &DAG) const override;
103  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
104  bool IsVarArg,
105  const SmallVectorImpl<ISD::InputArg> &Ins,
106  const SDLoc &DL, SelectionDAG &DAG,
107  SmallVectorImpl<SDValue> &InVals) const override;
108 
109  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
110  SelectionDAG &DAG) const override;
111 
112  const char *getClearCacheBuiltinName() const override {
113  report_fatal_error("llvm.clear_cache is not supported on wasm");
114  }
115 
116  bool
117  shouldSimplifyDemandedVectorElts(SDValue Op,
118  const TargetLoweringOpt &TLO) const override;
119 
120  // Custom lowering hooks.
121  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
122  SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
123  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
124  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
125  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
126  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
127  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
128  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
129  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
130  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
131  SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
132  SDValue LowerIntrinsic(SDValue Op, SelectionDAG &DAG) const;
133  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
134  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
135  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
136  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
137  SDValue LowerAccessVectorElement(SDValue Op, SelectionDAG &DAG) const;
138  SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
139  SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
140  SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
141  SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
142 
143  // Helper for LoadLoad and LowerStore
144  bool MatchTableForLowering(SelectionDAG &DAG, const SDLoc &DL,
145  const SDValue &Base, GlobalAddressSDNode *&GA,
146  SDValue &Idx) const;
147 
148  // Custom DAG combine hooks
149  SDValue
150  PerformDAGCombine(SDNode *N,
151  TargetLowering::DAGCombinerInfo &DCI) const override;
152 };
153 
154 namespace WebAssembly {
155 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
156  const TargetLibraryInfo *libInfo);
157 } // end namespace WebAssembly
158 
159 } // end namespace llvm
160 
161 #endif
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:114
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::WebAssemblyISD::NodeType
NodeType
Definition: WebAssemblyISelLowering.h:24
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::AttributeList
Definition: Attributes.h:432
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:769
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering
WebAssemblyTargetLowering(const TargetMachine &TM, const WebAssemblySubtarget &STI)
Definition: WebAssemblyISelLowering.cpp:45
llvm::WebAssemblyTargetLowering
Definition: WebAssemblyISelLowering.h:43
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
TargetLowering.h
llvm::WebAssembly::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: WebAssemblyFastISel.cpp:1432
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3510
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3928
llvm::Instruction
Definition: Instruction.h:41
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::TargetLowering::TargetLoweringOpt
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
Definition: TargetLowering.h:3649
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::WebAssemblyISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: WebAssemblyISelLowering.h:25
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:4170
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::WebAssemblyTargetLowering::getPointerTy
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: WebAssemblyISelLowering.cpp:352
uint32_t
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::WebAssemblySubtarget
Definition: WebAssemblySubtarget.h:35
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1311
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetLoweringBase::IntrinsicInfo
Definition: TargetLowering.h:1045
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1763
llvm::KnownBits
Definition: KnownBits.h:23
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:250
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:354
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:206
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:234
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::WebAssemblyTargetLowering::getPointerMemTy
MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const override
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
Definition: WebAssemblyISelLowering.cpp:361
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1323
N
#define N
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2592
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1485
llvm::WebAssemblyISD::FIRST_MEM_OPCODE
@ FIRST_MEM_OPCODE
Definition: WebAssemblyISelLowering.h:29
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
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