LLVM  14.0.0git
AVRISelLowering.cpp
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1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that AVR uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRISelLowering.h"
15 
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/IR/Function.h"
26 
27 #include "AVR.h"
28 #include "AVRMachineFunctionInfo.h"
29 #include "AVRSubtarget.h"
30 #include "AVRTargetMachine.h"
32 
33 namespace llvm {
34 
36  const AVRSubtarget &STI)
37  : TargetLowering(TM), Subtarget(STI) {
38  // Set up the register classes.
39  addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
40  addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
41 
42  // Compute derived properties from the register classes.
44 
50 
53 
58 
59  for (MVT VT : MVT::integer_valuetypes()) {
60  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
63  }
64  }
65 
67 
68  for (MVT VT : MVT::integer_valuetypes()) {
73  }
74 
75  // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
76  // revert into a sub since we don't have an add with immediate instruction.
79 
80  // our shift instructions are only able to shift 1 bit at a time, so handle
81  // this in a custom way.
91 
96 
102 
113 
115 
116  // Add support for postincrement and predecrement load/stores.
125 
127 
132 
133  // Atomic operations which must be lowered to rtlib calls
134  for (MVT VT : MVT::integer_valuetypes()) {
142  }
143 
144  // Division/remainder
153 
154  // Make division and modulus custom
161 
162  // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
165 
166  // Expand 16 bit multiplications.
169 
170  // Expand multiplications to libcalls when there is
171  // no hardware MUL.
175  }
176 
177  for (MVT VT : MVT::integer_valuetypes()) {
180  }
181 
182  for (MVT VT : MVT::integer_valuetypes()) {
186  }
187 
188  for (MVT VT : MVT::integer_valuetypes()) {
190  // TODO: The generated code is pretty poor. Investigate using the
191  // same "shift and subtract with carry" trick that we do for
192  // extending 8-bit to 16-bit. This may require infrastructure
193  // improvements in how we treat 16-bit "registers" to be feasible.
194  }
195 
196  // Division rtlib functions (not supported), use divmod functions instead
197  setLibcallName(RTLIB::SDIV_I8, nullptr);
198  setLibcallName(RTLIB::SDIV_I16, nullptr);
199  setLibcallName(RTLIB::SDIV_I32, nullptr);
200  setLibcallName(RTLIB::UDIV_I8, nullptr);
201  setLibcallName(RTLIB::UDIV_I16, nullptr);
202  setLibcallName(RTLIB::UDIV_I32, nullptr);
203 
204  // Modulus rtlib functions (not supported), use divmod functions instead
205  setLibcallName(RTLIB::SREM_I8, nullptr);
206  setLibcallName(RTLIB::SREM_I16, nullptr);
207  setLibcallName(RTLIB::SREM_I32, nullptr);
208  setLibcallName(RTLIB::UREM_I8, nullptr);
209  setLibcallName(RTLIB::UREM_I16, nullptr);
210  setLibcallName(RTLIB::UREM_I32, nullptr);
211 
212  // Division and modulus rtlib functions
213  setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
214  setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
215  setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
216  setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
217  setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
218  setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
219 
220  // Several of the runtime library functions use a special calling conv
222  setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
224  setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
225 
226  // Trigonometric rtlib functions
227  setLibcallName(RTLIB::SIN_F32, "sin");
228  setLibcallName(RTLIB::COS_F32, "cos");
229 
231  setMinimumJumpTableEntries(UINT_MAX);
232 }
233 
234 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
235 #define NODE(name) \
236  case AVRISD::name: \
237  return #name
238 
239  switch (Opcode) {
240  default:
241  return nullptr;
242  NODE(RET_FLAG);
243  NODE(RETI_FLAG);
244  NODE(CALL);
245  NODE(WRAPPER);
246  NODE(LSL);
247  NODE(LSR);
248  NODE(ROL);
249  NODE(ROR);
250  NODE(ASR);
251  NODE(LSLLOOP);
252  NODE(LSRLOOP);
253  NODE(ROLLOOP);
254  NODE(RORLOOP);
255  NODE(ASRLOOP);
256  NODE(BRCOND);
257  NODE(CMP);
258  NODE(CMPC);
259  NODE(TST);
260  NODE(SELECT_CC);
261 #undef NODE
262  }
263 }
264 
266  EVT VT) const {
267  assert(!VT.isVector() && "No AVR SetCC type for vectors!");
268  return MVT::i8;
269 }
270 
271 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
272  //: TODO: this function has to be completely rewritten to produce optimal
273  // code, for now it's producing very long but correct code.
274  unsigned Opc8;
275  const SDNode *N = Op.getNode();
276  EVT VT = Op.getValueType();
277  SDLoc dl(N);
279  "Expected power-of-2 shift amount");
280 
281  // Expand non-constant shifts to loops.
282  if (!isa<ConstantSDNode>(N->getOperand(1))) {
283  switch (Op.getOpcode()) {
284  default:
285  llvm_unreachable("Invalid shift opcode!");
286  case ISD::SHL:
287  return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
288  N->getOperand(1));
289  case ISD::SRL:
290  return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
291  N->getOperand(1));
292  case ISD::ROTL: {
293  SDValue Amt = N->getOperand(1);
294  EVT AmtVT = Amt.getValueType();
295  Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
296  DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
297  return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
298  }
299  case ISD::ROTR: {
300  SDValue Amt = N->getOperand(1);
301  EVT AmtVT = Amt.getValueType();
302  Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
303  DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
304  return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
305  }
306  case ISD::SRA:
307  return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
308  N->getOperand(1));
309  }
310  }
311 
312  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
313  SDValue Victim = N->getOperand(0);
314 
315  switch (Op.getOpcode()) {
316  case ISD::SRA:
317  Opc8 = AVRISD::ASR;
318  break;
319  case ISD::ROTL:
320  Opc8 = AVRISD::ROL;
321  ShiftAmount = ShiftAmount % VT.getSizeInBits();
322  break;
323  case ISD::ROTR:
324  Opc8 = AVRISD::ROR;
325  ShiftAmount = ShiftAmount % VT.getSizeInBits();
326  break;
327  case ISD::SRL:
328  Opc8 = AVRISD::LSR;
329  break;
330  case ISD::SHL:
331  Opc8 = AVRISD::LSL;
332  break;
333  default:
334  llvm_unreachable("Invalid shift opcode");
335  }
336 
337  // Optimize int8/int16 shifts.
338  if (VT.getSizeInBits() == 8) {
339  if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
340  // Optimize LSL when 4 <= ShiftAmount <= 6.
341  Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
342  Victim =
343  DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT));
344  ShiftAmount -= 4;
345  } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
346  ShiftAmount < 7) {
347  // Optimize LSR when 4 <= ShiftAmount <= 6.
348  Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
349  Victim =
350  DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT));
351  ShiftAmount -= 4;
352  } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
353  // Optimize LSL when ShiftAmount == 7.
354  Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim,
355  DAG.getConstant(7, dl, VT));
356  ShiftAmount = 0;
357  } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
358  // Optimize LSR when ShiftAmount == 7.
359  Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim,
360  DAG.getConstant(7, dl, VT));
361  ShiftAmount = 0;
362  } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) {
363  // Optimize ASR when ShiftAmount == 6.
364  Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
365  DAG.getConstant(6, dl, VT));
366  ShiftAmount = 0;
367  } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
368  // Optimize ASR when ShiftAmount == 7.
369  Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
370  DAG.getConstant(7, dl, VT));
371  ShiftAmount = 0;
372  }
373  } else if (VT.getSizeInBits() == 16) {
374  if (4 <= ShiftAmount && ShiftAmount < 8)
375  switch (Op.getOpcode()) {
376  case ISD::SHL:
377  Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
378  DAG.getConstant(4, dl, VT));
379  ShiftAmount -= 4;
380  break;
381  case ISD::SRL:
382  Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
383  DAG.getConstant(4, dl, VT));
384  ShiftAmount -= 4;
385  break;
386  default:
387  break;
388  }
389  else if (8 <= ShiftAmount && ShiftAmount < 12)
390  switch (Op.getOpcode()) {
391  case ISD::SHL:
392  Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
393  DAG.getConstant(8, dl, VT));
394  ShiftAmount -= 8;
395  // Only operate on the higher byte for remaining shift bits.
396  Opc8 = AVRISD::LSLHI;
397  break;
398  case ISD::SRL:
399  Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
400  DAG.getConstant(8, dl, VT));
401  ShiftAmount -= 8;
402  // Only operate on the lower byte for remaining shift bits.
403  Opc8 = AVRISD::LSRLO;
404  break;
405  case ISD::SRA:
406  Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
407  DAG.getConstant(8, dl, VT));
408  ShiftAmount -= 8;
409  // Only operate on the lower byte for remaining shift bits.
410  Opc8 = AVRISD::ASRLO;
411  break;
412  default:
413  break;
414  }
415  else if (12 <= ShiftAmount)
416  switch (Op.getOpcode()) {
417  case ISD::SHL:
418  Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
419  DAG.getConstant(12, dl, VT));
420  ShiftAmount -= 12;
421  // Only operate on the higher byte for remaining shift bits.
422  Opc8 = AVRISD::LSLHI;
423  break;
424  case ISD::SRL:
425  Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
426  DAG.getConstant(12, dl, VT));
427  ShiftAmount -= 12;
428  // Only operate on the lower byte for remaining shift bits.
429  Opc8 = AVRISD::LSRLO;
430  break;
431  case ISD::SRA:
432  Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
433  DAG.getConstant(8, dl, VT));
434  ShiftAmount -= 8;
435  // Only operate on the lower byte for remaining shift bits.
436  Opc8 = AVRISD::ASRLO;
437  break;
438  default:
439  break;
440  }
441  }
442 
443  while (ShiftAmount--) {
444  Victim = DAG.getNode(Opc8, dl, VT, Victim);
445  }
446 
447  return Victim;
448 }
449 
450 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
451  unsigned Opcode = Op->getOpcode();
452  assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
453  "Invalid opcode for Div/Rem lowering");
454  bool IsSigned = (Opcode == ISD::SDIVREM);
455  EVT VT = Op->getValueType(0);
456  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
457 
458  RTLIB::Libcall LC;
459  switch (VT.getSimpleVT().SimpleTy) {
460  default:
461  llvm_unreachable("Unexpected request for libcall!");
462  case MVT::i8:
463  LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
464  break;
465  case MVT::i16:
466  LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
467  break;
468  case MVT::i32:
469  LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
470  break;
471  }
472 
473  SDValue InChain = DAG.getEntryNode();
474 
476  TargetLowering::ArgListEntry Entry;
477  for (SDValue const &Value : Op->op_values()) {
478  Entry.Node = Value;
479  Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
480  Entry.IsSExt = IsSigned;
481  Entry.IsZExt = !IsSigned;
482  Args.push_back(Entry);
483  }
484 
485  SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
486  getPointerTy(DAG.getDataLayout()));
487 
488  Type *RetTy = (Type *)StructType::get(Ty, Ty);
489 
490  SDLoc dl(Op);
491  TargetLowering::CallLoweringInfo CLI(DAG);
492  CLI.setDebugLoc(dl)
493  .setChain(InChain)
494  .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
495  .setInRegister()
496  .setSExtResult(IsSigned)
497  .setZExtResult(!IsSigned);
498 
499  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
500  return CallInfo.first;
501 }
502 
503 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
504  SelectionDAG &DAG) const {
505  auto DL = DAG.getDataLayout();
506 
507  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
508  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
509 
510  // Create the TargetGlobalAddress node, folding in the constant offset.
511  SDValue Result =
512  DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
513  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
514 }
515 
516 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
517  SelectionDAG &DAG) const {
518  auto DL = DAG.getDataLayout();
519  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
520 
521  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
522 
523  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
524 }
525 
526 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
528  switch (CC) {
529  default:
530  llvm_unreachable("Unknown condition code!");
531  case ISD::SETEQ:
532  return AVRCC::COND_EQ;
533  case ISD::SETNE:
534  return AVRCC::COND_NE;
535  case ISD::SETGE:
536  return AVRCC::COND_GE;
537  case ISD::SETLT:
538  return AVRCC::COND_LT;
539  case ISD::SETUGE:
540  return AVRCC::COND_SH;
541  case ISD::SETULT:
542  return AVRCC::COND_LO;
543  }
544 }
545 
546 /// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
547 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
548  SelectionDAG &DAG, SDLoc DL) const {
549  assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
550  "LHS and RHS have different types");
551  assert(((LHS.getSimpleValueType() == MVT::i16) ||
552  (LHS.getSimpleValueType() == MVT::i8)) &&
553  "invalid comparison type");
554 
555  SDValue Cmp;
556 
557  if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) {
558  // Generate a CPI/CPC pair if RHS is a 16-bit constant.
559  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
560  DAG.getIntPtrConstant(0, DL));
561  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
562  DAG.getIntPtrConstant(1, DL));
563  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
564  DAG.getIntPtrConstant(0, DL));
565  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
566  DAG.getIntPtrConstant(1, DL));
567  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
568  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
569  } else {
570  // Generate ordinary 16-bit comparison.
571  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
572  }
573 
574  return Cmp;
575 }
576 
577 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
578 /// the given operands.
579 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
580  SDValue &AVRcc, SelectionDAG &DAG,
581  SDLoc DL) const {
582  SDValue Cmp;
583  EVT VT = LHS.getValueType();
584  bool UseTest = false;
585 
586  switch (CC) {
587  default:
588  break;
589  case ISD::SETLE: {
590  // Swap operands and reverse the branching condition.
591  std::swap(LHS, RHS);
592  CC = ISD::SETGE;
593  break;
594  }
595  case ISD::SETGT: {
596  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
597  switch (C->getSExtValue()) {
598  case -1: {
599  // When doing lhs > -1 use a tst instruction on the top part of lhs
600  // and use brpl instead of using a chain of cp/cpc.
601  UseTest = true;
602  AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
603  break;
604  }
605  case 0: {
606  // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
607  // __zero_reg__ in lhs.
608  RHS = LHS;
609  LHS = DAG.getConstant(0, DL, VT);
610  CC = ISD::SETLT;
611  break;
612  }
613  default: {
614  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
615  // us to fold the constant into the cmp instruction.
616  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
617  CC = ISD::SETGE;
618  break;
619  }
620  }
621  break;
622  }
623  // Swap operands and reverse the branching condition.
624  std::swap(LHS, RHS);
625  CC = ISD::SETLT;
626  break;
627  }
628  case ISD::SETLT: {
629  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
630  switch (C->getSExtValue()) {
631  case 1: {
632  // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
633  // __zero_reg__ in lhs.
634  RHS = LHS;
635  LHS = DAG.getConstant(0, DL, VT);
636  CC = ISD::SETGE;
637  break;
638  }
639  case 0: {
640  // When doing lhs < 0 use a tst instruction on the top part of lhs
641  // and use brmi instead of using a chain of cp/cpc.
642  UseTest = true;
643  AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
644  break;
645  }
646  }
647  }
648  break;
649  }
650  case ISD::SETULE: {
651  // Swap operands and reverse the branching condition.
652  std::swap(LHS, RHS);
653  CC = ISD::SETUGE;
654  break;
655  }
656  case ISD::SETUGT: {
657  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
658  // fold the constant into the cmp instruction.
659  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
660  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
661  CC = ISD::SETUGE;
662  break;
663  }
664  // Swap operands and reverse the branching condition.
665  std::swap(LHS, RHS);
666  CC = ISD::SETULT;
667  break;
668  }
669  }
670 
671  // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
672  // using the default and/or/xor expansion code which is much longer.
673  if (VT == MVT::i32) {
674  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
675  DAG.getIntPtrConstant(0, DL));
676  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
677  DAG.getIntPtrConstant(1, DL));
678  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
679  DAG.getIntPtrConstant(0, DL));
680  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
681  DAG.getIntPtrConstant(1, DL));
682 
683  if (UseTest) {
684  // When using tst we only care about the highest part.
685  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
686  DAG.getIntPtrConstant(1, DL));
687  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
688  } else {
689  Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL);
690  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
691  }
692  } else if (VT == MVT::i64) {
693  SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
694  DAG.getIntPtrConstant(0, DL));
695  SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
696  DAG.getIntPtrConstant(1, DL));
697 
698  SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
699  DAG.getIntPtrConstant(0, DL));
700  SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
701  DAG.getIntPtrConstant(1, DL));
702  SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
703  DAG.getIntPtrConstant(0, DL));
704  SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
705  DAG.getIntPtrConstant(1, DL));
706 
707  SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
708  DAG.getIntPtrConstant(0, DL));
709  SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
710  DAG.getIntPtrConstant(1, DL));
711 
712  SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
713  DAG.getIntPtrConstant(0, DL));
714  SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
715  DAG.getIntPtrConstant(1, DL));
716  SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
717  DAG.getIntPtrConstant(0, DL));
718  SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
719  DAG.getIntPtrConstant(1, DL));
720 
721  if (UseTest) {
722  // When using tst we only care about the highest part.
723  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
724  DAG.getIntPtrConstant(1, DL));
725  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
726  } else {
727  Cmp = getAVRCmp(LHS0, RHS0, DAG, DL);
728  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
729  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
730  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
731  }
732  } else if (VT == MVT::i8 || VT == MVT::i16) {
733  if (UseTest) {
734  // When using tst we only care about the highest part.
735  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
736  (VT == MVT::i8)
737  ? LHS
738  : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
739  LHS, DAG.getIntPtrConstant(1, DL)));
740  } else {
741  Cmp = getAVRCmp(LHS, RHS, DAG, DL);
742  }
743  } else {
744  llvm_unreachable("Invalid comparison size");
745  }
746 
747  // When using a test instruction AVRcc is already set.
748  if (!UseTest) {
749  AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
750  }
751 
752  return Cmp;
753 }
754 
755 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
756  SDValue Chain = Op.getOperand(0);
757  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
758  SDValue LHS = Op.getOperand(2);
759  SDValue RHS = Op.getOperand(3);
760  SDValue Dest = Op.getOperand(4);
761  SDLoc dl(Op);
762 
763  SDValue TargetCC;
764  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
765 
766  return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
767  Cmp);
768 }
769 
770 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
771  SDValue LHS = Op.getOperand(0);
772  SDValue RHS = Op.getOperand(1);
773  SDValue TrueV = Op.getOperand(2);
774  SDValue FalseV = Op.getOperand(3);
775  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
776  SDLoc dl(Op);
777 
778  SDValue TargetCC;
779  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
780 
781  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
782  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
783 
784  return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
785 }
786 
787 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
788  SDValue LHS = Op.getOperand(0);
789  SDValue RHS = Op.getOperand(1);
790  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
791  SDLoc DL(Op);
792 
793  SDValue TargetCC;
794  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
795 
796  SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
797  SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
798  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
799  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
800 
801  return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
802 }
803 
804 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
805  const MachineFunction &MF = DAG.getMachineFunction();
806  const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
807  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
808  auto DL = DAG.getDataLayout();
809  SDLoc dl(Op);
810 
811  // Vastart just stores the address of the VarArgsFrameIndex slot into the
812  // memory location argument.
813  SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
814 
815  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
816  MachinePointerInfo(SV));
817 }
818 
820  switch (Op.getOpcode()) {
821  default:
822  llvm_unreachable("Don't know how to custom lower this!");
823  case ISD::SHL:
824  case ISD::SRA:
825  case ISD::SRL:
826  case ISD::ROTL:
827  case ISD::ROTR:
828  return LowerShifts(Op, DAG);
829  case ISD::GlobalAddress:
830  return LowerGlobalAddress(Op, DAG);
831  case ISD::BlockAddress:
832  return LowerBlockAddress(Op, DAG);
833  case ISD::BR_CC:
834  return LowerBR_CC(Op, DAG);
835  case ISD::SELECT_CC:
836  return LowerSELECT_CC(Op, DAG);
837  case ISD::SETCC:
838  return LowerSETCC(Op, DAG);
839  case ISD::VASTART:
840  return LowerVASTART(Op, DAG);
841  case ISD::SDIVREM:
842  case ISD::UDIVREM:
843  return LowerDivRem(Op, DAG);
844  }
845 
846  return SDValue();
847 }
848 
849 /// Replace a node with an illegal result type
850 /// with a new node built out of custom code.
853  SelectionDAG &DAG) const {
854  SDLoc DL(N);
855 
856  switch (N->getOpcode()) {
857  case ISD::ADD: {
858  // Convert add (x, imm) into sub (x, -imm).
859  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
860  SDValue Sub = DAG.getNode(
861  ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
862  DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
863  Results.push_back(Sub);
864  }
865  break;
866  }
867  default: {
868  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
869 
870  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
871  Results.push_back(Res.getValue(I));
872 
873  break;
874  }
875  }
876 }
877 
878 /// Return true if the addressing mode represented
879 /// by AM is legal for this target, for a load/store of the specified type.
881  const AddrMode &AM, Type *Ty,
882  unsigned AS,
883  Instruction *I) const {
884  int64_t Offs = AM.BaseOffs;
885 
886  // Allow absolute addresses.
887  if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
888  return true;
889  }
890 
891  // Flash memory instructions only allow zero offsets.
892  if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
893  return false;
894  }
895 
896  // Allow reg+<6bit> offset.
897  if (Offs < 0)
898  Offs = -Offs;
899  if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 &&
900  isUInt<6>(Offs)) {
901  return true;
902  }
903 
904  return false;
905 }
906 
907 /// Returns true by value, base pointer and
908 /// offset pointer and addressing mode by reference if the node's address
909 /// can be legally represented as pre-indexed load / store address.
911  SDValue &Offset,
913  SelectionDAG &DAG) const {
914  EVT VT;
915  const SDNode *Op;
916  SDLoc DL(N);
917 
918  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
919  VT = LD->getMemoryVT();
920  Op = LD->getBasePtr().getNode();
921  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
922  return false;
924  return false;
925  }
926  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
927  VT = ST->getMemoryVT();
928  Op = ST->getBasePtr().getNode();
930  return false;
931  }
932  } else {
933  return false;
934  }
935 
936  if (VT != MVT::i8 && VT != MVT::i16) {
937  return false;
938  }
939 
940  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
941  return false;
942  }
943 
944  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
945  int RHSC = RHS->getSExtValue();
946  if (Op->getOpcode() == ISD::SUB)
947  RHSC = -RHSC;
948 
949  if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
950  return false;
951  }
952 
953  Base = Op->getOperand(0);
954  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
955  AM = ISD::PRE_DEC;
956 
957  return true;
958  }
959 
960  return false;
961 }
962 
963 /// Returns true by value, base pointer and
964 /// offset pointer and addressing mode by reference if this node can be
965 /// combined with a load / store to form a post-indexed load / store.
967  SDValue &Base,
968  SDValue &Offset,
970  SelectionDAG &DAG) const {
971  EVT VT;
972  SDLoc DL(N);
973 
974  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
975  VT = LD->getMemoryVT();
976  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
977  return false;
978  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
979  VT = ST->getMemoryVT();
981  return false;
982  }
983  } else {
984  return false;
985  }
986 
987  if (VT != MVT::i8 && VT != MVT::i16) {
988  return false;
989  }
990 
991  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
992  return false;
993  }
994 
995  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
996  int RHSC = RHS->getSExtValue();
997  if (Op->getOpcode() == ISD::SUB)
998  RHSC = -RHSC;
999  if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
1000  return false;
1001  }
1002 
1003  Base = Op->getOperand(0);
1004  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
1005  AM = ISD::POST_INC;
1006 
1007  return true;
1008  }
1009 
1010  return false;
1011 }
1012 
1014  const GlobalAddressSDNode *GA) const {
1015  return true;
1016 }
1017 
1018 //===----------------------------------------------------------------------===//
1019 // Formal Arguments Calling Convention Implementation
1020 //===----------------------------------------------------------------------===//
1021 
1022 #include "AVRGenCallingConv.inc"
1023 
1024 /// Registers for calling conventions, ordered in reverse as required by ABI.
1025 /// Both arrays must be of the same length.
1026 static const MCPhysReg RegList8[] = {
1027  AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1028  AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
1029  AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
1030 static const MCPhysReg RegList16[] = {
1031  AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
1032  AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
1033  AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
1034  AVR::R11R10, AVR::R10R9, AVR::R9R8};
1035 
1036 static_assert(array_lengthof(RegList8) == array_lengthof(RegList16),
1037  "8-bit and 16-bit register arrays must be of equal length");
1038 
1039 /// Analyze incoming and outgoing function arguments. We need custom C++ code
1040 /// to handle special constraints in the ABI.
1041 /// In addition, all pieces of a certain argument have to be passed either
1042 /// using registers or the stack but never mixing both.
1043 template <typename ArgT>
1044 static void
1046  const DataLayout *TD, const SmallVectorImpl<ArgT> &Args,
1047  SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) {
1048  unsigned NumArgs = Args.size();
1049  // This is the index of the last used register, in RegList*.
1050  // -1 means R26 (R26 is never actually used in CC).
1051  int RegLastIdx = -1;
1052  // Once a value is passed to the stack it will always be used
1053  bool UseStack = false;
1054  for (unsigned i = 0; i != NumArgs;) {
1055  MVT VT = Args[i].VT;
1056  // We have to count the number of bytes for each function argument, that is
1057  // those Args with the same OrigArgIndex. This is important in case the
1058  // function takes an aggregate type.
1059  // Current argument will be between [i..j).
1060  unsigned ArgIndex = Args[i].OrigArgIndex;
1061  unsigned TotalBytes = VT.getStoreSize();
1062  unsigned j = i + 1;
1063  for (; j != NumArgs; ++j) {
1064  if (Args[j].OrigArgIndex != ArgIndex)
1065  break;
1066  TotalBytes += Args[j].VT.getStoreSize();
1067  }
1068  // Round up to even number of bytes.
1069  TotalBytes = alignTo(TotalBytes, 2);
1070  // Skip zero sized arguments
1071  if (TotalBytes == 0)
1072  continue;
1073  // The index of the first register to be used
1074  unsigned RegIdx = RegLastIdx + TotalBytes;
1075  RegLastIdx = RegIdx;
1076  // If there are not enough registers, use the stack
1077  if (RegIdx >= array_lengthof(RegList8)) {
1078  UseStack = true;
1079  }
1080  for (; i != j; ++i) {
1081  MVT VT = Args[i].VT;
1082 
1083  if (UseStack) {
1084  auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
1085  unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
1086  TD->getABITypeAlign(evt));
1087  CCInfo.addLoc(
1089  } else {
1090  unsigned Reg;
1091  if (VT == MVT::i8) {
1092  Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1093  } else if (VT == MVT::i16) {
1094  Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1095  } else {
1097  "calling convention can only manage i8 and i16 types");
1098  }
1099  assert(Reg && "register not available in calling convention");
1100  CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1101  // Registers inside a particular argument are sorted in increasing order
1102  // (remember the array is reversed).
1103  RegIdx -= VT.getStoreSize();
1104  }
1105  }
1106  }
1107 }
1108 
1109 /// Count the total number of bytes needed to pass or return these arguments.
1110 template <typename ArgT>
1111 static unsigned
1113  unsigned TotalBytes = 0;
1114 
1115  for (const ArgT &Arg : Args) {
1116  TotalBytes += Arg.VT.getStoreSize();
1117  }
1118  return TotalBytes;
1119 }
1120 
1121 /// Analyze incoming and outgoing value of returning from a function.
1122 /// The algorithm is similar to analyzeArguments, but there can only be
1123 /// one value, possibly an aggregate, and it is limited to 8 bytes.
1124 template <typename ArgT>
1126  CCState &CCInfo) {
1127  unsigned NumArgs = Args.size();
1128  unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
1129  // CanLowerReturn() guarantees this assertion.
1130  assert(TotalBytes <= 8 &&
1131  "return values greater than 8 bytes cannot be lowered");
1132 
1133  // GCC-ABI says that the size is rounded up to the next even number,
1134  // but actually once it is more than 4 it will always round up to 8.
1135  if (TotalBytes > 4) {
1136  TotalBytes = 8;
1137  } else {
1138  TotalBytes = alignTo(TotalBytes, 2);
1139  }
1140 
1141  // The index of the first register to use.
1142  int RegIdx = TotalBytes - 1;
1143  for (unsigned i = 0; i != NumArgs; ++i) {
1144  MVT VT = Args[i].VT;
1145  unsigned Reg;
1146  if (VT == MVT::i8) {
1147  Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1148  } else if (VT == MVT::i16) {
1149  Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1150  } else {
1151  llvm_unreachable("calling convention can only manage i8 and i16 types");
1152  }
1153  assert(Reg && "register not available in calling convention");
1154  CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1155  // Registers sort in increasing order
1156  RegIdx -= VT.getStoreSize();
1157  }
1158 }
1159 
1160 SDValue AVRTargetLowering::LowerFormalArguments(
1161  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1162  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1163  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1164  MachineFunction &MF = DAG.getMachineFunction();
1165  MachineFrameInfo &MFI = MF.getFrameInfo();
1166  auto DL = DAG.getDataLayout();
1167 
1168  // Assign locations to all of the incoming arguments.
1169  SmallVector<CCValAssign, 16> ArgLocs;
1170  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1171  *DAG.getContext());
1172 
1173  // Variadic functions do not need all the analysis below.
1174  if (isVarArg) {
1175  CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
1176  } else {
1177  analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo);
1178  }
1179 
1180  SDValue ArgValue;
1181  for (CCValAssign &VA : ArgLocs) {
1182 
1183  // Arguments stored on registers.
1184  if (VA.isRegLoc()) {
1185  EVT RegVT = VA.getLocVT();
1186  const TargetRegisterClass *RC;
1187  if (RegVT == MVT::i8) {
1188  RC = &AVR::GPR8RegClass;
1189  } else if (RegVT == MVT::i16) {
1190  RC = &AVR::DREGSRegClass;
1191  } else {
1192  llvm_unreachable("Unknown argument type!");
1193  }
1194 
1195  Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
1196  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1197 
1198  // :NOTE: Clang should not promote any i8 into i16 but for safety the
1199  // following code will handle zexts or sexts generated by other
1200  // front ends. Otherwise:
1201  // If this is an 8 bit value, it is really passed promoted
1202  // to 16 bits. Insert an assert[sz]ext to capture this, then
1203  // truncate to the right size.
1204  switch (VA.getLocInfo()) {
1205  default:
1206  llvm_unreachable("Unknown loc info!");
1207  case CCValAssign::Full:
1208  break;
1209  case CCValAssign::BCvt:
1210  ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1211  break;
1212  case CCValAssign::SExt:
1213  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1214  DAG.getValueType(VA.getValVT()));
1215  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1216  break;
1217  case CCValAssign::ZExt:
1218  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1219  DAG.getValueType(VA.getValVT()));
1220  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1221  break;
1222  }
1223 
1224  InVals.push_back(ArgValue);
1225  } else {
1226  // Only arguments passed on the stack should make it here.
1227  assert(VA.isMemLoc());
1228 
1229  EVT LocVT = VA.getLocVT();
1230 
1231  // Create the frame index object for this incoming parameter.
1232  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1233  VA.getLocMemOffset(), true);
1234 
1235  // Create the SelectionDAG nodes corresponding to a load
1236  // from this parameter.
1237  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1238  InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1240  }
1241  }
1242 
1243  // If the function takes variable number of arguments, make a frame index for
1244  // the start of the first vararg value... for expansion of llvm.va_start.
1245  if (isVarArg) {
1246  unsigned StackSize = CCInfo.getNextStackOffset();
1247  AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1248 
1249  AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1250  }
1251 
1252  return Chain;
1253 }
1254 
1255 //===----------------------------------------------------------------------===//
1256 // Call Calling Convention Implementation
1257 //===----------------------------------------------------------------------===//
1258 
1259 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1260  SmallVectorImpl<SDValue> &InVals) const {
1261  SelectionDAG &DAG = CLI.DAG;
1262  SDLoc &DL = CLI.DL;
1263  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1264  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1265  SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1266  SDValue Chain = CLI.Chain;
1267  SDValue Callee = CLI.Callee;
1268  bool &isTailCall = CLI.IsTailCall;
1269  CallingConv::ID CallConv = CLI.CallConv;
1270  bool isVarArg = CLI.IsVarArg;
1271 
1272  MachineFunction &MF = DAG.getMachineFunction();
1273 
1274  // AVR does not yet support tail call optimization.
1275  isTailCall = false;
1276 
1277  // Analyze operands of the call, assigning locations to each operand.
1278  SmallVector<CCValAssign, 16> ArgLocs;
1279  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1280  *DAG.getContext());
1281 
1282  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1283  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1284  // node so that legalize doesn't hack it.
1285  const Function *F = nullptr;
1286  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1287  const GlobalValue *GV = G->getGlobal();
1288 
1289  F = cast<Function>(GV);
1290  Callee =
1291  DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
1292  } else if (const ExternalSymbolSDNode *ES =
1293  dyn_cast<ExternalSymbolSDNode>(Callee)) {
1294  Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1295  getPointerTy(DAG.getDataLayout()));
1296  }
1297 
1298  // Variadic functions do not need all the analysis below.
1299  if (isVarArg) {
1300  CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
1301  } else {
1302  analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo);
1303  }
1304 
1305  // Get a count of how many bytes are to be pushed on the stack.
1306  unsigned NumBytes = CCInfo.getNextStackOffset();
1307 
1308  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1309 
1310  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1311 
1312  // First, walk the register assignments, inserting copies.
1313  unsigned AI, AE;
1314  bool HasStackArgs = false;
1315  for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1316  CCValAssign &VA = ArgLocs[AI];
1317  EVT RegVT = VA.getLocVT();
1318  SDValue Arg = OutVals[AI];
1319 
1320  // Promote the value if needed. With Clang this should not happen.
1321  switch (VA.getLocInfo()) {
1322  default:
1323  llvm_unreachable("Unknown loc info!");
1324  case CCValAssign::Full:
1325  break;
1326  case CCValAssign::SExt:
1327  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1328  break;
1329  case CCValAssign::ZExt:
1330  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1331  break;
1332  case CCValAssign::AExt:
1333  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1334  break;
1335  case CCValAssign::BCvt:
1336  Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1337  break;
1338  }
1339 
1340  // Stop when we encounter a stack argument, we need to process them
1341  // in reverse order in the loop below.
1342  if (VA.isMemLoc()) {
1343  HasStackArgs = true;
1344  break;
1345  }
1346 
1347  // Arguments that can be passed on registers must be kept in the RegsToPass
1348  // vector.
1349  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1350  }
1351 
1352  // Second, stack arguments have to walked.
1353  // Previously this code created chained stores but those chained stores appear
1354  // to be unchained in the legalization phase. Therefore, do not attempt to
1355  // chain them here. In fact, chaining them here somehow causes the first and
1356  // second store to be reversed which is the exact opposite of the intended
1357  // effect.
1358  if (HasStackArgs) {
1359  SmallVector<SDValue, 8> MemOpChains;
1360  for (; AI != AE; AI++) {
1361  CCValAssign &VA = ArgLocs[AI];
1362  SDValue Arg = OutVals[AI];
1363 
1364  assert(VA.isMemLoc());
1365 
1366  // SP points to one stack slot further so add one to adjust it.
1367  SDValue PtrOff = DAG.getNode(
1368  ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1369  DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1370  DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1371 
1372  MemOpChains.push_back(
1373  DAG.getStore(Chain, DL, Arg, PtrOff,
1374  MachinePointerInfo::getStack(MF, VA.getLocMemOffset())));
1375  }
1376 
1377  if (!MemOpChains.empty())
1378  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1379  }
1380 
1381  // Build a sequence of copy-to-reg nodes chained together with token chain and
1382  // flag operands which copy the outgoing args into registers. The InFlag in
1383  // necessary since all emited instructions must be stuck together.
1384  SDValue InFlag;
1385  for (auto Reg : RegsToPass) {
1386  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1387  InFlag = Chain.getValue(1);
1388  }
1389 
1390  // Returns a chain & a flag for retval copy to use.
1391  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1392  SmallVector<SDValue, 8> Ops;
1393  Ops.push_back(Chain);
1394  Ops.push_back(Callee);
1395 
1396  // Add argument registers to the end of the list so that they are known live
1397  // into the call.
1398  for (auto Reg : RegsToPass) {
1399  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1400  }
1401 
1402  // Add a register mask operand representing the call-preserved registers.
1403  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1404  const uint32_t *Mask =
1405  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1406  assert(Mask && "Missing call preserved mask for calling convention");
1407  Ops.push_back(DAG.getRegisterMask(Mask));
1408 
1409  if (InFlag.getNode()) {
1410  Ops.push_back(InFlag);
1411  }
1412 
1413  Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1414  InFlag = Chain.getValue(1);
1415 
1416  // Create the CALLSEQ_END node.
1417  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1418  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1419 
1420  if (!Ins.empty()) {
1421  InFlag = Chain.getValue(1);
1422  }
1423 
1424  // Handle result values, copying them out of physregs into vregs that we
1425  // return.
1426  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1427  InVals);
1428 }
1429 
1430 /// Lower the result values of a call into the
1431 /// appropriate copies out of appropriate physical registers.
1432 ///
1433 SDValue AVRTargetLowering::LowerCallResult(
1434  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1435  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1436  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1437 
1438  // Assign locations to each value returned by this call.
1439  SmallVector<CCValAssign, 16> RVLocs;
1440  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1441  *DAG.getContext());
1442 
1443  // Handle runtime calling convs.
1444  if (CallConv == CallingConv::AVR_BUILTIN) {
1445  CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
1446  } else {
1447  analyzeReturnValues(Ins, CCInfo);
1448  }
1449 
1450  // Copy all of the result registers out of their specified physreg.
1451  for (CCValAssign const &RVLoc : RVLocs) {
1452  Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1453  InFlag)
1454  .getValue(1);
1455  InFlag = Chain.getValue(2);
1456  InVals.push_back(Chain.getValue(0));
1457  }
1458 
1459  return Chain;
1460 }
1461 
1462 //===----------------------------------------------------------------------===//
1463 // Return Value Calling Convention Implementation
1464 //===----------------------------------------------------------------------===//
1465 
1466 bool AVRTargetLowering::CanLowerReturn(
1467  CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1468  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1469  if (CallConv == CallingConv::AVR_BUILTIN) {
1470  SmallVector<CCValAssign, 16> RVLocs;
1471  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1472  return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
1473  }
1474 
1475  unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs);
1476  return TotalBytes <= 8;
1477 }
1478 
1479 SDValue
1480 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1481  bool isVarArg,
1482  const SmallVectorImpl<ISD::OutputArg> &Outs,
1483  const SmallVectorImpl<SDValue> &OutVals,
1484  const SDLoc &dl, SelectionDAG &DAG) const {
1485  // CCValAssign - represent the assignment of the return value to locations.
1486  SmallVector<CCValAssign, 16> RVLocs;
1487 
1488  // CCState - Info about the registers and stack slot.
1489  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1490  *DAG.getContext());
1491 
1492  MachineFunction &MF = DAG.getMachineFunction();
1493 
1494  // Analyze return values.
1495  if (CallConv == CallingConv::AVR_BUILTIN) {
1496  CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
1497  } else {
1498  analyzeReturnValues(Outs, CCInfo);
1499  }
1500 
1501  SDValue Flag;
1502  SmallVector<SDValue, 4> RetOps(1, Chain);
1503  // Copy the result values into the output registers.
1504  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1505  CCValAssign &VA = RVLocs[i];
1506  assert(VA.isRegLoc() && "Can only return in registers!");
1507 
1508  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1509 
1510  // Guarantee that all emitted copies are stuck together with flags.
1511  Flag = Chain.getValue(1);
1512  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1513  }
1514 
1515  // Don't emit the ret/reti instruction when the naked attribute is present in
1516  // the function being compiled.
1517  if (MF.getFunction().getAttributes().hasFnAttr(Attribute::Naked)) {
1518  return Chain;
1519  }
1520 
1521  const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1522 
1523  unsigned RetOpc =
1524  AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_FLAG : AVRISD::RET_FLAG;
1525 
1526  RetOps[0] = Chain; // Update chain.
1527 
1528  if (Flag.getNode()) {
1529  RetOps.push_back(Flag);
1530  }
1531 
1532  return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1533 }
1534 
1535 //===----------------------------------------------------------------------===//
1536 // Custom Inserters
1537 //===----------------------------------------------------------------------===//
1538 
1539 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1540  MachineBasicBlock *BB) const {
1541  unsigned Opc;
1542  const TargetRegisterClass *RC;
1543  bool HasRepeatedOperand = false;
1544  MachineFunction *F = BB->getParent();
1545  MachineRegisterInfo &RI = F->getRegInfo();
1546  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1547  DebugLoc dl = MI.getDebugLoc();
1548 
1549  switch (MI.getOpcode()) {
1550  default:
1551  llvm_unreachable("Invalid shift opcode!");
1552  case AVR::Lsl8:
1553  Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1554  RC = &AVR::GPR8RegClass;
1555  HasRepeatedOperand = true;
1556  break;
1557  case AVR::Lsl16:
1558  Opc = AVR::LSLWRd;
1559  RC = &AVR::DREGSRegClass;
1560  break;
1561  case AVR::Asr8:
1562  Opc = AVR::ASRRd;
1563  RC = &AVR::GPR8RegClass;
1564  break;
1565  case AVR::Asr16:
1566  Opc = AVR::ASRWRd;
1567  RC = &AVR::DREGSRegClass;
1568  break;
1569  case AVR::Lsr8:
1570  Opc = AVR::LSRRd;
1571  RC = &AVR::GPR8RegClass;
1572  break;
1573  case AVR::Lsr16:
1574  Opc = AVR::LSRWRd;
1575  RC = &AVR::DREGSRegClass;
1576  break;
1577  case AVR::Rol8:
1578  Opc = AVR::ROLBRd;
1579  RC = &AVR::GPR8RegClass;
1580  break;
1581  case AVR::Rol16:
1582  Opc = AVR::ROLWRd;
1583  RC = &AVR::DREGSRegClass;
1584  break;
1585  case AVR::Ror8:
1586  Opc = AVR::RORBRd;
1587  RC = &AVR::GPR8RegClass;
1588  break;
1589  case AVR::Ror16:
1590  Opc = AVR::RORWRd;
1591  RC = &AVR::DREGSRegClass;
1592  break;
1593  }
1594 
1595  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1596 
1598  for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I)
1599  ;
1600  if (I != F->end())
1601  ++I;
1602 
1603  // Create loop block.
1604  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1605  MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB);
1606  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1607 
1608  F->insert(I, LoopBB);
1609  F->insert(I, CheckBB);
1610  F->insert(I, RemBB);
1611 
1612  // Update machine-CFG edges by transferring all successors of the current
1613  // block to the block containing instructions after shift.
1614  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1615  BB->end());
1616  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1617 
1618  // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB.
1619  BB->addSuccessor(CheckBB);
1620  LoopBB->addSuccessor(CheckBB);
1621  CheckBB->addSuccessor(LoopBB);
1622  CheckBB->addSuccessor(RemBB);
1623 
1624  Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass);
1625  Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass);
1626  Register ShiftReg = RI.createVirtualRegister(RC);
1627  Register ShiftReg2 = RI.createVirtualRegister(RC);
1628  Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1629  Register SrcReg = MI.getOperand(1).getReg();
1630  Register DstReg = MI.getOperand(0).getReg();
1631 
1632  // BB:
1633  // rjmp CheckBB
1634  BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB);
1635 
1636  // LoopBB:
1637  // ShiftReg2 = shift ShiftReg
1638  auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1639  if (HasRepeatedOperand)
1640  ShiftMI.addReg(ShiftReg);
1641 
1642  // CheckBB:
1643  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1644  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1645  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1646  // ShiftAmt2 = ShiftAmt - 1;
1647  // if (ShiftAmt2 >= 0) goto LoopBB;
1648  BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg)
1649  .addReg(SrcReg)
1650  .addMBB(BB)
1651  .addReg(ShiftReg2)
1652  .addMBB(LoopBB);
1653  BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1654  .addReg(ShiftAmtSrcReg)
1655  .addMBB(BB)
1656  .addReg(ShiftAmtReg2)
1657  .addMBB(LoopBB);
1658  BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg)
1659  .addReg(SrcReg)
1660  .addMBB(BB)
1661  .addReg(ShiftReg2)
1662  .addMBB(LoopBB);
1663 
1664  BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2).addReg(ShiftAmtReg);
1665  BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB);
1666 
1667  MI.eraseFromParent(); // The pseudo instruction is gone now.
1668  return RemBB;
1669 }
1670 
1672  if (I->getOpcode() == AVR::COPY) {
1673  Register SrcReg = I->getOperand(1).getReg();
1674  return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1675  }
1676 
1677  return false;
1678 }
1679 
1680 // The mul instructions wreak havock on our zero_reg R1. We need to clear it
1681 // after the result has been evacuated. This is probably not the best way to do
1682 // it, but it works for now.
1683 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1684  MachineBasicBlock *BB) const {
1685  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1687  ++I; // in any case insert *after* the mul instruction
1688  if (isCopyMulResult(I))
1689  ++I;
1690  if (isCopyMulResult(I))
1691  ++I;
1692  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1693  .addReg(AVR::R1)
1694  .addReg(AVR::R1);
1695  return BB;
1696 }
1697 
1698 // Insert a read from R1, which almost always contains the value 0.
1699 MachineBasicBlock *
1700 AVRTargetLowering::insertCopyR1(MachineInstr &MI, MachineBasicBlock *BB) const {
1701  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1703  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::COPY))
1704  .add(MI.getOperand(0))
1705  .addReg(AVR::R1);
1706  MI.eraseFromParent();
1707  return BB;
1708 }
1709 
1710 MachineBasicBlock *
1712  MachineBasicBlock *MBB) const {
1713  int Opc = MI.getOpcode();
1714 
1715  // Pseudo shift instructions with a non constant shift amount are expanded
1716  // into a loop.
1717  switch (Opc) {
1718  case AVR::Lsl8:
1719  case AVR::Lsl16:
1720  case AVR::Lsr8:
1721  case AVR::Lsr16:
1722  case AVR::Rol8:
1723  case AVR::Rol16:
1724  case AVR::Ror8:
1725  case AVR::Ror16:
1726  case AVR::Asr8:
1727  case AVR::Asr16:
1728  return insertShift(MI, MBB);
1729  case AVR::MULRdRr:
1730  case AVR::MULSRdRr:
1731  return insertMul(MI, MBB);
1732  case AVR::CopyR1:
1733  return insertCopyR1(MI, MBB);
1734  }
1735 
1736  assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
1737  "Unexpected instr type to insert");
1738 
1739  const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1740  ->getParent()
1741  ->getSubtarget()
1742  .getInstrInfo();
1743  DebugLoc dl = MI.getDebugLoc();
1744 
1745  // To "insert" a SELECT instruction, we insert the diamond
1746  // control-flow pattern. The incoming instruction knows the
1747  // destination vreg to set, the condition code register to branch
1748  // on, the true/false values to select between, and a branch opcode
1749  // to use.
1750 
1751  MachineFunction *MF = MBB->getParent();
1752  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1753  MachineBasicBlock *FallThrough = MBB->getFallThrough();
1754 
1755  // If the current basic block falls through to another basic block,
1756  // we must insert an unconditional branch to the fallthrough destination
1757  // if we are to insert basic blocks at the prior fallthrough point.
1758  if (FallThrough != nullptr) {
1759  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
1760  }
1761 
1762  MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1763  MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1764 
1766  for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I)
1767  ;
1768  if (I != MF->end())
1769  ++I;
1770  MF->insert(I, trueMBB);
1771  MF->insert(I, falseMBB);
1772 
1773  // Transfer remaining instructions and all successors of the current
1774  // block to the block which will contain the Phi node for the
1775  // select.
1776  trueMBB->splice(trueMBB->begin(), MBB,
1777  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1779 
1780  AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
1781  BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1782  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1783  MBB->addSuccessor(falseMBB);
1784  MBB->addSuccessor(trueMBB);
1785 
1786  // Unconditionally flow back to the true block
1787  BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1788  falseMBB->addSuccessor(trueMBB);
1789 
1790  // Set up the Phi node to determine where we came from
1791  BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI),
1792  MI.getOperand(0).getReg())
1793  .addReg(MI.getOperand(1).getReg())
1794  .addMBB(MBB)
1795  .addReg(MI.getOperand(2).getReg())
1796  .addMBB(falseMBB);
1797 
1798  MI.eraseFromParent(); // The pseudo instruction is gone now.
1799  return trueMBB;
1800 }
1801 
1802 //===----------------------------------------------------------------------===//
1803 // Inline Asm Support
1804 //===----------------------------------------------------------------------===//
1805 
1808  if (Constraint.size() == 1) {
1809  // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1810  switch (Constraint[0]) {
1811  default:
1812  break;
1813  case 'a': // Simple upper registers
1814  case 'b': // Base pointer registers pairs
1815  case 'd': // Upper register
1816  case 'l': // Lower registers
1817  case 'e': // Pointer register pairs
1818  case 'q': // Stack pointer register
1819  case 'r': // Any register
1820  case 'w': // Special upper register pairs
1821  return C_RegisterClass;
1822  case 't': // Temporary register
1823  case 'x':
1824  case 'X': // Pointer register pair X
1825  case 'y':
1826  case 'Y': // Pointer register pair Y
1827  case 'z':
1828  case 'Z': // Pointer register pair Z
1829  return C_Register;
1830  case 'Q': // A memory address based on Y or Z pointer with displacement.
1831  return C_Memory;
1832  case 'G': // Floating point constant
1833  case 'I': // 6-bit positive integer constant
1834  case 'J': // 6-bit negative integer constant
1835  case 'K': // Integer constant (Range: 2)
1836  case 'L': // Integer constant (Range: 0)
1837  case 'M': // 8-bit integer constant
1838  case 'N': // Integer constant (Range: -1)
1839  case 'O': // Integer constant (Range: 8, 16, 24)
1840  case 'P': // Integer constant (Range: 1)
1841  case 'R': // Integer constant (Range: -6 to 5)x
1842  return C_Immediate;
1843  }
1844  }
1845 
1846  return TargetLowering::getConstraintType(Constraint);
1847 }
1848 
1849 unsigned
1851  // Not sure if this is actually the right thing to do, but we got to do
1852  // *something* [agnat]
1853  switch (ConstraintCode[0]) {
1854  case 'Q':
1855  return InlineAsm::Constraint_Q;
1856  }
1857  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1858 }
1859 
1862  AsmOperandInfo &info, const char *constraint) const {
1863  ConstraintWeight weight = CW_Invalid;
1864  Value *CallOperandVal = info.CallOperandVal;
1865 
1866  // If we don't have a value, we can't do a match,
1867  // but allow it at the lowest weight.
1868  // (this behaviour has been copied from the ARM backend)
1869  if (!CallOperandVal) {
1870  return CW_Default;
1871  }
1872 
1873  // Look at the constraint type.
1874  switch (*constraint) {
1875  default:
1877  break;
1878  case 'd':
1879  case 'r':
1880  case 'l':
1881  weight = CW_Register;
1882  break;
1883  case 'a':
1884  case 'b':
1885  case 'e':
1886  case 'q':
1887  case 't':
1888  case 'w':
1889  case 'x':
1890  case 'X':
1891  case 'y':
1892  case 'Y':
1893  case 'z':
1894  case 'Z':
1895  weight = CW_SpecificReg;
1896  break;
1897  case 'G':
1898  if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
1899  if (C->isZero()) {
1900  weight = CW_Constant;
1901  }
1902  }
1903  break;
1904  case 'I':
1905  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1906  if (isUInt<6>(C->getZExtValue())) {
1907  weight = CW_Constant;
1908  }
1909  }
1910  break;
1911  case 'J':
1912  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1913  if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
1914  weight = CW_Constant;
1915  }
1916  }
1917  break;
1918  case 'K':
1919  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1920  if (C->getZExtValue() == 2) {
1921  weight = CW_Constant;
1922  }
1923  }
1924  break;
1925  case 'L':
1926  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1927  if (C->getZExtValue() == 0) {
1928  weight = CW_Constant;
1929  }
1930  }
1931  break;
1932  case 'M':
1933  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1934  if (isUInt<8>(C->getZExtValue())) {
1935  weight = CW_Constant;
1936  }
1937  }
1938  break;
1939  case 'N':
1940  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1941  if (C->getSExtValue() == -1) {
1942  weight = CW_Constant;
1943  }
1944  }
1945  break;
1946  case 'O':
1947  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1948  if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
1949  (C->getZExtValue() == 24)) {
1950  weight = CW_Constant;
1951  }
1952  }
1953  break;
1954  case 'P':
1955  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1956  if (C->getZExtValue() == 1) {
1957  weight = CW_Constant;
1958  }
1959  }
1960  break;
1961  case 'R':
1962  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1963  if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
1964  weight = CW_Constant;
1965  }
1966  }
1967  break;
1968  case 'Q':
1969  weight = CW_Memory;
1970  break;
1971  }
1972 
1973  return weight;
1974 }
1975 
1976 std::pair<unsigned, const TargetRegisterClass *>
1978  StringRef Constraint,
1979  MVT VT) const {
1980  if (Constraint.size() == 1) {
1981  switch (Constraint[0]) {
1982  case 'a': // Simple upper registers r16..r23.
1983  if (VT == MVT::i8)
1984  return std::make_pair(0U, &AVR::LD8loRegClass);
1985  else if (VT == MVT::i16)
1986  return std::make_pair(0U, &AVR::DREGSLD8loRegClass);
1987  break;
1988  case 'b': // Base pointer registers: y, z.
1989  if (VT == MVT::i8 || VT == MVT::i16)
1990  return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1991  break;
1992  case 'd': // Upper registers r16..r31.
1993  if (VT == MVT::i8)
1994  return std::make_pair(0U, &AVR::LD8RegClass);
1995  else if (VT == MVT::i16)
1996  return std::make_pair(0U, &AVR::DLDREGSRegClass);
1997  break;
1998  case 'l': // Lower registers r0..r15.
1999  if (VT == MVT::i8)
2000  return std::make_pair(0U, &AVR::GPR8loRegClass);
2001  else if (VT == MVT::i16)
2002  return std::make_pair(0U, &AVR::DREGSloRegClass);
2003  break;
2004  case 'e': // Pointer register pairs: x, y, z.
2005  if (VT == MVT::i8 || VT == MVT::i16)
2006  return std::make_pair(0U, &AVR::PTRREGSRegClass);
2007  break;
2008  case 'q': // Stack pointer register: SPH:SPL.
2009  return std::make_pair(0U, &AVR::GPRSPRegClass);
2010  case 'r': // Any register: r0..r31.
2011  if (VT == MVT::i8)
2012  return std::make_pair(0U, &AVR::GPR8RegClass);
2013  else if (VT == MVT::i16)
2014  return std::make_pair(0U, &AVR::DREGSRegClass);
2015  break;
2016  case 't': // Temporary register: r0.
2017  if (VT == MVT::i8)
2018  return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
2019  break;
2020  case 'w': // Special upper register pairs: r24, r26, r28, r30.
2021  if (VT == MVT::i8 || VT == MVT::i16)
2022  return std::make_pair(0U, &AVR::IWREGSRegClass);
2023  break;
2024  case 'x': // Pointer register pair X: r27:r26.
2025  case 'X':
2026  if (VT == MVT::i8 || VT == MVT::i16)
2027  return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
2028  break;
2029  case 'y': // Pointer register pair Y: r29:r28.
2030  case 'Y':
2031  if (VT == MVT::i8 || VT == MVT::i16)
2032  return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
2033  break;
2034  case 'z': // Pointer register pair Z: r31:r30.
2035  case 'Z':
2036  if (VT == MVT::i8 || VT == MVT::i16)
2037  return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
2038  break;
2039  default:
2040  break;
2041  }
2042  }
2043 
2045  Subtarget.getRegisterInfo(), Constraint, VT);
2046 }
2047 
2049  std::string &Constraint,
2050  std::vector<SDValue> &Ops,
2051  SelectionDAG &DAG) const {
2052  SDValue Result;
2053  SDLoc DL(Op);
2054  EVT Ty = Op.getValueType();
2055 
2056  // Currently only support length 1 constraints.
2057  if (Constraint.length() != 1) {
2058  return;
2059  }
2060 
2061  char ConstraintLetter = Constraint[0];
2062  switch (ConstraintLetter) {
2063  default:
2064  break;
2065  // Deal with integers first:
2066  case 'I':
2067  case 'J':
2068  case 'K':
2069  case 'L':
2070  case 'M':
2071  case 'N':
2072  case 'O':
2073  case 'P':
2074  case 'R': {
2075  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2076  if (!C) {
2077  return;
2078  }
2079 
2080  int64_t CVal64 = C->getSExtValue();
2081  uint64_t CUVal64 = C->getZExtValue();
2082  switch (ConstraintLetter) {
2083  case 'I': // 0..63
2084  if (!isUInt<6>(CUVal64))
2085  return;
2086  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2087  break;
2088  case 'J': // -63..0
2089  if (CVal64 < -63 || CVal64 > 0)
2090  return;
2091  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2092  break;
2093  case 'K': // 2
2094  if (CUVal64 != 2)
2095  return;
2096  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2097  break;
2098  case 'L': // 0
2099  if (CUVal64 != 0)
2100  return;
2101  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2102  break;
2103  case 'M': // 0..255
2104  if (!isUInt<8>(CUVal64))
2105  return;
2106  // i8 type may be printed as a negative number,
2107  // e.g. 254 would be printed as -2,
2108  // so we force it to i16 at least.
2109  if (Ty.getSimpleVT() == MVT::i8) {
2110  Ty = MVT::i16;
2111  }
2112  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2113  break;
2114  case 'N': // -1
2115  if (CVal64 != -1)
2116  return;
2117  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2118  break;
2119  case 'O': // 8, 16, 24
2120  if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
2121  return;
2122  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2123  break;
2124  case 'P': // 1
2125  if (CUVal64 != 1)
2126  return;
2127  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2128  break;
2129  case 'R': // -6..5
2130  if (CVal64 < -6 || CVal64 > 5)
2131  return;
2132  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2133  break;
2134  }
2135 
2136  break;
2137  }
2138  case 'G':
2139  const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op);
2140  if (!FC || !FC->isZero())
2141  return;
2142  // Soften float to i8 0
2143  Result = DAG.getTargetConstant(0, DL, MVT::i8);
2144  break;
2145  }
2146 
2147  if (Result.getNode()) {
2148  Ops.push_back(Result);
2149  return;
2150  }
2151 
2152  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2153 }
2154 
2156  const MachineFunction &MF) const {
2157  Register Reg;
2158 
2159  if (VT == LLT::scalar(8)) {
2161  .Case("r0", AVR::R0)
2162  .Case("r1", AVR::R1)
2163  .Default(0);
2164  } else {
2166  .Case("r0", AVR::R1R0)
2167  .Case("sp", AVR::SP)
2168  .Default(0);
2169  }
2170 
2171  if (Reg)
2172  return Reg;
2173 
2175  Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
2176 }
2177 
2178 } // end of namespace llvm
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:68
i
i
Definition: README.txt:29
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1383
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:38
llvm::AVRTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: AVRISelLowering.cpp:1013
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1558
llvm::TargetLoweringBase::setSchedulingPreference
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
Definition: TargetLowering.h:2167
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1394
llvm::MVT::getStoreSize
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: MachineValueType.h:1076
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1319
llvm::AVRISD::ROR
@ ROR
Bit rotate right.
Definition: AVRISelLowering.h:50
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:22
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1088
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:36
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:196
llvm::StructType::get
static StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:408
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1391
llvm::AArch64_AM::LSL
@ LSL
Definition: AArch64AddressingModes.h:35
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:852
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1395
llvm::AVRTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: AVRISelLowering.cpp:1850
llvm::TargetLowering::getSingleConstraintMatchWeight
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Definition: TargetLowering.cpp:4981
llvm::AVRTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: AVRISelLowering.cpp:265
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4263
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:950
llvm::ISD::NON_EXTLOAD
@ NON_EXTLOAD
Definition: ISDOpcodes.h:1350
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1154
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:62
llvm::AVRTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: AVRISelLowering.cpp:234
llvm::ISD::PRE_DEC
@ PRE_DEC
Definition: ISDOpcodes.h:1319
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:666
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:182
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:935
llvm::CCState::addLoc
void addLoc(const CCValAssign &V)
Definition: CallingConvLower.h:253
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
llvm::AVRTargetMachine
A generic AVR implementation.
Definition: AVRTargetMachine.h:28
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1390
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1016
llvm::MachineFunction::end
iterator end()
Definition: MachineFunction.h:825
llvm::AVRISD::ROLLOOP
@ ROLLOOP
A loop of single left bit rotate instructions.
Definition: AVRISelLowering.h:54
llvm::AVR::ProgramMemory
@ ProgramMemory
Definition: AVR.h:43
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::isCopyMulResult
static bool isCopyMulResult(MachineBasicBlock::iterator const &I)
Definition: AVRISelLowering.cpp:1671
R600_InstFlag::FC
@ FC
Definition: R600Defines.h:32
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:732
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::TargetLoweringBase::getLibcallName
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
Definition: TargetLowering.h:2945
llvm::TargetLowering::CW_Constant
@ CW_Constant
Definition: TargetLowering.h:4284
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2300
llvm::AVRISD::SELECT_CC
@ SELECT_CC
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
Definition: AVRISelLowering.h:72
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:262
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::TargetLowering::C_Memory
@ C_Memory
Definition: TargetLowering.h:4266
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1385
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:715
llvm::TargetLoweringBase::setSupportsUnalignedAtomics
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
Definition: TargetLowering.h:2369
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:842
llvm::AVRISD::LSLHI
@ LSLHI
Higher 8-bit of word logical shift left.
Definition: AVRISelLowering.h:41
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:702
llvm::AArch64ISD::CALL
@ CALL
Definition: AArch64ISelLowering.h:52
llvm::AVRISD::ASRWN
@ ASRWN
Word arithmetic shift right N bits.
Definition: AVRISelLowering.h:48
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:46
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2332
llvm::TargetLowering::LowerCallTo
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
Definition: SelectionDAGBuilder.cpp:9521
llvm::AVRISD::CMPC
@ CMPC
Compare with carry instruction.
Definition: AVRISelLowering.h:65
llvm::AVRISD::LSLLOOP
@ LSLLOOP
A loop of single logical shift left instructions.
Definition: AVRISelLowering.h:52
llvm::AVRTargetLowering::getPreIndexedAddressParts
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
Definition: AVRISelLowering.cpp:910
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::AVRCC::COND_LT
@ COND_LT
Less than.
Definition: AVRInstrInfo.h:35
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:849
llvm::AVRTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
Definition: AVRISelLowering.cpp:851
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:2962
STLExtras.h
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1045
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1350
RHS
Value * RHS
Definition: X86PartialReduction.cpp:74
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::AVRISD::RETI_FLAG
@ RETI_FLAG
Return from ISR.
Definition: AVRISelLowering.h:31
llvm::AVRISD::LSLWN
@ LSLWN
Word logical shift left N bits.
Definition: AVRISelLowering.h:40
llvm::AVRISD::LSL
@ LSL
Logical shift left.
Definition: AVRISelLowering.h:38
SelectionDAG.h
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1564
llvm::AVRCC::COND_SH
@ COND_SH
Unsigned same or higher.
Definition: AVRInstrInfo.h:36
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:960
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:805
MachineRegisterInfo.h
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::AVRISD::CALL
@ CALL
Represents an abstract call instruction, which includes a bunch of information.
Definition: AVRISelLowering.h:34
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:660
llvm::analyzeReturnValues
static void analyzeReturnValues(const SmallVectorImpl< ArgT > &Args, CCState &CCInfo)
Analyze incoming and outgoing value of returning from a function.
Definition: AVRISelLowering.cpp:1125
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:185
llvm::MVT::integer_valuetypes
static auto integer_valuetypes()
Definition: MachineValueType.h:1416
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:750
LHS
Value * LHS
Definition: X86PartialReduction.cpp:73
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:967
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::AVRCC::COND_PL
@ COND_PL
Plus.
Definition: AVRInstrInfo.h:39
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:39
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:694
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1123
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:668
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:679
llvm::AVRISD::ASR
@ ASR
Arithmetic shift right.
Definition: AVRISelLowering.h:46
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:729
llvm::AArch64ISD::RET_FLAG
@ RET_FLAG
Definition: AArch64ISelLowering.h:66
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1392
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:747
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:256
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::TargetLoweringBase::AddrMode::HasBaseReg
bool HasBaseReg
Definition: TargetLowering.h:2399
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AVRSubtarget
A specific AVR target MCU.
Definition: AVRSubtarget.h:31
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1413
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3277
llvm::AVRISD::SWAP
@ SWAP
Swap Rd[7:4] <-> Rd[3:0].
Definition: AVRISelLowering.h:69
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:735
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:658
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2214
llvm::Instruction
Definition: Instruction.h:45
llvm::AArch64_AM::LSR
@ LSR
Definition: AArch64AddressingModes.h:36
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::DataLayout::getABITypeAlign
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:828
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1153
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition: TargetLowering.h:2269
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::AVRTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: AVRISelLowering.cpp:2048
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::AVRSubtarget::getInstrInfo
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:41
llvm::TargetLowering::C_Register
@ C_Register
Definition: TargetLowering.h:4264
llvm::CCState::getContext
LLVMContext & getContext() const
Definition: CallingConvLower.h:257
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:823
llvm::TargetLowering::C_Immediate
@ C_Immediate
Definition: TargetLowering.h:4267
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:632
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::TargetLoweringBase::setBooleanVectorContents
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Definition: TargetLowering.h:2162
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1435
llvm::AArch64_AM::ROR
@ ROR
Definition: AArch64AddressingModes.h:38
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AVRTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: AVRISelLowering.cpp:1711
llvm::AVRTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: AVRISelLowering.cpp:1861
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::AVRCC::COND_GE
@ COND_GE
Greater than or equal.
Definition: AVRInstrInfo.h:34
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1382
llvm::Sched::RegPressure
@ RegPressure
Definition: TargetLowering.h:100
llvm::AVRISD::TST
@ TST
Test for zero or minus instruction.
Definition: AVRISelLowering.h:67
llvm::ISD::POST_INC
@ POST_INC
Definition: ISDOpcodes.h:1319
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2231
llvm::AVRCC::CondCodes
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:31
llvm::TargetLowering::CW_SpecificReg
@ CW_SpecificReg
Definition: TargetLowering.h:4281
NODE
#define NODE(name)
llvm::ISD::Register
@ Register
Definition: ISDOpcodes.h:74
llvm::AVRTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: AVRISelLowering.cpp:1807
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:341
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:37
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::AVRISD::ASRLOOP
@ ASRLOOP
A loop of single arithmetic shift right instructions.
Definition: AVRISelLowering.h:56
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1151
llvm::ConstantFPSDNode
Definition: SelectionDAGNodes.h:1607
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:197
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::getTotalArgumentsSizeInBytes
static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl< ArgT > &Args)
Count the total number of bytes needed to pass or return these arguments.
Definition: AVRISelLowering.cpp:1112
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2180
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1150
llvm::TargetLowering::CW_Register
@ CW_Register
Definition: TargetLowering.h:4282
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AVRCC::COND_NE
@ COND_NE
Not equal.
Definition: AVRInstrInfo.h:33
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8327
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1129
llvm::AVRISD::LSRBN
@ LSRBN
Byte logical shift right N bits.
Definition: AVRISelLowering.h:43
llvm::TargetLowering::AsmOperandInfo
This contains information for each constraint that we are lowering.
Definition: TargetLowering.h:4289
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:420
llvm::CCValAssign::getMem
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:102
AVRTargetMachine.h
llvm::AVRTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: AVRISelLowering.cpp:819
llvm::StoreSDNode
This class is used to represent ISD::STORE nodes.
Definition: SelectionDAGNodes.h:2328
llvm::AVRISD::ROL
@ ROL
Bit rotate left.
Definition: AVRISelLowering.h:51
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1350
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:171
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::AVRTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: AVRISelLowering.cpp:1977
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3853
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:615
llvm::AVRISD::LSRWN
@ LSRWN
Word logical shift right N bits.
Definition: AVRISelLowering.h:44
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::AVRSubtarget::supportsMultiplication
bool supportsMultiplication() const
Definition: AVRSubtarget.h:79
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:405
llvm::AVRTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: AVRISelLowering.cpp:880
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:852
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1384
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1370
llvm::ISD::BasicBlock
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:71
AVRMCTargetDesc.h
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::AVRTargetLowering::getPostIndexedAddressParts
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
Definition: AVRISelLowering.cpp:966
llvm::CallingConv::AVR_BUILTIN
@ AVR_BUILTIN
Calling convention used for special AVR rtlib functions which have an "optimized" convention to prese...
Definition: CallingConv.h:199
llvm::TargetLowering::CW_Memory
@ CW_Memory
Definition: TargetLowering.h:4283
llvm::AVRCC::COND_MI
@ COND_MI
Minus.
Definition: AVRInstrInfo.h:38
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:716
llvm::RegList8
static const MCPhysReg RegList8[]
Registers for calling conventions, ordered in reverse as required by ABI.
Definition: AVRISelLowering.cpp:1026
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1046
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::TargetLowering::CW_Default
@ CW_Default
Definition: TargetLowering.h:4285
llvm::AVRTargetLowering::AVRTargetLowering
AVRTargetLowering(const AVRTargetMachine &TM, const AVRSubtarget &STI)
Definition: AVRISelLowering.cpp:35
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::AVRTargetLowering::Subtarget
const AVRSubtarget & Subtarget
Definition: AVRISelLowering.h:185
llvm::AVRISD::BRCOND
@ BRCOND
AVR conditional branches.
Definition: AVRISelLowering.h:61
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:237
llvm::AVRISD::LSR
@ LSR
Logical shift right.
Definition: AVRISelLowering.h:42
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:155
llvm::CCState::AllocateReg
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
Definition: CallingConvLower.h:351
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
AVRSubtarget.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::TargetLowering::LowerAsmOperandForConstraint
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Definition: TargetLowering.cpp:4617
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:967
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
llvm::TargetLoweringBase::AddrMode::BaseGV
GlobalValue * BaseGV
Definition: TargetLowering.h:2397
uint32_t
AVRMachineFunctionInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:4694
llvm::AVRISD::ASRBN
@ ASRBN
Byte arithmetic shift right N bits.
Definition: AVRISelLowering.h:47
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2250
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1143
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1350
llvm::TargetLowering::C_RegisterClass
@ C_RegisterClass
Definition: TargetLowering.h:4265
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:303
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:185
llvm::RegList16
static const MCPhysReg RegList16[]
Definition: AVRISelLowering.cpp:1030
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::StringRef::size
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
j
return j(j<< 16)
llvm::AArch64_AM::ASR
@ ASR
Definition: AArch64AddressingModes.h:37
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1393
llvm::TargetLoweringBase::AddrMode::BaseOffs
int64_t BaseOffs
Definition: TargetLowering.h:2398
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2238
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1720
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition: TargetLowering.h:2260
uint16_t
llvm::TargetLoweringBase::AddrMode::Scale
int64_t Scale
Definition: TargetLowering.h:2400
CallingConvLower.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::X86::FirstMacroFusionInstKind::Cmp
@ Cmp
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4272
Function.h
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Definition: CallingConvLower.h:425
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:200
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:270
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::AVRCC::COND_LO
@ COND_LO
Unsigned lower.
Definition: AVRInstrInfo.h:37
llvm::SDNode::getNumValues
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Definition: SelectionDAGNodes.h:965
llvm::analyzeArguments
static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo)
Analyze incoming and outgoing function arguments.
Definition: AVRISelLowering.cpp:1045
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:232
StringSwitch.h
AVR.h
llvm::TargetLowering::CW_Invalid
@ CW_Invalid
Definition: TargetLowering.h:4274
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:2940
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1041
llvm::AVRCC::COND_EQ
@ COND_EQ
Equal.
Definition: AVRInstrInfo.h:32
llvm::intCCToAVRCC
static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC)
IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
Definition: AVRISelLowering.cpp:527
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:717
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2148
llvm::AVRSubtarget::getRegisterInfo
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:51
llvm::AVRISD::WRAPPER
@ WRAPPER
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Definition: AVRISelLowering.h:37
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:657
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1008
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:272
MachineInstrBuilder.h
llvm::CCValAssign::getReg
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:79
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:198
llvm::AVRTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: AVRISelLowering.cpp:2155
llvm::ARCISD::CMP
@ CMP
Definition: ARCISelLowering.h:40
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1293
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:280
llvm::TargetLoweringBase::setMinimumJumpTableEntries
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
Definition: TargetLoweringBase.cpp:2018
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:659
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4364
llvm::AVRISD::RET_FLAG
@ RET_FLAG
Return from subroutine.
Definition: AVRISelLowering.h:29
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:667
llvm::AVRInstrInfo
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:64
llvm::AVRISD::LSRLO
@ LSRLO
Lower 8-bit of word logical shift right.
Definition: AVRISelLowering.h:45
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2396
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::AVRISD::LSRLOOP
@ LSRLOOP
A loop of single logical shift right instructions.
Definition: AVRISelLowering.h:53
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:614
llvm::AVRISD::ASRLO
@ ASRLO
Lower 8-bit of word arithmetic shift right.
Definition: AVRISelLowering.h:49
RegName
#define RegName(no)
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:889
llvm::msgpack::Type
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:48
llvm::AVRISD::CMP
@ CMP
Compare instruction.
Definition: AVRISelLowering.h:63
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:637
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:43
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1036
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:726
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::TargetLoweringBase::getLibcallCallingConv
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:2967
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1012
AVRISelLowering.h
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1021
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:661
llvm::AVRISD::LSLBN
@ LSLBN
Byte logical shift left N bits.
Definition: AVRISelLowering.h:39
llvm::TargetLowering::getConstraintType
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Definition: TargetLowering.cpp:4556
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:345
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:669
llvm::codeview::PublicSymFlags::Function
@ Function
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1152
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::ISD::EXTRACT_ELEMENT
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
Definition: ISDOpcodes.h:222
llvm::AVR::isProgramMemoryAccess
bool isProgramMemoryAccess(MemSDNode const *N)
Definition: AVR.h:73
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:289
llvm::DataLayout::getTypeAllocSize
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:506
TargetLoweringObjectFileImpl.h
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::AVRISD::RORLOOP
@ RORLOOP
A loop of single right bit rotate instructions.
Definition: AVRISelLowering.h:55