LLVM  16.0.0git
AVRISelLowering.cpp
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1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that AVR uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRISelLowering.h"
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/IR/Function.h"
27 
28 #include "AVR.h"
29 #include "AVRMachineFunctionInfo.h"
30 #include "AVRSubtarget.h"
31 #include "AVRTargetMachine.h"
33 
34 namespace llvm {
35 
37  const AVRSubtarget &STI)
38  : TargetLowering(TM), Subtarget(STI) {
39  // Set up the register classes.
40  addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
41  addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
42 
43  // Compute derived properties from the register classes.
45 
51 
54 
59 
61 
62  for (MVT VT : MVT::integer_valuetypes()) {
63  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
66  }
67  }
68 
70 
71  for (MVT VT : MVT::integer_valuetypes()) {
76  }
77 
78  // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
79  // revert into a sub since we don't have an add with immediate instruction.
82 
83  // our shift instructions are only able to shift 1 bit at a time, so handle
84  // this in a custom way.
94 
99 
105 
116 
118 
119  // Add support for postincrement and predecrement load/stores.
128 
130 
135 
136  // Atomic operations which must be lowered to rtlib calls
137  for (MVT VT : MVT::integer_valuetypes()) {
145  }
146 
147  // Division/remainder
156 
157  // Make division and modulus custom
164 
165  // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
168 
169  // Expand 16 bit multiplications.
172 
173  // Expand multiplications to libcalls when there is
174  // no hardware MUL.
178  }
179 
180  for (MVT VT : MVT::integer_valuetypes()) {
183  }
184 
185  for (MVT VT : MVT::integer_valuetypes()) {
189  }
190 
191  for (MVT VT : MVT::integer_valuetypes()) {
193  // TODO: The generated code is pretty poor. Investigate using the
194  // same "shift and subtract with carry" trick that we do for
195  // extending 8-bit to 16-bit. This may require infrastructure
196  // improvements in how we treat 16-bit "registers" to be feasible.
197  }
198 
199  // Division rtlib functions (not supported), use divmod functions instead
200  setLibcallName(RTLIB::SDIV_I8, nullptr);
201  setLibcallName(RTLIB::SDIV_I16, nullptr);
202  setLibcallName(RTLIB::SDIV_I32, nullptr);
203  setLibcallName(RTLIB::UDIV_I8, nullptr);
204  setLibcallName(RTLIB::UDIV_I16, nullptr);
205  setLibcallName(RTLIB::UDIV_I32, nullptr);
206 
207  // Modulus rtlib functions (not supported), use divmod functions instead
208  setLibcallName(RTLIB::SREM_I8, nullptr);
209  setLibcallName(RTLIB::SREM_I16, nullptr);
210  setLibcallName(RTLIB::SREM_I32, nullptr);
211  setLibcallName(RTLIB::UREM_I8, nullptr);
212  setLibcallName(RTLIB::UREM_I16, nullptr);
213  setLibcallName(RTLIB::UREM_I32, nullptr);
214 
215  // Division and modulus rtlib functions
216  setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
217  setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
218  setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
219  setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
220  setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
221  setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
222 
223  // Several of the runtime library functions use a special calling conv
225  setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN);
227  setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN);
228 
229  // Trigonometric rtlib functions
230  setLibcallName(RTLIB::SIN_F32, "sin");
231  setLibcallName(RTLIB::COS_F32, "cos");
232 
234  setMinimumJumpTableEntries(UINT_MAX);
235 }
236 
237 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
238 #define NODE(name) \
239  case AVRISD::name: \
240  return #name
241 
242  switch (Opcode) {
243  default:
244  return nullptr;
245  NODE(RET_FLAG);
246  NODE(RETI_FLAG);
247  NODE(CALL);
248  NODE(WRAPPER);
249  NODE(LSL);
250  NODE(LSR);
251  NODE(ROL);
252  NODE(ROR);
253  NODE(ASR);
254  NODE(LSLLOOP);
255  NODE(LSRLOOP);
256  NODE(ROLLOOP);
257  NODE(RORLOOP);
258  NODE(ASRLOOP);
259  NODE(BRCOND);
260  NODE(CMP);
261  NODE(CMPC);
262  NODE(TST);
263  NODE(SELECT_CC);
264 #undef NODE
265  }
266 }
267 
269  EVT VT) const {
270  assert(!VT.isVector() && "No AVR SetCC type for vectors!");
271  return MVT::i8;
272 }
273 
274 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
275  unsigned Opc8;
276  const SDNode *N = Op.getNode();
277  EVT VT = Op.getValueType();
278  SDLoc dl(N);
280  "Expected power-of-2 shift amount");
281 
282  // Expand non-constant shifts to loops.
283  if (!isa<ConstantSDNode>(N->getOperand(1))) {
284  switch (Op.getOpcode()) {
285  default:
286  llvm_unreachable("Invalid shift opcode!");
287  case ISD::SHL:
288  return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
289  N->getOperand(1));
290  case ISD::SRL:
291  return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
292  N->getOperand(1));
293  case ISD::ROTL: {
294  SDValue Amt = N->getOperand(1);
295  EVT AmtVT = Amt.getValueType();
296  Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
297  DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
298  return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
299  }
300  case ISD::ROTR: {
301  SDValue Amt = N->getOperand(1);
302  EVT AmtVT = Amt.getValueType();
303  Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
304  DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
305  return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
306  }
307  case ISD::SRA:
308  return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
309  N->getOperand(1));
310  }
311  }
312 
313  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
314  SDValue Victim = N->getOperand(0);
315 
316  switch (Op.getOpcode()) {
317  case ISD::SRA:
318  Opc8 = AVRISD::ASR;
319  break;
320  case ISD::ROTL:
321  Opc8 = AVRISD::ROL;
322  ShiftAmount = ShiftAmount % VT.getSizeInBits();
323  break;
324  case ISD::ROTR:
325  Opc8 = AVRISD::ROR;
326  ShiftAmount = ShiftAmount % VT.getSizeInBits();
327  break;
328  case ISD::SRL:
329  Opc8 = AVRISD::LSR;
330  break;
331  case ISD::SHL:
332  Opc8 = AVRISD::LSL;
333  break;
334  default:
335  llvm_unreachable("Invalid shift opcode");
336  }
337 
338  // Optimize int8/int16 shifts.
339  if (VT.getSizeInBits() == 8) {
340  if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
341  // Optimize LSL when 4 <= ShiftAmount <= 6.
342  Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
343  Victim =
344  DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT));
345  ShiftAmount -= 4;
346  } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
347  ShiftAmount < 7) {
348  // Optimize LSR when 4 <= ShiftAmount <= 6.
349  Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
350  Victim =
351  DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT));
352  ShiftAmount -= 4;
353  } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
354  // Optimize LSL when ShiftAmount == 7.
355  Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim,
356  DAG.getConstant(7, dl, VT));
357  ShiftAmount = 0;
358  } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
359  // Optimize LSR when ShiftAmount == 7.
360  Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim,
361  DAG.getConstant(7, dl, VT));
362  ShiftAmount = 0;
363  } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) {
364  // Optimize ASR when ShiftAmount == 6.
365  Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
366  DAG.getConstant(6, dl, VT));
367  ShiftAmount = 0;
368  } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
369  // Optimize ASR when ShiftAmount == 7.
370  Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
371  DAG.getConstant(7, dl, VT));
372  ShiftAmount = 0;
373  }
374  } else if (VT.getSizeInBits() == 16) {
375  if (Op.getOpcode() == ISD::SRA)
376  // Special optimization for int16 arithmetic right shift.
377  switch (ShiftAmount) {
378  case 15:
379  Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
380  DAG.getConstant(15, dl, VT));
381  ShiftAmount = 0;
382  break;
383  case 14:
384  Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
385  DAG.getConstant(14, dl, VT));
386  ShiftAmount = 0;
387  break;
388  case 7:
389  Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
390  DAG.getConstant(7, dl, VT));
391  ShiftAmount = 0;
392  break;
393  default:
394  break;
395  }
396  if (4 <= ShiftAmount && ShiftAmount < 8)
397  switch (Op.getOpcode()) {
398  case ISD::SHL:
399  Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
400  DAG.getConstant(4, dl, VT));
401  ShiftAmount -= 4;
402  break;
403  case ISD::SRL:
404  Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
405  DAG.getConstant(4, dl, VT));
406  ShiftAmount -= 4;
407  break;
408  default:
409  break;
410  }
411  else if (8 <= ShiftAmount && ShiftAmount < 12)
412  switch (Op.getOpcode()) {
413  case ISD::SHL:
414  Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
415  DAG.getConstant(8, dl, VT));
416  ShiftAmount -= 8;
417  // Only operate on the higher byte for remaining shift bits.
418  Opc8 = AVRISD::LSLHI;
419  break;
420  case ISD::SRL:
421  Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
422  DAG.getConstant(8, dl, VT));
423  ShiftAmount -= 8;
424  // Only operate on the lower byte for remaining shift bits.
425  Opc8 = AVRISD::LSRLO;
426  break;
427  case ISD::SRA:
428  Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
429  DAG.getConstant(8, dl, VT));
430  ShiftAmount -= 8;
431  // Only operate on the lower byte for remaining shift bits.
432  Opc8 = AVRISD::ASRLO;
433  break;
434  default:
435  break;
436  }
437  else if (12 <= ShiftAmount)
438  switch (Op.getOpcode()) {
439  case ISD::SHL:
440  Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
441  DAG.getConstant(12, dl, VT));
442  ShiftAmount -= 12;
443  // Only operate on the higher byte for remaining shift bits.
444  Opc8 = AVRISD::LSLHI;
445  break;
446  case ISD::SRL:
447  Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
448  DAG.getConstant(12, dl, VT));
449  ShiftAmount -= 12;
450  // Only operate on the lower byte for remaining shift bits.
451  Opc8 = AVRISD::LSRLO;
452  break;
453  case ISD::SRA:
454  Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
455  DAG.getConstant(8, dl, VT));
456  ShiftAmount -= 8;
457  // Only operate on the lower byte for remaining shift bits.
458  Opc8 = AVRISD::ASRLO;
459  break;
460  default:
461  break;
462  }
463  }
464 
465  while (ShiftAmount--) {
466  Victim = DAG.getNode(Opc8, dl, VT, Victim);
467  }
468 
469  return Victim;
470 }
471 
472 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
473  unsigned Opcode = Op->getOpcode();
474  assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
475  "Invalid opcode for Div/Rem lowering");
476  bool IsSigned = (Opcode == ISD::SDIVREM);
477  EVT VT = Op->getValueType(0);
478  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
479 
480  RTLIB::Libcall LC;
481  switch (VT.getSimpleVT().SimpleTy) {
482  default:
483  llvm_unreachable("Unexpected request for libcall!");
484  case MVT::i8:
485  LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
486  break;
487  case MVT::i16:
488  LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
489  break;
490  case MVT::i32:
491  LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
492  break;
493  }
494 
495  SDValue InChain = DAG.getEntryNode();
496 
498  TargetLowering::ArgListEntry Entry;
499  for (SDValue const &Value : Op->op_values()) {
500  Entry.Node = Value;
501  Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
502  Entry.IsSExt = IsSigned;
503  Entry.IsZExt = !IsSigned;
504  Args.push_back(Entry);
505  }
506 
507  SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
508  getPointerTy(DAG.getDataLayout()));
509 
510  Type *RetTy = (Type *)StructType::get(Ty, Ty);
511 
512  SDLoc dl(Op);
513  TargetLowering::CallLoweringInfo CLI(DAG);
514  CLI.setDebugLoc(dl)
515  .setChain(InChain)
516  .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
517  .setInRegister()
518  .setSExtResult(IsSigned)
519  .setZExtResult(!IsSigned);
520 
521  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
522  return CallInfo.first;
523 }
524 
525 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
526  SelectionDAG &DAG) const {
527  auto DL = DAG.getDataLayout();
528 
529  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
530  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
531 
532  // Create the TargetGlobalAddress node, folding in the constant offset.
533  SDValue Result =
534  DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
535  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
536 }
537 
538 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
539  SelectionDAG &DAG) const {
540  auto DL = DAG.getDataLayout();
541  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
542 
543  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
544 
545  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
546 }
547 
548 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
550  switch (CC) {
551  default:
552  llvm_unreachable("Unknown condition code!");
553  case ISD::SETEQ:
554  return AVRCC::COND_EQ;
555  case ISD::SETNE:
556  return AVRCC::COND_NE;
557  case ISD::SETGE:
558  return AVRCC::COND_GE;
559  case ISD::SETLT:
560  return AVRCC::COND_LT;
561  case ISD::SETUGE:
562  return AVRCC::COND_SH;
563  case ISD::SETULT:
564  return AVRCC::COND_LO;
565  }
566 }
567 
568 /// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
569 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
570  SelectionDAG &DAG, SDLoc DL) const {
571  assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
572  "LHS and RHS have different types");
573  assert(((LHS.getSimpleValueType() == MVT::i16) ||
574  (LHS.getSimpleValueType() == MVT::i8)) &&
575  "invalid comparison type");
576 
577  SDValue Cmp;
578 
579  if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) {
580  // Generate a CPI/CPC pair if RHS is a 16-bit constant.
581  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
582  DAG.getIntPtrConstant(0, DL));
583  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
584  DAG.getIntPtrConstant(1, DL));
585  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
586  DAG.getIntPtrConstant(0, DL));
587  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
588  DAG.getIntPtrConstant(1, DL));
589  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
590  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
591  } else {
592  // Generate ordinary 16-bit comparison.
593  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
594  }
595 
596  return Cmp;
597 }
598 
599 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
600 /// the given operands.
601 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
602  SDValue &AVRcc, SelectionDAG &DAG,
603  SDLoc DL) const {
604  SDValue Cmp;
605  EVT VT = LHS.getValueType();
606  bool UseTest = false;
607 
608  switch (CC) {
609  default:
610  break;
611  case ISD::SETLE: {
612  // Swap operands and reverse the branching condition.
613  std::swap(LHS, RHS);
614  CC = ISD::SETGE;
615  break;
616  }
617  case ISD::SETGT: {
618  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
619  switch (C->getSExtValue()) {
620  case -1: {
621  // When doing lhs > -1 use a tst instruction on the top part of lhs
622  // and use brpl instead of using a chain of cp/cpc.
623  UseTest = true;
624  AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
625  break;
626  }
627  case 0: {
628  // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
629  // __zero_reg__ in lhs.
630  RHS = LHS;
631  LHS = DAG.getConstant(0, DL, VT);
632  CC = ISD::SETLT;
633  break;
634  }
635  default: {
636  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
637  // us to fold the constant into the cmp instruction.
638  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
639  CC = ISD::SETGE;
640  break;
641  }
642  }
643  break;
644  }
645  // Swap operands and reverse the branching condition.
646  std::swap(LHS, RHS);
647  CC = ISD::SETLT;
648  break;
649  }
650  case ISD::SETLT: {
651  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
652  switch (C->getSExtValue()) {
653  case 1: {
654  // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
655  // __zero_reg__ in lhs.
656  RHS = LHS;
657  LHS = DAG.getConstant(0, DL, VT);
658  CC = ISD::SETGE;
659  break;
660  }
661  case 0: {
662  // When doing lhs < 0 use a tst instruction on the top part of lhs
663  // and use brmi instead of using a chain of cp/cpc.
664  UseTest = true;
665  AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
666  break;
667  }
668  }
669  }
670  break;
671  }
672  case ISD::SETULE: {
673  // Swap operands and reverse the branching condition.
674  std::swap(LHS, RHS);
675  CC = ISD::SETUGE;
676  break;
677  }
678  case ISD::SETUGT: {
679  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
680  // fold the constant into the cmp instruction.
681  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
682  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
683  CC = ISD::SETUGE;
684  break;
685  }
686  // Swap operands and reverse the branching condition.
687  std::swap(LHS, RHS);
688  CC = ISD::SETULT;
689  break;
690  }
691  }
692 
693  // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
694  // using the default and/or/xor expansion code which is much longer.
695  if (VT == MVT::i32) {
696  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
697  DAG.getIntPtrConstant(0, DL));
698  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
699  DAG.getIntPtrConstant(1, DL));
700  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
701  DAG.getIntPtrConstant(0, DL));
702  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
703  DAG.getIntPtrConstant(1, DL));
704 
705  if (UseTest) {
706  // When using tst we only care about the highest part.
707  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
708  DAG.getIntPtrConstant(1, DL));
709  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
710  } else {
711  Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL);
712  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
713  }
714  } else if (VT == MVT::i64) {
715  SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
716  DAG.getIntPtrConstant(0, DL));
717  SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
718  DAG.getIntPtrConstant(1, DL));
719 
720  SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
721  DAG.getIntPtrConstant(0, DL));
722  SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
723  DAG.getIntPtrConstant(1, DL));
724  SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
725  DAG.getIntPtrConstant(0, DL));
726  SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
727  DAG.getIntPtrConstant(1, DL));
728 
729  SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
730  DAG.getIntPtrConstant(0, DL));
731  SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
732  DAG.getIntPtrConstant(1, DL));
733 
734  SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
735  DAG.getIntPtrConstant(0, DL));
736  SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
737  DAG.getIntPtrConstant(1, DL));
738  SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
739  DAG.getIntPtrConstant(0, DL));
740  SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
741  DAG.getIntPtrConstant(1, DL));
742 
743  if (UseTest) {
744  // When using tst we only care about the highest part.
745  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
746  DAG.getIntPtrConstant(1, DL));
747  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
748  } else {
749  Cmp = getAVRCmp(LHS0, RHS0, DAG, DL);
750  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
751  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
752  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
753  }
754  } else if (VT == MVT::i8 || VT == MVT::i16) {
755  if (UseTest) {
756  // When using tst we only care about the highest part.
757  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
758  (VT == MVT::i8)
759  ? LHS
760  : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
761  LHS, DAG.getIntPtrConstant(1, DL)));
762  } else {
763  Cmp = getAVRCmp(LHS, RHS, DAG, DL);
764  }
765  } else {
766  llvm_unreachable("Invalid comparison size");
767  }
768 
769  // When using a test instruction AVRcc is already set.
770  if (!UseTest) {
771  AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
772  }
773 
774  return Cmp;
775 }
776 
777 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
778  SDValue Chain = Op.getOperand(0);
779  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
780  SDValue LHS = Op.getOperand(2);
781  SDValue RHS = Op.getOperand(3);
782  SDValue Dest = Op.getOperand(4);
783  SDLoc dl(Op);
784 
785  SDValue TargetCC;
786  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
787 
788  return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
789  Cmp);
790 }
791 
792 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
793  SDValue LHS = Op.getOperand(0);
794  SDValue RHS = Op.getOperand(1);
795  SDValue TrueV = Op.getOperand(2);
796  SDValue FalseV = Op.getOperand(3);
797  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
798  SDLoc dl(Op);
799 
800  SDValue TargetCC;
801  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
802 
803  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
804  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
805 
806  return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
807 }
808 
809 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
810  SDValue LHS = Op.getOperand(0);
811  SDValue RHS = Op.getOperand(1);
812  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
813  SDLoc DL(Op);
814 
815  SDValue TargetCC;
816  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
817 
818  SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
819  SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
820  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
821  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
822 
823  return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
824 }
825 
826 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
827  const MachineFunction &MF = DAG.getMachineFunction();
828  const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
829  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
830  auto DL = DAG.getDataLayout();
831  SDLoc dl(Op);
832 
833  // Vastart just stores the address of the VarArgsFrameIndex slot into the
834  // memory location argument.
835  SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
836 
837  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
838  MachinePointerInfo(SV));
839 }
840 
841 // Modify the existing ISD::INLINEASM node to add the implicit register r1.
842 SDValue AVRTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
843  SDValue R1Reg = DAG.getRegister(AVR::R1, MVT::i8);
844  if (Op.getOperand(Op.getNumOperands() - 1) == R1Reg ||
845  Op.getOperand(Op.getNumOperands() - 2) == R1Reg) {
846  // R1 has already been added. Don't add it again.
847  // If this isn't handled, we get called over and over again.
848  return Op;
849  }
850 
851  // Get a list of operands to the new INLINEASM node. This is mostly a copy,
852  // with some edits.
853  // Add the following operands at the end (but before the glue node, if it's
854  // there):
855  // - The flags of the implicit R1 register operand.
856  // - The implicit R1 register operand itself.
857  SDLoc dl(Op);
858  SmallVector<SDValue, 8> Ops;
859  SDNode *N = Op.getNode();
860  SDValue Glue;
861  for (unsigned I = 0; I < N->getNumOperands(); I++) {
862  SDValue Operand = N->getOperand(I);
863  if (Operand.getValueType() == MVT::Glue) {
864  // The glue operand always needs to be at the end, so we need to treat it
865  // specially.
866  Glue = Operand;
867  } else {
868  Ops.push_back(Operand);
869  }
870  }
872  Ops.push_back(DAG.getTargetConstant(Flags, dl, MVT::i32));
873  Ops.push_back(R1Reg);
874  if (Glue) {
875  Ops.push_back(Glue);
876  }
877 
878  // Replace the current INLINEASM node with a new one that has R1 as implicit
879  // parameter.
880  SDValue New = DAG.getNode(N->getOpcode(), dl, N->getVTList(), Ops);
881  DAG.ReplaceAllUsesOfValueWith(Op, New);
882  DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), New.getValue(1));
883 
884  return New;
885 }
886 
888  switch (Op.getOpcode()) {
889  default:
890  llvm_unreachable("Don't know how to custom lower this!");
891  case ISD::SHL:
892  case ISD::SRA:
893  case ISD::SRL:
894  case ISD::ROTL:
895  case ISD::ROTR:
896  return LowerShifts(Op, DAG);
897  case ISD::GlobalAddress:
898  return LowerGlobalAddress(Op, DAG);
899  case ISD::BlockAddress:
900  return LowerBlockAddress(Op, DAG);
901  case ISD::BR_CC:
902  return LowerBR_CC(Op, DAG);
903  case ISD::SELECT_CC:
904  return LowerSELECT_CC(Op, DAG);
905  case ISD::SETCC:
906  return LowerSETCC(Op, DAG);
907  case ISD::VASTART:
908  return LowerVASTART(Op, DAG);
909  case ISD::SDIVREM:
910  case ISD::UDIVREM:
911  return LowerDivRem(Op, DAG);
912  case ISD::INLINEASM:
913  return LowerINLINEASM(Op, DAG);
914  }
915 
916  return SDValue();
917 }
918 
919 /// Replace a node with an illegal result type
920 /// with a new node built out of custom code.
923  SelectionDAG &DAG) const {
924  SDLoc DL(N);
925 
926  switch (N->getOpcode()) {
927  case ISD::ADD: {
928  // Convert add (x, imm) into sub (x, -imm).
929  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
930  SDValue Sub = DAG.getNode(
931  ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
932  DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
933  Results.push_back(Sub);
934  }
935  break;
936  }
937  default: {
938  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
939 
940  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
941  Results.push_back(Res.getValue(I));
942 
943  break;
944  }
945  }
946 }
947 
948 /// Return true if the addressing mode represented
949 /// by AM is legal for this target, for a load/store of the specified type.
951  const AddrMode &AM, Type *Ty,
952  unsigned AS,
953  Instruction *I) const {
954  int64_t Offs = AM.BaseOffs;
955 
956  // Allow absolute addresses.
957  if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
958  return true;
959  }
960 
961  // Flash memory instructions only allow zero offsets.
962  if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
963  return false;
964  }
965 
966  // Allow reg+<6bit> offset.
967  if (Offs < 0)
968  Offs = -Offs;
969  if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 &&
970  isUInt<6>(Offs)) {
971  return true;
972  }
973 
974  return false;
975 }
976 
977 /// Returns true by value, base pointer and
978 /// offset pointer and addressing mode by reference if the node's address
979 /// can be legally represented as pre-indexed load / store address.
981  SDValue &Offset,
983  SelectionDAG &DAG) const {
984  EVT VT;
985  const SDNode *Op;
986  SDLoc DL(N);
987 
988  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
989  VT = LD->getMemoryVT();
990  Op = LD->getBasePtr().getNode();
991  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
992  return false;
994  return false;
995  }
996  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
997  VT = ST->getMemoryVT();
998  Op = ST->getBasePtr().getNode();
1000  return false;
1001  }
1002  } else {
1003  return false;
1004  }
1005 
1006  if (VT != MVT::i8 && VT != MVT::i16) {
1007  return false;
1008  }
1009 
1010  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1011  return false;
1012  }
1013 
1014  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1015  int RHSC = RHS->getSExtValue();
1016  if (Op->getOpcode() == ISD::SUB)
1017  RHSC = -RHSC;
1018 
1019  if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
1020  return false;
1021  }
1022 
1023  Base = Op->getOperand(0);
1024  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
1025  AM = ISD::PRE_DEC;
1026 
1027  return true;
1028  }
1029 
1030  return false;
1031 }
1032 
1033 /// Returns true by value, base pointer and
1034 /// offset pointer and addressing mode by reference if this node can be
1035 /// combined with a load / store to form a post-indexed load / store.
1037  SDValue &Base,
1038  SDValue &Offset,
1039  ISD::MemIndexedMode &AM,
1040  SelectionDAG &DAG) const {
1041  EVT VT;
1042  SDLoc DL(N);
1043 
1044  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1045  VT = LD->getMemoryVT();
1046  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1047  return false;
1048  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1049  VT = ST->getMemoryVT();
1051  return false;
1052  }
1053  } else {
1054  return false;
1055  }
1056 
1057  if (VT != MVT::i8 && VT != MVT::i16) {
1058  return false;
1059  }
1060 
1061  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1062  return false;
1063  }
1064 
1065  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1066  int RHSC = RHS->getSExtValue();
1067  if (Op->getOpcode() == ISD::SUB)
1068  RHSC = -RHSC;
1069  if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
1070  return false;
1071  }
1072 
1073  Base = Op->getOperand(0);
1074  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
1075  AM = ISD::POST_INC;
1076 
1077  return true;
1078  }
1079 
1080  return false;
1081 }
1082 
1084  const GlobalAddressSDNode *GA) const {
1085  return true;
1086 }
1087 
1088 //===----------------------------------------------------------------------===//
1089 // Formal Arguments Calling Convention Implementation
1090 //===----------------------------------------------------------------------===//
1091 
1092 #include "AVRGenCallingConv.inc"
1093 
1094 /// Registers for calling conventions, ordered in reverse as required by ABI.
1095 /// Both arrays must be of the same length.
1096 static const MCPhysReg RegList8AVR[] = {
1097  AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1098  AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
1099  AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
1100 static const MCPhysReg RegList8Tiny[] = {AVR::R25, AVR::R24, AVR::R23,
1101  AVR::R22, AVR::R21, AVR::R20};
1102 static const MCPhysReg RegList16AVR[] = {
1103  AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
1104  AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
1105  AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
1106  AVR::R11R10, AVR::R10R9, AVR::R9R8};
1107 static const MCPhysReg RegList16Tiny[] = {AVR::R26R25, AVR::R25R24,
1108  AVR::R24R23, AVR::R23R22,
1109  AVR::R22R21, AVR::R21R20};
1110 
1111 static_assert(std::size(RegList8AVR) == std::size(RegList16AVR),
1112  "8-bit and 16-bit register arrays must be of equal length");
1113 static_assert(std::size(RegList8Tiny) == std::size(RegList16Tiny),
1114  "8-bit and 16-bit register arrays must be of equal length");
1115 
1116 /// Analyze incoming and outgoing function arguments. We need custom C++ code
1117 /// to handle special constraints in the ABI.
1118 /// In addition, all pieces of a certain argument have to be passed either
1119 /// using registers or the stack but never mixing both.
1120 template <typename ArgT>
1122  const Function *F, const DataLayout *TD,
1123  const SmallVectorImpl<ArgT> &Args,
1125  CCState &CCInfo, bool Tiny) {
1126  // Choose the proper register list for argument passing according to the ABI.
1127  ArrayRef<MCPhysReg> RegList8;
1128  ArrayRef<MCPhysReg> RegList16;
1129  if (Tiny) {
1132  } else {
1135  }
1136 
1137  unsigned NumArgs = Args.size();
1138  // This is the index of the last used register, in RegList*.
1139  // -1 means R26 (R26 is never actually used in CC).
1140  int RegLastIdx = -1;
1141  // Once a value is passed to the stack it will always be used
1142  bool UseStack = false;
1143  for (unsigned i = 0; i != NumArgs;) {
1144  MVT VT = Args[i].VT;
1145  // We have to count the number of bytes for each function argument, that is
1146  // those Args with the same OrigArgIndex. This is important in case the
1147  // function takes an aggregate type.
1148  // Current argument will be between [i..j).
1149  unsigned ArgIndex = Args[i].OrigArgIndex;
1150  unsigned TotalBytes = VT.getStoreSize();
1151  unsigned j = i + 1;
1152  for (; j != NumArgs; ++j) {
1153  if (Args[j].OrigArgIndex != ArgIndex)
1154  break;
1155  TotalBytes += Args[j].VT.getStoreSize();
1156  }
1157  // Round up to even number of bytes.
1158  TotalBytes = alignTo(TotalBytes, 2);
1159  // Skip zero sized arguments
1160  if (TotalBytes == 0)
1161  continue;
1162  // The index of the first register to be used
1163  unsigned RegIdx = RegLastIdx + TotalBytes;
1164  RegLastIdx = RegIdx;
1165  // If there are not enough registers, use the stack
1166  if (RegIdx >= RegList8.size()) {
1167  UseStack = true;
1168  }
1169  for (; i != j; ++i) {
1170  MVT VT = Args[i].VT;
1171 
1172  if (UseStack) {
1173  auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
1174  unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
1175  TD->getABITypeAlign(evt));
1176  CCInfo.addLoc(
1177  CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full));
1178  } else {
1179  unsigned Reg;
1180  if (VT == MVT::i8) {
1181  Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1182  } else if (VT == MVT::i16) {
1183  Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1184  } else {
1186  "calling convention can only manage i8 and i16 types");
1187  }
1188  assert(Reg && "register not available in calling convention");
1189  CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1190  // Registers inside a particular argument are sorted in increasing order
1191  // (remember the array is reversed).
1192  RegIdx -= VT.getStoreSize();
1193  }
1194  }
1195  }
1196 }
1197 
1198 /// Count the total number of bytes needed to pass or return these arguments.
1199 template <typename ArgT>
1200 static unsigned
1202  unsigned TotalBytes = 0;
1203 
1204  for (const ArgT &Arg : Args) {
1205  TotalBytes += Arg.VT.getStoreSize();
1206  }
1207  return TotalBytes;
1208 }
1209 
1210 /// Analyze incoming and outgoing value of returning from a function.
1211 /// The algorithm is similar to analyzeArguments, but there can only be
1212 /// one value, possibly an aggregate, and it is limited to 8 bytes.
1213 template <typename ArgT>
1215  CCState &CCInfo, bool Tiny) {
1216  unsigned NumArgs = Args.size();
1217  unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
1218  // CanLowerReturn() guarantees this assertion.
1219  if (Tiny)
1220  assert(TotalBytes <= 4 &&
1221  "return values greater than 4 bytes cannot be lowered on AVRTiny");
1222  else
1223  assert(TotalBytes <= 8 &&
1224  "return values greater than 8 bytes cannot be lowered on AVR");
1225 
1226  // Choose the proper register list for argument passing according to the ABI.
1227  ArrayRef<MCPhysReg> RegList8;
1228  ArrayRef<MCPhysReg> RegList16;
1229  if (Tiny) {
1232  } else {
1235  }
1236 
1237  // GCC-ABI says that the size is rounded up to the next even number,
1238  // but actually once it is more than 4 it will always round up to 8.
1239  if (TotalBytes > 4) {
1240  TotalBytes = 8;
1241  } else {
1242  TotalBytes = alignTo(TotalBytes, 2);
1243  }
1244 
1245  // The index of the first register to use.
1246  int RegIdx = TotalBytes - 1;
1247  for (unsigned i = 0; i != NumArgs; ++i) {
1248  MVT VT = Args[i].VT;
1249  unsigned Reg;
1250  if (VT == MVT::i8) {
1251  Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1252  } else if (VT == MVT::i16) {
1253  Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1254  } else {
1255  llvm_unreachable("calling convention can only manage i8 and i16 types");
1256  }
1257  assert(Reg && "register not available in calling convention");
1258  CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1259  // Registers sort in increasing order
1260  RegIdx -= VT.getStoreSize();
1261  }
1262 }
1263 
1264 SDValue AVRTargetLowering::LowerFormalArguments(
1265  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1266  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1267  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1268  MachineFunction &MF = DAG.getMachineFunction();
1269  MachineFrameInfo &MFI = MF.getFrameInfo();
1270  auto DL = DAG.getDataLayout();
1271 
1272  // Assign locations to all of the incoming arguments.
1273  SmallVector<CCValAssign, 16> ArgLocs;
1274  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1275  *DAG.getContext());
1276 
1277  // Variadic functions do not need all the analysis below.
1278  if (isVarArg) {
1279  CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
1280  } else {
1281  analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo,
1283  }
1284 
1285  SDValue ArgValue;
1286  for (CCValAssign &VA : ArgLocs) {
1287 
1288  // Arguments stored on registers.
1289  if (VA.isRegLoc()) {
1290  EVT RegVT = VA.getLocVT();
1291  const TargetRegisterClass *RC;
1292  if (RegVT == MVT::i8) {
1293  RC = &AVR::GPR8RegClass;
1294  } else if (RegVT == MVT::i16) {
1295  RC = &AVR::DREGSRegClass;
1296  } else {
1297  llvm_unreachable("Unknown argument type!");
1298  }
1299 
1300  Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
1301  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1302 
1303  // :NOTE: Clang should not promote any i8 into i16 but for safety the
1304  // following code will handle zexts or sexts generated by other
1305  // front ends. Otherwise:
1306  // If this is an 8 bit value, it is really passed promoted
1307  // to 16 bits. Insert an assert[sz]ext to capture this, then
1308  // truncate to the right size.
1309  switch (VA.getLocInfo()) {
1310  default:
1311  llvm_unreachable("Unknown loc info!");
1312  case CCValAssign::Full:
1313  break;
1314  case CCValAssign::BCvt:
1315  ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1316  break;
1317  case CCValAssign::SExt:
1318  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1319  DAG.getValueType(VA.getValVT()));
1320  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1321  break;
1322  case CCValAssign::ZExt:
1323  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1324  DAG.getValueType(VA.getValVT()));
1325  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1326  break;
1327  }
1328 
1329  InVals.push_back(ArgValue);
1330  } else {
1331  // Only arguments passed on the stack should make it here.
1332  assert(VA.isMemLoc());
1333 
1334  EVT LocVT = VA.getLocVT();
1335 
1336  // Create the frame index object for this incoming parameter.
1337  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1338  VA.getLocMemOffset(), true);
1339 
1340  // Create the SelectionDAG nodes corresponding to a load
1341  // from this parameter.
1342  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1343  InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1345  }
1346  }
1347 
1348  // If the function takes variable number of arguments, make a frame index for
1349  // the start of the first vararg value... for expansion of llvm.va_start.
1350  if (isVarArg) {
1351  unsigned StackSize = CCInfo.getNextStackOffset();
1352  AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1353 
1354  AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1355  }
1356 
1357  return Chain;
1358 }
1359 
1360 //===----------------------------------------------------------------------===//
1361 // Call Calling Convention Implementation
1362 //===----------------------------------------------------------------------===//
1363 
1364 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1365  SmallVectorImpl<SDValue> &InVals) const {
1366  SelectionDAG &DAG = CLI.DAG;
1367  SDLoc &DL = CLI.DL;
1368  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1369  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1370  SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1371  SDValue Chain = CLI.Chain;
1372  SDValue Callee = CLI.Callee;
1373  bool &isTailCall = CLI.IsTailCall;
1374  CallingConv::ID CallConv = CLI.CallConv;
1375  bool isVarArg = CLI.IsVarArg;
1376 
1377  MachineFunction &MF = DAG.getMachineFunction();
1378 
1379  // AVR does not yet support tail call optimization.
1380  isTailCall = false;
1381 
1382  // Analyze operands of the call, assigning locations to each operand.
1383  SmallVector<CCValAssign, 16> ArgLocs;
1384  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1385  *DAG.getContext());
1386 
1387  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1388  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1389  // node so that legalize doesn't hack it.
1390  const Function *F = nullptr;
1391  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1392  const GlobalValue *GV = G->getGlobal();
1393  if (isa<Function>(GV))
1394  F = cast<Function>(GV);
1395  Callee =
1396  DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
1397  } else if (const ExternalSymbolSDNode *ES =
1398  dyn_cast<ExternalSymbolSDNode>(Callee)) {
1399  Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1400  getPointerTy(DAG.getDataLayout()));
1401  }
1402 
1403  // Variadic functions do not need all the analysis below.
1404  if (isVarArg) {
1405  CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
1406  } else {
1407  analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo,
1409  }
1410 
1411  // Get a count of how many bytes are to be pushed on the stack.
1412  unsigned NumBytes = CCInfo.getNextStackOffset();
1413 
1414  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1415 
1416  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1417 
1418  // First, walk the register assignments, inserting copies.
1419  unsigned AI, AE;
1420  bool HasStackArgs = false;
1421  for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1422  CCValAssign &VA = ArgLocs[AI];
1423  EVT RegVT = VA.getLocVT();
1424  SDValue Arg = OutVals[AI];
1425 
1426  // Promote the value if needed. With Clang this should not happen.
1427  switch (VA.getLocInfo()) {
1428  default:
1429  llvm_unreachable("Unknown loc info!");
1430  case CCValAssign::Full:
1431  break;
1432  case CCValAssign::SExt:
1433  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1434  break;
1435  case CCValAssign::ZExt:
1436  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1437  break;
1438  case CCValAssign::AExt:
1439  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1440  break;
1441  case CCValAssign::BCvt:
1442  Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1443  break;
1444  }
1445 
1446  // Stop when we encounter a stack argument, we need to process them
1447  // in reverse order in the loop below.
1448  if (VA.isMemLoc()) {
1449  HasStackArgs = true;
1450  break;
1451  }
1452 
1453  // Arguments that can be passed on registers must be kept in the RegsToPass
1454  // vector.
1455  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1456  }
1457 
1458  // Second, stack arguments have to walked.
1459  // Previously this code created chained stores but those chained stores appear
1460  // to be unchained in the legalization phase. Therefore, do not attempt to
1461  // chain them here. In fact, chaining them here somehow causes the first and
1462  // second store to be reversed which is the exact opposite of the intended
1463  // effect.
1464  if (HasStackArgs) {
1465  SmallVector<SDValue, 8> MemOpChains;
1466  for (; AI != AE; AI++) {
1467  CCValAssign &VA = ArgLocs[AI];
1468  SDValue Arg = OutVals[AI];
1469 
1470  assert(VA.isMemLoc());
1471 
1472  // SP points to one stack slot further so add one to adjust it.
1473  SDValue PtrOff = DAG.getNode(
1474  ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1475  DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1476  DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1477 
1478  MemOpChains.push_back(
1479  DAG.getStore(Chain, DL, Arg, PtrOff,
1480  MachinePointerInfo::getStack(MF, VA.getLocMemOffset())));
1481  }
1482 
1483  if (!MemOpChains.empty())
1484  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1485  }
1486 
1487  // Build a sequence of copy-to-reg nodes chained together with token chain and
1488  // flag operands which copy the outgoing args into registers. The InFlag in
1489  // necessary since all emited instructions must be stuck together.
1490  SDValue InFlag;
1491  for (auto Reg : RegsToPass) {
1492  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1493  InFlag = Chain.getValue(1);
1494  }
1495 
1496  // Returns a chain & a flag for retval copy to use.
1497  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1498  SmallVector<SDValue, 8> Ops;
1499  Ops.push_back(Chain);
1500  Ops.push_back(Callee);
1501 
1502  // Add argument registers to the end of the list so that they are known live
1503  // into the call.
1504  for (auto Reg : RegsToPass) {
1505  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1506  }
1507 
1508  // The R1 register must be passed as an implicit register so that R1 is
1509  // correctly zeroed in interrupts.
1510  Ops.push_back(DAG.getRegister(AVR::R1, MVT::i8));
1511 
1512  // Add a register mask operand representing the call-preserved registers.
1513  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1514  const uint32_t *Mask =
1515  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1516  assert(Mask && "Missing call preserved mask for calling convention");
1517  Ops.push_back(DAG.getRegisterMask(Mask));
1518 
1519  if (InFlag.getNode()) {
1520  Ops.push_back(InFlag);
1521  }
1522 
1523  Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1524  InFlag = Chain.getValue(1);
1525 
1526  // Create the CALLSEQ_END node.
1527  Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, InFlag, DL);
1528 
1529  if (!Ins.empty()) {
1530  InFlag = Chain.getValue(1);
1531  }
1532 
1533  // Handle result values, copying them out of physregs into vregs that we
1534  // return.
1535  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1536  InVals);
1537 }
1538 
1539 /// Lower the result values of a call into the
1540 /// appropriate copies out of appropriate physical registers.
1541 ///
1542 SDValue AVRTargetLowering::LowerCallResult(
1543  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1544  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1545  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1546 
1547  // Assign locations to each value returned by this call.
1548  SmallVector<CCValAssign, 16> RVLocs;
1549  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1550  *DAG.getContext());
1551 
1552  // Handle runtime calling convs.
1553  if (CallConv == CallingConv::AVR_BUILTIN) {
1554  CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
1555  } else {
1557  }
1558 
1559  // Copy all of the result registers out of their specified physreg.
1560  for (CCValAssign const &RVLoc : RVLocs) {
1561  Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1562  InFlag)
1563  .getValue(1);
1564  InFlag = Chain.getValue(2);
1565  InVals.push_back(Chain.getValue(0));
1566  }
1567 
1568  return Chain;
1569 }
1570 
1571 //===----------------------------------------------------------------------===//
1572 // Return Value Calling Convention Implementation
1573 //===----------------------------------------------------------------------===//
1574 
1575 bool AVRTargetLowering::CanLowerReturn(
1576  CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1577  const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1578  if (CallConv == CallingConv::AVR_BUILTIN) {
1579  SmallVector<CCValAssign, 16> RVLocs;
1580  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1581  return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
1582  }
1583 
1584  unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs);
1585  return TotalBytes <= (unsigned)(Subtarget.hasTinyEncoding() ? 4 : 8);
1586 }
1587 
1588 SDValue
1589 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1590  bool isVarArg,
1591  const SmallVectorImpl<ISD::OutputArg> &Outs,
1592  const SmallVectorImpl<SDValue> &OutVals,
1593  const SDLoc &dl, SelectionDAG &DAG) const {
1594  // CCValAssign - represent the assignment of the return value to locations.
1595  SmallVector<CCValAssign, 16> RVLocs;
1596 
1597  // CCState - Info about the registers and stack slot.
1598  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1599  *DAG.getContext());
1600 
1601  MachineFunction &MF = DAG.getMachineFunction();
1602 
1603  // Analyze return values.
1604  if (CallConv == CallingConv::AVR_BUILTIN) {
1605  CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
1606  } else {
1608  }
1609 
1610  SDValue Flag;
1611  SmallVector<SDValue, 4> RetOps(1, Chain);
1612  // Copy the result values into the output registers.
1613  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1614  CCValAssign &VA = RVLocs[i];
1615  assert(VA.isRegLoc() && "Can only return in registers!");
1616 
1617  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1618 
1619  // Guarantee that all emitted copies are stuck together with flags.
1620  Flag = Chain.getValue(1);
1621  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1622  }
1623 
1624  // Don't emit the ret/reti instruction when the naked attribute is present in
1625  // the function being compiled.
1626  if (MF.getFunction().getAttributes().hasFnAttr(Attribute::Naked)) {
1627  return Chain;
1628  }
1629 
1630  const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1631 
1632  if (!AFI->isInterruptOrSignalHandler()) {
1633  // The return instruction has an implicit R1 operand: it must contain zero
1634  // on return.
1635  // This is not needed in interrupts however, where R1 is handled specially
1636  // (only pushed/popped when needed).
1637  RetOps.push_back(DAG.getRegister(AVR::R1, MVT::i8));
1638  }
1639 
1640  unsigned RetOpc =
1641  AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_FLAG : AVRISD::RET_FLAG;
1642 
1643  RetOps[0] = Chain; // Update chain.
1644 
1645  if (Flag.getNode()) {
1646  RetOps.push_back(Flag);
1647  }
1648 
1649  return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1650 }
1651 
1652 //===----------------------------------------------------------------------===//
1653 // Custom Inserters
1654 //===----------------------------------------------------------------------===//
1655 
1656 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1657  MachineBasicBlock *BB) const {
1658  unsigned Opc;
1659  const TargetRegisterClass *RC;
1660  bool HasRepeatedOperand = false;
1661  MachineFunction *F = BB->getParent();
1662  MachineRegisterInfo &RI = F->getRegInfo();
1663  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1664  DebugLoc dl = MI.getDebugLoc();
1665 
1666  switch (MI.getOpcode()) {
1667  default:
1668  llvm_unreachable("Invalid shift opcode!");
1669  case AVR::Lsl8:
1670  Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1671  RC = &AVR::GPR8RegClass;
1672  HasRepeatedOperand = true;
1673  break;
1674  case AVR::Lsl16:
1675  Opc = AVR::LSLWRd;
1676  RC = &AVR::DREGSRegClass;
1677  break;
1678  case AVR::Asr8:
1679  Opc = AVR::ASRRd;
1680  RC = &AVR::GPR8RegClass;
1681  break;
1682  case AVR::Asr16:
1683  Opc = AVR::ASRWRd;
1684  RC = &AVR::DREGSRegClass;
1685  break;
1686  case AVR::Lsr8:
1687  Opc = AVR::LSRRd;
1688  RC = &AVR::GPR8RegClass;
1689  break;
1690  case AVR::Lsr16:
1691  Opc = AVR::LSRWRd;
1692  RC = &AVR::DREGSRegClass;
1693  break;
1694  case AVR::Rol8:
1695  Opc = AVR::ROLBRd;
1696  RC = &AVR::GPR8RegClass;
1697  break;
1698  case AVR::Rol16:
1699  Opc = AVR::ROLWRd;
1700  RC = &AVR::DREGSRegClass;
1701  break;
1702  case AVR::Ror8:
1703  Opc = AVR::RORBRd;
1704  RC = &AVR::GPR8RegClass;
1705  break;
1706  case AVR::Ror16:
1707  Opc = AVR::RORWRd;
1708  RC = &AVR::DREGSRegClass;
1709  break;
1710  }
1711 
1712  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1713 
1715  for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I)
1716  ;
1717  if (I != F->end())
1718  ++I;
1719 
1720  // Create loop block.
1721  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1722  MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB);
1723  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1724 
1725  F->insert(I, LoopBB);
1726  F->insert(I, CheckBB);
1727  F->insert(I, RemBB);
1728 
1729  // Update machine-CFG edges by transferring all successors of the current
1730  // block to the block containing instructions after shift.
1731  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1732  BB->end());
1733  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1734 
1735  // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB.
1736  BB->addSuccessor(CheckBB);
1737  LoopBB->addSuccessor(CheckBB);
1738  CheckBB->addSuccessor(LoopBB);
1739  CheckBB->addSuccessor(RemBB);
1740 
1741  Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass);
1742  Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass);
1743  Register ShiftReg = RI.createVirtualRegister(RC);
1744  Register ShiftReg2 = RI.createVirtualRegister(RC);
1745  Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1746  Register SrcReg = MI.getOperand(1).getReg();
1747  Register DstReg = MI.getOperand(0).getReg();
1748 
1749  // BB:
1750  // rjmp CheckBB
1751  BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB);
1752 
1753  // LoopBB:
1754  // ShiftReg2 = shift ShiftReg
1755  auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1756  if (HasRepeatedOperand)
1757  ShiftMI.addReg(ShiftReg);
1758 
1759  // CheckBB:
1760  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1761  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1762  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1763  // ShiftAmt2 = ShiftAmt - 1;
1764  // if (ShiftAmt2 >= 0) goto LoopBB;
1765  BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg)
1766  .addReg(SrcReg)
1767  .addMBB(BB)
1768  .addReg(ShiftReg2)
1769  .addMBB(LoopBB);
1770  BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1771  .addReg(ShiftAmtSrcReg)
1772  .addMBB(BB)
1773  .addReg(ShiftAmtReg2)
1774  .addMBB(LoopBB);
1775  BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg)
1776  .addReg(SrcReg)
1777  .addMBB(BB)
1778  .addReg(ShiftReg2)
1779  .addMBB(LoopBB);
1780 
1781  BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2).addReg(ShiftAmtReg);
1782  BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB);
1783 
1784  MI.eraseFromParent(); // The pseudo instruction is gone now.
1785  return RemBB;
1786 }
1787 
1789  if (I->getOpcode() == AVR::COPY) {
1790  Register SrcReg = I->getOperand(1).getReg();
1791  return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1792  }
1793 
1794  return false;
1795 }
1796 
1797 // The mul instructions wreak havock on our zero_reg R1. We need to clear it
1798 // after the result has been evacuated. This is probably not the best way to do
1799 // it, but it works for now.
1800 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1801  MachineBasicBlock *BB) const {
1802  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1804  ++I; // in any case insert *after* the mul instruction
1805  if (isCopyMulResult(I))
1806  ++I;
1807  if (isCopyMulResult(I))
1808  ++I;
1809  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1810  .addReg(AVR::R1)
1811  .addReg(AVR::R1);
1812  return BB;
1813 }
1814 
1815 // Insert a read from R1, which almost always contains the value 0.
1816 MachineBasicBlock *
1817 AVRTargetLowering::insertCopyR1(MachineInstr &MI, MachineBasicBlock *BB) const {
1818  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1820  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::COPY))
1821  .add(MI.getOperand(0))
1822  .addReg(AVR::R1);
1823  MI.eraseFromParent();
1824  return BB;
1825 }
1826 
1827 // Lower atomicrmw operation to disable interrupts, do operation, and restore
1828 // interrupts. This works because all AVR microcontrollers are single core.
1829 MachineBasicBlock *AVRTargetLowering::insertAtomicArithmeticOp(
1830  MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, int Width) const {
1831  MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
1832  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1834  const Register SCRATCH_REGISTER = AVR::R0;
1835  DebugLoc dl = MI.getDebugLoc();
1836 
1837  // Example instruction sequence, for an atomic 8-bit add:
1838  // ldi r25, 5
1839  // in r0, SREG
1840  // cli
1841  // ld r24, X
1842  // add r25, r24
1843  // st X, r25
1844  // out SREG, r0
1845 
1846  const TargetRegisterClass *RC =
1847  (Width == 8) ? &AVR::GPR8RegClass : &AVR::DREGSRegClass;
1848  unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
1849  unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
1850 
1851  // Disable interrupts.
1852  BuildMI(*BB, I, dl, TII.get(AVR::INRdA), SCRATCH_REGISTER)
1854  BuildMI(*BB, I, dl, TII.get(AVR::BCLRs)).addImm(7);
1855 
1856  // Load the original value.
1857  BuildMI(*BB, I, dl, TII.get(LoadOpcode), MI.getOperand(0).getReg())
1858  .add(MI.getOperand(1));
1859 
1860  // Do the arithmetic operation.
1861  Register Result = MRI.createVirtualRegister(RC);
1862  BuildMI(*BB, I, dl, TII.get(Opcode), Result)
1863  .addReg(MI.getOperand(0).getReg())
1864  .add(MI.getOperand(2));
1865 
1866  // Store the result.
1867  BuildMI(*BB, I, dl, TII.get(StoreOpcode))
1868  .add(MI.getOperand(1))
1869  .addReg(Result);
1870 
1871  // Restore interrupts.
1872  BuildMI(*BB, I, dl, TII.get(AVR::OUTARr))
1874  .addReg(SCRATCH_REGISTER);
1875 
1876  // Remove the pseudo instruction.
1877  MI.eraseFromParent();
1878  return BB;
1879 }
1880 
1881 MachineBasicBlock *
1883  MachineBasicBlock *MBB) const {
1884  int Opc = MI.getOpcode();
1885 
1886  // Pseudo shift instructions with a non constant shift amount are expanded
1887  // into a loop.
1888  switch (Opc) {
1889  case AVR::Lsl8:
1890  case AVR::Lsl16:
1891  case AVR::Lsr8:
1892  case AVR::Lsr16:
1893  case AVR::Rol8:
1894  case AVR::Rol16:
1895  case AVR::Ror8:
1896  case AVR::Ror16:
1897  case AVR::Asr8:
1898  case AVR::Asr16:
1899  return insertShift(MI, MBB);
1900  case AVR::MULRdRr:
1901  case AVR::MULSRdRr:
1902  return insertMul(MI, MBB);
1903  case AVR::CopyR1:
1904  return insertCopyR1(MI, MBB);
1905  case AVR::AtomicLoadAdd8:
1906  return insertAtomicArithmeticOp(MI, MBB, AVR::ADDRdRr, 8);
1907  case AVR::AtomicLoadAdd16:
1908  return insertAtomicArithmeticOp(MI, MBB, AVR::ADDWRdRr, 16);
1909  case AVR::AtomicLoadSub8:
1910  return insertAtomicArithmeticOp(MI, MBB, AVR::SUBRdRr, 8);
1911  case AVR::AtomicLoadSub16:
1912  return insertAtomicArithmeticOp(MI, MBB, AVR::SUBWRdRr, 16);
1913  case AVR::AtomicLoadAnd8:
1914  return insertAtomicArithmeticOp(MI, MBB, AVR::ANDRdRr, 8);
1915  case AVR::AtomicLoadAnd16:
1916  return insertAtomicArithmeticOp(MI, MBB, AVR::ANDWRdRr, 16);
1917  case AVR::AtomicLoadOr8:
1918  return insertAtomicArithmeticOp(MI, MBB, AVR::ORRdRr, 8);
1919  case AVR::AtomicLoadOr16:
1920  return insertAtomicArithmeticOp(MI, MBB, AVR::ORWRdRr, 16);
1921  case AVR::AtomicLoadXor8:
1922  return insertAtomicArithmeticOp(MI, MBB, AVR::EORRdRr, 8);
1923  case AVR::AtomicLoadXor16:
1924  return insertAtomicArithmeticOp(MI, MBB, AVR::EORWRdRr, 16);
1925  }
1926 
1927  assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
1928  "Unexpected instr type to insert");
1929 
1930  const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1931  ->getParent()
1932  ->getSubtarget()
1933  .getInstrInfo();
1934  DebugLoc dl = MI.getDebugLoc();
1935 
1936  // To "insert" a SELECT instruction, we insert the diamond
1937  // control-flow pattern. The incoming instruction knows the
1938  // destination vreg to set, the condition code register to branch
1939  // on, the true/false values to select between, and a branch opcode
1940  // to use.
1941 
1942  MachineFunction *MF = MBB->getParent();
1943  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1944  MachineBasicBlock *FallThrough = MBB->getFallThrough();
1945 
1946  // If the current basic block falls through to another basic block,
1947  // we must insert an unconditional branch to the fallthrough destination
1948  // if we are to insert basic blocks at the prior fallthrough point.
1949  if (FallThrough != nullptr) {
1950  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
1951  }
1952 
1953  MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1954  MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1955 
1957  for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I)
1958  ;
1959  if (I != MF->end())
1960  ++I;
1961  MF->insert(I, trueMBB);
1962  MF->insert(I, falseMBB);
1963 
1964  // Transfer remaining instructions and all successors of the current
1965  // block to the block which will contain the Phi node for the
1966  // select.
1967  trueMBB->splice(trueMBB->begin(), MBB,
1968  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1970 
1971  AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
1972  BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1973  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1974  MBB->addSuccessor(falseMBB);
1975  MBB->addSuccessor(trueMBB);
1976 
1977  // Unconditionally flow back to the true block
1978  BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1979  falseMBB->addSuccessor(trueMBB);
1980 
1981  // Set up the Phi node to determine where we came from
1982  BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI),
1983  MI.getOperand(0).getReg())
1984  .addReg(MI.getOperand(1).getReg())
1985  .addMBB(MBB)
1986  .addReg(MI.getOperand(2).getReg())
1987  .addMBB(falseMBB);
1988 
1989  MI.eraseFromParent(); // The pseudo instruction is gone now.
1990  return trueMBB;
1991 }
1992 
1993 //===----------------------------------------------------------------------===//
1994 // Inline Asm Support
1995 //===----------------------------------------------------------------------===//
1996 
1999  if (Constraint.size() == 1) {
2000  // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
2001  switch (Constraint[0]) {
2002  default:
2003  break;
2004  case 'a': // Simple upper registers
2005  case 'b': // Base pointer registers pairs
2006  case 'd': // Upper register
2007  case 'l': // Lower registers
2008  case 'e': // Pointer register pairs
2009  case 'q': // Stack pointer register
2010  case 'r': // Any register
2011  case 'w': // Special upper register pairs
2012  return C_RegisterClass;
2013  case 't': // Temporary register
2014  case 'x':
2015  case 'X': // Pointer register pair X
2016  case 'y':
2017  case 'Y': // Pointer register pair Y
2018  case 'z':
2019  case 'Z': // Pointer register pair Z
2020  return C_Register;
2021  case 'Q': // A memory address based on Y or Z pointer with displacement.
2022  return C_Memory;
2023  case 'G': // Floating point constant
2024  case 'I': // 6-bit positive integer constant
2025  case 'J': // 6-bit negative integer constant
2026  case 'K': // Integer constant (Range: 2)
2027  case 'L': // Integer constant (Range: 0)
2028  case 'M': // 8-bit integer constant
2029  case 'N': // Integer constant (Range: -1)
2030  case 'O': // Integer constant (Range: 8, 16, 24)
2031  case 'P': // Integer constant (Range: 1)
2032  case 'R': // Integer constant (Range: -6 to 5)x
2033  return C_Immediate;
2034  }
2035  }
2036 
2037  return TargetLowering::getConstraintType(Constraint);
2038 }
2039 
2040 unsigned
2042  // Not sure if this is actually the right thing to do, but we got to do
2043  // *something* [agnat]
2044  switch (ConstraintCode[0]) {
2045  case 'Q':
2046  return InlineAsm::Constraint_Q;
2047  }
2048  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
2049 }
2050 
2053  AsmOperandInfo &info, const char *constraint) const {
2054  ConstraintWeight weight = CW_Invalid;
2055  Value *CallOperandVal = info.CallOperandVal;
2056 
2057  // If we don't have a value, we can't do a match,
2058  // but allow it at the lowest weight.
2059  // (this behaviour has been copied from the ARM backend)
2060  if (!CallOperandVal) {
2061  return CW_Default;
2062  }
2063 
2064  // Look at the constraint type.
2065  switch (*constraint) {
2066  default:
2068  break;
2069  case 'd':
2070  case 'r':
2071  case 'l':
2072  weight = CW_Register;
2073  break;
2074  case 'a':
2075  case 'b':
2076  case 'e':
2077  case 'q':
2078  case 't':
2079  case 'w':
2080  case 'x':
2081  case 'X':
2082  case 'y':
2083  case 'Y':
2084  case 'z':
2085  case 'Z':
2086  weight = CW_SpecificReg;
2087  break;
2088  case 'G':
2089  if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
2090  if (C->isZero()) {
2091  weight = CW_Constant;
2092  }
2093  }
2094  break;
2095  case 'I':
2096  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2097  if (isUInt<6>(C->getZExtValue())) {
2098  weight = CW_Constant;
2099  }
2100  }
2101  break;
2102  case 'J':
2103  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2104  if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
2105  weight = CW_Constant;
2106  }
2107  }
2108  break;
2109  case 'K':
2110  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2111  if (C->getZExtValue() == 2) {
2112  weight = CW_Constant;
2113  }
2114  }
2115  break;
2116  case 'L':
2117  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2118  if (C->getZExtValue() == 0) {
2119  weight = CW_Constant;
2120  }
2121  }
2122  break;
2123  case 'M':
2124  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2125  if (isUInt<8>(C->getZExtValue())) {
2126  weight = CW_Constant;
2127  }
2128  }
2129  break;
2130  case 'N':
2131  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2132  if (C->getSExtValue() == -1) {
2133  weight = CW_Constant;
2134  }
2135  }
2136  break;
2137  case 'O':
2138  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2139  if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
2140  (C->getZExtValue() == 24)) {
2141  weight = CW_Constant;
2142  }
2143  }
2144  break;
2145  case 'P':
2146  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2147  if (C->getZExtValue() == 1) {
2148  weight = CW_Constant;
2149  }
2150  }
2151  break;
2152  case 'R':
2153  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2154  if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
2155  weight = CW_Constant;
2156  }
2157  }
2158  break;
2159  case 'Q':
2160  weight = CW_Memory;
2161  break;
2162  }
2163 
2164  return weight;
2165 }
2166 
2167 std::pair<unsigned, const TargetRegisterClass *>
2169  StringRef Constraint,
2170  MVT VT) const {
2171  if (Constraint.size() == 1) {
2172  switch (Constraint[0]) {
2173  case 'a': // Simple upper registers r16..r23.
2174  if (VT == MVT::i8)
2175  return std::make_pair(0U, &AVR::LD8loRegClass);
2176  else if (VT == MVT::i16)
2177  return std::make_pair(0U, &AVR::DREGSLD8loRegClass);
2178  break;
2179  case 'b': // Base pointer registers: y, z.
2180  if (VT == MVT::i8 || VT == MVT::i16)
2181  return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
2182  break;
2183  case 'd': // Upper registers r16..r31.
2184  if (VT == MVT::i8)
2185  return std::make_pair(0U, &AVR::LD8RegClass);
2186  else if (VT == MVT::i16)
2187  return std::make_pair(0U, &AVR::DLDREGSRegClass);
2188  break;
2189  case 'l': // Lower registers r0..r15.
2190  if (VT == MVT::i8)
2191  return std::make_pair(0U, &AVR::GPR8loRegClass);
2192  else if (VT == MVT::i16)
2193  return std::make_pair(0U, &AVR::DREGSloRegClass);
2194  break;
2195  case 'e': // Pointer register pairs: x, y, z.
2196  if (VT == MVT::i8 || VT == MVT::i16)
2197  return std::make_pair(0U, &AVR::PTRREGSRegClass);
2198  break;
2199  case 'q': // Stack pointer register: SPH:SPL.
2200  return std::make_pair(0U, &AVR::GPRSPRegClass);
2201  case 'r': // Any register: r0..r31.
2202  if (VT == MVT::i8)
2203  return std::make_pair(0U, &AVR::GPR8RegClass);
2204  else if (VT == MVT::i16)
2205  return std::make_pair(0U, &AVR::DREGSRegClass);
2206  break;
2207  case 't': // Temporary register: r0.
2208  if (VT == MVT::i8)
2209  return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
2210  break;
2211  case 'w': // Special upper register pairs: r24, r26, r28, r30.
2212  if (VT == MVT::i8 || VT == MVT::i16)
2213  return std::make_pair(0U, &AVR::IWREGSRegClass);
2214  break;
2215  case 'x': // Pointer register pair X: r27:r26.
2216  case 'X':
2217  if (VT == MVT::i8 || VT == MVT::i16)
2218  return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
2219  break;
2220  case 'y': // Pointer register pair Y: r29:r28.
2221  case 'Y':
2222  if (VT == MVT::i8 || VT == MVT::i16)
2223  return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
2224  break;
2225  case 'z': // Pointer register pair Z: r31:r30.
2226  case 'Z':
2227  if (VT == MVT::i8 || VT == MVT::i16)
2228  return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
2229  break;
2230  default:
2231  break;
2232  }
2233  }
2234 
2236  Subtarget.getRegisterInfo(), Constraint, VT);
2237 }
2238 
2240  std::string &Constraint,
2241  std::vector<SDValue> &Ops,
2242  SelectionDAG &DAG) const {
2243  SDValue Result;
2244  SDLoc DL(Op);
2245  EVT Ty = Op.getValueType();
2246 
2247  // Currently only support length 1 constraints.
2248  if (Constraint.length() != 1) {
2249  return;
2250  }
2251 
2252  char ConstraintLetter = Constraint[0];
2253  switch (ConstraintLetter) {
2254  default:
2255  break;
2256  // Deal with integers first:
2257  case 'I':
2258  case 'J':
2259  case 'K':
2260  case 'L':
2261  case 'M':
2262  case 'N':
2263  case 'O':
2264  case 'P':
2265  case 'R': {
2266  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2267  if (!C) {
2268  return;
2269  }
2270 
2271  int64_t CVal64 = C->getSExtValue();
2272  uint64_t CUVal64 = C->getZExtValue();
2273  switch (ConstraintLetter) {
2274  case 'I': // 0..63
2275  if (!isUInt<6>(CUVal64))
2276  return;
2277  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2278  break;
2279  case 'J': // -63..0
2280  if (CVal64 < -63 || CVal64 > 0)
2281  return;
2282  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2283  break;
2284  case 'K': // 2
2285  if (CUVal64 != 2)
2286  return;
2287  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2288  break;
2289  case 'L': // 0
2290  if (CUVal64 != 0)
2291  return;
2292  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2293  break;
2294  case 'M': // 0..255
2295  if (!isUInt<8>(CUVal64))
2296  return;
2297  // i8 type may be printed as a negative number,
2298  // e.g. 254 would be printed as -2,
2299  // so we force it to i16 at least.
2300  if (Ty.getSimpleVT() == MVT::i8) {
2301  Ty = MVT::i16;
2302  }
2303  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2304  break;
2305  case 'N': // -1
2306  if (CVal64 != -1)
2307  return;
2308  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2309  break;
2310  case 'O': // 8, 16, 24
2311  if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
2312  return;
2313  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2314  break;
2315  case 'P': // 1
2316  if (CUVal64 != 1)
2317  return;
2318  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2319  break;
2320  case 'R': // -6..5
2321  if (CVal64 < -6 || CVal64 > 5)
2322  return;
2323  Result = DAG.getTargetConstant(CVal64, DL, Ty);
2324  break;
2325  }
2326 
2327  break;
2328  }
2329  case 'G':
2330  const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op);
2331  if (!FC || !FC->isZero())
2332  return;
2333  // Soften float to i8 0
2334  Result = DAG.getTargetConstant(0, DL, MVT::i8);
2335  break;
2336  }
2337 
2338  if (Result.getNode()) {
2339  Ops.push_back(Result);
2340  return;
2341  }
2342 
2343  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2344 }
2345 
2347  const MachineFunction &MF) const {
2348  Register Reg;
2349 
2350  if (VT == LLT::scalar(8)) {
2352  .Case("r0", AVR::R0)
2353  .Case("r1", AVR::R1)
2354  .Default(0);
2355  } else {
2357  .Case("r0", AVR::R1R0)
2358  .Case("sp", AVR::SP)
2359  .Default(0);
2360  }
2361 
2362  if (Reg)
2363  return Reg;
2364 
2366  Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
2367 }
2368 
2369 } // end of namespace llvm
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:70
i
i
Definition: README.txt:29
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1437
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:156
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:36
llvm::AVRTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: AVRISelLowering.cpp:1083
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1582
llvm::TargetLoweringBase::setSchedulingPreference
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
Definition: TargetLowering.h:2292
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1448
llvm::MVT::getStoreSize
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: MachineValueType.h:1115
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1373
llvm::AVRISD::ROR
@ ROR
Bit rotate right.
Definition: AVRISelLowering.h:50
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:196
llvm::StructType::get
static StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:406
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1445
llvm::AArch64_AM::LSL
@ LSL
Definition: AArch64AddressingModes.h:35
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1449
llvm::AVRTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: AVRISelLowering.cpp:2041
llvm::TargetLowering::getSingleConstraintMatchWeight
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Definition: TargetLowering.cpp:5543
llvm::AVRTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: AVRISelLowering.cpp:268
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4550
llvm::AVRSubtarget::hasTinyEncoding
bool hasTinyEncoding() const
Definition: AVRSubtarget.h:81
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:991
PHI
Rewrite undef for PHI
Definition: AMDGPURewriteUndefForPHI.cpp:101
llvm::ISD::NON_EXTLOAD
@ NON_EXTLOAD
Definition: ISDOpcodes.h:1404
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1195
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
llvm::AVRTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: AVRISelLowering.cpp:237
llvm::ISD::PRE_DEC
@ PRE_DEC
Definition: ISDOpcodes.h:1373
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:700
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:976
llvm::CCState::addLoc
void addLoc(const CCValAssign &V)
Definition: CallingConvLower.h:251
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
llvm::AVRTargetMachine
A generic AVR implementation.
Definition: AVRTargetMachine.h:28
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1444
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1057
llvm::MachineFunction::end
iterator end()
Definition: MachineFunction.h:856
llvm::AVRISD::ROLLOOP
@ ROLLOOP
A loop of single left bit rotate instructions.
Definition: AVRISelLowering.h:54
llvm::AVR::ProgramMemory
@ ProgramMemory
Definition: AVR.h:43
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::isCopyMulResult
static bool isCopyMulResult(MachineBasicBlock::iterator const &I)
Definition: AVRISelLowering.cpp:1788
R600_InstFlag::FC
@ FC
Definition: R600Defines.h:32
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::TargetLoweringBase::getLibcallName
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
Definition: TargetLowering.h:3152
llvm::TargetLowering::CW_Constant
@ CW_Constant
Definition: TargetLowering.h:4572
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2344
llvm::AVRISD::SELECT_CC
@ SELECT_CC
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
Definition: AVRISelLowering.h:72
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:273
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::TargetLowering::C_Memory
@ C_Memory
Definition: TargetLowering.h:4553
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1439
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::TargetLoweringBase::setSupportsUnalignedAtomics
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
Definition: TargetLowering.h:2545
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:873
llvm::AVRISD::LSLHI
@ LSLHI
Higher 8-bit of word logical shift left.
Definition: AVRISelLowering.h:41
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:736
llvm::AArch64ISD::CALL
@ CALL
Definition: AArch64ISelLowering.h:53
llvm::AVRISD::ASRWN
@ ASRWN
Word arithmetic shift right N bits.
Definition: AVRISelLowering.h:48
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:44
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2502
llvm::TargetLowering::LowerCallTo
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
Definition: SelectionDAGBuilder.cpp:9808
llvm::AVRISD::CMPC
@ CMPC
Compare with carry instruction.
Definition: AVRISelLowering.h:65
llvm::AVRISD::LSLLOOP
@ LSLLOOP
A loop of single logical shift left instructions.
Definition: AVRISelLowering.h:52
llvm::AVRTargetLowering::getPreIndexedAddressParts
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
Definition: AVRISelLowering.cpp:980
llvm::AVRCC::COND_LT
@ COND_LT
Less than.
Definition: AVRInstrInfo.h:35
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:772
llvm::AVRTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
Definition: AVRISelLowering.cpp:921
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:3169
STLExtras.h
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1086
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1404
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::analyzeArguments
static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool Tiny)
Analyze incoming and outgoing function arguments.
Definition: AVRISelLowering.cpp:1121
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:458
llvm::AVRISD::RETI_FLAG
@ RETI_FLAG
Return from ISR.
Definition: AVRISelLowering.h:31
llvm::AVRISD::LSLWN
@ LSLWN
Word logical shift left N bits.
Definition: AVRISelLowering.h:40
llvm::AVRISD::LSL
@ LSL
Logical shift left.
Definition: AVRISelLowering.h:38
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition: TargetLowering.h:2422
llvm::AVRCC::COND_SH
@ COND_SH
Unsigned same or higher.
Definition: AVRInstrInfo.h:36
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:1001
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:836
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition: TargetLowering.h:2405
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1025
llvm::AVRISD::CALL
@ CALL
Represents an abstract call instruction, which includes a bunch of information.
Definition: AVRISelLowering.h:34
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:694
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::MVT::integer_valuetypes
static auto integer_valuetypes()
Definition: MachineValueType.h:1478
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:762
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1008
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::AVRCC::COND_PL
@ COND_PL
Plus.
Definition: AVRInstrInfo.h:39
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:37
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1141
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:702
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::AVRISD::ASR
@ ASR
Arithmetic shift right.
Definition: AVRISelLowering.h:46
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::AArch64ISD::RET_FLAG
@ RET_FLAG
Definition: AArch64ISelLowering.h:80
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1446
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:781
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::TargetLoweringBase::AddrMode::HasBaseReg
bool HasBaseReg
Definition: TargetLowering.h:2575
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AVRSubtarget
A specific AVR target MCU.
Definition: AVRSubtarget.h:31
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1514
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3486
llvm::AVRISD::SWAP
@ SWAP
Swap Rd[7:4] <-> Rd[3:0].
Definition: AVRISelLowering.h:69
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2339
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:240
llvm::Instruction
Definition: Instruction.h:42
llvm::AArch64_AM::LSR
@ LSR
Definition: AArch64AddressingModes.h:36
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::DataLayout::getABITypeAlign
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:829
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1194
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::AVRTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: AVRISelLowering.cpp:2239
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::AVRSubtarget::getInstrInfo
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:41
llvm::TargetLowering::C_Register
@ C_Register
Definition: TargetLowering.h:4551
llvm::CCState::getContext
LLVMContext & getContext() const
Definition: CallingConvLower.h:255
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:854
llvm::TargetLowering::C_Immediate
@ C_Immediate
Definition: TargetLowering.h:4555
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::TargetLoweringBase::setBooleanVectorContents
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Definition: TargetLowering.h:2287
llvm::AArch64_AM::ROR
@ ROR
Definition: AArch64AddressingModes.h:38
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:182
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AVRTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: AVRISelLowering.cpp:1882
llvm::AVRTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: AVRISelLowering.cpp:2052
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::AVRCC::COND_GE
@ COND_GE
Greater than or equal.
Definition: AVRInstrInfo.h:34
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1436
llvm::Sched::RegPressure
@ RegPressure
Definition: TargetLowering.h:100
llvm::AVRISD::TST
@ TST
Test for zero or minus instruction.
Definition: AVRISelLowering.h:67
llvm::ISD::POST_INC
@ POST_INC
Definition: ISDOpcodes.h:1373
llvm::analyzeReturnValues
static void analyzeReturnValues(const SmallVectorImpl< ArgT > &Args, CCState &CCInfo, bool Tiny)
Analyze incoming and outgoing value of returning from a function.
Definition: AVRISelLowering.cpp:1214
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:200
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2356
llvm::AVRCC::CondCodes
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:31
llvm::TargetLowering::CW_SpecificReg
@ CW_SpecificReg
Definition: TargetLowering.h:4569
NODE
#define NODE(name)
llvm::ISD::Register
@ Register
Definition: ISDOpcodes.h:74
llvm::AVRTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: AVRISelLowering.cpp:1998
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:35
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::AVRISD::ASRLOOP
@ ASRLOOP
A loop of single arithmetic shift right instructions.
Definition: AVRISelLowering.h:56
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1192
llvm::ConstantFPSDNode
Definition: SelectionDAGNodes.h:1631
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:197
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::getTotalArgumentsSizeInBytes
static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl< ArgT > &Args)
Count the total number of bytes needed to pass or return these arguments.
Definition: AVRISelLowering.cpp:1201
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2305
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1191
llvm::TargetLowering::CW_Register
@ CW_Register
Definition: TargetLowering.h:4570
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AVRCC::COND_NE
@ COND_NE
Not equal.
Definition: AVRInstrInfo.h:33
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:9047
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1170
llvm::AVRISD::LSRBN
@ LSRBN
Byte logical shift right N bits.
Definition: AVRISelLowering.h:43
llvm::TargetLowering::AsmOperandInfo
This contains information for each constraint that we are lowering.
Definition: TargetLowering.h:4577
size
i< reg-> size
Definition: README.txt:166
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:439
ArrayRef.h
llvm::CCValAssign::getMem
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:100
AVRTargetMachine.h
llvm::AVRTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: AVRISelLowering.cpp:887
llvm::RegList16AVR
static const MCPhysReg RegList16AVR[]
Definition: AVRISelLowering.cpp:1102
llvm::StoreSDNode
This class is used to represent ISD::STORE nodes.
Definition: SelectionDAGNodes.h:2372
llvm::AVRISD::ROL
@ ROL
Bit rotate left.
Definition: AVRISelLowering.h:51
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1404
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:179
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::AVRTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: AVRISelLowering.cpp:2168
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:4134
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:638
llvm::AVRISD::LSRWN
@ LSRWN
Word logical shift right N bits.
Definition: AVRISelLowering.h:44
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::AVRSubtarget::supportsMultiplication
bool supportsMultiplication() const
Definition: AVRSubtarget.h:79
llvm::AVRTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: AVRISelLowering.cpp:950
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1438
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
llvm::ISD::BasicBlock
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:71
AVRMCTargetDesc.h
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::AVRTargetLowering::getPostIndexedAddressParts
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
Definition: AVRISelLowering.cpp:1036
llvm::TargetLowering::CW_Memory
@ CW_Memory
Definition: TargetLowering.h:4571
llvm::AVRCC::COND_MI
@ COND_MI
Minus.
Definition: AVRInstrInfo.h:38
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:750
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1087
info
lazy value info
Definition: LazyValueInfo.cpp:59
llvm::TargetLowering::CW_Default
@ CW_Default
Definition: TargetLowering.h:4573
llvm::AVRTargetLowering::AVRTargetLowering
AVRTargetLowering(const AVRTargetMachine &TM, const AVRSubtarget &STI)
Definition: AVRISelLowering.cpp:36
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::AVRTargetLowering::Subtarget
const AVRSubtarget & Subtarget
Definition: AVRISelLowering.h:185
llvm::AVRISD::BRCOND
@ BRCOND
AVR conditional branches.
Definition: AVRISelLowering.h:61
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:269
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::AVRISD::LSR
@ LSR
Logical shift right.
Definition: AVRISelLowering.h:42
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::CCState::AllocateReg
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
Definition: CallingConvLower.h:349
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
AVRSubtarget.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::TargetLowering::LowerAsmOperandForConstraint
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Definition: TargetLowering.cpp:5171
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:1009
llvm::InlineAsm::getFlagWord
static unsigned getFlagWord(unsigned Kind, unsigned NumOps)
Definition: InlineAsm.h:293
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
llvm::TargetLoweringBase::AddrMode::BaseGV
GlobalValue * BaseGV
Definition: TargetLowering.h:2573
llvm::ms_demangle::IntrinsicFunctionKind::New
@ New
uint32_t
AVRMachineFunctionInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:5254
llvm::AVRISD::ASRBN
@ ASRBN
Byte arithmetic shift right N bits.
Definition: AVRISelLowering.h:47
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2395
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1184
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1404
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetLowering::C_RegisterClass
@ C_RegisterClass
Definition: TargetLowering.h:4552
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:314
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
j
return j(j<< 16)
llvm::AArch64_AM::ASR
@ ASR
Definition: AArch64AddressingModes.h:37
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1447
llvm::TargetLoweringBase::AddrMode::BaseOffs
int64_t BaseOffs
Definition: TargetLowering.h:2574
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2373
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1759
llvm::CallingConv::AVR_BUILTIN
@ AVR_BUILTIN
Used for special AVR rtlib functions which have an "optimized" convention to preserve registers.
Definition: CallingConv.h:184
uint16_t
llvm::TargetLoweringBase::AddrMode::Scale
int64_t Scale
Definition: TargetLowering.h:2576
CallingConvLower.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::RegList8Tiny
static const MCPhysReg RegList8Tiny[]
Definition: AVRISelLowering.cpp:1100
llvm::X86::FirstMacroFusionInstKind::Cmp
@ Cmp
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4560
Function.h
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Definition: CallingConvLower.h:423
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:200
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:270
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::AVRCC::COND_LO
@ COND_LO
Unsigned lower.
Definition: AVRInstrInfo.h:37
llvm::SDNode::getNumValues
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Definition: SelectionDAGNodes.h:983
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:232
StringSwitch.h
AVR.h
llvm::TargetLowering::CW_Invalid
@ CW_Invalid
Definition: TargetLowering.h:4562
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:3143
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1082
llvm::AVRCC::COND_EQ
@ COND_EQ
Equal.
Definition: AVRInstrInfo.h:32
llvm::intCCToAVRCC
static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC)
IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
Definition: AVRISelLowering.cpp:549
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:751
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2273
llvm::AVRSubtarget::getRegisterInfo
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:51
llvm::AVRISD::WRAPPER
@ WRAPPER
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Definition: AVRISelLowering.h:37
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1019
llvm::RegList16Tiny
static const MCPhysReg RegList16Tiny[]
Definition: AVRISelLowering.cpp:1107
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
MachineInstrBuilder.h
llvm::RegList8AVR
static const MCPhysReg RegList8AVR[]
Registers for calling conventions, ordered in reverse as required by ABI.
Definition: AVRISelLowering.cpp:1096
llvm::CCValAssign::getReg
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:77
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:198
llvm::AVRTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: AVRISelLowering.cpp:2346
llvm::ARCISD::CMP
@ CMP
Definition: ARCISelLowering.h:40
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1284
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:280
llvm::TargetLoweringBase::setMinimumJumpTableEntries
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
Definition: TargetLoweringBase.cpp:1998
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::TargetLowering::getInlineAsmMemConstraint
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Definition: TargetLowering.h:4652
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::AVRISD::RET_FLAG
@ RET_FLAG
Return from subroutine.
Definition: AVRISelLowering.h:29
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:701
llvm::AVRInstrInfo
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:64
llvm::AVRISD::LSRLO
@ LSRLO
Lower 8-bit of word logical shift right.
Definition: AVRISelLowering.h:45
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2572
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::AVRISD::LSRLOOP
@ LSRLOOP
A loop of single logical shift right instructions.
Definition: AVRISelLowering.h:53
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:637
llvm::AVRISD::ASRLO
@ ASRLO
Lower 8-bit of word arithmetic shift right.
Definition: AVRISelLowering.h:49
RegName
#define RegName(no)
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:901
llvm::msgpack::Type
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:48
llvm::AVRISD::CMP
@ CMP
Compare instruction.
Definition: AVRISelLowering.h:63
llvm::StringSwitch::Default
R Default(T Value)
Definition: StringSwitch.h:183
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:669
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:45
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:47
llvm::omp::RTLDependInfoFields::Flags
@ Flags
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1077
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::AVRSubtarget::getIORegSREG
int getIORegSREG() const
Definition: AVRSubtarget.h:99
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
llvm::InlineAsm::Constraint_Q
@ Constraint_Q
Definition: InlineAsm.h:263
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::TargetLoweringBase::getLibcallCallingConv
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:3174
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1053
AVRISelLowering.h
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1032
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:695
llvm::AVRISD::LSLBN
@ LSLBN
Byte logical shift left N bits.
Definition: AVRISelLowering.h:39
llvm::TargetLowering::getConstraintType
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Definition: TargetLowering.cpp:5109
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:356
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:703
llvm::codeview::PublicSymFlags::Function
@ Function
llvm::ISD::ATOMIC_LOAD_MAX
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1193
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::ISD::EXTRACT_ELEMENT
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
Definition: ISDOpcodes.h:222
llvm::AVR::isProgramMemoryAccess
bool isProgramMemoryAccess(MemSDNode const *N)
Definition: AVR.h:73
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
llvm::DataLayout::getTypeAllocSize
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:506
TargetLoweringObjectFileImpl.h
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::AVRISD::RORLOOP
@ RORLOOP
A loop of single right bit rotate instructions.
Definition: AVRISelLowering.h:55