LLVM 18.0.0git
AVRISelLowering.cpp
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1//===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AVR uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AVRISelLowering.h"
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/STLExtras.h"
25#include "llvm/IR/Function.h"
27
28#include "AVR.h"
30#include "AVRSubtarget.h"
31#include "AVRTargetMachine.h"
33
34namespace llvm {
35
37 const AVRSubtarget &STI)
38 : TargetLowering(TM), Subtarget(STI) {
39 // Set up the register classes.
40 addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
41 addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
42
43 // Compute derived properties from the register classes.
45
51
54
59
61
62 for (MVT VT : MVT::integer_valuetypes()) {
63 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
64 setLoadExtAction(N, VT, MVT::i1, Promote);
65 setLoadExtAction(N, VT, MVT::i8, Expand);
66 }
67 }
68
69 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
70
71 for (MVT VT : MVT::integer_valuetypes()) {
76 }
77
78 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
79 // revert into a sub since we don't have an add with immediate instruction.
82
83 // our shift instructions are only able to shift 1 bit at a time, so handle
84 // this in a custom way.
97
102
108
119
121
122 // Add support for postincrement and predecrement load/stores.
131
133
138
139 // Atomic operations which must be lowered to rtlib calls
140 for (MVT VT : MVT::integer_valuetypes()) {
148 }
149
150 // Division/remainder
159
160 // Make division and modulus custom
167
168 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
171
172 // Expand 16 bit multiplications.
175
176 // Expand multiplications to libcalls when there is
177 // no hardware MUL.
178 if (!Subtarget.supportsMultiplication()) {
181 }
182
183 for (MVT VT : MVT::integer_valuetypes()) {
186 }
187
188 for (MVT VT : MVT::integer_valuetypes()) {
192 }
193
194 for (MVT VT : MVT::integer_valuetypes()) {
196 // TODO: The generated code is pretty poor. Investigate using the
197 // same "shift and subtract with carry" trick that we do for
198 // extending 8-bit to 16-bit. This may require infrastructure
199 // improvements in how we treat 16-bit "registers" to be feasible.
200 }
201
202 // Division rtlib functions (not supported), use divmod functions instead
203 setLibcallName(RTLIB::SDIV_I8, nullptr);
204 setLibcallName(RTLIB::SDIV_I16, nullptr);
205 setLibcallName(RTLIB::SDIV_I32, nullptr);
206 setLibcallName(RTLIB::UDIV_I8, nullptr);
207 setLibcallName(RTLIB::UDIV_I16, nullptr);
208 setLibcallName(RTLIB::UDIV_I32, nullptr);
209
210 // Modulus rtlib functions (not supported), use divmod functions instead
211 setLibcallName(RTLIB::SREM_I8, nullptr);
212 setLibcallName(RTLIB::SREM_I16, nullptr);
213 setLibcallName(RTLIB::SREM_I32, nullptr);
214 setLibcallName(RTLIB::UREM_I8, nullptr);
215 setLibcallName(RTLIB::UREM_I16, nullptr);
216 setLibcallName(RTLIB::UREM_I32, nullptr);
217
218 // Division and modulus rtlib functions
219 setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
220 setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
221 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
222 setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
223 setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
224 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
225
226 // Several of the runtime library functions use a special calling conv
231
232 // Trigonometric rtlib functions
233 setLibcallName(RTLIB::SIN_F32, "sin");
234 setLibcallName(RTLIB::COS_F32, "cos");
235
238}
239
240const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
241#define NODE(name) \
242 case AVRISD::name: \
243 return #name
244
245 switch (Opcode) {
246 default:
247 return nullptr;
248 NODE(RET_GLUE);
249 NODE(RETI_GLUE);
250 NODE(CALL);
251 NODE(WRAPPER);
252 NODE(LSL);
253 NODE(LSLW);
254 NODE(LSR);
255 NODE(LSRW);
256 NODE(ROL);
257 NODE(ROR);
258 NODE(ASR);
259 NODE(ASRW);
260 NODE(LSLLOOP);
261 NODE(LSRLOOP);
262 NODE(ROLLOOP);
263 NODE(RORLOOP);
264 NODE(ASRLOOP);
265 NODE(BRCOND);
266 NODE(CMP);
267 NODE(CMPC);
268 NODE(TST);
269 NODE(SELECT_CC);
270#undef NODE
271 }
272}
273
275 EVT VT) const {
276 assert(!VT.isVector() && "No AVR SetCC type for vectors!");
277 return MVT::i8;
278}
279
280SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
281 unsigned Opc8;
282 const SDNode *N = Op.getNode();
283 EVT VT = Op.getValueType();
284 SDLoc dl(N);
285 assert(llvm::has_single_bit<uint32_t>(VT.getSizeInBits()) &&
286 "Expected power-of-2 shift amount");
287
288 if (VT.getSizeInBits() == 32) {
289 if (!isa<ConstantSDNode>(N->getOperand(1))) {
290 // 32-bit shifts are converted to a loop in IR.
291 // This should be unreachable.
292 report_fatal_error("Expected a constant shift amount!");
293 }
294 SDVTList ResTys = DAG.getVTList(MVT::i16, MVT::i16);
295 SDValue SrcLo =
296 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i16, Op.getOperand(0),
297 DAG.getConstant(0, dl, MVT::i16));
298 SDValue SrcHi =
299 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i16, Op.getOperand(0),
300 DAG.getConstant(1, dl, MVT::i16));
301 uint64_t ShiftAmount =
302 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
303 if (ShiftAmount == 16) {
304 // Special case these two operations because they appear to be used by the
305 // generic codegen parts to lower 32-bit numbers.
306 // TODO: perhaps we can lower shift amounts bigger than 16 to a 16-bit
307 // shift of a part of the 32-bit value?
308 switch (Op.getOpcode()) {
309 case ISD::SHL: {
310 SDValue Zero = DAG.getConstant(0, dl, MVT::i16);
311 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i32, Zero, SrcLo);
312 }
313 case ISD::SRL: {
314 SDValue Zero = DAG.getConstant(0, dl, MVT::i16);
315 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i32, SrcHi, Zero);
316 }
317 }
318 }
319 SDValue Cnt = DAG.getTargetConstant(ShiftAmount, dl, MVT::i8);
320 unsigned Opc;
321 switch (Op.getOpcode()) {
322 default:
323 llvm_unreachable("Invalid 32-bit shift opcode!");
324 case ISD::SHL:
325 Opc = AVRISD::LSLW;
326 break;
327 case ISD::SRL:
328 Opc = AVRISD::LSRW;
329 break;
330 case ISD::SRA:
331 Opc = AVRISD::ASRW;
332 break;
333 }
334 SDValue Result = DAG.getNode(Opc, dl, ResTys, SrcLo, SrcHi, Cnt);
335 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i32, Result.getValue(0),
336 Result.getValue(1));
337 }
338
339 // Expand non-constant shifts to loops.
340 if (!isa<ConstantSDNode>(N->getOperand(1))) {
341 switch (Op.getOpcode()) {
342 default:
343 llvm_unreachable("Invalid shift opcode!");
344 case ISD::SHL:
345 return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
346 N->getOperand(1));
347 case ISD::SRL:
348 return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
349 N->getOperand(1));
350 case ISD::ROTL: {
351 SDValue Amt = N->getOperand(1);
352 EVT AmtVT = Amt.getValueType();
353 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
354 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
355 return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
356 }
357 case ISD::ROTR: {
358 SDValue Amt = N->getOperand(1);
359 EVT AmtVT = Amt.getValueType();
360 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
361 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
362 return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
363 }
364 case ISD::SRA:
365 return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
366 N->getOperand(1));
367 }
368 }
369
370 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
371 SDValue Victim = N->getOperand(0);
372
373 switch (Op.getOpcode()) {
374 case ISD::SRA:
375 Opc8 = AVRISD::ASR;
376 break;
377 case ISD::ROTL:
378 Opc8 = AVRISD::ROL;
379 ShiftAmount = ShiftAmount % VT.getSizeInBits();
380 break;
381 case ISD::ROTR:
382 Opc8 = AVRISD::ROR;
383 ShiftAmount = ShiftAmount % VT.getSizeInBits();
384 break;
385 case ISD::SRL:
386 Opc8 = AVRISD::LSR;
387 break;
388 case ISD::SHL:
389 Opc8 = AVRISD::LSL;
390 break;
391 default:
392 llvm_unreachable("Invalid shift opcode");
393 }
394
395 // Optimize int8/int16 shifts.
396 if (VT.getSizeInBits() == 8) {
397 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
398 // Optimize LSL when 4 <= ShiftAmount <= 6.
399 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
400 Victim =
401 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT));
402 ShiftAmount -= 4;
403 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
404 ShiftAmount < 7) {
405 // Optimize LSR when 4 <= ShiftAmount <= 6.
406 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
407 Victim =
408 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT));
409 ShiftAmount -= 4;
410 } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
411 // Optimize LSL when ShiftAmount == 7.
412 Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim,
413 DAG.getConstant(7, dl, VT));
414 ShiftAmount = 0;
415 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
416 // Optimize LSR when ShiftAmount == 7.
417 Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim,
418 DAG.getConstant(7, dl, VT));
419 ShiftAmount = 0;
420 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) {
421 // Optimize ASR when ShiftAmount == 6.
422 Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
423 DAG.getConstant(6, dl, VT));
424 ShiftAmount = 0;
425 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
426 // Optimize ASR when ShiftAmount == 7.
427 Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
428 DAG.getConstant(7, dl, VT));
429 ShiftAmount = 0;
430 } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 3) {
431 // Optimize left rotation 3 bits to swap then right rotation 1 bit.
432 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
433 Victim =
434 DAG.getNode(AVRISD::ROR, dl, VT, Victim, DAG.getConstant(1, dl, VT));
435 ShiftAmount = 0;
436 } else if (Op.getOpcode() == ISD::ROTR && ShiftAmount == 3) {
437 // Optimize right rotation 3 bits to swap then left rotation 1 bit.
438 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
439 Victim =
440 DAG.getNode(AVRISD::ROL, dl, VT, Victim, DAG.getConstant(1, dl, VT));
441 ShiftAmount = 0;
442 } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 7) {
443 // Optimize left rotation 7 bits to right rotation 1 bit.
444 Victim =
445 DAG.getNode(AVRISD::ROR, dl, VT, Victim, DAG.getConstant(1, dl, VT));
446 ShiftAmount = 0;
447 } else if (Op.getOpcode() == ISD::ROTR && ShiftAmount == 7) {
448 // Optimize right rotation 7 bits to left rotation 1 bit.
449 Victim =
450 DAG.getNode(AVRISD::ROL, dl, VT, Victim, DAG.getConstant(1, dl, VT));
451 ShiftAmount = 0;
452 } else if ((Op.getOpcode() == ISD::ROTR || Op.getOpcode() == ISD::ROTL) &&
453 ShiftAmount >= 4) {
454 // Optimize left/right rotation with the SWAP instruction.
455 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
456 ShiftAmount -= 4;
457 }
458 } else if (VT.getSizeInBits() == 16) {
459 if (Op.getOpcode() == ISD::SRA)
460 // Special optimization for int16 arithmetic right shift.
461 switch (ShiftAmount) {
462 case 15:
463 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
464 DAG.getConstant(15, dl, VT));
465 ShiftAmount = 0;
466 break;
467 case 14:
468 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
469 DAG.getConstant(14, dl, VT));
470 ShiftAmount = 0;
471 break;
472 case 7:
473 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
474 DAG.getConstant(7, dl, VT));
475 ShiftAmount = 0;
476 break;
477 default:
478 break;
479 }
480 if (4 <= ShiftAmount && ShiftAmount < 8)
481 switch (Op.getOpcode()) {
482 case ISD::SHL:
483 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
484 DAG.getConstant(4, dl, VT));
485 ShiftAmount -= 4;
486 break;
487 case ISD::SRL:
488 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
489 DAG.getConstant(4, dl, VT));
490 ShiftAmount -= 4;
491 break;
492 default:
493 break;
494 }
495 else if (8 <= ShiftAmount && ShiftAmount < 12)
496 switch (Op.getOpcode()) {
497 case ISD::SHL:
498 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
499 DAG.getConstant(8, dl, VT));
500 ShiftAmount -= 8;
501 // Only operate on the higher byte for remaining shift bits.
502 Opc8 = AVRISD::LSLHI;
503 break;
504 case ISD::SRL:
505 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
506 DAG.getConstant(8, dl, VT));
507 ShiftAmount -= 8;
508 // Only operate on the lower byte for remaining shift bits.
509 Opc8 = AVRISD::LSRLO;
510 break;
511 case ISD::SRA:
512 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
513 DAG.getConstant(8, dl, VT));
514 ShiftAmount -= 8;
515 // Only operate on the lower byte for remaining shift bits.
516 Opc8 = AVRISD::ASRLO;
517 break;
518 default:
519 break;
520 }
521 else if (12 <= ShiftAmount)
522 switch (Op.getOpcode()) {
523 case ISD::SHL:
524 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
525 DAG.getConstant(12, dl, VT));
526 ShiftAmount -= 12;
527 // Only operate on the higher byte for remaining shift bits.
528 Opc8 = AVRISD::LSLHI;
529 break;
530 case ISD::SRL:
531 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
532 DAG.getConstant(12, dl, VT));
533 ShiftAmount -= 12;
534 // Only operate on the lower byte for remaining shift bits.
535 Opc8 = AVRISD::LSRLO;
536 break;
537 case ISD::SRA:
538 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
539 DAG.getConstant(8, dl, VT));
540 ShiftAmount -= 8;
541 // Only operate on the lower byte for remaining shift bits.
542 Opc8 = AVRISD::ASRLO;
543 break;
544 default:
545 break;
546 }
547 }
548
549 while (ShiftAmount--) {
550 Victim = DAG.getNode(Opc8, dl, VT, Victim);
551 }
552
553 return Victim;
554}
555
556SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
557 unsigned Opcode = Op->getOpcode();
558 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
559 "Invalid opcode for Div/Rem lowering");
560 bool IsSigned = (Opcode == ISD::SDIVREM);
561 EVT VT = Op->getValueType(0);
562 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
563
565 switch (VT.getSimpleVT().SimpleTy) {
566 default:
567 llvm_unreachable("Unexpected request for libcall!");
568 case MVT::i8:
569 LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
570 break;
571 case MVT::i16:
572 LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
573 break;
574 case MVT::i32:
575 LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
576 break;
577 }
578
579 SDValue InChain = DAG.getEntryNode();
580
582 TargetLowering::ArgListEntry Entry;
583 for (SDValue const &Value : Op->op_values()) {
584 Entry.Node = Value;
585 Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
586 Entry.IsSExt = IsSigned;
587 Entry.IsZExt = !IsSigned;
588 Args.push_back(Entry);
589 }
590
591 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
592 getPointerTy(DAG.getDataLayout()));
593
594 Type *RetTy = (Type *)StructType::get(Ty, Ty);
595
596 SDLoc dl(Op);
597 TargetLowering::CallLoweringInfo CLI(DAG);
598 CLI.setDebugLoc(dl)
599 .setChain(InChain)
600 .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
601 .setInRegister()
602 .setSExtResult(IsSigned)
603 .setZExtResult(!IsSigned);
604
605 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
606 return CallInfo.first;
607}
608
609SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
610 SelectionDAG &DAG) const {
611 auto DL = DAG.getDataLayout();
612
613 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
614 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
615
616 // Create the TargetGlobalAddress node, folding in the constant offset.
617 SDValue Result =
618 DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
619 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
620}
621
622SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
623 SelectionDAG &DAG) const {
624 auto DL = DAG.getDataLayout();
625 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
626
627 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
628
629 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
630}
631
632/// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
634 switch (CC) {
635 default:
636 llvm_unreachable("Unknown condition code!");
637 case ISD::SETEQ:
638 return AVRCC::COND_EQ;
639 case ISD::SETNE:
640 return AVRCC::COND_NE;
641 case ISD::SETGE:
642 return AVRCC::COND_GE;
643 case ISD::SETLT:
644 return AVRCC::COND_LT;
645 case ISD::SETUGE:
646 return AVRCC::COND_SH;
647 case ISD::SETULT:
648 return AVRCC::COND_LO;
649 }
650}
651
652/// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
653SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
654 SelectionDAG &DAG, SDLoc DL) const {
655 assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
656 "LHS and RHS have different types");
657 assert(((LHS.getSimpleValueType() == MVT::i16) ||
658 (LHS.getSimpleValueType() == MVT::i8)) &&
659 "invalid comparison type");
660
661 SDValue Cmp;
662
663 if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) {
664 uint64_t Imm = cast<ConstantSDNode>(RHS)->getZExtValue();
665 // Generate a CPI/CPC pair if RHS is a 16-bit constant. Use the zero
666 // register for the constant RHS if its lower or higher byte is zero.
667 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
668 DAG.getIntPtrConstant(0, DL));
669 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
670 DAG.getIntPtrConstant(1, DL));
671 SDValue RHSlo = (Imm & 0xff) == 0
672 ? DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8)
673 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
674 DAG.getIntPtrConstant(0, DL));
675 SDValue RHShi = (Imm & 0xff00) == 0
676 ? DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8)
677 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
678 DAG.getIntPtrConstant(1, DL));
679 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
680 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
681 } else if (RHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(LHS)) {
682 // Generate a CPI/CPC pair if LHS is a 16-bit constant. Use the zero
683 // register for the constant LHS if its lower or higher byte is zero.
684 uint64_t Imm = cast<ConstantSDNode>(LHS)->getZExtValue();
685 SDValue LHSlo = (Imm & 0xff) == 0
686 ? DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8)
687 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
688 DAG.getIntPtrConstant(0, DL));
689 SDValue LHShi = (Imm & 0xff00) == 0
690 ? DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8)
691 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
692 DAG.getIntPtrConstant(1, DL));
693 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
694 DAG.getIntPtrConstant(0, DL));
695 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
696 DAG.getIntPtrConstant(1, DL));
697 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
698 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
699 } else {
700 // Generate ordinary 16-bit comparison.
701 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
702 }
703
704 return Cmp;
705}
706
707/// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
708/// the given operands.
709SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
710 SDValue &AVRcc, SelectionDAG &DAG,
711 SDLoc DL) const {
712 SDValue Cmp;
713 EVT VT = LHS.getValueType();
714 bool UseTest = false;
715
716 switch (CC) {
717 default:
718 break;
719 case ISD::SETLE: {
720 // Swap operands and reverse the branching condition.
721 std::swap(LHS, RHS);
722 CC = ISD::SETGE;
723 break;
724 }
725 case ISD::SETGT: {
726 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
727 switch (C->getSExtValue()) {
728 case -1: {
729 // When doing lhs > -1 use a tst instruction on the top part of lhs
730 // and use brpl instead of using a chain of cp/cpc.
731 UseTest = true;
732 AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
733 break;
734 }
735 case 0: {
736 // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
737 // __zero_reg__ in lhs.
738 RHS = LHS;
739 LHS = DAG.getConstant(0, DL, VT);
740 CC = ISD::SETLT;
741 break;
742 }
743 default: {
744 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
745 // us to fold the constant into the cmp instruction.
746 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
747 CC = ISD::SETGE;
748 break;
749 }
750 }
751 break;
752 }
753 // Swap operands and reverse the branching condition.
754 std::swap(LHS, RHS);
755 CC = ISD::SETLT;
756 break;
757 }
758 case ISD::SETLT: {
759 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
760 switch (C->getSExtValue()) {
761 case 1: {
762 // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
763 // __zero_reg__ in lhs.
764 RHS = LHS;
765 LHS = DAG.getConstant(0, DL, VT);
766 CC = ISD::SETGE;
767 break;
768 }
769 case 0: {
770 // When doing lhs < 0 use a tst instruction on the top part of lhs
771 // and use brmi instead of using a chain of cp/cpc.
772 UseTest = true;
773 AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
774 break;
775 }
776 }
777 }
778 break;
779 }
780 case ISD::SETULE: {
781 // Swap operands and reverse the branching condition.
782 std::swap(LHS, RHS);
783 CC = ISD::SETUGE;
784 break;
785 }
786 case ISD::SETUGT: {
787 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
788 // fold the constant into the cmp instruction.
789 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
790 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
791 CC = ISD::SETUGE;
792 break;
793 }
794 // Swap operands and reverse the branching condition.
795 std::swap(LHS, RHS);
796 CC = ISD::SETULT;
797 break;
798 }
799 }
800
801 // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
802 // using the default and/or/xor expansion code which is much longer.
803 if (VT == MVT::i32) {
804 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
805 DAG.getIntPtrConstant(0, DL));
806 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
807 DAG.getIntPtrConstant(1, DL));
808 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
809 DAG.getIntPtrConstant(0, DL));
810 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
811 DAG.getIntPtrConstant(1, DL));
812
813 if (UseTest) {
814 // When using tst we only care about the highest part.
815 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
816 DAG.getIntPtrConstant(1, DL));
817 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
818 } else {
819 Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL);
820 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
821 }
822 } else if (VT == MVT::i64) {
823 SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
824 DAG.getIntPtrConstant(0, DL));
825 SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
826 DAG.getIntPtrConstant(1, DL));
827
828 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
829 DAG.getIntPtrConstant(0, DL));
830 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
831 DAG.getIntPtrConstant(1, DL));
832 SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
833 DAG.getIntPtrConstant(0, DL));
834 SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
835 DAG.getIntPtrConstant(1, DL));
836
837 SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
838 DAG.getIntPtrConstant(0, DL));
839 SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
840 DAG.getIntPtrConstant(1, DL));
841
842 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
843 DAG.getIntPtrConstant(0, DL));
844 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
845 DAG.getIntPtrConstant(1, DL));
846 SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
847 DAG.getIntPtrConstant(0, DL));
848 SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
849 DAG.getIntPtrConstant(1, DL));
850
851 if (UseTest) {
852 // When using tst we only care about the highest part.
853 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
854 DAG.getIntPtrConstant(1, DL));
855 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
856 } else {
857 Cmp = getAVRCmp(LHS0, RHS0, DAG, DL);
858 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
859 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
860 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
861 }
862 } else if (VT == MVT::i8 || VT == MVT::i16) {
863 if (UseTest) {
864 // When using tst we only care about the highest part.
865 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
866 (VT == MVT::i8)
867 ? LHS
868 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
869 LHS, DAG.getIntPtrConstant(1, DL)));
870 } else {
871 Cmp = getAVRCmp(LHS, RHS, DAG, DL);
872 }
873 } else {
874 llvm_unreachable("Invalid comparison size");
875 }
876
877 // When using a test instruction AVRcc is already set.
878 if (!UseTest) {
879 AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
880 }
881
882 return Cmp;
883}
884
885SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
886 SDValue Chain = Op.getOperand(0);
887 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
888 SDValue LHS = Op.getOperand(2);
889 SDValue RHS = Op.getOperand(3);
890 SDValue Dest = Op.getOperand(4);
891 SDLoc dl(Op);
892
893 SDValue TargetCC;
894 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
895
896 return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
897 Cmp);
898}
899
900SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
901 SDValue LHS = Op.getOperand(0);
902 SDValue RHS = Op.getOperand(1);
903 SDValue TrueV = Op.getOperand(2);
904 SDValue FalseV = Op.getOperand(3);
905 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
906 SDLoc dl(Op);
907
908 SDValue TargetCC;
909 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
910
911 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
912 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
913
914 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
915}
916
917SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
918 SDValue LHS = Op.getOperand(0);
919 SDValue RHS = Op.getOperand(1);
920 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
921 SDLoc DL(Op);
922
923 SDValue TargetCC;
924 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
925
926 SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
927 SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
928 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
929 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
930
931 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
932}
933
934SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
935 const MachineFunction &MF = DAG.getMachineFunction();
936 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
937 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
938 auto DL = DAG.getDataLayout();
939 SDLoc dl(Op);
940
941 // Vastart just stores the address of the VarArgsFrameIndex slot into the
942 // memory location argument.
943 SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
944
945 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
946 MachinePointerInfo(SV));
947}
948
949// Modify the existing ISD::INLINEASM node to add the implicit zero register.
950SDValue AVRTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
951 SDValue ZeroReg = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8);
952 if (Op.getOperand(Op.getNumOperands() - 1) == ZeroReg ||
953 Op.getOperand(Op.getNumOperands() - 2) == ZeroReg) {
954 // Zero register has already been added. Don't add it again.
955 // If this isn't handled, we get called over and over again.
956 return Op;
957 }
958
959 // Get a list of operands to the new INLINEASM node. This is mostly a copy,
960 // with some edits.
961 // Add the following operands at the end (but before the glue node, if it's
962 // there):
963 // - The flags of the implicit zero register operand.
964 // - The implicit zero register operand itself.
965 SDLoc dl(Op);
966 SmallVector<SDValue, 8> Ops;
967 SDNode *N = Op.getNode();
968 SDValue Glue;
969 for (unsigned I = 0; I < N->getNumOperands(); I++) {
970 SDValue Operand = N->getOperand(I);
971 if (Operand.getValueType() == MVT::Glue) {
972 // The glue operand always needs to be at the end, so we need to treat it
973 // specially.
974 Glue = Operand;
975 } else {
976 Ops.push_back(Operand);
977 }
978 }
979 InlineAsm::Flag Flags(InlineAsm::Kind::RegUse, 1);
980 Ops.push_back(DAG.getTargetConstant(Flags, dl, MVT::i32));
981 Ops.push_back(ZeroReg);
982 if (Glue) {
983 Ops.push_back(Glue);
984 }
985
986 // Replace the current INLINEASM node with a new one that has the zero
987 // register as implicit parameter.
988 SDValue New = DAG.getNode(N->getOpcode(), dl, N->getVTList(), Ops);
989 DAG.ReplaceAllUsesOfValueWith(Op, New);
990 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), New.getValue(1));
991
992 return New;
993}
994
996 switch (Op.getOpcode()) {
997 default:
998 llvm_unreachable("Don't know how to custom lower this!");
999 case ISD::SHL:
1000 case ISD::SRA:
1001 case ISD::SRL:
1002 case ISD::ROTL:
1003 case ISD::ROTR:
1004 return LowerShifts(Op, DAG);
1005 case ISD::GlobalAddress:
1006 return LowerGlobalAddress(Op, DAG);
1007 case ISD::BlockAddress:
1008 return LowerBlockAddress(Op, DAG);
1009 case ISD::BR_CC:
1010 return LowerBR_CC(Op, DAG);
1011 case ISD::SELECT_CC:
1012 return LowerSELECT_CC(Op, DAG);
1013 case ISD::SETCC:
1014 return LowerSETCC(Op, DAG);
1015 case ISD::VASTART:
1016 return LowerVASTART(Op, DAG);
1017 case ISD::SDIVREM:
1018 case ISD::UDIVREM:
1019 return LowerDivRem(Op, DAG);
1020 case ISD::INLINEASM:
1021 return LowerINLINEASM(Op, DAG);
1022 }
1023
1024 return SDValue();
1025}
1026
1027/// Replace a node with an illegal result type
1028/// with a new node built out of custom code.
1031 SelectionDAG &DAG) const {
1032 SDLoc DL(N);
1033
1034 switch (N->getOpcode()) {
1035 case ISD::ADD: {
1036 // Convert add (x, imm) into sub (x, -imm).
1037 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1038 SDValue Sub = DAG.getNode(
1039 ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
1040 DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
1041 Results.push_back(Sub);
1042 }
1043 break;
1044 }
1045 default: {
1046 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1047
1048 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1049 Results.push_back(Res.getValue(I));
1050
1051 break;
1052 }
1053 }
1054}
1055
1056/// Return true if the addressing mode represented
1057/// by AM is legal for this target, for a load/store of the specified type.
1059 const AddrMode &AM, Type *Ty,
1060 unsigned AS,
1061 Instruction *I) const {
1062 int64_t Offs = AM.BaseOffs;
1063
1064 // Allow absolute addresses.
1065 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
1066 return true;
1067 }
1068
1069 // Flash memory instructions only allow zero offsets.
1070 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
1071 return false;
1072 }
1073
1074 // Allow reg+<6bit> offset.
1075 if (Offs < 0)
1076 Offs = -Offs;
1077 if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 &&
1078 isUInt<6>(Offs)) {
1079 return true;
1080 }
1081
1082 return false;
1083}
1084
1085/// Returns true by value, base pointer and
1086/// offset pointer and addressing mode by reference if the node's address
1087/// can be legally represented as pre-indexed load / store address.
1089 SDValue &Offset,
1091 SelectionDAG &DAG) const {
1092 EVT VT;
1093 const SDNode *Op;
1094 SDLoc DL(N);
1095
1096 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1097 VT = LD->getMemoryVT();
1098 Op = LD->getBasePtr().getNode();
1099 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1100 return false;
1102 return false;
1103 }
1104 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1105 VT = ST->getMemoryVT();
1106 Op = ST->getBasePtr().getNode();
1108 return false;
1109 }
1110 } else {
1111 return false;
1112 }
1113
1114 if (VT != MVT::i8 && VT != MVT::i16) {
1115 return false;
1116 }
1117
1118 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1119 return false;
1120 }
1121
1122 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1123 int RHSC = RHS->getSExtValue();
1124 if (Op->getOpcode() == ISD::SUB)
1125 RHSC = -RHSC;
1126
1127 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
1128 return false;
1129 }
1130
1131 Base = Op->getOperand(0);
1132 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
1133 AM = ISD::PRE_DEC;
1134
1135 return true;
1136 }
1137
1138 return false;
1139}
1140
1141/// Returns true by value, base pointer and
1142/// offset pointer and addressing mode by reference if this node can be
1143/// combined with a load / store to form a post-indexed load / store.
1145 SDValue &Base,
1146 SDValue &Offset,
1148 SelectionDAG &DAG) const {
1149 EVT VT;
1150 SDLoc DL(N);
1151
1152 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1153 VT = LD->getMemoryVT();
1154 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1155 return false;
1156 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1157 VT = ST->getMemoryVT();
1158 // We can not store to program memory.
1160 return false;
1161 // Since the high byte need to be stored first, we can not emit
1162 // i16 post increment store like:
1163 // st X+, r24
1164 // st X+, r25
1165 if (VT == MVT::i16 && !Subtarget.hasLowByteFirst())
1166 return false;
1167 } else {
1168 return false;
1169 }
1170
1171 if (VT != MVT::i8 && VT != MVT::i16) {
1172 return false;
1173 }
1174
1175 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1176 return false;
1177 }
1178
1179 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1180 int RHSC = RHS->getSExtValue();
1181 if (Op->getOpcode() == ISD::SUB)
1182 RHSC = -RHSC;
1183 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
1184 return false;
1185 }
1186
1187 // FIXME: We temporarily disable post increment load from program memory,
1188 // due to bug https://github.com/llvm/llvm-project/issues/59914.
1189 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
1191 return false;
1192
1193 Base = Op->getOperand(0);
1194 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
1195 AM = ISD::POST_INC;
1196
1197 return true;
1198 }
1199
1200 return false;
1201}
1202
1204 const GlobalAddressSDNode *GA) const {
1205 return true;
1206}
1207
1208//===----------------------------------------------------------------------===//
1209// Formal Arguments Calling Convention Implementation
1210//===----------------------------------------------------------------------===//
1211
1212#include "AVRGenCallingConv.inc"
1213
1214/// Registers for calling conventions, ordered in reverse as required by ABI.
1215/// Both arrays must be of the same length.
1216static const MCPhysReg RegList8AVR[] = {
1217 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1218 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
1219 AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
1220static const MCPhysReg RegList8Tiny[] = {AVR::R25, AVR::R24, AVR::R23,
1221 AVR::R22, AVR::R21, AVR::R20};
1222static const MCPhysReg RegList16AVR[] = {
1223 AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
1224 AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
1225 AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
1226 AVR::R11R10, AVR::R10R9, AVR::R9R8};
1227static const MCPhysReg RegList16Tiny[] = {AVR::R26R25, AVR::R25R24,
1228 AVR::R24R23, AVR::R23R22,
1229 AVR::R22R21, AVR::R21R20};
1230
1231static_assert(std::size(RegList8AVR) == std::size(RegList16AVR),
1232 "8-bit and 16-bit register arrays must be of equal length");
1233static_assert(std::size(RegList8Tiny) == std::size(RegList16Tiny),
1234 "8-bit and 16-bit register arrays must be of equal length");
1235
1236/// Analyze incoming and outgoing function arguments. We need custom C++ code
1237/// to handle special constraints in the ABI.
1238/// In addition, all pieces of a certain argument have to be passed either
1239/// using registers or the stack but never mixing both.
1240template <typename ArgT>
1242 const Function *F, const DataLayout *TD,
1243 const SmallVectorImpl<ArgT> &Args,
1245 CCState &CCInfo, bool Tiny) {
1246 // Choose the proper register list for argument passing according to the ABI.
1247 ArrayRef<MCPhysReg> RegList8;
1248 ArrayRef<MCPhysReg> RegList16;
1249 if (Tiny) {
1250 RegList8 = ArrayRef(RegList8Tiny, std::size(RegList8Tiny));
1251 RegList16 = ArrayRef(RegList16Tiny, std::size(RegList16Tiny));
1252 } else {
1253 RegList8 = ArrayRef(RegList8AVR, std::size(RegList8AVR));
1254 RegList16 = ArrayRef(RegList16AVR, std::size(RegList16AVR));
1255 }
1256
1257 unsigned NumArgs = Args.size();
1258 // This is the index of the last used register, in RegList*.
1259 // -1 means R26 (R26 is never actually used in CC).
1260 int RegLastIdx = -1;
1261 // Once a value is passed to the stack it will always be used
1262 bool UseStack = false;
1263 for (unsigned i = 0; i != NumArgs;) {
1264 MVT VT = Args[i].VT;
1265 // We have to count the number of bytes for each function argument, that is
1266 // those Args with the same OrigArgIndex. This is important in case the
1267 // function takes an aggregate type.
1268 // Current argument will be between [i..j).
1269 unsigned ArgIndex = Args[i].OrigArgIndex;
1270 unsigned TotalBytes = VT.getStoreSize();
1271 unsigned j = i + 1;
1272 for (; j != NumArgs; ++j) {
1273 if (Args[j].OrigArgIndex != ArgIndex)
1274 break;
1275 TotalBytes += Args[j].VT.getStoreSize();
1276 }
1277 // Round up to even number of bytes.
1278 TotalBytes = alignTo(TotalBytes, 2);
1279 // Skip zero sized arguments
1280 if (TotalBytes == 0)
1281 continue;
1282 // The index of the first register to be used
1283 unsigned RegIdx = RegLastIdx + TotalBytes;
1284 RegLastIdx = RegIdx;
1285 // If there are not enough registers, use the stack
1286 if (RegIdx >= RegList8.size()) {
1287 UseStack = true;
1288 }
1289 for (; i != j; ++i) {
1290 MVT VT = Args[i].VT;
1291
1292 if (UseStack) {
1293 auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
1294 unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
1295 TD->getABITypeAlign(evt));
1296 CCInfo.addLoc(
1298 } else {
1299 unsigned Reg;
1300 if (VT == MVT::i8) {
1301 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1302 } else if (VT == MVT::i16) {
1303 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1304 } else {
1306 "calling convention can only manage i8 and i16 types");
1307 }
1308 assert(Reg && "register not available in calling convention");
1309 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1310 // Registers inside a particular argument are sorted in increasing order
1311 // (remember the array is reversed).
1312 RegIdx -= VT.getStoreSize();
1313 }
1314 }
1315 }
1316}
1317
1318/// Count the total number of bytes needed to pass or return these arguments.
1319template <typename ArgT>
1320static unsigned
1322 unsigned TotalBytes = 0;
1323
1324 for (const ArgT &Arg : Args) {
1325 TotalBytes += Arg.VT.getStoreSize();
1326 }
1327 return TotalBytes;
1328}
1329
1330/// Analyze incoming and outgoing value of returning from a function.
1331/// The algorithm is similar to analyzeArguments, but there can only be
1332/// one value, possibly an aggregate, and it is limited to 8 bytes.
1333template <typename ArgT>
1335 CCState &CCInfo, bool Tiny) {
1336 unsigned NumArgs = Args.size();
1337 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
1338 // CanLowerReturn() guarantees this assertion.
1339 if (Tiny)
1340 assert(TotalBytes <= 4 &&
1341 "return values greater than 4 bytes cannot be lowered on AVRTiny");
1342 else
1343 assert(TotalBytes <= 8 &&
1344 "return values greater than 8 bytes cannot be lowered on AVR");
1345
1346 // Choose the proper register list for argument passing according to the ABI.
1347 ArrayRef<MCPhysReg> RegList8;
1348 ArrayRef<MCPhysReg> RegList16;
1349 if (Tiny) {
1350 RegList8 = ArrayRef(RegList8Tiny, std::size(RegList8Tiny));
1351 RegList16 = ArrayRef(RegList16Tiny, std::size(RegList16Tiny));
1352 } else {
1353 RegList8 = ArrayRef(RegList8AVR, std::size(RegList8AVR));
1354 RegList16 = ArrayRef(RegList16AVR, std::size(RegList16AVR));
1355 }
1356
1357 // GCC-ABI says that the size is rounded up to the next even number,
1358 // but actually once it is more than 4 it will always round up to 8.
1359 if (TotalBytes > 4) {
1360 TotalBytes = 8;
1361 } else {
1362 TotalBytes = alignTo(TotalBytes, 2);
1363 }
1364
1365 // The index of the first register to use.
1366 int RegIdx = TotalBytes - 1;
1367 for (unsigned i = 0; i != NumArgs; ++i) {
1368 MVT VT = Args[i].VT;
1369 unsigned Reg;
1370 if (VT == MVT::i8) {
1371 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1372 } else if (VT == MVT::i16) {
1373 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1374 } else {
1375 llvm_unreachable("calling convention can only manage i8 and i16 types");
1376 }
1377 assert(Reg && "register not available in calling convention");
1378 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1379 // Registers sort in increasing order
1380 RegIdx -= VT.getStoreSize();
1381 }
1382}
1383
1384SDValue AVRTargetLowering::LowerFormalArguments(
1385 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1386 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1387 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1388 MachineFunction &MF = DAG.getMachineFunction();
1389 MachineFrameInfo &MFI = MF.getFrameInfo();
1390 auto DL = DAG.getDataLayout();
1391
1392 // Assign locations to all of the incoming arguments.
1393 SmallVector<CCValAssign, 16> ArgLocs;
1394 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1395 *DAG.getContext());
1396
1397 // Variadic functions do not need all the analysis below.
1398 if (isVarArg) {
1399 CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
1400 } else {
1401 analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo,
1402 Subtarget.hasTinyEncoding());
1403 }
1404
1405 SDValue ArgValue;
1406 for (CCValAssign &VA : ArgLocs) {
1407
1408 // Arguments stored on registers.
1409 if (VA.isRegLoc()) {
1410 EVT RegVT = VA.getLocVT();
1411 const TargetRegisterClass *RC;
1412 if (RegVT == MVT::i8) {
1413 RC = &AVR::GPR8RegClass;
1414 } else if (RegVT == MVT::i16) {
1415 RC = &AVR::DREGSRegClass;
1416 } else {
1417 llvm_unreachable("Unknown argument type!");
1418 }
1419
1420 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
1421 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1422
1423 // :NOTE: Clang should not promote any i8 into i16 but for safety the
1424 // following code will handle zexts or sexts generated by other
1425 // front ends. Otherwise:
1426 // If this is an 8 bit value, it is really passed promoted
1427 // to 16 bits. Insert an assert[sz]ext to capture this, then
1428 // truncate to the right size.
1429 switch (VA.getLocInfo()) {
1430 default:
1431 llvm_unreachable("Unknown loc info!");
1432 case CCValAssign::Full:
1433 break;
1434 case CCValAssign::BCvt:
1435 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1436 break;
1437 case CCValAssign::SExt:
1438 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1439 DAG.getValueType(VA.getValVT()));
1440 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1441 break;
1442 case CCValAssign::ZExt:
1443 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1444 DAG.getValueType(VA.getValVT()));
1445 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1446 break;
1447 }
1448
1449 InVals.push_back(ArgValue);
1450 } else {
1451 // Only arguments passed on the stack should make it here.
1452 assert(VA.isMemLoc());
1453
1454 EVT LocVT = VA.getLocVT();
1455
1456 // Create the frame index object for this incoming parameter.
1457 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1458 VA.getLocMemOffset(), true);
1459
1460 // Create the SelectionDAG nodes corresponding to a load
1461 // from this parameter.
1462 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1463 InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1465 }
1466 }
1467
1468 // If the function takes variable number of arguments, make a frame index for
1469 // the start of the first vararg value... for expansion of llvm.va_start.
1470 if (isVarArg) {
1471 unsigned StackSize = CCInfo.getStackSize();
1472 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1473
1474 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1475 }
1476
1477 return Chain;
1478}
1479
1480//===----------------------------------------------------------------------===//
1481// Call Calling Convention Implementation
1482//===----------------------------------------------------------------------===//
1483
1484SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1485 SmallVectorImpl<SDValue> &InVals) const {
1486 SelectionDAG &DAG = CLI.DAG;
1487 SDLoc &DL = CLI.DL;
1488 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1489 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1490 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1491 SDValue Chain = CLI.Chain;
1492 SDValue Callee = CLI.Callee;
1493 bool &isTailCall = CLI.IsTailCall;
1494 CallingConv::ID CallConv = CLI.CallConv;
1495 bool isVarArg = CLI.IsVarArg;
1496
1497 MachineFunction &MF = DAG.getMachineFunction();
1498
1499 // AVR does not yet support tail call optimization.
1500 isTailCall = false;
1501
1502 // Analyze operands of the call, assigning locations to each operand.
1503 SmallVector<CCValAssign, 16> ArgLocs;
1504 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1505 *DAG.getContext());
1506
1507 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1508 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1509 // node so that legalize doesn't hack it.
1510 const Function *F = nullptr;
1511 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1512 const GlobalValue *GV = G->getGlobal();
1513 if (isa<Function>(GV))
1514 F = cast<Function>(GV);
1515 Callee =
1516 DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
1517 } else if (const ExternalSymbolSDNode *ES =
1518 dyn_cast<ExternalSymbolSDNode>(Callee)) {
1519 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1520 getPointerTy(DAG.getDataLayout()));
1521 }
1522
1523 // Variadic functions do not need all the analysis below.
1524 if (isVarArg) {
1525 CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
1526 } else {
1527 analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo,
1528 Subtarget.hasTinyEncoding());
1529 }
1530
1531 // Get a count of how many bytes are to be pushed on the stack.
1532 unsigned NumBytes = CCInfo.getStackSize();
1533
1534 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1535
1536 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1537
1538 // First, walk the register assignments, inserting copies.
1539 unsigned AI, AE;
1540 bool HasStackArgs = false;
1541 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1542 CCValAssign &VA = ArgLocs[AI];
1543 EVT RegVT = VA.getLocVT();
1544 SDValue Arg = OutVals[AI];
1545
1546 // Promote the value if needed. With Clang this should not happen.
1547 switch (VA.getLocInfo()) {
1548 default:
1549 llvm_unreachable("Unknown loc info!");
1550 case CCValAssign::Full:
1551 break;
1552 case CCValAssign::SExt:
1553 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1554 break;
1555 case CCValAssign::ZExt:
1556 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1557 break;
1558 case CCValAssign::AExt:
1559 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1560 break;
1561 case CCValAssign::BCvt:
1562 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1563 break;
1564 }
1565
1566 // Stop when we encounter a stack argument, we need to process them
1567 // in reverse order in the loop below.
1568 if (VA.isMemLoc()) {
1569 HasStackArgs = true;
1570 break;
1571 }
1572
1573 // Arguments that can be passed on registers must be kept in the RegsToPass
1574 // vector.
1575 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1576 }
1577
1578 // Second, stack arguments have to walked.
1579 // Previously this code created chained stores but those chained stores appear
1580 // to be unchained in the legalization phase. Therefore, do not attempt to
1581 // chain them here. In fact, chaining them here somehow causes the first and
1582 // second store to be reversed which is the exact opposite of the intended
1583 // effect.
1584 if (HasStackArgs) {
1585 SmallVector<SDValue, 8> MemOpChains;
1586 for (; AI != AE; AI++) {
1587 CCValAssign &VA = ArgLocs[AI];
1588 SDValue Arg = OutVals[AI];
1589
1590 assert(VA.isMemLoc());
1591
1592 // SP points to one stack slot further so add one to adjust it.
1593 SDValue PtrOff = DAG.getNode(
1594 ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1595 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1596 DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1597
1598 MemOpChains.push_back(
1599 DAG.getStore(Chain, DL, Arg, PtrOff,
1600 MachinePointerInfo::getStack(MF, VA.getLocMemOffset())));
1601 }
1602
1603 if (!MemOpChains.empty())
1604 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1605 }
1606
1607 // Build a sequence of copy-to-reg nodes chained together with token chain and
1608 // flag operands which copy the outgoing args into registers. The InGlue in
1609 // necessary since all emited instructions must be stuck together.
1610 SDValue InGlue;
1611 for (auto Reg : RegsToPass) {
1612 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InGlue);
1613 InGlue = Chain.getValue(1);
1614 }
1615
1616 // Returns a chain & a flag for retval copy to use.
1617 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1618 SmallVector<SDValue, 8> Ops;
1619 Ops.push_back(Chain);
1620 Ops.push_back(Callee);
1621
1622 // Add argument registers to the end of the list so that they are known live
1623 // into the call.
1624 for (auto Reg : RegsToPass) {
1625 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1626 }
1627
1628 // The zero register (usually R1) must be passed as an implicit register so
1629 // that this register is correctly zeroed in interrupts.
1630 Ops.push_back(DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8));
1631
1632 // Add a register mask operand representing the call-preserved registers.
1633 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1634 const uint32_t *Mask =
1635 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1636 assert(Mask && "Missing call preserved mask for calling convention");
1637 Ops.push_back(DAG.getRegisterMask(Mask));
1638
1639 if (InGlue.getNode()) {
1640 Ops.push_back(InGlue);
1641 }
1642
1643 Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1644 InGlue = Chain.getValue(1);
1645
1646 // Create the CALLSEQ_END node.
1647 Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, InGlue, DL);
1648
1649 if (!Ins.empty()) {
1650 InGlue = Chain.getValue(1);
1651 }
1652
1653 // Handle result values, copying them out of physregs into vregs that we
1654 // return.
1655 return LowerCallResult(Chain, InGlue, CallConv, isVarArg, Ins, DL, DAG,
1656 InVals);
1657}
1658
1659/// Lower the result values of a call into the
1660/// appropriate copies out of appropriate physical registers.
1661///
1662SDValue AVRTargetLowering::LowerCallResult(
1663 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg,
1664 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1665 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1666
1667 // Assign locations to each value returned by this call.
1668 SmallVector<CCValAssign, 16> RVLocs;
1669 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1670 *DAG.getContext());
1671
1672 // Handle runtime calling convs.
1673 if (CallConv == CallingConv::AVR_BUILTIN) {
1674 CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
1675 } else {
1676 analyzeReturnValues(Ins, CCInfo, Subtarget.hasTinyEncoding());
1677 }
1678
1679 // Copy all of the result registers out of their specified physreg.
1680 for (CCValAssign const &RVLoc : RVLocs) {
1681 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1682 InGlue)
1683 .getValue(1);
1684 InGlue = Chain.getValue(2);
1685 InVals.push_back(Chain.getValue(0));
1686 }
1687
1688 return Chain;
1689}
1690
1691//===----------------------------------------------------------------------===//
1692// Return Value Calling Convention Implementation
1693//===----------------------------------------------------------------------===//
1694
1695bool AVRTargetLowering::CanLowerReturn(
1696 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1697 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1698 if (CallConv == CallingConv::AVR_BUILTIN) {
1699 SmallVector<CCValAssign, 16> RVLocs;
1700 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1701 return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
1702 }
1703
1704 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs);
1705 return TotalBytes <= (unsigned)(Subtarget.hasTinyEncoding() ? 4 : 8);
1706}
1707
1708SDValue
1709AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1710 bool isVarArg,
1711 const SmallVectorImpl<ISD::OutputArg> &Outs,
1712 const SmallVectorImpl<SDValue> &OutVals,
1713 const SDLoc &dl, SelectionDAG &DAG) const {
1714 // CCValAssign - represent the assignment of the return value to locations.
1715 SmallVector<CCValAssign, 16> RVLocs;
1716
1717 // CCState - Info about the registers and stack slot.
1718 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1719 *DAG.getContext());
1720
1721 MachineFunction &MF = DAG.getMachineFunction();
1722
1723 // Analyze return values.
1724 if (CallConv == CallingConv::AVR_BUILTIN) {
1725 CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
1726 } else {
1727 analyzeReturnValues(Outs, CCInfo, Subtarget.hasTinyEncoding());
1728 }
1729
1730 SDValue Glue;
1731 SmallVector<SDValue, 4> RetOps(1, Chain);
1732 // Copy the result values into the output registers.
1733 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1734 CCValAssign &VA = RVLocs[i];
1735 assert(VA.isRegLoc() && "Can only return in registers!");
1736
1737 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Glue);
1738
1739 // Guarantee that all emitted copies are stuck together with flags.
1740 Glue = Chain.getValue(1);
1741 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1742 }
1743
1744 // Don't emit the ret/reti instruction when the naked attribute is present in
1745 // the function being compiled.
1746 if (MF.getFunction().getAttributes().hasFnAttr(Attribute::Naked)) {
1747 return Chain;
1748 }
1749
1750 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1751
1752 if (!AFI->isInterruptOrSignalHandler()) {
1753 // The return instruction has an implicit zero register operand: it must
1754 // contain zero on return.
1755 // This is not needed in interrupts however, where the zero register is
1756 // handled specially (only pushed/popped when needed).
1757 RetOps.push_back(DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8));
1758 }
1759
1760 unsigned RetOpc =
1761 AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_GLUE : AVRISD::RET_GLUE;
1762
1763 RetOps[0] = Chain; // Update chain.
1764
1765 if (Glue.getNode()) {
1766 RetOps.push_back(Glue);
1767 }
1768
1769 return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1770}
1771
1772//===----------------------------------------------------------------------===//
1773// Custom Inserters
1774//===----------------------------------------------------------------------===//
1775
1776MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1777 MachineBasicBlock *BB,
1778 bool Tiny) const {
1779 unsigned Opc;
1780 const TargetRegisterClass *RC;
1781 bool HasRepeatedOperand = false;
1782 MachineFunction *F = BB->getParent();
1783 MachineRegisterInfo &RI = F->getRegInfo();
1784 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1785 DebugLoc dl = MI.getDebugLoc();
1786
1787 switch (MI.getOpcode()) {
1788 default:
1789 llvm_unreachable("Invalid shift opcode!");
1790 case AVR::Lsl8:
1791 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1792 RC = &AVR::GPR8RegClass;
1793 HasRepeatedOperand = true;
1794 break;
1795 case AVR::Lsl16:
1796 Opc = AVR::LSLWRd;
1797 RC = &AVR::DREGSRegClass;
1798 break;
1799 case AVR::Asr8:
1800 Opc = AVR::ASRRd;
1801 RC = &AVR::GPR8RegClass;
1802 break;
1803 case AVR::Asr16:
1804 Opc = AVR::ASRWRd;
1805 RC = &AVR::DREGSRegClass;
1806 break;
1807 case AVR::Lsr8:
1808 Opc = AVR::LSRRd;
1809 RC = &AVR::GPR8RegClass;
1810 break;
1811 case AVR::Lsr16:
1812 Opc = AVR::LSRWRd;
1813 RC = &AVR::DREGSRegClass;
1814 break;
1815 case AVR::Rol8:
1816 Opc = Tiny ? AVR::ROLBRdR17 : AVR::ROLBRdR1;
1817 RC = &AVR::GPR8RegClass;
1818 break;
1819 case AVR::Rol16:
1820 Opc = AVR::ROLWRd;
1821 RC = &AVR::DREGSRegClass;
1822 break;
1823 case AVR::Ror8:
1824 Opc = AVR::RORBRd;
1825 RC = &AVR::GPR8RegClass;
1826 break;
1827 case AVR::Ror16:
1828 Opc = AVR::RORWRd;
1829 RC = &AVR::DREGSRegClass;
1830 break;
1831 }
1832
1833 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1834
1836 for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I)
1837 ;
1838 if (I != F->end())
1839 ++I;
1840
1841 // Create loop block.
1842 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1843 MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB);
1844 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1845
1846 F->insert(I, LoopBB);
1847 F->insert(I, CheckBB);
1848 F->insert(I, RemBB);
1849
1850 // Update machine-CFG edges by transferring all successors of the current
1851 // block to the block containing instructions after shift.
1852 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1853 BB->end());
1854 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1855
1856 // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB.
1857 BB->addSuccessor(CheckBB);
1858 LoopBB->addSuccessor(CheckBB);
1859 CheckBB->addSuccessor(LoopBB);
1860 CheckBB->addSuccessor(RemBB);
1861
1862 Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass);
1863 Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass);
1864 Register ShiftReg = RI.createVirtualRegister(RC);
1865 Register ShiftReg2 = RI.createVirtualRegister(RC);
1866 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1867 Register SrcReg = MI.getOperand(1).getReg();
1868 Register DstReg = MI.getOperand(0).getReg();
1869
1870 // BB:
1871 // rjmp CheckBB
1872 BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB);
1873
1874 // LoopBB:
1875 // ShiftReg2 = shift ShiftReg
1876 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1877 if (HasRepeatedOperand)
1878 ShiftMI.addReg(ShiftReg);
1879
1880 // CheckBB:
1881 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1882 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1883 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1884 // ShiftAmt2 = ShiftAmt - 1;
1885 // if (ShiftAmt2 >= 0) goto LoopBB;
1886 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg)
1887 .addReg(SrcReg)
1888 .addMBB(BB)
1889 .addReg(ShiftReg2)
1890 .addMBB(LoopBB);
1891 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1892 .addReg(ShiftAmtSrcReg)
1893 .addMBB(BB)
1894 .addReg(ShiftAmtReg2)
1895 .addMBB(LoopBB);
1896 BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg)
1897 .addReg(SrcReg)
1898 .addMBB(BB)
1899 .addReg(ShiftReg2)
1900 .addMBB(LoopBB);
1901
1902 BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2).addReg(ShiftAmtReg);
1903 BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB);
1904
1905 MI.eraseFromParent(); // The pseudo instruction is gone now.
1906 return RemBB;
1907}
1908
1909// Do a multibyte AVR shift. Insert shift instructions and put the output
1910// registers in the Regs array.
1911// Because AVR does not have a normal shift instruction (only a single bit shift
1912// instruction), we have to emulate this behavior with other instructions.
1913// It first tries large steps (moving registers around) and then smaller steps
1914// like single bit shifts.
1915// Large shifts actually reduce the number of shifted registers, so the below
1916// algorithms have to work independently of the number of registers that are
1917// shifted.
1918// For more information and background, see this blogpost:
1919// https://aykevl.nl/2021/02/avr-bitshift
1921 MutableArrayRef<std::pair<Register, int>> Regs,
1922 ISD::NodeType Opc, int64_t ShiftAmt) {
1924 const AVRSubtarget &STI = BB->getParent()->getSubtarget<AVRSubtarget>();
1926 const DebugLoc &dl = MI.getDebugLoc();
1927
1928 const bool ShiftLeft = Opc == ISD::SHL;
1929 const bool ArithmeticShift = Opc == ISD::SRA;
1930
1931 // Zero a register, for use in later operations.
1932 Register ZeroReg = MRI.createVirtualRegister(&AVR::GPR8RegClass);
1933 BuildMI(*BB, MI, dl, TII.get(AVR::COPY), ZeroReg)
1934 .addReg(STI.getZeroRegister());
1935
1936 // Do a shift modulo 6 or 7. This is a bit more complicated than most shifts
1937 // and is hard to compose with the rest, so these are special cased.
1938 // The basic idea is to shift one or two bits in the opposite direction and
1939 // then move registers around to get the correct end result.
1940 if (ShiftLeft && (ShiftAmt % 8) >= 6) {
1941 // Left shift modulo 6 or 7.
1942
1943 // Create a slice of the registers we're going to modify, to ease working
1944 // with them.
1945 size_t ShiftRegsOffset = ShiftAmt / 8;
1946 size_t ShiftRegsSize = Regs.size() - ShiftRegsOffset;
1948 Regs.slice(ShiftRegsOffset, ShiftRegsSize);
1949
1950 // Shift one to the right, keeping the least significant bit as the carry
1951 // bit.
1952 insertMultibyteShift(MI, BB, ShiftRegs, ISD::SRL, 1);
1953
1954 // Rotate the least significant bit from the carry bit into a new register
1955 // (that starts out zero).
1956 Register LowByte = MRI.createVirtualRegister(&AVR::GPR8RegClass);
1957 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), LowByte).addReg(ZeroReg);
1958
1959 // Shift one more to the right if this is a modulo-6 shift.
1960 if (ShiftAmt % 8 == 6) {
1961 insertMultibyteShift(MI, BB, ShiftRegs, ISD::SRL, 1);
1962 Register NewLowByte = MRI.createVirtualRegister(&AVR::GPR8RegClass);
1963 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), NewLowByte).addReg(LowByte);
1964 LowByte = NewLowByte;
1965 }
1966
1967 // Move all registers to the left, zeroing the bottom registers as needed.
1968 for (size_t I = 0; I < Regs.size(); I++) {
1969 int ShiftRegsIdx = I + 1;
1970 if (ShiftRegsIdx < (int)ShiftRegs.size()) {
1971 Regs[I] = ShiftRegs[ShiftRegsIdx];
1972 } else if (ShiftRegsIdx == (int)ShiftRegs.size()) {
1973 Regs[I] = std::pair(LowByte, 0);
1974 } else {
1975 Regs[I] = std::pair(ZeroReg, 0);
1976 }
1977 }
1978
1979 return;
1980 }
1981
1982 // Right shift modulo 6 or 7.
1983 if (!ShiftLeft && (ShiftAmt % 8) >= 6) {
1984 // Create a view on the registers we're going to modify, to ease working
1985 // with them.
1986 size_t ShiftRegsSize = Regs.size() - (ShiftAmt / 8);
1988 Regs.slice(0, ShiftRegsSize);
1989
1990 // Shift one to the left.
1991 insertMultibyteShift(MI, BB, ShiftRegs, ISD::SHL, 1);
1992
1993 // Sign or zero extend the most significant register into a new register.
1994 // The HighByte is the byte that still has one (or two) bits from the
1995 // original value. The ExtByte is purely a zero/sign extend byte (all bits
1996 // are either 0 or 1).
1997 Register HighByte = MRI.createVirtualRegister(&AVR::GPR8RegClass);
1998 Register ExtByte = 0;
1999 if (ArithmeticShift) {
2000 // Sign-extend bit that was shifted out last.
2001 BuildMI(*BB, MI, dl, TII.get(AVR::SBCRdRr), HighByte)
2002 .addReg(HighByte, RegState::Undef)
2003 .addReg(HighByte, RegState::Undef);
2004 ExtByte = HighByte;
2005 // The highest bit of the original value is the same as the zero-extend
2006 // byte, so HighByte and ExtByte are the same.
2007 } else {
2008 // Use the zero register for zero extending.
2009 ExtByte = ZeroReg;
2010 // Rotate most significant bit into a new register (that starts out zero).
2011 BuildMI(*BB, MI, dl, TII.get(AVR::ADCRdRr), HighByte)
2012 .addReg(ExtByte)
2013 .addReg(ExtByte);
2014 }
2015
2016 // Shift one more to the left for modulo 6 shifts.
2017 if (ShiftAmt % 8 == 6) {
2018 insertMultibyteShift(MI, BB, ShiftRegs, ISD::SHL, 1);
2019 // Shift the topmost bit into the HighByte.
2020 Register NewExt = MRI.createVirtualRegister(&AVR::GPR8RegClass);
2021 BuildMI(*BB, MI, dl, TII.get(AVR::ADCRdRr), NewExt)
2022 .addReg(HighByte)
2023 .addReg(HighByte);
2024 HighByte = NewExt;
2025 }
2026
2027 // Move all to the right, while sign or zero extending.
2028 for (int I = Regs.size() - 1; I >= 0; I--) {
2029 int ShiftRegsIdx = I - (Regs.size() - ShiftRegs.size()) - 1;
2030 if (ShiftRegsIdx >= 0) {
2031 Regs[I] = ShiftRegs[ShiftRegsIdx];
2032 } else if (ShiftRegsIdx == -1) {
2033 Regs[I] = std::pair(HighByte, 0);
2034 } else {
2035 Regs[I] = std::pair(ExtByte, 0);
2036 }
2037 }
2038
2039 return;
2040 }
2041
2042 // For shift amounts of at least one register, simply rename the registers and
2043 // zero the bottom registers.
2044 while (ShiftLeft && ShiftAmt >= 8) {
2045 // Move all registers one to the left.
2046 for (size_t I = 0; I < Regs.size() - 1; I++) {
2047 Regs[I] = Regs[I + 1];
2048 }
2049
2050 // Zero the least significant register.
2051 Regs[Regs.size() - 1] = std::pair(ZeroReg, 0);
2052
2053 // Continue shifts with the leftover registers.
2054 Regs = Regs.drop_back(1);
2055
2056 ShiftAmt -= 8;
2057 }
2058
2059 // And again, the same for right shifts.
2060 Register ShrExtendReg = 0;
2061 if (!ShiftLeft && ShiftAmt >= 8) {
2062 if (ArithmeticShift) {
2063 // Sign extend the most significant register into ShrExtendReg.
2064 ShrExtendReg = MRI.createVirtualRegister(&AVR::GPR8RegClass);
2065 Register Tmp = MRI.createVirtualRegister(&AVR::GPR8RegClass);
2066 BuildMI(*BB, MI, dl, TII.get(AVR::ADDRdRr), Tmp)
2067 .addReg(Regs[0].first, 0, Regs[0].second)
2068 .addReg(Regs[0].first, 0, Regs[0].second);
2069 BuildMI(*BB, MI, dl, TII.get(AVR::SBCRdRr), ShrExtendReg)
2070 .addReg(Tmp)
2071 .addReg(Tmp);
2072 } else {
2073 ShrExtendReg = ZeroReg;
2074 }
2075 for (; ShiftAmt >= 8; ShiftAmt -= 8) {
2076 // Move all registers one to the right.
2077 for (size_t I = Regs.size() - 1; I != 0; I--) {
2078 Regs[I] = Regs[I - 1];
2079 }
2080
2081 // Zero or sign extend the most significant register.
2082 Regs[0] = std::pair(ShrExtendReg, 0);
2083
2084 // Continue shifts with the leftover registers.
2085 Regs = Regs.drop_front(1);
2086 }
2087 }
2088
2089 // The bigger shifts are already handled above.
2090 assert((ShiftAmt < 8) && "Unexpect shift amount");
2091
2092 // Shift by four bits, using a complicated swap/eor/andi/eor sequence.
2093 // It only works for logical shifts because the bits shifted in are all
2094 // zeroes.
2095 // To shift a single byte right, it produces code like this:
2096 // swap r0
2097 // andi r0, 0x0f
2098 // For a two-byte (16-bit) shift, it adds the following instructions to shift
2099 // the upper byte into the lower byte:
2100 // swap r1
2101 // eor r0, r1
2102 // andi r1, 0x0f
2103 // eor r0, r1
2104 // For bigger shifts, it repeats the above sequence. For example, for a 3-byte
2105 // (24-bit) shift it adds:
2106 // swap r2
2107 // eor r1, r2
2108 // andi r2, 0x0f
2109 // eor r1, r2
2110 if (!ArithmeticShift && ShiftAmt >= 4) {
2111 Register Prev = 0;
2112 for (size_t I = 0; I < Regs.size(); I++) {
2113 size_t Idx = ShiftLeft ? I : Regs.size() - I - 1;
2114 Register SwapReg = MRI.createVirtualRegister(&AVR::LD8RegClass);
2115 BuildMI(*BB, MI, dl, TII.get(AVR::SWAPRd), SwapReg)
2116 .addReg(Regs[Idx].first, 0, Regs[Idx].second);
2117 if (I != 0) {
2118 Register R = MRI.createVirtualRegister(&AVR::GPR8RegClass);
2119 BuildMI(*BB, MI, dl, TII.get(AVR::EORRdRr), R)
2120 .addReg(Prev)
2121 .addReg(SwapReg);
2122 Prev = R;
2123 }
2124 Register AndReg = MRI.createVirtualRegister(&AVR::LD8RegClass);
2125 BuildMI(*BB, MI, dl, TII.get(AVR::ANDIRdK), AndReg)
2126 .addReg(SwapReg)
2127 .addImm(ShiftLeft ? 0xf0 : 0x0f);
2128 if (I != 0) {
2129 Register R = MRI.createVirtualRegister(&AVR::GPR8RegClass);
2130 BuildMI(*BB, MI, dl, TII.get(AVR::EORRdRr), R)
2131 .addReg(Prev)
2132 .addReg(AndReg);
2133 size_t PrevIdx = ShiftLeft ? Idx - 1 : Idx + 1;
2134 Regs[PrevIdx] = std::pair(R, 0);
2135 }
2136 Prev = AndReg;
2137 Regs[Idx] = std::pair(AndReg, 0);
2138 }
2139 ShiftAmt -= 4;
2140 }
2141
2142 // Shift by one. This is the fallback that always works, and the shift
2143 // operation that is used for 1, 2, and 3 bit shifts.
2144 while (ShiftLeft && ShiftAmt) {
2145 // Shift one to the left.
2146 for (ssize_t I = Regs.size() - 1; I >= 0; I--) {
2147 Register Out = MRI.createVirtualRegister(&AVR::GPR8RegClass);
2148 Register In = Regs[I].first;
2149 Register InSubreg = Regs[I].second;
2150 if (I == (ssize_t)Regs.size() - 1) { // first iteration
2151 BuildMI(*BB, MI, dl, TII.get(AVR::ADDRdRr), Out)
2152 .addReg(In, 0, InSubreg)
2153 .addReg(In, 0, InSubreg);
2154 } else {
2155 BuildMI(*BB, MI, dl, TII.get(AVR::ADCRdRr), Out)
2156 .addReg(In, 0, InSubreg)
2157 .addReg(In, 0, InSubreg);
2158 }
2159 Regs[I] = std::pair(Out, 0);
2160 }
2161 ShiftAmt--;
2162 }
2163 while (!ShiftLeft && ShiftAmt) {
2164 // Shift one to the right.
2165 for (size_t I = 0; I < Regs.size(); I++) {
2166 Register Out = MRI.createVirtualRegister(&AVR::GPR8RegClass);
2167 Register In = Regs[I].first;
2168 Register InSubreg = Regs[I].second;
2169 if (I == 0) {
2170 unsigned Opc = ArithmeticShift ? AVR::ASRRd : AVR::LSRRd;
2171 BuildMI(*BB, MI, dl, TII.get(Opc), Out).addReg(In, 0, InSubreg);
2172 } else {
2173 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), Out).addReg(In, 0, InSubreg);
2174 }
2175 Regs[I] = std::pair(Out, 0);
2176 }
2177 ShiftAmt--;
2178 }
2179
2180 if (ShiftAmt != 0) {
2181 llvm_unreachable("don't know how to shift!"); // sanity check
2182 }
2183}
2184
2185// Do a wide (32-bit) shift.
2186MachineBasicBlock *
2187AVRTargetLowering::insertWideShift(MachineInstr &MI,
2188 MachineBasicBlock *BB) const {
2189 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2190 const DebugLoc &dl = MI.getDebugLoc();
2191
2192 // How much to shift to the right (meaning: a negative number indicates a left
2193 // shift).
2194 int64_t ShiftAmt = MI.getOperand(4).getImm();
2195 ISD::NodeType Opc;
2196 switch (MI.getOpcode()) {
2197 case AVR::Lsl32:
2198 Opc = ISD::SHL;
2199 break;
2200 case AVR::Lsr32:
2201 Opc = ISD::SRL;
2202 break;
2203 case AVR::Asr32:
2204 Opc = ISD::SRA;
2205 break;
2206 }
2207
2208 // Read the input registers, with the most significant register at index 0.
2209 std::array<std::pair<Register, int>, 4> Registers = {
2210 std::pair(MI.getOperand(3).getReg(), AVR::sub_hi),
2211 std::pair(MI.getOperand(3).getReg(), AVR::sub_lo),
2212 std::pair(MI.getOperand(2).getReg(), AVR::sub_hi),
2213 std::pair(MI.getOperand(2).getReg(), AVR::sub_lo),
2214 };
2215
2216 // Do the shift. The registers are modified in-place.
2217 insertMultibyteShift(MI, BB, Registers, Opc, ShiftAmt);
2218
2219 // Combine the 8-bit registers into 16-bit register pairs.
2220 // This done either from LSB to MSB or from MSB to LSB, depending on the
2221 // shift. It's an optimization so that the register allocator will use the
2222 // fewest movs possible (which order we use isn't a correctness issue, just an
2223 // optimization issue).
2224 // - lsl prefers starting from the most significant byte (2nd case).
2225 // - lshr prefers starting from the least significant byte (1st case).
2226 // - for ashr it depends on the number of shifted bytes.
2227 // Some shift operations still don't get the most optimal mov sequences even
2228 // with this distinction. TODO: figure out why and try to fix it (but we're
2229 // already equal to or faster than avr-gcc in all cases except ashr 8).
2230 if (Opc != ISD::SHL &&
2231 (Opc != ISD::SRA || (ShiftAmt < 16 || ShiftAmt >= 22))) {
2232 // Use the resulting registers starting with the least significant byte.
2233 BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(0).getReg())
2234 .addReg(Registers[3].first, 0, Registers[3].second)
2235 .addImm(AVR::sub_lo)
2236 .addReg(Registers[2].first, 0, Registers[2].second)
2237 .addImm(AVR::sub_hi);
2238 BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(1).getReg())
2239 .addReg(Registers[1].first, 0, Registers[1].second)
2240 .addImm(AVR::sub_lo)
2241 .addReg(Registers[0].first, 0, Registers[0].second)
2242 .addImm(AVR::sub_hi);
2243 } else {
2244 // Use the resulting registers starting with the most significant byte.
2245 BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(1).getReg())
2246 .addReg(Registers[0].first, 0, Registers[0].second)
2247 .addImm(AVR::sub_hi)
2248 .addReg(Registers[1].first, 0, Registers[1].second)
2249 .addImm(AVR::sub_lo);
2250 BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(0).getReg())
2251 .addReg(Registers[2].first, 0, Registers[2].second)
2252 .addImm(AVR::sub_hi)
2253 .addReg(Registers[3].first, 0, Registers[3].second)
2254 .addImm(AVR::sub_lo);
2255 }
2256
2257 // Remove the pseudo instruction.
2258 MI.eraseFromParent();
2259 return BB;
2260}
2261
2263 if (I->getOpcode() == AVR::COPY) {
2264 Register SrcReg = I->getOperand(1).getReg();
2265 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
2266 }
2267
2268 return false;
2269}
2270
2271// The mul instructions wreak havock on our zero_reg R1. We need to clear it
2272// after the result has been evacuated. This is probably not the best way to do
2273// it, but it works for now.
2274MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
2275 MachineBasicBlock *BB) const {
2276 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2278 ++I; // in any case insert *after* the mul instruction
2279 if (isCopyMulResult(I))
2280 ++I;
2281 if (isCopyMulResult(I))
2282 ++I;
2283 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
2284 .addReg(AVR::R1)
2285 .addReg(AVR::R1);
2286 return BB;
2287}
2288
2289// Insert a read from the zero register.
2290MachineBasicBlock *
2291AVRTargetLowering::insertCopyZero(MachineInstr &MI,
2292 MachineBasicBlock *BB) const {
2293 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2295 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::COPY))
2296 .add(MI.getOperand(0))
2298 MI.eraseFromParent();
2299 return BB;
2300}
2301
2302// Lower atomicrmw operation to disable interrupts, do operation, and restore
2303// interrupts. This works because all AVR microcontrollers are single core.
2304MachineBasicBlock *AVRTargetLowering::insertAtomicArithmeticOp(
2305 MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, int Width) const {
2306 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
2307 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2309 DebugLoc dl = MI.getDebugLoc();
2310
2311 // Example instruction sequence, for an atomic 8-bit add:
2312 // ldi r25, 5
2313 // in r0, SREG
2314 // cli
2315 // ld r24, X
2316 // add r25, r24
2317 // st X, r25
2318 // out SREG, r0
2319
2320 const TargetRegisterClass *RC =
2321 (Width == 8) ? &AVR::GPR8RegClass : &AVR::DREGSRegClass;
2322 unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
2323 unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
2324
2325 // Disable interrupts.
2326 BuildMI(*BB, I, dl, TII.get(AVR::INRdA), Subtarget.getTmpRegister())
2328 BuildMI(*BB, I, dl, TII.get(AVR::BCLRs)).addImm(7);
2329
2330 // Load the original value.
2331 BuildMI(*BB, I, dl, TII.get(LoadOpcode), MI.getOperand(0).getReg())
2332 .add(MI.getOperand(1));
2333
2334 // Do the arithmetic operation.
2335 Register Result = MRI.createVirtualRegister(RC);
2336 BuildMI(*BB, I, dl, TII.get(Opcode), Result)
2337 .addReg(MI.getOperand(0).getReg())
2338 .add(MI.getOperand(2));
2339
2340 // Store the result.
2341 BuildMI(*BB, I, dl, TII.get(StoreOpcode))
2342 .add(MI.getOperand(1))
2343 .addReg(Result);
2344
2345 // Restore interrupts.
2346 BuildMI(*BB, I, dl, TII.get(AVR::OUTARr))
2349
2350 // Remove the pseudo instruction.
2351 MI.eraseFromParent();
2352 return BB;
2353}
2354
2355MachineBasicBlock *
2357 MachineBasicBlock *MBB) const {
2358 int Opc = MI.getOpcode();
2359 const AVRSubtarget &STI = MBB->getParent()->getSubtarget<AVRSubtarget>();
2360
2361 // Pseudo shift instructions with a non constant shift amount are expanded
2362 // into a loop.
2363 switch (Opc) {
2364 case AVR::Lsl8:
2365 case AVR::Lsl16:
2366 case AVR::Lsr8:
2367 case AVR::Lsr16:
2368 case AVR::Rol8:
2369 case AVR::Rol16:
2370 case AVR::Ror8:
2371 case AVR::Ror16:
2372 case AVR::Asr8:
2373 case AVR::Asr16:
2374 return insertShift(MI, MBB, STI.hasTinyEncoding());
2375 case AVR::Lsl32:
2376 case AVR::Lsr32:
2377 case AVR::Asr32:
2378 return insertWideShift(MI, MBB);
2379 case AVR::MULRdRr:
2380 case AVR::MULSRdRr:
2381 return insertMul(MI, MBB);
2382 case AVR::CopyZero:
2383 return insertCopyZero(MI, MBB);
2384 case AVR::AtomicLoadAdd8:
2385 return insertAtomicArithmeticOp(MI, MBB, AVR::ADDRdRr, 8);
2386 case AVR::AtomicLoadAdd16:
2387 return insertAtomicArithmeticOp(MI, MBB, AVR::ADDWRdRr, 16);
2388 case AVR::AtomicLoadSub8:
2389 return insertAtomicArithmeticOp(MI, MBB, AVR::SUBRdRr, 8);
2390 case AVR::AtomicLoadSub16:
2391 return insertAtomicArithmeticOp(MI, MBB, AVR::SUBWRdRr, 16);
2392 case AVR::AtomicLoadAnd8:
2393 return insertAtomicArithmeticOp(MI, MBB, AVR::ANDRdRr, 8);
2394 case AVR::AtomicLoadAnd16:
2395 return insertAtomicArithmeticOp(MI, MBB, AVR::ANDWRdRr, 16);
2396 case AVR::AtomicLoadOr8:
2397 return insertAtomicArithmeticOp(MI, MBB, AVR::ORRdRr, 8);
2398 case AVR::AtomicLoadOr16:
2399 return insertAtomicArithmeticOp(MI, MBB, AVR::ORWRdRr, 16);
2400 case AVR::AtomicLoadXor8:
2401 return insertAtomicArithmeticOp(MI, MBB, AVR::EORRdRr, 8);
2402 case AVR::AtomicLoadXor16:
2403 return insertAtomicArithmeticOp(MI, MBB, AVR::EORWRdRr, 16);
2404 }
2405
2406 assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
2407 "Unexpected instr type to insert");
2408
2409 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
2410 ->getParent()
2411 ->getSubtarget()
2412 .getInstrInfo();
2413 DebugLoc dl = MI.getDebugLoc();
2414
2415 // To "insert" a SELECT instruction, we insert the diamond
2416 // control-flow pattern. The incoming instruction knows the
2417 // destination vreg to set, the condition code register to branch
2418 // on, the true/false values to select between, and a branch opcode
2419 // to use.
2420
2421 MachineFunction *MF = MBB->getParent();
2422 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
2423 MachineBasicBlock *FallThrough = MBB->getFallThrough();
2424
2425 // If the current basic block falls through to another basic block,
2426 // we must insert an unconditional branch to the fallthrough destination
2427 // if we are to insert basic blocks at the prior fallthrough point.
2428 if (FallThrough != nullptr) {
2429 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
2430 }
2431
2432 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2433 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2434
2436 for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I)
2437 ;
2438 if (I != MF->end())
2439 ++I;
2440 MF->insert(I, trueMBB);
2441 MF->insert(I, falseMBB);
2442
2443 // Set the call frame size on entry to the new basic blocks.
2444 unsigned CallFrameSize = TII.getCallFrameSizeAt(MI);
2445 trueMBB->setCallFrameSize(CallFrameSize);
2446 falseMBB->setCallFrameSize(CallFrameSize);
2447
2448 // Transfer remaining instructions and all successors of the current
2449 // block to the block which will contain the Phi node for the
2450 // select.
2451 trueMBB->splice(trueMBB->begin(), MBB,
2452 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
2454
2455 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
2456 BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
2457 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
2458 MBB->addSuccessor(falseMBB);
2459 MBB->addSuccessor(trueMBB);
2460
2461 // Unconditionally flow back to the true block
2462 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
2463 falseMBB->addSuccessor(trueMBB);
2464
2465 // Set up the Phi node to determine where we came from
2466 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI),
2467 MI.getOperand(0).getReg())
2468 .addReg(MI.getOperand(1).getReg())
2469 .addMBB(MBB)
2470 .addReg(MI.getOperand(2).getReg())
2471 .addMBB(falseMBB);
2472
2473 MI.eraseFromParent(); // The pseudo instruction is gone now.
2474 return trueMBB;
2475}
2476
2477//===----------------------------------------------------------------------===//
2478// Inline Asm Support
2479//===----------------------------------------------------------------------===//
2480
2483 if (Constraint.size() == 1) {
2484 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
2485 switch (Constraint[0]) {
2486 default:
2487 break;
2488 case 'a': // Simple upper registers
2489 case 'b': // Base pointer registers pairs
2490 case 'd': // Upper register
2491 case 'l': // Lower registers
2492 case 'e': // Pointer register pairs
2493 case 'q': // Stack pointer register
2494 case 'r': // Any register
2495 case 'w': // Special upper register pairs
2496 return C_RegisterClass;
2497 case 't': // Temporary register
2498 case 'x':
2499 case 'X': // Pointer register pair X
2500 case 'y':
2501 case 'Y': // Pointer register pair Y
2502 case 'z':
2503 case 'Z': // Pointer register pair Z
2504 return C_Register;
2505 case 'Q': // A memory address based on Y or Z pointer with displacement.
2506 return C_Memory;
2507 case 'G': // Floating point constant
2508 case 'I': // 6-bit positive integer constant
2509 case 'J': // 6-bit negative integer constant
2510 case 'K': // Integer constant (Range: 2)
2511 case 'L': // Integer constant (Range: 0)
2512 case 'M': // 8-bit integer constant
2513 case 'N': // Integer constant (Range: -1)
2514 case 'O': // Integer constant (Range: 8, 16, 24)
2515 case 'P': // Integer constant (Range: 1)
2516 case 'R': // Integer constant (Range: -6 to 5)x
2517 return C_Immediate;
2518 }
2519 }
2520
2521 return TargetLowering::getConstraintType(Constraint);
2522}
2523
2526 // Not sure if this is actually the right thing to do, but we got to do
2527 // *something* [agnat]
2528 switch (ConstraintCode[0]) {
2529 case 'Q':
2531 }
2532 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
2533}
2534
2537 AsmOperandInfo &info, const char *constraint) const {
2539 Value *CallOperandVal = info.CallOperandVal;
2540
2541 // If we don't have a value, we can't do a match,
2542 // but allow it at the lowest weight.
2543 // (this behaviour has been copied from the ARM backend)
2544 if (!CallOperandVal) {
2545 return CW_Default;
2546 }
2547
2548 // Look at the constraint type.
2549 switch (*constraint) {
2550 default:
2552 break;
2553 case 'd':
2554 case 'r':
2555 case 'l':
2556 weight = CW_Register;
2557 break;
2558 case 'a':
2559 case 'b':
2560 case 'e':
2561 case 'q':
2562 case 't':
2563 case 'w':
2564 case 'x':
2565 case 'X':
2566 case 'y':
2567 case 'Y':
2568 case 'z':
2569 case 'Z':
2570 weight = CW_SpecificReg;
2571 break;
2572 case 'G':
2573 if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
2574 if (C->isZero()) {
2575 weight = CW_Constant;
2576 }
2577 }
2578 break;
2579 case 'I':
2580 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2581 if (isUInt<6>(C->getZExtValue())) {
2582 weight = CW_Constant;
2583 }
2584 }
2585 break;
2586 case 'J':
2587 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2588 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
2589 weight = CW_Constant;
2590 }
2591 }
2592 break;
2593 case 'K':
2594 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2595 if (C->getZExtValue() == 2) {
2596 weight = CW_Constant;
2597 }
2598 }
2599 break;
2600 case 'L':
2601 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2602 if (C->getZExtValue() == 0) {
2603 weight = CW_Constant;
2604 }
2605 }
2606 break;
2607 case 'M':
2608 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2609 if (isUInt<8>(C->getZExtValue())) {
2610 weight = CW_Constant;
2611 }
2612 }
2613 break;
2614 case 'N':
2615 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2616 if (C->getSExtValue() == -1) {
2617 weight = CW_Constant;
2618 }
2619 }
2620 break;
2621 case 'O':
2622 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2623 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
2624 (C->getZExtValue() == 24)) {
2625 weight = CW_Constant;
2626 }
2627 }
2628 break;
2629 case 'P':
2630 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2631 if (C->getZExtValue() == 1) {
2632 weight = CW_Constant;
2633 }
2634 }
2635 break;
2636 case 'R':
2637 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2638 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
2639 weight = CW_Constant;
2640 }
2641 }
2642 break;
2643 case 'Q':
2644 weight = CW_Memory;
2645 break;
2646 }
2647
2648 return weight;
2649}
2650
2651std::pair<unsigned, const TargetRegisterClass *>
2653 StringRef Constraint,
2654 MVT VT) const {
2655 if (Constraint.size() == 1) {
2656 switch (Constraint[0]) {
2657 case 'a': // Simple upper registers r16..r23.
2658 if (VT == MVT::i8)
2659 return std::make_pair(0U, &AVR::LD8loRegClass);
2660 else if (VT == MVT::i16)
2661 return std::make_pair(0U, &AVR::DREGSLD8loRegClass);
2662 break;
2663 case 'b': // Base pointer registers: y, z.
2664 if (VT == MVT::i8 || VT == MVT::i16)
2665 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
2666 break;
2667 case 'd': // Upper registers r16..r31.
2668 if (VT == MVT::i8)
2669 return std::make_pair(0U, &AVR::LD8RegClass);
2670 else if (VT == MVT::i16)
2671 return std::make_pair(0U, &AVR::DLDREGSRegClass);
2672 break;
2673 case 'l': // Lower registers r0..r15.
2674 if (VT == MVT::i8)
2675 return std::make_pair(0U, &AVR::GPR8loRegClass);
2676 else if (VT == MVT::i16)
2677 return std::make_pair(0U, &AVR::DREGSloRegClass);
2678 break;
2679 case 'e': // Pointer register pairs: x, y, z.
2680 if (VT == MVT::i8 || VT == MVT::i16)
2681 return std::make_pair(0U, &AVR::PTRREGSRegClass);
2682 break;
2683 case 'q': // Stack pointer register: SPH:SPL.
2684 return std::make_pair(0U, &AVR::GPRSPRegClass);
2685 case 'r': // Any register: r0..r31.
2686 if (VT == MVT::i8)
2687 return std::make_pair(0U, &AVR::GPR8RegClass);
2688 else if (VT == MVT::i16)
2689 return std::make_pair(0U, &AVR::DREGSRegClass);
2690 break;
2691 case 't': // Temporary register: r0.
2692 if (VT == MVT::i8)
2693 return std::make_pair(unsigned(Subtarget.getTmpRegister()),
2694 &AVR::GPR8RegClass);
2695 break;
2696 case 'w': // Special upper register pairs: r24, r26, r28, r30.
2697 if (VT == MVT::i8 || VT == MVT::i16)
2698 return std::make_pair(0U, &AVR::IWREGSRegClass);
2699 break;
2700 case 'x': // Pointer register pair X: r27:r26.
2701 case 'X':
2702 if (VT == MVT::i8 || VT == MVT::i16)
2703 return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
2704 break;
2705 case 'y': // Pointer register pair Y: r29:r28.
2706 case 'Y':
2707 if (VT == MVT::i8 || VT == MVT::i16)
2708 return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
2709 break;
2710 case 'z': // Pointer register pair Z: r31:r30.
2711 case 'Z':
2712 if (VT == MVT::i8 || VT == MVT::i16)
2713 return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
2714 break;
2715 default:
2716 break;
2717 }
2718 }
2719
2721 Subtarget.getRegisterInfo(), Constraint, VT);
2722}
2723
2725 StringRef Constraint,
2726 std::vector<SDValue> &Ops,
2727 SelectionDAG &DAG) const {
2728 SDValue Result;
2729 SDLoc DL(Op);
2730 EVT Ty = Op.getValueType();
2731
2732 // Currently only support length 1 constraints.
2733 if (Constraint.size() != 1) {
2734 return;
2735 }
2736
2737 char ConstraintLetter = Constraint[0];
2738 switch (ConstraintLetter) {
2739 default:
2740 break;
2741 // Deal with integers first:
2742 case 'I':
2743 case 'J':
2744 case 'K':
2745 case 'L':
2746 case 'M':
2747 case 'N':
2748 case 'O':
2749 case 'P':
2750 case 'R': {
2751 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2752 if (!C) {
2753 return;
2754 }
2755
2756 int64_t CVal64 = C->getSExtValue();
2757 uint64_t CUVal64 = C->getZExtValue();
2758 switch (ConstraintLetter) {
2759 case 'I': // 0..63
2760 if (!isUInt<6>(CUVal64))
2761 return;
2762 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2763 break;
2764 case 'J': // -63..0
2765 if (CVal64 < -63 || CVal64 > 0)
2766 return;
2767 Result = DAG.getTargetConstant(CVal64, DL, Ty);
2768 break;
2769 case 'K': // 2
2770 if (CUVal64 != 2)
2771 return;
2772 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2773 break;
2774 case 'L': // 0
2775 if (CUVal64 != 0)
2776 return;
2777 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2778 break;
2779 case 'M': // 0..255
2780 if (!isUInt<8>(CUVal64))
2781 return;
2782 // i8 type may be printed as a negative number,
2783 // e.g. 254 would be printed as -2,
2784 // so we force it to i16 at least.
2785 if (Ty.getSimpleVT() == MVT::i8) {
2786 Ty = MVT::i16;
2787 }
2788 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2789 break;
2790 case 'N': // -1
2791 if (CVal64 != -1)
2792 return;
2793 Result = DAG.getTargetConstant(CVal64, DL, Ty);
2794 break;
2795 case 'O': // 8, 16, 24
2796 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
2797 return;
2798 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2799 break;
2800 case 'P': // 1
2801 if (CUVal64 != 1)
2802 return;
2803 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2804 break;
2805 case 'R': // -6..5
2806 if (CVal64 < -6 || CVal64 > 5)
2807 return;
2808 Result = DAG.getTargetConstant(CVal64, DL, Ty);
2809 break;
2810 }
2811
2812 break;
2813 }
2814 case 'G':
2815 const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op);
2816 if (!FC || !FC->isZero())
2817 return;
2818 // Soften float to i8 0
2819 Result = DAG.getTargetConstant(0, DL, MVT::i8);
2820 break;
2821 }
2822
2823 if (Result.getNode()) {
2824 Ops.push_back(Result);
2825 return;
2826 }
2827
2828 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2829}
2830
2832 const MachineFunction &MF) const {
2833 Register Reg;
2834
2835 if (VT == LLT::scalar(8)) {
2837 .Case("r0", AVR::R0)
2838 .Case("r1", AVR::R1)
2839 .Default(0);
2840 } else {
2842 .Case("r0", AVR::R1R0)
2843 .Case("sp", AVR::SP)
2844 .Default(0);
2845 }
2846
2847 if (Reg)
2848 return Reg;
2849
2851 Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
2852}
2853
2854} // end of namespace llvm
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define NODE(NodeKind)
#define RegName(no)
lazy value info
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
unsigned Reg
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI Pre allocate WWM Registers
This file contains some templates that are useful if you are working with the STL at all.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Value * RHS
Value * LHS
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:66
A specific AVR target MCU.
Definition: AVRSubtarget.h:32
Register getTmpRegister() const
Definition: AVRSubtarget.h:91
Register getZeroRegister() const
Definition: AVRSubtarget.h:94
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:42
int getIORegSREG() const
Definition: AVRSubtarget.h:85
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:52
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
const AVRSubtarget & Subtarget
InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
AVRTargetLowering(const AVRTargetMachine &TM, const AVRSubtarget &STI)
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
A generic AVR implementation.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
LLVM Basic Block Representation.
Definition: BasicBlock.h:56
CCState - This class holds information needed while lowering arguments and return values.
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
LLVMContext & getContext() const
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
void addLoc(const CCValAssign &V)
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:260
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:863
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:504
A debug info location.
Definition: DebugLoc.h:33
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
This class is used to represent ISD::LOAD nodes.
Machine Value Type.
static auto integer_valuetypes()
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
void setCallFrameSize(unsigned N)
Set the call frame size on entry to this basic block.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineInstrBundleIterator< MachineInstr > iterator
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
BasicBlockListType::iterator iterator
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
MutableArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:376
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDValue getValue(unsigned R) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:674
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
static StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:374
TargetInstrInfo - Interface to description of machine instruction set.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
std::vector< ArgListEntry > ArgListTy
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:33
@ COND_SH
Unsigned same or higher.
Definition: AVRInstrInfo.h:38
@ COND_GE
Greater than or equal.
Definition: AVRInstrInfo.h:36
@ COND_MI
Minus.
Definition: AVRInstrInfo.h:40
@ COND_LO
Unsigned lower.
Definition: AVRInstrInfo.h:39
@ COND_LT
Less than.
Definition: AVRInstrInfo.h:37
@ COND_PL
Plus.
Definition: AVRInstrInfo.h:41
@ COND_EQ
Equal.
Definition: AVRInstrInfo.h:34
@ COND_NE
Not equal.
Definition: AVRInstrInfo.h:35
@ ASRWN
Word arithmetic shift right N bits.
@ RET_GLUE
Return from subroutine.
@ SWAP
Swap Rd[7:4] <-> Rd[3:0].
@ RETI_GLUE
Return from ISR.
@ LSLW
Wide logical shift left.
@ ROLLOOP
A loop of single left bit rotate instructions.
@ ASRLO
Lower 8-bit of word arithmetic shift right.
@ ASRLOOP
A loop of single arithmetic shift right instructions.
@ LSRLOOP
A loop of single logical shift right instructions.
@ ROL
Bit rotate left.
@ LSR
Logical shift right.
@ LSRLO
Lower 8-bit of word logical shift right.
@ TST
Test for zero or minus instruction.
@ LSRBN
Byte logical shift right N bits.
@ ASRW
Wide arithmetic shift right.
@ SELECT_CC
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
@ CMPC
Compare with carry instruction.
@ LSLWN
Word logical shift left N bits.
@ RORLOOP
A loop of single right bit rotate instructions.
@ CMP
Compare instruction.
@ ASRBN
Byte arithmetic shift right N bits.
@ ROR
Bit rotate right.
@ CALL
Represents an abstract call instruction, which includes a bunch of information.
@ ASR
Arithmetic shift right.
@ LSRW
Wide logical shift right.
@ LSL
Logical shift left.
@ LSLBN
Byte logical shift left N bits.
@ LSLHI
Higher 8-bit of word logical shift left.
@ LSRWN
Word logical shift right N bits.
@ WRAPPER
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
@ LSLLOOP
A loop of single logical shift left instructions.
@ BRCOND
AVR conditional branches.
bool isProgramMemoryAccess(MemSDNode const *N)
Definition: AVR.h:74
@ ProgramMemory
Definition: AVR.h:44
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:119
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ AVR_BUILTIN
Used for special AVR rtlib functions which have an "optimized" convention to preserve registers.
Definition: CallingConv.h:180
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:750
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1121
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1117
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1258
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:714
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1150
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1260
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1261
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:780
@ GlobalAddress
Definition: ISDOpcodes.h:78
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:900
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:229
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:774
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1072
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1259
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:1051
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:727
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
Definition: ISDOpcodes.h:222
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1146
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:71
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:651
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:705
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:777
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:742
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1237
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1262
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:1036
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:795
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:680
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1251
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1089
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:783
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1141
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:1065
@ BlockAddress
Definition: ISDOpcodes.h:84
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:763
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
@ AssertZext
Definition: ISDOpcodes.h:62
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1452
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1503
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
@ Undef
Value of the register doesn't matter.
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:48
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
static void analyzeReturnValues(const SmallVectorImpl< ArgT > &Args, CCState &CCInfo, bool Tiny)
Analyze incoming and outgoing value of returning from a function.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static const MCPhysReg RegList16Tiny[]
static const MCPhysReg RegList8Tiny[]
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool Tiny)
Analyze incoming and outgoing function arguments.
static const MCPhysReg RegList16AVR[]
static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl< ArgT > &Args)
Count the total number of bytes needed to pass or return these arguments.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
DWARFExpression::Operation Op
static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC)
IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
static bool isCopyMulResult(MachineBasicBlock::iterator const &I)
static void insertMultibyteShift(MachineInstr &MI, MachineBasicBlock *BB, MutableArrayRef< std::pair< Register, int > > Regs, ISD::NodeType Opc, int64_t ShiftAmt)
static const MCPhysReg RegList8AVR[]
Registers for calling conventions, ordered in reverse as required by ABI.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:860
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:351
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:299
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:160
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:194
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
This contains information for each constraint that we are lowering.
This structure contains all information that is necessary for lowering calls.