LLVM 17.0.0git
AVRISelLowering.cpp
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1//===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AVR uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AVRISelLowering.h"
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/STLExtras.h"
25#include "llvm/IR/Function.h"
27
28#include "AVR.h"
30#include "AVRSubtarget.h"
31#include "AVRTargetMachine.h"
33
34namespace llvm {
35
37 const AVRSubtarget &STI)
38 : TargetLowering(TM), Subtarget(STI) {
39 // Set up the register classes.
40 addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
41 addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
42
43 // Compute derived properties from the register classes.
45
51
54
59
61
62 for (MVT VT : MVT::integer_valuetypes()) {
63 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
66 }
67 }
68
70
71 for (MVT VT : MVT::integer_valuetypes()) {
76 }
77
78 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
79 // revert into a sub since we don't have an add with immediate instruction.
82
83 // our shift instructions are only able to shift 1 bit at a time, so handle
84 // this in a custom way.
97
102
108
119
121
122 // Add support for postincrement and predecrement load/stores.
131
133
138
139 // Atomic operations which must be lowered to rtlib calls
140 for (MVT VT : MVT::integer_valuetypes()) {
148 }
149
150 // Division/remainder
159
160 // Make division and modulus custom
167
168 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
171
172 // Expand 16 bit multiplications.
175
176 // Expand multiplications to libcalls when there is
177 // no hardware MUL.
181 }
182
183 for (MVT VT : MVT::integer_valuetypes()) {
186 }
187
188 for (MVT VT : MVT::integer_valuetypes()) {
192 }
193
194 for (MVT VT : MVT::integer_valuetypes()) {
196 // TODO: The generated code is pretty poor. Investigate using the
197 // same "shift and subtract with carry" trick that we do for
198 // extending 8-bit to 16-bit. This may require infrastructure
199 // improvements in how we treat 16-bit "registers" to be feasible.
200 }
201
202 // Division rtlib functions (not supported), use divmod functions instead
203 setLibcallName(RTLIB::SDIV_I8, nullptr);
204 setLibcallName(RTLIB::SDIV_I16, nullptr);
205 setLibcallName(RTLIB::SDIV_I32, nullptr);
206 setLibcallName(RTLIB::UDIV_I8, nullptr);
207 setLibcallName(RTLIB::UDIV_I16, nullptr);
208 setLibcallName(RTLIB::UDIV_I32, nullptr);
209
210 // Modulus rtlib functions (not supported), use divmod functions instead
211 setLibcallName(RTLIB::SREM_I8, nullptr);
212 setLibcallName(RTLIB::SREM_I16, nullptr);
213 setLibcallName(RTLIB::SREM_I32, nullptr);
214 setLibcallName(RTLIB::UREM_I8, nullptr);
215 setLibcallName(RTLIB::UREM_I16, nullptr);
216 setLibcallName(RTLIB::UREM_I32, nullptr);
217
218 // Division and modulus rtlib functions
219 setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
220 setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
221 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
222 setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
223 setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
224 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
225
226 // Several of the runtime library functions use a special calling conv
231
232 // Trigonometric rtlib functions
233 setLibcallName(RTLIB::SIN_F32, "sin");
234 setLibcallName(RTLIB::COS_F32, "cos");
235
238}
239
240const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
241#define NODE(name) \
242 case AVRISD::name: \
243 return #name
244
245 switch (Opcode) {
246 default:
247 return nullptr;
248 NODE(RET_FLAG);
249 NODE(RETI_FLAG);
250 NODE(CALL);
251 NODE(WRAPPER);
252 NODE(LSL);
253 NODE(LSLW);
254 NODE(LSR);
255 NODE(LSRW);
256 NODE(ROL);
257 NODE(ROR);
258 NODE(ASR);
259 NODE(ASRW);
260 NODE(LSLLOOP);
261 NODE(LSRLOOP);
262 NODE(ROLLOOP);
263 NODE(RORLOOP);
264 NODE(ASRLOOP);
265 NODE(BRCOND);
266 NODE(CMP);
267 NODE(CMPC);
268 NODE(TST);
269 NODE(SELECT_CC);
270#undef NODE
271 }
272}
273
275 EVT VT) const {
276 assert(!VT.isVector() && "No AVR SetCC type for vectors!");
277 return MVT::i8;
278}
279
280SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
281 unsigned Opc8;
282 const SDNode *N = Op.getNode();
283 EVT VT = Op.getValueType();
284 SDLoc dl(N);
285 assert(llvm::has_single_bit<uint32_t>(VT.getSizeInBits()) &&
286 "Expected power-of-2 shift amount");
287
288 if (VT.getSizeInBits() == 32) {
289 if (!isa<ConstantSDNode>(N->getOperand(1))) {
290 // 32-bit shifts are converted to a loop in IR.
291 // This should be unreachable.
292 report_fatal_error("Expected a constant shift amount!");
293 }
294 SDVTList ResTys = DAG.getVTList(MVT::i16, MVT::i16);
295 SDValue SrcLo =
296 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i16, Op.getOperand(0),
297 DAG.getConstant(0, dl, MVT::i16));
298 SDValue SrcHi =
299 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i16, Op.getOperand(0),
300 DAG.getConstant(1, dl, MVT::i16));
301 uint64_t ShiftAmount =
302 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
303 if (ShiftAmount == 16) {
304 // Special case these two operations because they appear to be used by the
305 // generic codegen parts to lower 32-bit numbers.
306 // TODO: perhaps we can lower shift amounts bigger than 16 to a 16-bit
307 // shift of a part of the 32-bit value?
308 switch (Op.getOpcode()) {
309 case ISD::SHL: {
310 SDValue Zero = DAG.getConstant(0, dl, MVT::i16);
311 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i32, Zero, SrcLo);
312 }
313 case ISD::SRL: {
314 SDValue Zero = DAG.getConstant(0, dl, MVT::i16);
315 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i32, SrcHi, Zero);
316 }
317 }
318 }
319 SDValue Cnt = DAG.getTargetConstant(ShiftAmount, dl, MVT::i8);
320 unsigned Opc;
321 switch (Op.getOpcode()) {
322 default:
323 llvm_unreachable("Invalid 32-bit shift opcode!");
324 case ISD::SHL:
325 Opc = AVRISD::LSLW;
326 break;
327 case ISD::SRL:
328 Opc = AVRISD::LSRW;
329 break;
330 case ISD::SRA:
331 Opc = AVRISD::ASRW;
332 break;
333 }
334 SDValue Result = DAG.getNode(Opc, dl, ResTys, SrcLo, SrcHi, Cnt);
335 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i32, Result.getValue(0),
336 Result.getValue(1));
337 }
338
339 // Expand non-constant shifts to loops.
340 if (!isa<ConstantSDNode>(N->getOperand(1))) {
341 switch (Op.getOpcode()) {
342 default:
343 llvm_unreachable("Invalid shift opcode!");
344 case ISD::SHL:
345 return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
346 N->getOperand(1));
347 case ISD::SRL:
348 return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
349 N->getOperand(1));
350 case ISD::ROTL: {
351 SDValue Amt = N->getOperand(1);
352 EVT AmtVT = Amt.getValueType();
353 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
354 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
355 return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
356 }
357 case ISD::ROTR: {
358 SDValue Amt = N->getOperand(1);
359 EVT AmtVT = Amt.getValueType();
360 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
361 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
362 return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
363 }
364 case ISD::SRA:
365 return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
366 N->getOperand(1));
367 }
368 }
369
370 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
371 SDValue Victim = N->getOperand(0);
372
373 switch (Op.getOpcode()) {
374 case ISD::SRA:
375 Opc8 = AVRISD::ASR;
376 break;
377 case ISD::ROTL:
378 Opc8 = AVRISD::ROL;
379 ShiftAmount = ShiftAmount % VT.getSizeInBits();
380 break;
381 case ISD::ROTR:
382 Opc8 = AVRISD::ROR;
383 ShiftAmount = ShiftAmount % VT.getSizeInBits();
384 break;
385 case ISD::SRL:
386 Opc8 = AVRISD::LSR;
387 break;
388 case ISD::SHL:
389 Opc8 = AVRISD::LSL;
390 break;
391 default:
392 llvm_unreachable("Invalid shift opcode");
393 }
394
395 // Optimize int8/int16 shifts.
396 if (VT.getSizeInBits() == 8) {
397 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
398 // Optimize LSL when 4 <= ShiftAmount <= 6.
399 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
400 Victim =
401 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT));
402 ShiftAmount -= 4;
403 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
404 ShiftAmount < 7) {
405 // Optimize LSR when 4 <= ShiftAmount <= 6.
406 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
407 Victim =
408 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT));
409 ShiftAmount -= 4;
410 } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
411 // Optimize LSL when ShiftAmount == 7.
412 Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim,
413 DAG.getConstant(7, dl, VT));
414 ShiftAmount = 0;
415 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
416 // Optimize LSR when ShiftAmount == 7.
417 Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim,
418 DAG.getConstant(7, dl, VT));
419 ShiftAmount = 0;
420 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) {
421 // Optimize ASR when ShiftAmount == 6.
422 Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
423 DAG.getConstant(6, dl, VT));
424 ShiftAmount = 0;
425 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
426 // Optimize ASR when ShiftAmount == 7.
427 Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
428 DAG.getConstant(7, dl, VT));
429 ShiftAmount = 0;
430 }
431 } else if (VT.getSizeInBits() == 16) {
432 if (Op.getOpcode() == ISD::SRA)
433 // Special optimization for int16 arithmetic right shift.
434 switch (ShiftAmount) {
435 case 15:
436 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
437 DAG.getConstant(15, dl, VT));
438 ShiftAmount = 0;
439 break;
440 case 14:
441 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
442 DAG.getConstant(14, dl, VT));
443 ShiftAmount = 0;
444 break;
445 case 7:
446 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
447 DAG.getConstant(7, dl, VT));
448 ShiftAmount = 0;
449 break;
450 default:
451 break;
452 }
453 if (4 <= ShiftAmount && ShiftAmount < 8)
454 switch (Op.getOpcode()) {
455 case ISD::SHL:
456 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
457 DAG.getConstant(4, dl, VT));
458 ShiftAmount -= 4;
459 break;
460 case ISD::SRL:
461 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
462 DAG.getConstant(4, dl, VT));
463 ShiftAmount -= 4;
464 break;
465 default:
466 break;
467 }
468 else if (8 <= ShiftAmount && ShiftAmount < 12)
469 switch (Op.getOpcode()) {
470 case ISD::SHL:
471 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
472 DAG.getConstant(8, dl, VT));
473 ShiftAmount -= 8;
474 // Only operate on the higher byte for remaining shift bits.
475 Opc8 = AVRISD::LSLHI;
476 break;
477 case ISD::SRL:
478 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
479 DAG.getConstant(8, dl, VT));
480 ShiftAmount -= 8;
481 // Only operate on the lower byte for remaining shift bits.
482 Opc8 = AVRISD::LSRLO;
483 break;
484 case ISD::SRA:
485 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
486 DAG.getConstant(8, dl, VT));
487 ShiftAmount -= 8;
488 // Only operate on the lower byte for remaining shift bits.
489 Opc8 = AVRISD::ASRLO;
490 break;
491 default:
492 break;
493 }
494 else if (12 <= ShiftAmount)
495 switch (Op.getOpcode()) {
496 case ISD::SHL:
497 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim,
498 DAG.getConstant(12, dl, VT));
499 ShiftAmount -= 12;
500 // Only operate on the higher byte for remaining shift bits.
501 Opc8 = AVRISD::LSLHI;
502 break;
503 case ISD::SRL:
504 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim,
505 DAG.getConstant(12, dl, VT));
506 ShiftAmount -= 12;
507 // Only operate on the lower byte for remaining shift bits.
508 Opc8 = AVRISD::LSRLO;
509 break;
510 case ISD::SRA:
511 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim,
512 DAG.getConstant(8, dl, VT));
513 ShiftAmount -= 8;
514 // Only operate on the lower byte for remaining shift bits.
515 Opc8 = AVRISD::ASRLO;
516 break;
517 default:
518 break;
519 }
520 }
521
522 while (ShiftAmount--) {
523 Victim = DAG.getNode(Opc8, dl, VT, Victim);
524 }
525
526 return Victim;
527}
528
529SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
530 unsigned Opcode = Op->getOpcode();
531 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
532 "Invalid opcode for Div/Rem lowering");
533 bool IsSigned = (Opcode == ISD::SDIVREM);
534 EVT VT = Op->getValueType(0);
535 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
536
538 switch (VT.getSimpleVT().SimpleTy) {
539 default:
540 llvm_unreachable("Unexpected request for libcall!");
541 case MVT::i8:
542 LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
543 break;
544 case MVT::i16:
545 LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
546 break;
547 case MVT::i32:
548 LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
549 break;
550 }
551
552 SDValue InChain = DAG.getEntryNode();
553
555 TargetLowering::ArgListEntry Entry;
556 for (SDValue const &Value : Op->op_values()) {
557 Entry.Node = Value;
558 Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
559 Entry.IsSExt = IsSigned;
560 Entry.IsZExt = !IsSigned;
561 Args.push_back(Entry);
562 }
563
564 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
565 getPointerTy(DAG.getDataLayout()));
566
567 Type *RetTy = (Type *)StructType::get(Ty, Ty);
568
569 SDLoc dl(Op);
570 TargetLowering::CallLoweringInfo CLI(DAG);
571 CLI.setDebugLoc(dl)
572 .setChain(InChain)
573 .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
574 .setInRegister()
575 .setSExtResult(IsSigned)
576 .setZExtResult(!IsSigned);
577
578 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
579 return CallInfo.first;
580}
581
582SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
583 SelectionDAG &DAG) const {
584 auto DL = DAG.getDataLayout();
585
586 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
587 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
588
589 // Create the TargetGlobalAddress node, folding in the constant offset.
590 SDValue Result =
591 DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
592 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
593}
594
595SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
596 SelectionDAG &DAG) const {
597 auto DL = DAG.getDataLayout();
598 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
599
600 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
601
602 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
603}
604
605/// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
607 switch (CC) {
608 default:
609 llvm_unreachable("Unknown condition code!");
610 case ISD::SETEQ:
611 return AVRCC::COND_EQ;
612 case ISD::SETNE:
613 return AVRCC::COND_NE;
614 case ISD::SETGE:
615 return AVRCC::COND_GE;
616 case ISD::SETLT:
617 return AVRCC::COND_LT;
618 case ISD::SETUGE:
619 return AVRCC::COND_SH;
620 case ISD::SETULT:
621 return AVRCC::COND_LO;
622 }
623}
624
625/// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
626SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
627 SelectionDAG &DAG, SDLoc DL) const {
628 assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
629 "LHS and RHS have different types");
630 assert(((LHS.getSimpleValueType() == MVT::i16) ||
631 (LHS.getSimpleValueType() == MVT::i8)) &&
632 "invalid comparison type");
633
634 SDValue Cmp;
635
636 if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) {
637 uint64_t Imm = cast<ConstantSDNode>(RHS)->getZExtValue();
638 // Generate a CPI/CPC pair if RHS is a 16-bit constant. Use the zero
639 // register for the constant RHS if its lower or higher byte is zero.
640 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
641 DAG.getIntPtrConstant(0, DL));
642 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
643 DAG.getIntPtrConstant(1, DL));
644 SDValue RHSlo = (Imm & 0xff) == 0
645 ? DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8)
646 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
647 DAG.getIntPtrConstant(0, DL));
648 SDValue RHShi = (Imm & 0xff00) == 0
649 ? DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8)
650 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
651 DAG.getIntPtrConstant(1, DL));
652 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
653 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
654 } else if (RHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(LHS)) {
655 // Generate a CPI/CPC pair if LHS is a 16-bit constant. Use the zero
656 // register for the constant LHS if its lower or higher byte is zero.
657 uint64_t Imm = cast<ConstantSDNode>(LHS)->getZExtValue();
658 SDValue LHSlo = (Imm & 0xff) == 0
659 ? DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8)
660 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
661 DAG.getIntPtrConstant(0, DL));
662 SDValue LHShi = (Imm & 0xff00) == 0
663 ? DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8)
664 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS,
665 DAG.getIntPtrConstant(1, DL));
666 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
667 DAG.getIntPtrConstant(0, DL));
668 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS,
669 DAG.getIntPtrConstant(1, DL));
670 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
671 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
672 } else {
673 // Generate ordinary 16-bit comparison.
674 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
675 }
676
677 return Cmp;
678}
679
680/// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
681/// the given operands.
682SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
683 SDValue &AVRcc, SelectionDAG &DAG,
684 SDLoc DL) const {
685 SDValue Cmp;
686 EVT VT = LHS.getValueType();
687 bool UseTest = false;
688
689 switch (CC) {
690 default:
691 break;
692 case ISD::SETLE: {
693 // Swap operands and reverse the branching condition.
694 std::swap(LHS, RHS);
695 CC = ISD::SETGE;
696 break;
697 }
698 case ISD::SETGT: {
699 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
700 switch (C->getSExtValue()) {
701 case -1: {
702 // When doing lhs > -1 use a tst instruction on the top part of lhs
703 // and use brpl instead of using a chain of cp/cpc.
704 UseTest = true;
705 AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
706 break;
707 }
708 case 0: {
709 // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
710 // __zero_reg__ in lhs.
711 RHS = LHS;
712 LHS = DAG.getConstant(0, DL, VT);
713 CC = ISD::SETLT;
714 break;
715 }
716 default: {
717 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
718 // us to fold the constant into the cmp instruction.
719 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
720 CC = ISD::SETGE;
721 break;
722 }
723 }
724 break;
725 }
726 // Swap operands and reverse the branching condition.
727 std::swap(LHS, RHS);
728 CC = ISD::SETLT;
729 break;
730 }
731 case ISD::SETLT: {
732 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
733 switch (C->getSExtValue()) {
734 case 1: {
735 // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
736 // __zero_reg__ in lhs.
737 RHS = LHS;
738 LHS = DAG.getConstant(0, DL, VT);
739 CC = ISD::SETGE;
740 break;
741 }
742 case 0: {
743 // When doing lhs < 0 use a tst instruction on the top part of lhs
744 // and use brmi instead of using a chain of cp/cpc.
745 UseTest = true;
746 AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
747 break;
748 }
749 }
750 }
751 break;
752 }
753 case ISD::SETULE: {
754 // Swap operands and reverse the branching condition.
755 std::swap(LHS, RHS);
756 CC = ISD::SETUGE;
757 break;
758 }
759 case ISD::SETUGT: {
760 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
761 // fold the constant into the cmp instruction.
762 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
763 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
764 CC = ISD::SETUGE;
765 break;
766 }
767 // Swap operands and reverse the branching condition.
768 std::swap(LHS, RHS);
769 CC = ISD::SETULT;
770 break;
771 }
772 }
773
774 // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
775 // using the default and/or/xor expansion code which is much longer.
776 if (VT == MVT::i32) {
777 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
778 DAG.getIntPtrConstant(0, DL));
779 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
780 DAG.getIntPtrConstant(1, DL));
781 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
782 DAG.getIntPtrConstant(0, DL));
783 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
784 DAG.getIntPtrConstant(1, DL));
785
786 if (UseTest) {
787 // When using tst we only care about the highest part.
788 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
789 DAG.getIntPtrConstant(1, DL));
790 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
791 } else {
792 Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL);
793 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
794 }
795 } else if (VT == MVT::i64) {
796 SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
797 DAG.getIntPtrConstant(0, DL));
798 SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
799 DAG.getIntPtrConstant(1, DL));
800
801 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
802 DAG.getIntPtrConstant(0, DL));
803 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
804 DAG.getIntPtrConstant(1, DL));
805 SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
806 DAG.getIntPtrConstant(0, DL));
807 SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
808 DAG.getIntPtrConstant(1, DL));
809
810 SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
811 DAG.getIntPtrConstant(0, DL));
812 SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
813 DAG.getIntPtrConstant(1, DL));
814
815 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
816 DAG.getIntPtrConstant(0, DL));
817 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
818 DAG.getIntPtrConstant(1, DL));
819 SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
820 DAG.getIntPtrConstant(0, DL));
821 SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
822 DAG.getIntPtrConstant(1, DL));
823
824 if (UseTest) {
825 // When using tst we only care about the highest part.
826 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
827 DAG.getIntPtrConstant(1, DL));
828 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
829 } else {
830 Cmp = getAVRCmp(LHS0, RHS0, DAG, DL);
831 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
832 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
833 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
834 }
835 } else if (VT == MVT::i8 || VT == MVT::i16) {
836 if (UseTest) {
837 // When using tst we only care about the highest part.
838 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
839 (VT == MVT::i8)
840 ? LHS
841 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
842 LHS, DAG.getIntPtrConstant(1, DL)));
843 } else {
844 Cmp = getAVRCmp(LHS, RHS, DAG, DL);
845 }
846 } else {
847 llvm_unreachable("Invalid comparison size");
848 }
849
850 // When using a test instruction AVRcc is already set.
851 if (!UseTest) {
852 AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
853 }
854
855 return Cmp;
856}
857
858SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
859 SDValue Chain = Op.getOperand(0);
860 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
861 SDValue LHS = Op.getOperand(2);
862 SDValue RHS = Op.getOperand(3);
863 SDValue Dest = Op.getOperand(4);
864 SDLoc dl(Op);
865
866 SDValue TargetCC;
867 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
868
869 return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
870 Cmp);
871}
872
873SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
874 SDValue LHS = Op.getOperand(0);
875 SDValue RHS = Op.getOperand(1);
876 SDValue TrueV = Op.getOperand(2);
877 SDValue FalseV = Op.getOperand(3);
878 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
879 SDLoc dl(Op);
880
881 SDValue TargetCC;
882 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
883
884 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
885 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
886
887 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
888}
889
890SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
891 SDValue LHS = Op.getOperand(0);
892 SDValue RHS = Op.getOperand(1);
893 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
894 SDLoc DL(Op);
895
896 SDValue TargetCC;
897 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
898
899 SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
900 SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
901 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
902 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
903
904 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
905}
906
907SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
908 const MachineFunction &MF = DAG.getMachineFunction();
909 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
910 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
911 auto DL = DAG.getDataLayout();
912 SDLoc dl(Op);
913
914 // Vastart just stores the address of the VarArgsFrameIndex slot into the
915 // memory location argument.
916 SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
917
918 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
919 MachinePointerInfo(SV));
920}
921
922// Modify the existing ISD::INLINEASM node to add the implicit zero register.
923SDValue AVRTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
924 SDValue ZeroReg = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8);
925 if (Op.getOperand(Op.getNumOperands() - 1) == ZeroReg ||
926 Op.getOperand(Op.getNumOperands() - 2) == ZeroReg) {
927 // Zero register has already been added. Don't add it again.
928 // If this isn't handled, we get called over and over again.
929 return Op;
930 }
931
932 // Get a list of operands to the new INLINEASM node. This is mostly a copy,
933 // with some edits.
934 // Add the following operands at the end (but before the glue node, if it's
935 // there):
936 // - The flags of the implicit zero register operand.
937 // - The implicit zero register operand itself.
938 SDLoc dl(Op);
939 SmallVector<SDValue, 8> Ops;
940 SDNode *N = Op.getNode();
941 SDValue Glue;
942 for (unsigned I = 0; I < N->getNumOperands(); I++) {
943 SDValue Operand = N->getOperand(I);
944 if (Operand.getValueType() == MVT::Glue) {
945 // The glue operand always needs to be at the end, so we need to treat it
946 // specially.
947 Glue = Operand;
948 } else {
949 Ops.push_back(Operand);
950 }
951 }
953 Ops.push_back(DAG.getTargetConstant(Flags, dl, MVT::i32));
954 Ops.push_back(ZeroReg);
955 if (Glue) {
956 Ops.push_back(Glue);
957 }
958
959 // Replace the current INLINEASM node with a new one that has the zero
960 // register as implicit parameter.
961 SDValue New = DAG.getNode(N->getOpcode(), dl, N->getVTList(), Ops);
962 DAG.ReplaceAllUsesOfValueWith(Op, New);
963 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), New.getValue(1));
964
965 return New;
966}
967
969 switch (Op.getOpcode()) {
970 default:
971 llvm_unreachable("Don't know how to custom lower this!");
972 case ISD::SHL:
973 case ISD::SRA:
974 case ISD::SRL:
975 case ISD::ROTL:
976 case ISD::ROTR:
977 return LowerShifts(Op, DAG);
979 return LowerGlobalAddress(Op, DAG);
981 return LowerBlockAddress(Op, DAG);
982 case ISD::BR_CC:
983 return LowerBR_CC(Op, DAG);
984 case ISD::SELECT_CC:
985 return LowerSELECT_CC(Op, DAG);
986 case ISD::SETCC:
987 return LowerSETCC(Op, DAG);
988 case ISD::VASTART:
989 return LowerVASTART(Op, DAG);
990 case ISD::SDIVREM:
991 case ISD::UDIVREM:
992 return LowerDivRem(Op, DAG);
993 case ISD::INLINEASM:
994 return LowerINLINEASM(Op, DAG);
995 }
996
997 return SDValue();
998}
999
1000/// Replace a node with an illegal result type
1001/// with a new node built out of custom code.
1004 SelectionDAG &DAG) const {
1005 SDLoc DL(N);
1006
1007 switch (N->getOpcode()) {
1008 case ISD::ADD: {
1009 // Convert add (x, imm) into sub (x, -imm).
1010 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1011 SDValue Sub = DAG.getNode(
1012 ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
1013 DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
1014 Results.push_back(Sub);
1015 }
1016 break;
1017 }
1018 default: {
1019 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1020
1021 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1022 Results.push_back(Res.getValue(I));
1023
1024 break;
1025 }
1026 }
1027}
1028
1029/// Return true if the addressing mode represented
1030/// by AM is legal for this target, for a load/store of the specified type.
1032 const AddrMode &AM, Type *Ty,
1033 unsigned AS,
1034 Instruction *I) const {
1035 int64_t Offs = AM.BaseOffs;
1036
1037 // Allow absolute addresses.
1038 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
1039 return true;
1040 }
1041
1042 // Flash memory instructions only allow zero offsets.
1043 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
1044 return false;
1045 }
1046
1047 // Allow reg+<6bit> offset.
1048 if (Offs < 0)
1049 Offs = -Offs;
1050 if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 &&
1051 isUInt<6>(Offs)) {
1052 return true;
1053 }
1054
1055 return false;
1056}
1057
1058/// Returns true by value, base pointer and
1059/// offset pointer and addressing mode by reference if the node's address
1060/// can be legally represented as pre-indexed load / store address.
1062 SDValue &Offset,
1064 SelectionDAG &DAG) const {
1065 EVT VT;
1066 const SDNode *Op;
1067 SDLoc DL(N);
1068
1069 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1070 VT = LD->getMemoryVT();
1071 Op = LD->getBasePtr().getNode();
1072 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1073 return false;
1075 return false;
1076 }
1077 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1078 VT = ST->getMemoryVT();
1079 Op = ST->getBasePtr().getNode();
1081 return false;
1082 }
1083 } else {
1084 return false;
1085 }
1086
1087 if (VT != MVT::i8 && VT != MVT::i16) {
1088 return false;
1089 }
1090
1091 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1092 return false;
1093 }
1094
1095 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1096 int RHSC = RHS->getSExtValue();
1097 if (Op->getOpcode() == ISD::SUB)
1098 RHSC = -RHSC;
1099
1100 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
1101 return false;
1102 }
1103
1104 Base = Op->getOperand(0);
1105 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
1106 AM = ISD::PRE_DEC;
1107
1108 return true;
1109 }
1110
1111 return false;
1112}
1113
1114/// Returns true by value, base pointer and
1115/// offset pointer and addressing mode by reference if this node can be
1116/// combined with a load / store to form a post-indexed load / store.
1118 SDValue &Base,
1119 SDValue &Offset,
1121 SelectionDAG &DAG) const {
1122 EVT VT;
1123 SDLoc DL(N);
1124
1125 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1126 VT = LD->getMemoryVT();
1127 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1128 return false;
1129 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1130 VT = ST->getMemoryVT();
1132 return false;
1133 }
1134 } else {
1135 return false;
1136 }
1137
1138 if (VT != MVT::i8 && VT != MVT::i16) {
1139 return false;
1140 }
1141
1142 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1143 return false;
1144 }
1145
1146 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1147 int RHSC = RHS->getSExtValue();
1148 if (Op->getOpcode() == ISD::SUB)
1149 RHSC = -RHSC;
1150 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
1151 return false;
1152 }
1153
1154 Base = Op->getOperand(0);
1155 Offset = DAG.getConstant(RHSC, DL, MVT::i8);
1156 AM = ISD::POST_INC;
1157
1158 return true;
1159 }
1160
1161 return false;
1162}
1163
1165 const GlobalAddressSDNode *GA) const {
1166 return true;
1167}
1168
1169//===----------------------------------------------------------------------===//
1170// Formal Arguments Calling Convention Implementation
1171//===----------------------------------------------------------------------===//
1172
1173#include "AVRGenCallingConv.inc"
1174
1175/// Registers for calling conventions, ordered in reverse as required by ABI.
1176/// Both arrays must be of the same length.
1177static const MCPhysReg RegList8AVR[] = {
1178 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1179 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
1180 AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
1181static const MCPhysReg RegList8Tiny[] = {AVR::R25, AVR::R24, AVR::R23,
1182 AVR::R22, AVR::R21, AVR::R20};
1183static const MCPhysReg RegList16AVR[] = {
1184 AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
1185 AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
1186 AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
1187 AVR::R11R10, AVR::R10R9, AVR::R9R8};
1188static const MCPhysReg RegList16Tiny[] = {AVR::R26R25, AVR::R25R24,
1189 AVR::R24R23, AVR::R23R22,
1190 AVR::R22R21, AVR::R21R20};
1191
1192static_assert(std::size(RegList8AVR) == std::size(RegList16AVR),
1193 "8-bit and 16-bit register arrays must be of equal length");
1194static_assert(std::size(RegList8Tiny) == std::size(RegList16Tiny),
1195 "8-bit and 16-bit register arrays must be of equal length");
1196
1197/// Analyze incoming and outgoing function arguments. We need custom C++ code
1198/// to handle special constraints in the ABI.
1199/// In addition, all pieces of a certain argument have to be passed either
1200/// using registers or the stack but never mixing both.
1201template <typename ArgT>
1203 const Function *F, const DataLayout *TD,
1204 const SmallVectorImpl<ArgT> &Args,
1206 CCState &CCInfo, bool Tiny) {
1207 // Choose the proper register list for argument passing according to the ABI.
1208 ArrayRef<MCPhysReg> RegList8;
1209 ArrayRef<MCPhysReg> RegList16;
1210 if (Tiny) {
1211 RegList8 = ArrayRef(RegList8Tiny, std::size(RegList8Tiny));
1212 RegList16 = ArrayRef(RegList16Tiny, std::size(RegList16Tiny));
1213 } else {
1214 RegList8 = ArrayRef(RegList8AVR, std::size(RegList8AVR));
1215 RegList16 = ArrayRef(RegList16AVR, std::size(RegList16AVR));
1216 }
1217
1218 unsigned NumArgs = Args.size();
1219 // This is the index of the last used register, in RegList*.
1220 // -1 means R26 (R26 is never actually used in CC).
1221 int RegLastIdx = -1;
1222 // Once a value is passed to the stack it will always be used
1223 bool UseStack = false;
1224 for (unsigned i = 0; i != NumArgs;) {
1225 MVT VT = Args[i].VT;
1226 // We have to count the number of bytes for each function argument, that is
1227 // those Args with the same OrigArgIndex. This is important in case the
1228 // function takes an aggregate type.
1229 // Current argument will be between [i..j).
1230 unsigned ArgIndex = Args[i].OrigArgIndex;
1231 unsigned TotalBytes = VT.getStoreSize();
1232 unsigned j = i + 1;
1233 for (; j != NumArgs; ++j) {
1234 if (Args[j].OrigArgIndex != ArgIndex)
1235 break;
1236 TotalBytes += Args[j].VT.getStoreSize();
1237 }
1238 // Round up to even number of bytes.
1239 TotalBytes = alignTo(TotalBytes, 2);
1240 // Skip zero sized arguments
1241 if (TotalBytes == 0)
1242 continue;
1243 // The index of the first register to be used
1244 unsigned RegIdx = RegLastIdx + TotalBytes;
1245 RegLastIdx = RegIdx;
1246 // If there are not enough registers, use the stack
1247 if (RegIdx >= RegList8.size()) {
1248 UseStack = true;
1249 }
1250 for (; i != j; ++i) {
1251 MVT VT = Args[i].VT;
1252
1253 if (UseStack) {
1254 auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
1255 unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
1256 TD->getABITypeAlign(evt));
1257 CCInfo.addLoc(
1259 } else {
1260 unsigned Reg;
1261 if (VT == MVT::i8) {
1262 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1263 } else if (VT == MVT::i16) {
1264 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1265 } else {
1267 "calling convention can only manage i8 and i16 types");
1268 }
1269 assert(Reg && "register not available in calling convention");
1270 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1271 // Registers inside a particular argument are sorted in increasing order
1272 // (remember the array is reversed).
1273 RegIdx -= VT.getStoreSize();
1274 }
1275 }
1276 }
1277}
1278
1279/// Count the total number of bytes needed to pass or return these arguments.
1280template <typename ArgT>
1281static unsigned
1283 unsigned TotalBytes = 0;
1284
1285 for (const ArgT &Arg : Args) {
1286 TotalBytes += Arg.VT.getStoreSize();
1287 }
1288 return TotalBytes;
1289}
1290
1291/// Analyze incoming and outgoing value of returning from a function.
1292/// The algorithm is similar to analyzeArguments, but there can only be
1293/// one value, possibly an aggregate, and it is limited to 8 bytes.
1294template <typename ArgT>
1296 CCState &CCInfo, bool Tiny) {
1297 unsigned NumArgs = Args.size();
1298 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
1299 // CanLowerReturn() guarantees this assertion.
1300 if (Tiny)
1301 assert(TotalBytes <= 4 &&
1302 "return values greater than 4 bytes cannot be lowered on AVRTiny");
1303 else
1304 assert(TotalBytes <= 8 &&
1305 "return values greater than 8 bytes cannot be lowered on AVR");
1306
1307 // Choose the proper register list for argument passing according to the ABI.
1308 ArrayRef<MCPhysReg> RegList8;
1309 ArrayRef<MCPhysReg> RegList16;
1310 if (Tiny) {
1311 RegList8 = ArrayRef(RegList8Tiny, std::size(RegList8Tiny));
1312 RegList16 = ArrayRef(RegList16Tiny, std::size(RegList16Tiny));
1313 } else {
1314 RegList8 = ArrayRef(RegList8AVR, std::size(RegList8AVR));
1315 RegList16 = ArrayRef(RegList16AVR, std::size(RegList16AVR));
1316 }
1317
1318 // GCC-ABI says that the size is rounded up to the next even number,
1319 // but actually once it is more than 4 it will always round up to 8.
1320 if (TotalBytes > 4) {
1321 TotalBytes = 8;
1322 } else {
1323 TotalBytes = alignTo(TotalBytes, 2);
1324 }
1325
1326 // The index of the first register to use.
1327 int RegIdx = TotalBytes - 1;
1328 for (unsigned i = 0; i != NumArgs; ++i) {
1329 MVT VT = Args[i].VT;
1330 unsigned Reg;
1331 if (VT == MVT::i8) {
1332 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1333 } else if (VT == MVT::i16) {
1334 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1335 } else {
1336 llvm_unreachable("calling convention can only manage i8 and i16 types");
1337 }
1338 assert(Reg && "register not available in calling convention");
1339 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
1340 // Registers sort in increasing order
1341 RegIdx -= VT.getStoreSize();
1342 }
1343}
1344
1345SDValue AVRTargetLowering::LowerFormalArguments(
1346 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1347 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1348 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1349 MachineFunction &MF = DAG.getMachineFunction();
1350 MachineFrameInfo &MFI = MF.getFrameInfo();
1351 auto DL = DAG.getDataLayout();
1352
1353 // Assign locations to all of the incoming arguments.
1354 SmallVector<CCValAssign, 16> ArgLocs;
1355 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1356 *DAG.getContext());
1357
1358 // Variadic functions do not need all the analysis below.
1359 if (isVarArg) {
1360 CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
1361 } else {
1362 analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo,
1364 }
1365
1366 SDValue ArgValue;
1367 for (CCValAssign &VA : ArgLocs) {
1368
1369 // Arguments stored on registers.
1370 if (VA.isRegLoc()) {
1371 EVT RegVT = VA.getLocVT();
1372 const TargetRegisterClass *RC;
1373 if (RegVT == MVT::i8) {
1374 RC = &AVR::GPR8RegClass;
1375 } else if (RegVT == MVT::i16) {
1376 RC = &AVR::DREGSRegClass;
1377 } else {
1378 llvm_unreachable("Unknown argument type!");
1379 }
1380
1381 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
1382 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1383
1384 // :NOTE: Clang should not promote any i8 into i16 but for safety the
1385 // following code will handle zexts or sexts generated by other
1386 // front ends. Otherwise:
1387 // If this is an 8 bit value, it is really passed promoted
1388 // to 16 bits. Insert an assert[sz]ext to capture this, then
1389 // truncate to the right size.
1390 switch (VA.getLocInfo()) {
1391 default:
1392 llvm_unreachable("Unknown loc info!");
1393 case CCValAssign::Full:
1394 break;
1395 case CCValAssign::BCvt:
1396 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1397 break;
1398 case CCValAssign::SExt:
1399 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1400 DAG.getValueType(VA.getValVT()));
1401 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1402 break;
1403 case CCValAssign::ZExt:
1404 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1405 DAG.getValueType(VA.getValVT()));
1406 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1407 break;
1408 }
1409
1410 InVals.push_back(ArgValue);
1411 } else {
1412 // Only arguments passed on the stack should make it here.
1413 assert(VA.isMemLoc());
1414
1415 EVT LocVT = VA.getLocVT();
1416
1417 // Create the frame index object for this incoming parameter.
1418 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1419 VA.getLocMemOffset(), true);
1420
1421 // Create the SelectionDAG nodes corresponding to a load
1422 // from this parameter.
1423 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1424 InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1426 }
1427 }
1428
1429 // If the function takes variable number of arguments, make a frame index for
1430 // the start of the first vararg value... for expansion of llvm.va_start.
1431 if (isVarArg) {
1432 unsigned StackSize = CCInfo.getNextStackOffset();
1433 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1434
1435 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1436 }
1437
1438 return Chain;
1439}
1440
1441//===----------------------------------------------------------------------===//
1442// Call Calling Convention Implementation
1443//===----------------------------------------------------------------------===//
1444
1445SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1446 SmallVectorImpl<SDValue> &InVals) const {
1447 SelectionDAG &DAG = CLI.DAG;
1448 SDLoc &DL = CLI.DL;
1449 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1450 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1451 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1452 SDValue Chain = CLI.Chain;
1453 SDValue Callee = CLI.Callee;
1454 bool &isTailCall = CLI.IsTailCall;
1455 CallingConv::ID CallConv = CLI.CallConv;
1456 bool isVarArg = CLI.IsVarArg;
1457
1458 MachineFunction &MF = DAG.getMachineFunction();
1459
1460 // AVR does not yet support tail call optimization.
1461 isTailCall = false;
1462
1463 // Analyze operands of the call, assigning locations to each operand.
1464 SmallVector<CCValAssign, 16> ArgLocs;
1465 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1466 *DAG.getContext());
1467
1468 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1469 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1470 // node so that legalize doesn't hack it.
1471 const Function *F = nullptr;
1472 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1473 const GlobalValue *GV = G->getGlobal();
1474 if (isa<Function>(GV))
1475 F = cast<Function>(GV);
1476 Callee =
1477 DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
1478 } else if (const ExternalSymbolSDNode *ES =
1479 dyn_cast<ExternalSymbolSDNode>(Callee)) {
1480 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1481 getPointerTy(DAG.getDataLayout()));
1482 }
1483
1484 // Variadic functions do not need all the analysis below.
1485 if (isVarArg) {
1486 CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
1487 } else {
1488 analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo,
1490 }
1491
1492 // Get a count of how many bytes are to be pushed on the stack.
1493 unsigned NumBytes = CCInfo.getNextStackOffset();
1494
1495 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
1496
1497 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1498
1499 // First, walk the register assignments, inserting copies.
1500 unsigned AI, AE;
1501 bool HasStackArgs = false;
1502 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1503 CCValAssign &VA = ArgLocs[AI];
1504 EVT RegVT = VA.getLocVT();
1505 SDValue Arg = OutVals[AI];
1506
1507 // Promote the value if needed. With Clang this should not happen.
1508 switch (VA.getLocInfo()) {
1509 default:
1510 llvm_unreachable("Unknown loc info!");
1511 case CCValAssign::Full:
1512 break;
1513 case CCValAssign::SExt:
1514 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1515 break;
1516 case CCValAssign::ZExt:
1517 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1518 break;
1519 case CCValAssign::AExt:
1520 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1521 break;
1522 case CCValAssign::BCvt:
1523 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1524 break;
1525 }
1526
1527 // Stop when we encounter a stack argument, we need to process them
1528 // in reverse order in the loop below.
1529 if (VA.isMemLoc()) {
1530 HasStackArgs = true;
1531 break;
1532 }
1533
1534 // Arguments that can be passed on registers must be kept in the RegsToPass
1535 // vector.
1536 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1537 }
1538
1539 // Second, stack arguments have to walked.
1540 // Previously this code created chained stores but those chained stores appear
1541 // to be unchained in the legalization phase. Therefore, do not attempt to
1542 // chain them here. In fact, chaining them here somehow causes the first and
1543 // second store to be reversed which is the exact opposite of the intended
1544 // effect.
1545 if (HasStackArgs) {
1546 SmallVector<SDValue, 8> MemOpChains;
1547 for (; AI != AE; AI++) {
1548 CCValAssign &VA = ArgLocs[AI];
1549 SDValue Arg = OutVals[AI];
1550
1551 assert(VA.isMemLoc());
1552
1553 // SP points to one stack slot further so add one to adjust it.
1554 SDValue PtrOff = DAG.getNode(
1555 ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1556 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1557 DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1558
1559 MemOpChains.push_back(
1560 DAG.getStore(Chain, DL, Arg, PtrOff,
1561 MachinePointerInfo::getStack(MF, VA.getLocMemOffset())));
1562 }
1563
1564 if (!MemOpChains.empty())
1565 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1566 }
1567
1568 // Build a sequence of copy-to-reg nodes chained together with token chain and
1569 // flag operands which copy the outgoing args into registers. The InFlag in
1570 // necessary since all emited instructions must be stuck together.
1571 SDValue InFlag;
1572 for (auto Reg : RegsToPass) {
1573 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1574 InFlag = Chain.getValue(1);
1575 }
1576
1577 // Returns a chain & a flag for retval copy to use.
1578 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1579 SmallVector<SDValue, 8> Ops;
1580 Ops.push_back(Chain);
1581 Ops.push_back(Callee);
1582
1583 // Add argument registers to the end of the list so that they are known live
1584 // into the call.
1585 for (auto Reg : RegsToPass) {
1586 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1587 }
1588
1589 // The zero register (usually R1) must be passed as an implicit register so
1590 // that this register is correctly zeroed in interrupts.
1591 Ops.push_back(DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8));
1592
1593 // Add a register mask operand representing the call-preserved registers.
1594 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1595 const uint32_t *Mask =
1596 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1597 assert(Mask && "Missing call preserved mask for calling convention");
1598 Ops.push_back(DAG.getRegisterMask(Mask));
1599
1600 if (InFlag.getNode()) {
1601 Ops.push_back(InFlag);
1602 }
1603
1604 Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1605 InFlag = Chain.getValue(1);
1606
1607 // Create the CALLSEQ_END node.
1608 Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, InFlag, DL);
1609
1610 if (!Ins.empty()) {
1611 InFlag = Chain.getValue(1);
1612 }
1613
1614 // Handle result values, copying them out of physregs into vregs that we
1615 // return.
1616 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1617 InVals);
1618}
1619
1620/// Lower the result values of a call into the
1621/// appropriate copies out of appropriate physical registers.
1622///
1623SDValue AVRTargetLowering::LowerCallResult(
1624 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1625 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1626 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1627
1628 // Assign locations to each value returned by this call.
1629 SmallVector<CCValAssign, 16> RVLocs;
1630 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1631 *DAG.getContext());
1632
1633 // Handle runtime calling convs.
1634 if (CallConv == CallingConv::AVR_BUILTIN) {
1635 CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
1636 } else {
1638 }
1639
1640 // Copy all of the result registers out of their specified physreg.
1641 for (CCValAssign const &RVLoc : RVLocs) {
1642 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1643 InFlag)
1644 .getValue(1);
1645 InFlag = Chain.getValue(2);
1646 InVals.push_back(Chain.getValue(0));
1647 }
1648
1649 return Chain;
1650}
1651
1652//===----------------------------------------------------------------------===//
1653// Return Value Calling Convention Implementation
1654//===----------------------------------------------------------------------===//
1655
1656bool AVRTargetLowering::CanLowerReturn(
1657 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1658 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
1659 if (CallConv == CallingConv::AVR_BUILTIN) {
1660 SmallVector<CCValAssign, 16> RVLocs;
1661 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1662 return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
1663 }
1664
1665 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs);
1666 return TotalBytes <= (unsigned)(Subtarget.hasTinyEncoding() ? 4 : 8);
1667}
1668
1669SDValue
1670AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1671 bool isVarArg,
1672 const SmallVectorImpl<ISD::OutputArg> &Outs,
1673 const SmallVectorImpl<SDValue> &OutVals,
1674 const SDLoc &dl, SelectionDAG &DAG) const {
1675 // CCValAssign - represent the assignment of the return value to locations.
1676 SmallVector<CCValAssign, 16> RVLocs;
1677
1678 // CCState - Info about the registers and stack slot.
1679 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1680 *DAG.getContext());
1681
1682 MachineFunction &MF = DAG.getMachineFunction();
1683
1684 // Analyze return values.
1685 if (CallConv == CallingConv::AVR_BUILTIN) {
1686 CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
1687 } else {
1689 }
1690
1691 SDValue Flag;
1692 SmallVector<SDValue, 4> RetOps(1, Chain);
1693 // Copy the result values into the output registers.
1694 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1695 CCValAssign &VA = RVLocs[i];
1696 assert(VA.isRegLoc() && "Can only return in registers!");
1697
1698 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1699
1700 // Guarantee that all emitted copies are stuck together with flags.
1701 Flag = Chain.getValue(1);
1702 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1703 }
1704
1705 // Don't emit the ret/reti instruction when the naked attribute is present in
1706 // the function being compiled.
1707 if (MF.getFunction().getAttributes().hasFnAttr(Attribute::Naked)) {
1708 return Chain;
1709 }
1710
1711 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1712
1713 if (!AFI->isInterruptOrSignalHandler()) {
1714 // The return instruction has an implicit zero register operand: it must
1715 // contain zero on return.
1716 // This is not needed in interrupts however, where the zero register is
1717 // handled specially (only pushed/popped when needed).
1718 RetOps.push_back(DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8));
1719 }
1720
1721 unsigned RetOpc =
1722 AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_FLAG : AVRISD::RET_FLAG;
1723
1724 RetOps[0] = Chain; // Update chain.
1725
1726 if (Flag.getNode()) {
1727 RetOps.push_back(Flag);
1728 }
1729
1730 return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1731}
1732
1733//===----------------------------------------------------------------------===//
1734// Custom Inserters
1735//===----------------------------------------------------------------------===//
1736
1737MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1738 MachineBasicBlock *BB) const {
1739 unsigned Opc;
1740 const TargetRegisterClass *RC;
1741 bool HasRepeatedOperand = false;
1742 bool HasZeroOperand = false;
1743 MachineFunction *F = BB->getParent();
1744 MachineRegisterInfo &RI = F->getRegInfo();
1745 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1746 DebugLoc dl = MI.getDebugLoc();
1747
1748 switch (MI.getOpcode()) {
1749 default:
1750 llvm_unreachable("Invalid shift opcode!");
1751 case AVR::Lsl8:
1752 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1753 RC = &AVR::GPR8RegClass;
1754 HasRepeatedOperand = true;
1755 break;
1756 case AVR::Lsl16:
1757 Opc = AVR::LSLWRd;
1758 RC = &AVR::DREGSRegClass;
1759 break;
1760 case AVR::Asr8:
1761 Opc = AVR::ASRRd;
1762 RC = &AVR::GPR8RegClass;
1763 break;
1764 case AVR::Asr16:
1765 Opc = AVR::ASRWRd;
1766 RC = &AVR::DREGSRegClass;
1767 break;
1768 case AVR::Lsr8:
1769 Opc = AVR::LSRRd;
1770 RC = &AVR::GPR8RegClass;
1771 break;
1772 case AVR::Lsr16:
1773 Opc = AVR::LSRWRd;
1774 RC = &AVR::DREGSRegClass;
1775 break;
1776 case AVR::Rol8:
1777 Opc = AVR::ROLBRd;
1778 RC = &AVR::GPR8RegClass;
1779 HasZeroOperand = true;
1780 break;
1781 case AVR::Rol16:
1782 Opc = AVR::ROLWRd;
1783 RC = &AVR::DREGSRegClass;
1784 break;
1785 case AVR::Ror8:
1786 Opc = AVR::RORBRd;
1787 RC = &AVR::GPR8RegClass;
1788 break;
1789 case AVR::Ror16:
1790 Opc = AVR::RORWRd;
1791 RC = &AVR::DREGSRegClass;
1792 break;
1793 }
1794
1795 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1796
1798 for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I)
1799 ;
1800 if (I != F->end())
1801 ++I;
1802
1803 // Create loop block.
1804 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1805 MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB);
1806 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1807
1808 F->insert(I, LoopBB);
1809 F->insert(I, CheckBB);
1810 F->insert(I, RemBB);
1811
1812 // Update machine-CFG edges by transferring all successors of the current
1813 // block to the block containing instructions after shift.
1814 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1815 BB->end());
1816 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1817
1818 // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB.
1819 BB->addSuccessor(CheckBB);
1820 LoopBB->addSuccessor(CheckBB);
1821 CheckBB->addSuccessor(LoopBB);
1822 CheckBB->addSuccessor(RemBB);
1823
1824 Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass);
1825 Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass);
1826 Register ShiftReg = RI.createVirtualRegister(RC);
1827 Register ShiftReg2 = RI.createVirtualRegister(RC);
1828 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1829 Register SrcReg = MI.getOperand(1).getReg();
1830 Register DstReg = MI.getOperand(0).getReg();
1831
1832 // BB:
1833 // rjmp CheckBB
1834 BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB);
1835
1836 // LoopBB:
1837 // ShiftReg2 = shift ShiftReg
1838 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1839 if (HasRepeatedOperand)
1840 ShiftMI.addReg(ShiftReg);
1841 if (HasZeroOperand)
1842 ShiftMI.addReg(Subtarget.getZeroRegister());
1843
1844 // CheckBB:
1845 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1846 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1847 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1848 // ShiftAmt2 = ShiftAmt - 1;
1849 // if (ShiftAmt2 >= 0) goto LoopBB;
1850 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg)
1851 .addReg(SrcReg)
1852 .addMBB(BB)
1853 .addReg(ShiftReg2)
1854 .addMBB(LoopBB);
1855 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1856 .addReg(ShiftAmtSrcReg)
1857 .addMBB(BB)
1858 .addReg(ShiftAmtReg2)
1859 .addMBB(LoopBB);
1860 BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg)
1861 .addReg(SrcReg)
1862 .addMBB(BB)
1863 .addReg(ShiftReg2)
1864 .addMBB(LoopBB);
1865
1866 BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2).addReg(ShiftAmtReg);
1867 BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB);
1868
1869 MI.eraseFromParent(); // The pseudo instruction is gone now.
1870 return RemBB;
1871}
1872
1873// Do a multibyte AVR shift. Insert shift instructions and put the output
1874// registers in the Regs array.
1875// Because AVR does not have a normal shift instruction (only a single bit shift
1876// instruction), we have to emulate this behavior with other instructions.
1877// It first tries large steps (moving registers around) and then smaller steps
1878// like single bit shifts.
1879// Large shifts actually reduce the number of shifted registers, so the below
1880// algorithms have to work independently of the number of registers that are
1881// shifted.
1882// For more information and background, see this blogpost:
1883// https://aykevl.nl/2021/02/avr-bitshift
1885 MutableArrayRef<std::pair<Register, int>> Regs,
1886 ISD::NodeType Opc, int64_t ShiftAmt) {
1888 const AVRSubtarget &STI = BB->getParent()->getSubtarget<AVRSubtarget>();
1890 const DebugLoc &dl = MI.getDebugLoc();
1891
1892 const bool ShiftLeft = Opc == ISD::SHL;
1893 const bool ArithmeticShift = Opc == ISD::SRA;
1894
1895 // Zero a register, for use in later operations.
1896 Register ZeroReg = MRI.createVirtualRegister(&AVR::GPR8RegClass);
1897 BuildMI(*BB, MI, dl, TII.get(AVR::COPY), ZeroReg)
1898 .addReg(STI.getZeroRegister());
1899
1900 // Do a shift modulo 6 or 7. This is a bit more complicated than most shifts
1901 // and is hard to compose with the rest, so these are special cased.
1902 // The basic idea is to shift one or two bits in the opposite direction and
1903 // then move registers around to get the correct end result.
1904 if (ShiftLeft && (ShiftAmt % 8) >= 6) {
1905 // Left shift modulo 6 or 7.
1906
1907 // Create a slice of the registers we're going to modify, to ease working
1908 // with them.
1909 size_t ShiftRegsOffset = ShiftAmt / 8;
1910 size_t ShiftRegsSize = Regs.size() - ShiftRegsOffset;
1912 Regs.slice(ShiftRegsOffset, ShiftRegsSize);
1913
1914 // Shift one to the right, keeping the least significant bit as the carry
1915 // bit.
1916 insertMultibyteShift(MI, BB, ShiftRegs, ISD::SRL, 1);
1917
1918 // Rotate the least significant bit from the carry bit into a new register
1919 // (that starts out zero).
1920 Register LowByte = MRI.createVirtualRegister(&AVR::GPR8RegClass);
1921 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), LowByte).addReg(ZeroReg);
1922
1923 // Shift one more to the right if this is a modulo-6 shift.
1924 if (ShiftAmt % 8 == 6) {
1925 insertMultibyteShift(MI, BB, ShiftRegs, ISD::SRL, 1);
1926 Register NewLowByte = MRI.createVirtualRegister(&AVR::GPR8RegClass);
1927 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), NewLowByte).addReg(LowByte);
1928 LowByte = NewLowByte;
1929 }
1930
1931 // Move all registers to the left, zeroing the bottom registers as needed.
1932 for (size_t I = 0; I < Regs.size(); I++) {
1933 int ShiftRegsIdx = I + 1;
1934 if (ShiftRegsIdx < (int)ShiftRegs.size()) {
1935 Regs[I] = ShiftRegs[ShiftRegsIdx];
1936 } else if (ShiftRegsIdx == (int)ShiftRegs.size()) {
1937 Regs[I] = std::pair(LowByte, 0);
1938 } else {
1939 Regs[I] = std::pair(ZeroReg, 0);
1940 }
1941 }
1942
1943 return;
1944 }
1945
1946 // Right shift modulo 6 or 7.
1947 if (!ShiftLeft && (ShiftAmt % 8) >= 6) {
1948 // Create a view on the registers we're going to modify, to ease working
1949 // with them.
1950 size_t ShiftRegsSize = Regs.size() - (ShiftAmt / 8);
1952 Regs.slice(0, ShiftRegsSize);
1953
1954 // Shift one to the left.
1955 insertMultibyteShift(MI, BB, ShiftRegs, ISD::SHL, 1);
1956
1957 // Sign or zero extend the most significant register into a new register.
1958 // The HighByte is the byte that still has one (or two) bits from the
1959 // original value. The ExtByte is purely a zero/sign extend byte (all bits
1960 // are either 0 or 1).
1961 Register HighByte = MRI.createVirtualRegister(&AVR::GPR8RegClass);
1962 Register ExtByte = 0;
1963 if (ArithmeticShift) {
1964 // Sign-extend bit that was shifted out last.
1965 BuildMI(*BB, MI, dl, TII.get(AVR::SBCRdRr), HighByte)
1966 .addReg(HighByte, RegState::Undef)
1967 .addReg(HighByte, RegState::Undef);
1968 ExtByte = HighByte;
1969 // The highest bit of the original value is the same as the zero-extend
1970 // byte, so HighByte and ExtByte are the same.
1971 } else {
1972 // Use the zero register for zero extending.
1973 ExtByte = ZeroReg;
1974 // Rotate most significant bit into a new register (that starts out zero).
1975 BuildMI(*BB, MI, dl, TII.get(AVR::ADCRdRr), HighByte)
1976 .addReg(ExtByte)
1977 .addReg(ExtByte);
1978 }
1979
1980 // Shift one more to the left for modulo 6 shifts.
1981 if (ShiftAmt % 8 == 6) {
1982 insertMultibyteShift(MI, BB, ShiftRegs, ISD::SHL, 1);
1983 // Shift the topmost bit into the HighByte.
1984 Register NewExt = MRI.createVirtualRegister(&AVR::GPR8RegClass);
1985 BuildMI(*BB, MI, dl, TII.get(AVR::ADCRdRr), NewExt)
1986 .addReg(HighByte)
1987 .addReg(HighByte);
1988 HighByte = NewExt;
1989 }
1990
1991 // Move all to the right, while sign or zero extending.
1992 for (int I = Regs.size() - 1; I >= 0; I--) {
1993 int ShiftRegsIdx = I - (Regs.size() - ShiftRegs.size()) - 1;
1994 if (ShiftRegsIdx >= 0) {
1995 Regs[I] = ShiftRegs[ShiftRegsIdx];
1996 } else if (ShiftRegsIdx == -1) {
1997 Regs[I] = std::pair(HighByte, 0);
1998 } else {
1999 Regs[I] = std::pair(ExtByte, 0);
2000 }
2001 }
2002
2003 return;
2004 }
2005
2006 // For shift amounts of at least one register, simply rename the registers and
2007 // zero the bottom registers.
2008 while (ShiftLeft && ShiftAmt >= 8) {
2009 // Move all registers one to the left.
2010 for (size_t I = 0; I < Regs.size() - 1; I++) {
2011 Regs[I] = Regs[I + 1];
2012 }
2013
2014 // Zero the least significant register.
2015 Regs[Regs.size() - 1] = std::pair(ZeroReg, 0);
2016
2017 // Continue shifts with the leftover registers.
2018 Regs = Regs.drop_back(1);
2019
2020 ShiftAmt -= 8;
2021 }
2022
2023 // And again, the same for right shifts.
2024 Register ShrExtendReg = 0;
2025 if (!ShiftLeft && ShiftAmt >= 8) {
2026 if (ArithmeticShift) {
2027 // Sign extend the most significant register into ShrExtendReg.
2028 ShrExtendReg = MRI.createVirtualRegister(&AVR::GPR8RegClass);
2029 Register Tmp = MRI.createVirtualRegister(&AVR::GPR8RegClass);
2030 BuildMI(*BB, MI, dl, TII.get(AVR::ADDRdRr), Tmp)
2031 .addReg(Regs[0].first, 0, Regs[0].second)
2032 .addReg(Regs[0].first, 0, Regs[0].second);
2033 BuildMI(*BB, MI, dl, TII.get(AVR::SBCRdRr), ShrExtendReg)
2034 .addReg(Tmp)
2035 .addReg(Tmp);
2036 } else {
2037 ShrExtendReg = ZeroReg;
2038 }
2039 for (; ShiftAmt >= 8; ShiftAmt -= 8) {
2040 // Move all registers one to the right.
2041 for (size_t I = Regs.size() - 1; I != 0; I--) {
2042 Regs[I] = Regs[I - 1];
2043 }
2044
2045 // Zero or sign extend the most significant register.
2046 Regs[0] = std::pair(ShrExtendReg, 0);
2047
2048 // Continue shifts with the leftover registers.
2049 Regs = Regs.drop_front(1);
2050 }
2051 }
2052
2053 // The bigger shifts are already handled above.
2054 assert((ShiftAmt < 8) && "Unexpect shift amount");
2055
2056 // Shift by four bits, using a complicated swap/eor/andi/eor sequence.
2057 // It only works for logical shifts because the bits shifted in are all
2058 // zeroes.
2059 // To shift a single byte right, it produces code like this:
2060 // swap r0
2061 // andi r0, 0x0f
2062 // For a two-byte (16-bit) shift, it adds the following instructions to shift
2063 // the upper byte into the lower byte:
2064 // swap r1
2065 // eor r0, r1
2066 // andi r1, 0x0f
2067 // eor r0, r1
2068 // For bigger shifts, it repeats the above sequence. For example, for a 3-byte
2069 // (24-bit) shift it adds:
2070 // swap r2
2071 // eor r1, r2
2072 // andi r2, 0x0f
2073 // eor r1, r2
2074 if (!ArithmeticShift && ShiftAmt >= 4) {
2075 Register Prev = 0;
2076 for (size_t I = 0; I < Regs.size(); I++) {
2077 size_t Idx = ShiftLeft ? I : Regs.size() - I - 1;
2078 Register SwapReg = MRI.createVirtualRegister(&AVR::LD8RegClass);
2079 BuildMI(*BB, MI, dl, TII.get(AVR::SWAPRd), SwapReg)
2080 .addReg(Regs[Idx].first, 0, Regs[Idx].second);
2081 if (I != 0) {
2082 Register R = MRI.createVirtualRegister(&AVR::GPR8RegClass);
2083 BuildMI(*BB, MI, dl, TII.get(AVR::EORRdRr), R)
2084 .addReg(Prev)
2085 .addReg(SwapReg);
2086 Prev = R;
2087 }
2088 Register AndReg = MRI.createVirtualRegister(&AVR::LD8RegClass);
2089 BuildMI(*BB, MI, dl, TII.get(AVR::ANDIRdK), AndReg)
2090 .addReg(SwapReg)
2091 .addImm(ShiftLeft ? 0xf0 : 0x0f);
2092 if (I != 0) {
2093 Register R = MRI.createVirtualRegister(&AVR::GPR8RegClass);
2094 BuildMI(*BB, MI, dl, TII.get(AVR::EORRdRr), R)
2095 .addReg(Prev)
2096 .addReg(AndReg);
2097 size_t PrevIdx = ShiftLeft ? Idx - 1 : Idx + 1;
2098 Regs[PrevIdx] = std::pair(R, 0);
2099 }
2100 Prev = AndReg;
2101 Regs[Idx] = std::pair(AndReg, 0);
2102 }
2103 ShiftAmt -= 4;
2104 }
2105
2106 // Shift by one. This is the fallback that always works, and the shift
2107 // operation that is used for 1, 2, and 3 bit shifts.
2108 while (ShiftLeft && ShiftAmt) {
2109 // Shift one to the left.
2110 for (ssize_t I = Regs.size() - 1; I >= 0; I--) {
2111 Register Out = MRI.createVirtualRegister(&AVR::GPR8RegClass);
2112 Register In = Regs[I].first;
2113 Register InSubreg = Regs[I].second;
2114 if (I == (ssize_t)Regs.size() - 1) { // first iteration
2115 BuildMI(*BB, MI, dl, TII.get(AVR::ADDRdRr), Out)
2116 .addReg(In, 0, InSubreg)
2117 .addReg(In, 0, InSubreg);
2118 } else {
2119 BuildMI(*BB, MI, dl, TII.get(AVR::ADCRdRr), Out)
2120 .addReg(In, 0, InSubreg)
2121 .addReg(In, 0, InSubreg);
2122 }
2123 Regs[I] = std::pair(Out, 0);
2124 }
2125 ShiftAmt--;
2126 }
2127 while (!ShiftLeft && ShiftAmt) {
2128 // Shift one to the right.
2129 for (size_t I = 0; I < Regs.size(); I++) {
2130 Register Out = MRI.createVirtualRegister(&AVR::GPR8RegClass);
2131 Register In = Regs[I].first;
2132 Register InSubreg = Regs[I].second;
2133 if (I == 0) {
2134 unsigned Opc = ArithmeticShift ? AVR::ASRRd : AVR::LSRRd;
2135 BuildMI(*BB, MI, dl, TII.get(Opc), Out).addReg(In, 0, InSubreg);
2136 } else {
2137 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), Out).addReg(In, 0, InSubreg);
2138 }
2139 Regs[I] = std::pair(Out, 0);
2140 }
2141 ShiftAmt--;
2142 }
2143
2144 if (ShiftAmt != 0) {
2145 llvm_unreachable("don't know how to shift!"); // sanity check
2146 }
2147}
2148
2149// Do a wide (32-bit) shift.
2150MachineBasicBlock *
2151AVRTargetLowering::insertWideShift(MachineInstr &MI,
2152 MachineBasicBlock *BB) const {
2153 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2154 const DebugLoc &dl = MI.getDebugLoc();
2155
2156 // How much to shift to the right (meaning: a negative number indicates a left
2157 // shift).
2158 int64_t ShiftAmt = MI.getOperand(4).getImm();
2159 ISD::NodeType Opc;
2160 switch (MI.getOpcode()) {
2161 case AVR::Lsl32:
2162 Opc = ISD::SHL;
2163 break;
2164 case AVR::Lsr32:
2165 Opc = ISD::SRL;
2166 break;
2167 case AVR::Asr32:
2168 Opc = ISD::SRA;
2169 break;
2170 }
2171
2172 // Read the input registers, with the most significant register at index 0.
2173 std::array<std::pair<Register, int>, 4> Registers = {
2174 std::pair(MI.getOperand(3).getReg(), AVR::sub_hi),
2175 std::pair(MI.getOperand(3).getReg(), AVR::sub_lo),
2176 std::pair(MI.getOperand(2).getReg(), AVR::sub_hi),
2177 std::pair(MI.getOperand(2).getReg(), AVR::sub_lo),
2178 };
2179
2180 // Do the shift. The registers are modified in-place.
2181 insertMultibyteShift(MI, BB, Registers, Opc, ShiftAmt);
2182
2183 // Combine the 8-bit registers into 16-bit register pairs.
2184 // This done either from LSB to MSB or from MSB to LSB, depending on the
2185 // shift. It's an optimization so that the register allocator will use the
2186 // fewest movs possible (which order we use isn't a correctness issue, just an
2187 // optimization issue).
2188 // - lsl prefers starting from the most significant byte (2nd case).
2189 // - lshr prefers starting from the least significant byte (1st case).
2190 // - for ashr it depends on the number of shifted bytes.
2191 // Some shift operations still don't get the most optimal mov sequences even
2192 // with this distinction. TODO: figure out why and try to fix it (but we're
2193 // already equal to or faster than avr-gcc in all cases except ashr 8).
2194 if (Opc != ISD::SHL &&
2195 (Opc != ISD::SRA || (ShiftAmt < 16 || ShiftAmt >= 22))) {
2196 // Use the resulting registers starting with the least significant byte.
2197 BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(0).getReg())
2198 .addReg(Registers[3].first, 0, Registers[3].second)
2199 .addImm(AVR::sub_lo)
2200 .addReg(Registers[2].first, 0, Registers[2].second)
2201 .addImm(AVR::sub_hi);
2202 BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(1).getReg())
2203 .addReg(Registers[1].first, 0, Registers[1].second)
2204 .addImm(AVR::sub_lo)
2205 .addReg(Registers[0].first, 0, Registers[0].second)
2206 .addImm(AVR::sub_hi);
2207 } else {
2208 // Use the resulting registers starting with the most significant byte.
2209 BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(1).getReg())
2210 .addReg(Registers[0].first, 0, Registers[0].second)
2211 .addImm(AVR::sub_hi)
2212 .addReg(Registers[1].first, 0, Registers[1].second)
2213 .addImm(AVR::sub_lo);
2214 BuildMI(*BB, MI, dl, TII.get(AVR::REG_SEQUENCE), MI.getOperand(0).getReg())
2215 .addReg(Registers[2].first, 0, Registers[2].second)
2216 .addImm(AVR::sub_hi)
2217 .addReg(Registers[3].first, 0, Registers[3].second)
2218 .addImm(AVR::sub_lo);
2219 }
2220
2221 // Remove the pseudo instruction.
2222 MI.eraseFromParent();
2223 return BB;
2224}
2225
2227 if (I->getOpcode() == AVR::COPY) {
2228 Register SrcReg = I->getOperand(1).getReg();
2229 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
2230 }
2231
2232 return false;
2233}
2234
2235// The mul instructions wreak havock on our zero_reg R1. We need to clear it
2236// after the result has been evacuated. This is probably not the best way to do
2237// it, but it works for now.
2238MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
2239 MachineBasicBlock *BB) const {
2240 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2242 ++I; // in any case insert *after* the mul instruction
2243 if (isCopyMulResult(I))
2244 ++I;
2245 if (isCopyMulResult(I))
2246 ++I;
2247 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
2248 .addReg(AVR::R1)
2249 .addReg(AVR::R1);
2250 return BB;
2251}
2252
2253// Insert a read from the zero register.
2254MachineBasicBlock *
2255AVRTargetLowering::insertCopyZero(MachineInstr &MI,
2256 MachineBasicBlock *BB) const {
2257 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2259 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::COPY))
2260 .add(MI.getOperand(0))
2262 MI.eraseFromParent();
2263 return BB;
2264}
2265
2266// Lower atomicrmw operation to disable interrupts, do operation, and restore
2267// interrupts. This works because all AVR microcontrollers are single core.
2268MachineBasicBlock *AVRTargetLowering::insertAtomicArithmeticOp(
2269 MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, int Width) const {
2270 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
2271 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2273 DebugLoc dl = MI.getDebugLoc();
2274
2275 // Example instruction sequence, for an atomic 8-bit add:
2276 // ldi r25, 5
2277 // in r0, SREG
2278 // cli
2279 // ld r24, X
2280 // add r25, r24
2281 // st X, r25
2282 // out SREG, r0
2283
2284 const TargetRegisterClass *RC =
2285 (Width == 8) ? &AVR::GPR8RegClass : &AVR::DREGSRegClass;
2286 unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
2287 unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
2288
2289 // Disable interrupts.
2290 BuildMI(*BB, I, dl, TII.get(AVR::INRdA), Subtarget.getTmpRegister())
2292 BuildMI(*BB, I, dl, TII.get(AVR::BCLRs)).addImm(7);
2293
2294 // Load the original value.
2295 BuildMI(*BB, I, dl, TII.get(LoadOpcode), MI.getOperand(0).getReg())
2296 .add(MI.getOperand(1));
2297
2298 // Do the arithmetic operation.
2299 Register Result = MRI.createVirtualRegister(RC);
2300 BuildMI(*BB, I, dl, TII.get(Opcode), Result)
2301 .addReg(MI.getOperand(0).getReg())
2302 .add(MI.getOperand(2));
2303
2304 // Store the result.
2305 BuildMI(*BB, I, dl, TII.get(StoreOpcode))
2306 .add(MI.getOperand(1))
2307 .addReg(Result);
2308
2309 // Restore interrupts.
2310 BuildMI(*BB, I, dl, TII.get(AVR::OUTARr))
2313
2314 // Remove the pseudo instruction.
2315 MI.eraseFromParent();
2316 return BB;
2317}
2318
2319MachineBasicBlock *
2321 MachineBasicBlock *MBB) const {
2322 int Opc = MI.getOpcode();
2323
2324 // Pseudo shift instructions with a non constant shift amount are expanded
2325 // into a loop.
2326 switch (Opc) {
2327 case AVR::Lsl8:
2328 case AVR::Lsl16:
2329 case AVR::Lsr8:
2330 case AVR::Lsr16:
2331 case AVR::Rol8:
2332 case AVR::Rol16:
2333 case AVR::Ror8:
2334 case AVR::Ror16:
2335 case AVR::Asr8:
2336 case AVR::Asr16:
2337 return insertShift(MI, MBB);
2338 case AVR::Lsl32:
2339 case AVR::Lsr32:
2340 case AVR::Asr32:
2341 return insertWideShift(MI, MBB);
2342 case AVR::MULRdRr:
2343 case AVR::MULSRdRr:
2344 return insertMul(MI, MBB);
2345 case AVR::CopyZero:
2346 return insertCopyZero(MI, MBB);
2347 case AVR::AtomicLoadAdd8:
2348 return insertAtomicArithmeticOp(MI, MBB, AVR::ADDRdRr, 8);
2349 case AVR::AtomicLoadAdd16:
2350 return insertAtomicArithmeticOp(MI, MBB, AVR::ADDWRdRr, 16);
2351 case AVR::AtomicLoadSub8:
2352 return insertAtomicArithmeticOp(MI, MBB, AVR::SUBRdRr, 8);
2353 case AVR::AtomicLoadSub16:
2354 return insertAtomicArithmeticOp(MI, MBB, AVR::SUBWRdRr, 16);
2355 case AVR::AtomicLoadAnd8:
2356 return insertAtomicArithmeticOp(MI, MBB, AVR::ANDRdRr, 8);
2357 case AVR::AtomicLoadAnd16:
2358 return insertAtomicArithmeticOp(MI, MBB, AVR::ANDWRdRr, 16);
2359 case AVR::AtomicLoadOr8:
2360 return insertAtomicArithmeticOp(MI, MBB, AVR::ORRdRr, 8);
2361 case AVR::AtomicLoadOr16:
2362 return insertAtomicArithmeticOp(MI, MBB, AVR::ORWRdRr, 16);
2363 case AVR::AtomicLoadXor8:
2364 return insertAtomicArithmeticOp(MI, MBB, AVR::EORRdRr, 8);
2365 case AVR::AtomicLoadXor16:
2366 return insertAtomicArithmeticOp(MI, MBB, AVR::EORWRdRr, 16);
2367 }
2368
2369 assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
2370 "Unexpected instr type to insert");
2371
2372 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
2373 ->getParent()
2374 ->getSubtarget()
2375 .getInstrInfo();
2376 DebugLoc dl = MI.getDebugLoc();
2377
2378 // To "insert" a SELECT instruction, we insert the diamond
2379 // control-flow pattern. The incoming instruction knows the
2380 // destination vreg to set, the condition code register to branch
2381 // on, the true/false values to select between, and a branch opcode
2382 // to use.
2383
2384 MachineFunction *MF = MBB->getParent();
2385 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
2386 MachineBasicBlock *FallThrough = MBB->getFallThrough();
2387
2388 // If the current basic block falls through to another basic block,
2389 // we must insert an unconditional branch to the fallthrough destination
2390 // if we are to insert basic blocks at the prior fallthrough point.
2391 if (FallThrough != nullptr) {
2392 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
2393 }
2394
2395 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2396 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
2397
2399 for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I)
2400 ;
2401 if (I != MF->end())
2402 ++I;
2403 MF->insert(I, trueMBB);
2404 MF->insert(I, falseMBB);
2405
2406 // Transfer remaining instructions and all successors of the current
2407 // block to the block which will contain the Phi node for the
2408 // select.
2409 trueMBB->splice(trueMBB->begin(), MBB,
2410 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
2412
2413 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
2414 BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
2415 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
2416 MBB->addSuccessor(falseMBB);
2417 MBB->addSuccessor(trueMBB);
2418
2419 // Unconditionally flow back to the true block
2420 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
2421 falseMBB->addSuccessor(trueMBB);
2422
2423 // Set up the Phi node to determine where we came from
2424 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI),
2425 MI.getOperand(0).getReg())
2426 .addReg(MI.getOperand(1).getReg())
2427 .addMBB(MBB)
2428 .addReg(MI.getOperand(2).getReg())
2429 .addMBB(falseMBB);
2430
2431 MI.eraseFromParent(); // The pseudo instruction is gone now.
2432 return trueMBB;
2433}
2434
2435//===----------------------------------------------------------------------===//
2436// Inline Asm Support
2437//===----------------------------------------------------------------------===//
2438
2441 if (Constraint.size() == 1) {
2442 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
2443 switch (Constraint[0]) {
2444 default:
2445 break;
2446 case 'a': // Simple upper registers
2447 case 'b': // Base pointer registers pairs
2448 case 'd': // Upper register
2449 case 'l': // Lower registers
2450 case 'e': // Pointer register pairs
2451 case 'q': // Stack pointer register
2452 case 'r': // Any register
2453 case 'w': // Special upper register pairs
2454 return C_RegisterClass;
2455 case 't': // Temporary register
2456 case 'x':
2457 case 'X': // Pointer register pair X
2458 case 'y':
2459 case 'Y': // Pointer register pair Y
2460 case 'z':
2461 case 'Z': // Pointer register pair Z
2462 return C_Register;
2463 case 'Q': // A memory address based on Y or Z pointer with displacement.
2464 return C_Memory;
2465 case 'G': // Floating point constant
2466 case 'I': // 6-bit positive integer constant
2467 case 'J': // 6-bit negative integer constant
2468 case 'K': // Integer constant (Range: 2)
2469 case 'L': // Integer constant (Range: 0)
2470 case 'M': // 8-bit integer constant
2471 case 'N': // Integer constant (Range: -1)
2472 case 'O': // Integer constant (Range: 8, 16, 24)
2473 case 'P': // Integer constant (Range: 1)
2474 case 'R': // Integer constant (Range: -6 to 5)x
2475 return C_Immediate;
2476 }
2477 }
2478
2479 return TargetLowering::getConstraintType(Constraint);
2480}
2481
2482unsigned
2484 // Not sure if this is actually the right thing to do, but we got to do
2485 // *something* [agnat]
2486 switch (ConstraintCode[0]) {
2487 case 'Q':
2489 }
2490 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
2491}
2492
2495 AsmOperandInfo &info, const char *constraint) const {
2497 Value *CallOperandVal = info.CallOperandVal;
2498
2499 // If we don't have a value, we can't do a match,
2500 // but allow it at the lowest weight.
2501 // (this behaviour has been copied from the ARM backend)
2502 if (!CallOperandVal) {
2503 return CW_Default;
2504 }
2505
2506 // Look at the constraint type.
2507 switch (*constraint) {
2508 default:
2510 break;
2511 case 'd':
2512 case 'r':
2513 case 'l':
2514 weight = CW_Register;
2515 break;
2516 case 'a':
2517 case 'b':
2518 case 'e':
2519 case 'q':
2520 case 't':
2521 case 'w':
2522 case 'x':
2523 case 'X':
2524 case 'y':
2525 case 'Y':
2526 case 'z':
2527 case 'Z':
2528 weight = CW_SpecificReg;
2529 break;
2530 case 'G':
2531 if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
2532 if (C->isZero()) {
2533 weight = CW_Constant;
2534 }
2535 }
2536 break;
2537 case 'I':
2538 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2539 if (isUInt<6>(C->getZExtValue())) {
2540 weight = CW_Constant;
2541 }
2542 }
2543 break;
2544 case 'J':
2545 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2546 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
2547 weight = CW_Constant;
2548 }
2549 }
2550 break;
2551 case 'K':
2552 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2553 if (C->getZExtValue() == 2) {
2554 weight = CW_Constant;
2555 }
2556 }
2557 break;
2558 case 'L':
2559 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2560 if (C->getZExtValue() == 0) {
2561 weight = CW_Constant;
2562 }
2563 }
2564 break;
2565 case 'M':
2566 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2567 if (isUInt<8>(C->getZExtValue())) {
2568 weight = CW_Constant;
2569 }
2570 }
2571 break;
2572 case 'N':
2573 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2574 if (C->getSExtValue() == -1) {
2575 weight = CW_Constant;
2576 }
2577 }
2578 break;
2579 case 'O':
2580 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2581 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
2582 (C->getZExtValue() == 24)) {
2583 weight = CW_Constant;
2584 }
2585 }
2586 break;
2587 case 'P':
2588 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2589 if (C->getZExtValue() == 1) {
2590 weight = CW_Constant;
2591 }
2592 }
2593 break;
2594 case 'R':
2595 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
2596 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
2597 weight = CW_Constant;
2598 }
2599 }
2600 break;
2601 case 'Q':
2602 weight = CW_Memory;
2603 break;
2604 }
2605
2606 return weight;
2607}
2608
2609std::pair<unsigned, const TargetRegisterClass *>
2611 StringRef Constraint,
2612 MVT VT) const {
2613 if (Constraint.size() == 1) {
2614 switch (Constraint[0]) {
2615 case 'a': // Simple upper registers r16..r23.
2616 if (VT == MVT::i8)
2617 return std::make_pair(0U, &AVR::LD8loRegClass);
2618 else if (VT == MVT::i16)
2619 return std::make_pair(0U, &AVR::DREGSLD8loRegClass);
2620 break;
2621 case 'b': // Base pointer registers: y, z.
2622 if (VT == MVT::i8 || VT == MVT::i16)
2623 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
2624 break;
2625 case 'd': // Upper registers r16..r31.
2626 if (VT == MVT::i8)
2627 return std::make_pair(0U, &AVR::LD8RegClass);
2628 else if (VT == MVT::i16)
2629 return std::make_pair(0U, &AVR::DLDREGSRegClass);
2630 break;
2631 case 'l': // Lower registers r0..r15.
2632 if (VT == MVT::i8)
2633 return std::make_pair(0U, &AVR::GPR8loRegClass);
2634 else if (VT == MVT::i16)
2635 return std::make_pair(0U, &AVR::DREGSloRegClass);
2636 break;
2637 case 'e': // Pointer register pairs: x, y, z.
2638 if (VT == MVT::i8 || VT == MVT::i16)
2639 return std::make_pair(0U, &AVR::PTRREGSRegClass);
2640 break;
2641 case 'q': // Stack pointer register: SPH:SPL.
2642 return std::make_pair(0U, &AVR::GPRSPRegClass);
2643 case 'r': // Any register: r0..r31.
2644 if (VT == MVT::i8)
2645 return std::make_pair(0U, &AVR::GPR8RegClass);
2646 else if (VT == MVT::i16)
2647 return std::make_pair(0U, &AVR::DREGSRegClass);
2648 break;
2649 case 't': // Temporary register: r0.
2650 if (VT == MVT::i8)
2651 return std::make_pair(unsigned(Subtarget.getTmpRegister()),
2652 &AVR::GPR8RegClass);
2653 break;
2654 case 'w': // Special upper register pairs: r24, r26, r28, r30.
2655 if (VT == MVT::i8 || VT == MVT::i16)
2656 return std::make_pair(0U, &AVR::IWREGSRegClass);
2657 break;
2658 case 'x': // Pointer register pair X: r27:r26.
2659 case 'X':
2660 if (VT == MVT::i8 || VT == MVT::i16)
2661 return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
2662 break;
2663 case 'y': // Pointer register pair Y: r29:r28.
2664 case 'Y':
2665 if (VT == MVT::i8 || VT == MVT::i16)
2666 return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
2667 break;
2668 case 'z': // Pointer register pair Z: r31:r30.
2669 case 'Z':
2670 if (VT == MVT::i8 || VT == MVT::i16)
2671 return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
2672 break;
2673 default:
2674 break;
2675 }
2676 }
2677
2679 Subtarget.getRegisterInfo(), Constraint, VT);
2680}
2681
2683 std::string &Constraint,
2684 std::vector<SDValue> &Ops,
2685 SelectionDAG &DAG) const {
2686 SDValue Result;
2687 SDLoc DL(Op);
2688 EVT Ty = Op.getValueType();
2689
2690 // Currently only support length 1 constraints.
2691 if (Constraint.length() != 1) {
2692 return;
2693 }
2694
2695 char ConstraintLetter = Constraint[0];
2696 switch (ConstraintLetter) {
2697 default:
2698 break;
2699 // Deal with integers first:
2700 case 'I':
2701 case 'J':
2702 case 'K':
2703 case 'L':
2704 case 'M':
2705 case 'N':
2706 case 'O':
2707 case 'P':
2708 case 'R': {
2709 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2710 if (!C) {
2711 return;
2712 }
2713
2714 int64_t CVal64 = C->getSExtValue();
2715 uint64_t CUVal64 = C->getZExtValue();
2716 switch (ConstraintLetter) {
2717 case 'I': // 0..63
2718 if (!isUInt<6>(CUVal64))
2719 return;
2720 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2721 break;
2722 case 'J': // -63..0
2723 if (CVal64 < -63 || CVal64 > 0)
2724 return;
2725 Result = DAG.getTargetConstant(CVal64, DL, Ty);
2726 break;
2727 case 'K': // 2
2728 if (CUVal64 != 2)
2729 return;
2730 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2731 break;
2732 case 'L': // 0
2733 if (CUVal64 != 0)
2734 return;
2735 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2736 break;
2737 case 'M': // 0..255
2738 if (!isUInt<8>(CUVal64))
2739 return;
2740 // i8 type may be printed as a negative number,
2741 // e.g. 254 would be printed as -2,
2742 // so we force it to i16 at least.
2743 if (Ty.getSimpleVT() == MVT::i8) {
2744 Ty = MVT::i16;
2745 }
2746 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2747 break;
2748 case 'N': // -1
2749 if (CVal64 != -1)
2750 return;
2751 Result = DAG.getTargetConstant(CVal64, DL, Ty);
2752 break;
2753 case 'O': // 8, 16, 24
2754 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
2755 return;
2756 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2757 break;
2758 case 'P': // 1
2759 if (CUVal64 != 1)
2760 return;
2761 Result = DAG.getTargetConstant(CUVal64, DL, Ty);
2762 break;
2763 case 'R': // -6..5
2764 if (CVal64 < -6 || CVal64 > 5)
2765 return;
2766 Result = DAG.getTargetConstant(CVal64, DL, Ty);
2767 break;
2768 }
2769
2770 break;
2771 }
2772 case 'G':
2773 const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op);
2774 if (!FC || !FC->isZero())
2775 return;
2776 // Soften float to i8 0
2777 Result = DAG.getTargetConstant(0, DL, MVT::i8);
2778 break;
2779 }
2780
2781 if (Result.getNode()) {
2782 Ops.push_back(Result);
2783 return;
2784 }
2785
2786 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2787}
2788
2790 const MachineFunction &MF) const {
2791 Register Reg;
2792
2793 if (VT == LLT::scalar(8)) {
2795 .Case("r0", AVR::R0)
2796 .Case("r1", AVR::R1)
2797 .Default(0);
2798 } else {
2800 .Case("r0", AVR::R1R0)
2801 .Case("sp", AVR::SP)
2802 .Default(0);
2803 }
2804
2805 if (Reg)
2806 return Reg;
2807
2809 Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
2810}
2811
2812} // end of namespace llvm
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Callee
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Function Alias Analysis Results
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define NODE(NodeKind)
#define RegName(no)
lazy value info
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
unsigned Reg
typename CallsiteContextGraph< DerivedCCG, FuncTy, CallTy >::CallInfo CallInfo
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI Pre allocate WWM Registers
This file contains some templates that are useful if you are working with the STL at all.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
@ Flags
Definition: TextStubV5.cpp:93
Value * RHS
Value * LHS
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:64
A specific AVR target MCU.
Definition: AVRSubtarget.h:32
Register getTmpRegister() const
Definition: AVRSubtarget.h:106
bool hasTinyEncoding() const
Definition: AVRSubtarget.h:82
Register getZeroRegister() const
Definition: AVRSubtarget.h:109
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:42
int getIORegSREG() const
Definition: AVRSubtarget.h:100
bool supportsMultiplication() const
Definition: AVRSubtarget.h:80
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:52
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
const AVRSubtarget & Subtarget
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
AVRTargetLowering(const AVRTargetMachine &TM, const AVRSubtarget &STI)
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
A generic AVR implementation.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
LLVM Basic Block Representation.
Definition: BasicBlock.h:56
CCState - This class holds information needed while lowering arguments and return values.
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
LLVMContext & getContext() const
void addLoc(const CCValAssign &V)
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:260
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:848
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:500
A debug info location.
Definition: DebugLoc.h:33
static unsigned getFlagWord(unsigned Kind, unsigned NumOps)
Definition: InlineAsm.h:293
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
This class is used to represent ISD::LOAD nodes.
Machine Value Type.
static auto integer_valuetypes()
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineInstrBundleIterator< MachineInstr > iterator
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
BasicBlockListType::iterator iterator
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:305
MutableArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:374
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDValue getValue(unsigned R) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:675
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
static StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:426
TargetInstrInfo - Interface to description of machine instruction set.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
std::vector< ArgListEntry > ArgListTy
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:31
@ COND_SH
Unsigned same or higher.
Definition: AVRInstrInfo.h:36
@ COND_GE
Greater than or equal.
Definition: AVRInstrInfo.h:34
@ COND_MI
Minus.
Definition: AVRInstrInfo.h:38
@ COND_LO
Unsigned lower.
Definition: AVRInstrInfo.h:37
@ COND_LT
Less than.
Definition: AVRInstrInfo.h:35
@ COND_PL
Plus.
Definition: AVRInstrInfo.h:39
@ COND_EQ
Equal.
Definition: AVRInstrInfo.h:32
@ COND_NE
Not equal.
Definition: AVRInstrInfo.h:33
@ ASRWN
Word arithmetic shift right N bits.
@ SWAP
Swap Rd[7:4] <-> Rd[3:0].
@ LSLW
Wide logical shift left.
@ ROLLOOP
A loop of single left bit rotate instructions.
@ ASRLO
Lower 8-bit of word arithmetic shift right.
@ RETI_FLAG
Return from ISR.
@ ASRLOOP
A loop of single arithmetic shift right instructions.
@ LSRLOOP
A loop of single logical shift right instructions.
@ ROL
Bit rotate left.
@ LSR
Logical shift right.
@ LSRLO
Lower 8-bit of word logical shift right.
@ TST
Test for zero or minus instruction.
@ LSRBN
Byte logical shift right N bits.
@ ASRW
Wide arithmetic shift right.
@ SELECT_CC
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
@ CMPC
Compare with carry instruction.
@ LSLWN
Word logical shift left N bits.
@ RORLOOP
A loop of single right bit rotate instructions.
@ CMP
Compare instruction.
@ ASRBN
Byte arithmetic shift right N bits.
@ ROR
Bit rotate right.
@ CALL
Represents an abstract call instruction, which includes a bunch of information.
@ ASR
Arithmetic shift right.
@ RET_FLAG
Return from subroutine.
@ LSRW
Wide logical shift right.
@ LSL
Logical shift left.
@ LSLBN
Byte logical shift left N bits.
@ LSLHI
Higher 8-bit of word logical shift left.
@ LSRWN
Word logical shift right N bits.
@ WRAPPER
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
@ LSLLOOP
A loop of single logical shift left instructions.
@ BRCOND
AVR conditional branches.
bool isProgramMemoryAccess(MemSDNode const *N)
Definition: AVR.h:75
@ ProgramMemory
Definition: AVR.h:45
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:119
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ AVR_BUILTIN
Used for special AVR rtlib functions which have an "optimized" convention to preserve registers.
Definition: CallingConv.h:180
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:749
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1069
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1065
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1206
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:713
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1098
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1208
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1209
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:779
@ GlobalAddress
Definition: ISDOpcodes.h:78
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:898
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:229
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:773
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1020
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1207
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:1003
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:726
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
Definition: ISDOpcodes.h:222
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1094
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:71
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:650
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:704
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:776
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:741
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1185
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1210
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:988
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:794
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:679
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1199
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1037
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:782
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1089
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:1013
@ BlockAddress
Definition: ISDOpcodes.h:84
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:762
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
@ AssertZext
Definition: ISDOpcodes.h:62
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1396
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1447
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:148
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
@ Undef
Value of the register doesn't matter.
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:48
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
static void analyzeReturnValues(const SmallVectorImpl< ArgT > &Args, CCState &CCInfo, bool Tiny)
Analyze incoming and outgoing value of returning from a function.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static const MCPhysReg RegList16Tiny[]
static const MCPhysReg RegList8Tiny[]
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool Tiny)
Analyze incoming and outgoing function arguments.
static const MCPhysReg RegList16AVR[]
static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl< ArgT > &Args)
Count the total number of bytes needed to pass or return these arguments.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC)
IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
static bool isCopyMulResult(MachineBasicBlock::iterator const &I)
static void insertMultibyteShift(MachineInstr &MI, MachineBasicBlock *BB, MutableArrayRef< std::pair< Register, int > > Regs, ISD::NodeType Opc, int64_t ShiftAmt)
static const MCPhysReg RegList8AVR[]
Registers for calling conventions, ordered in reverse as required by ABI.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:860
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:351
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:299
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:160
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:194
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
This contains information for each constraint that we are lowering.
This structure contains all information that is necessary for lowering calls.