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AVRISelLowering.h
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1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that AVR uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_AVR_ISEL_LOWERING_H
15 #define LLVM_AVR_ISEL_LOWERING_H
16 
19 
20 namespace llvm {
21 
22 namespace AVRISD {
23 
24 /// AVR Specific DAG Nodes
25 enum NodeType {
26  /// Start the numbering where the builtin ops leave off.
28  /// Return from subroutine.
30  /// Return from ISR.
32  /// Represents an abstract call instruction,
33  /// which includes a bunch of information.
35  /// A wrapper node for TargetConstantPool,
36  /// TargetExternalSymbol, and TargetGlobalAddress.
38  LSL, ///< Logical shift left.
39  LSLBN, ///< Byte logical shift left N bits.
40  LSLWN, ///< Word logical shift left N bits.
41  LSLHI, ///< Higher 8-bit of word logical shift left.
42  LSR, ///< Logical shift right.
43  LSRBN, ///< Byte logical shift right N bits.
44  LSRWN, ///< Word logical shift right N bits.
45  LSRLO, ///< Lower 8-bit of word logical shift right.
46  ASR, ///< Arithmetic shift right.
47  ASRBN, ///< Byte arithmetic shift right N bits.
48  ASRWN, ///< Word arithmetic shift right N bits.
49  ASRLO, ///< Lower 8-bit of word arithmetic shift right.
50  ROR, ///< Bit rotate right.
51  ROL, ///< Bit rotate left.
52  LSLLOOP, ///< A loop of single logical shift left instructions.
53  LSRLOOP, ///< A loop of single logical shift right instructions.
54  ROLLOOP, ///< A loop of single left bit rotate instructions.
55  RORLOOP, ///< A loop of single right bit rotate instructions.
56  ASRLOOP, ///< A loop of single arithmetic shift right instructions.
57  /// AVR conditional branches. Operand 0 is the chain operand, operand 1
58  /// is the block to branch if condition is true, operand 2 is the
59  /// condition code, and operand 3 is the flag operand produced by a CMP
60  /// or TEST instruction.
62  /// Compare instruction.
63  CMP,
64  /// Compare with carry instruction.
66  /// Test for zero or minus instruction.
67  TST,
68  /// Swap Rd[7:4] <-> Rd[3:0].
70  /// Operand 0 and operand 1 are selection variable, operand 2
71  /// is condition code and operand 3 is flag operand.
73 };
74 
75 } // end of namespace AVRISD
76 
77 class AVRSubtarget;
78 class AVRTargetMachine;
79 
80 /// Performs target lowering for the AVR.
82 public:
83  explicit AVRTargetLowering(const AVRTargetMachine &TM,
84  const AVRSubtarget &STI);
85 
86 public:
87  MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
88  return MVT::i8;
89  }
90 
92  return MVT::i8;
93  }
94 
95  const char *getTargetNodeName(unsigned Opcode) const override;
96 
97  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
98 
100  SelectionDAG &DAG) const override;
101 
102  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
103  unsigned AS,
104  Instruction *I = nullptr) const override;
105 
108  SelectionDAG &DAG) const override;
109 
111  SDValue &Offset, ISD::MemIndexedMode &AM,
112  SelectionDAG &DAG) const override;
113 
114  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
115 
117  EVT VT) const override;
118 
121  MachineBasicBlock *MBB) const override;
122 
123  ConstraintType getConstraintType(StringRef Constraint) const override;
124 
126  getSingleConstraintMatchWeight(AsmOperandInfo &info,
127  const char *constraint) const override;
128 
129  std::pair<unsigned, const TargetRegisterClass *>
131  StringRef Constraint, MVT VT) const override;
132 
133  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
134 
135  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
136  std::vector<SDValue> &Ops,
137  SelectionDAG &DAG) const override;
138 
139  Register getRegisterByName(const char *RegName, LLT VT,
140  const MachineFunction &MF) const override;
141 
143  const DataLayout &DL) const override {
144  return false;
145  }
146 
147 private:
148  SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
149  SelectionDAG &DAG, SDLoc dl) const;
150  SDValue getAVRCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
151  SDLoc dl) const;
152  SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
153  SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
154  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
155  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
156  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
157  SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
158  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
159  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
160  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
161 
162  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
163  bool isVarArg,
165  LLVMContext &Context) const override;
166 
167  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
169  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
170  SelectionDAG &DAG) const override;
171  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
172  bool isVarArg,
174  const SDLoc &dl, SelectionDAG &DAG,
175  SmallVectorImpl<SDValue> &InVals) const override;
177  SmallVectorImpl<SDValue> &InVals) const override;
178  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
179  CallingConv::ID CallConv, bool isVarArg,
181  const SDLoc &dl, SelectionDAG &DAG,
182  SmallVectorImpl<SDValue> &InVals) const;
183 
184 protected:
186 
187 private:
188  MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const;
190  MachineBasicBlock *insertCopyR1(MachineInstr &MI,
191  MachineBasicBlock *BB) const;
192  MachineBasicBlock *insertAtomicArithmeticOp(MachineInstr &MI,
194  unsigned Opcode, int Width) const;
195 };
196 
197 } // end namespace llvm
198 
199 #endif // LLVM_AVR_ISEL_LOWERING_H
llvm::AVRTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: AVRISelLowering.cpp:1083
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1373
llvm::AVRISD::ROR
@ ROR
Bit rotate right.
Definition: AVRISelLowering.h:50
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AVRISD::FIRST_NUMBER
@ FIRST_NUMBER
Start the numbering where the builtin ops leave off.
Definition: AVRISelLowering.h:27
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1103
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::AVRTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: AVRISelLowering.cpp:2037
llvm::AVRTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: AVRISelLowering.cpp:268
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4495
llvm::AVRTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: AVRISelLowering.cpp:237
llvm::AVRTargetMachine
A generic AVR implementation.
Definition: AVRTargetMachine.h:28
llvm::AVRISD::ROLLOOP
@ ROLLOOP
A loop of single left bit rotate instructions.
Definition: AVRISelLowering.h:54
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:462
llvm::AVRISD::SELECT_CC
@ SELECT_CC
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
Definition: AVRISelLowering.h:72
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::AVRISD::LSLHI
@ LSLHI
Higher 8-bit of word logical shift left.
Definition: AVRISelLowering.h:41
llvm::AVRISD::ASRWN
@ ASRWN
Word arithmetic shift right N bits.
Definition: AVRISelLowering.h:48
llvm::AVRISD::CMPC
@ CMPC
Compare with carry instruction.
Definition: AVRISelLowering.h:65
llvm::AVRISD::LSLLOOP
@ LSLLOOP
A loop of single logical shift left instructions.
Definition: AVRISelLowering.h:52
llvm::AVRTargetLowering::getPreIndexedAddressParts
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
Definition: AVRISelLowering.cpp:980
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:830
llvm::AVRTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
Definition: AVRISelLowering.cpp:921
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::AVRISD::RETI_FLAG
@ RETI_FLAG
Return from ISR.
Definition: AVRISelLowering.h:31
llvm::AVRISD::LSLWN
@ LSLWN
Word logical shift left N bits.
Definition: AVRISelLowering.h:40
llvm::AVRISD::LSL
@ LSL
Logical shift left.
Definition: AVRISelLowering.h:38
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::AVRISD::CALL
@ CALL
Represents an abstract call instruction, which includes a bunch of information.
Definition: AVRISelLowering.h:34
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:33
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
TargetLowering.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::AVRISD::ASR
@ ASR
Arithmetic shift right.
Definition: AVRISelLowering.h:46
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::AVRSubtarget
A specific AVR target MCU.
Definition: AVRSubtarget.h:31
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3446
llvm::AVRISD::SWAP
@ SWAP
Swap Rd[7:4] <-> Rd[3:0].
Definition: AVRISelLowering.h:69
llvm::Instruction
Definition: Instruction.h:42
llvm::AVRTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: AVRISelLowering.cpp:2235
llvm::AVRTargetLowering::getCmpLibcallReturnType
MVT::SimpleValueType getCmpLibcallReturnType() const override
Return the ValueType for comparison libcalls.
Definition: AVRISelLowering.h:91
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AVRTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: AVRISelLowering.cpp:1878
llvm::AVRTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: AVRISelLowering.cpp:2048
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::AVRISD::TST
@ TST
Test for zero or minus instruction.
Definition: AVRISelLowering.h:67
llvm::AVRISD::NodeType
NodeType
AVR Specific DAG Nodes.
Definition: AVRISelLowering.h:25
llvm::AVRTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: AVRISelLowering.cpp:1994
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::AVRISD::ASRLOOP
@ ASRLOOP
A loop of single arithmetic shift right instructions.
Definition: AVRISelLowering.h:56
llvm::AVRTargetLowering
Performs target lowering for the AVR.
Definition: AVRISelLowering.h:81
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AVRTargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: AVRISelLowering.h:87
llvm::AVRISD::LSRBN
@ LSRBN
Byte logical shift right N bits.
Definition: AVRISelLowering.h:43
llvm::AVRTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: AVRISelLowering.cpp:887
llvm::AVRISD::ROL
@ ROL
Bit rotate left.
Definition: AVRISelLowering.h:51
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::AVRTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: AVRISelLowering.cpp:2164
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:4079
llvm::AVRISD::LSRWN
@ LSRWN
Word logical shift right N bits.
Definition: AVRISelLowering.h:44
llvm::AVRTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: AVRISelLowering.cpp:950
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::AVRTargetLowering::getPostIndexedAddressParts
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
Definition: AVRISelLowering.cpp:1036
info
lazy value info
Definition: LazyValueInfo.cpp:58
llvm::AVRTargetLowering::AVRTargetLowering
AVRTargetLowering(const AVRTargetMachine &TM, const AVRSubtarget &STI)
Definition: AVRISelLowering.cpp:36
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::AVRTargetLowering::Subtarget
const AVRSubtarget & Subtarget
Definition: AVRISelLowering.h:185
llvm::AVRISD::BRCOND
@ BRCOND
AVR conditional branches.
Definition: AVRISelLowering.h:61
llvm::AVRISD::LSR
@ LSR
Logical shift right.
Definition: AVRISelLowering.h:42
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1307
llvm::AVRISD::ASRBN
@ ASRBN
Byte arithmetic shift right N bits.
Definition: AVRISelLowering.h:47
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1757
CallingConvLower.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4505
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::AVRISD::WRAPPER
@ WRAPPER
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Definition: AVRISelLowering.h:37
llvm::AVRTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: AVRISelLowering.cpp:2342
N
#define N
llvm::AVRISD::RET_FLAG
@ RET_FLAG
Return from subroutine.
Definition: AVRISelLowering.h:29
llvm::AVRISD::LSRLO
@ LSRLO
Lower 8-bit of word logical shift right.
Definition: AVRISelLowering.h:45
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::AVRISD::LSRLOOP
@ LSRLOOP
A loop of single logical shift right instructions.
Definition: AVRISelLowering.h:53
llvm::AVRISD::ASRLO
@ ASRLO
Lower 8-bit of word arithmetic shift right.
Definition: AVRISelLowering.h:49
RegName
#define RegName(no)
llvm::AVRISD::CMP
@ CMP
Compare instruction.
Definition: AVRISelLowering.h:63
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::AVRTargetLowering::shouldSplitFunctionArgumentsAsLittleEndian
bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const override
For most targets, an LLVM type must be broken down into multiple smaller types.
Definition: AVRISelLowering.h:142
llvm::AVRISD::LSLBN
@ LSLBN
Byte logical shift left N bits.
Definition: AVRISelLowering.h:39
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::AVRISD::RORLOOP
@ RORLOOP
A loop of single right bit rotate instructions.
Definition: AVRISelLowering.h:55