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14 #ifndef LLVM_AVR_ISEL_LOWERING_H
15 #define LLVM_AVR_ISEL_LOWERING_H
81 class AVRTargetMachine;
120 EVT VT)
const override;
130 const char *constraint)
const override;
132 std::pair<unsigned, const TargetRegisterClass *>
139 std::vector<SDValue> &Ops,
152 unsigned ExpansionFactor)
const override {
205 unsigned Opcode,
int Width)
const;
210 #endif // LLVM_AVR_ISEL_LOWERING_H
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
This is an optimization pass for GlobalISel generic memory operations.
@ FIRST_NUMBER
Start the numbering where the builtin ops leave off.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
A generic AVR implementation.
@ LSRW
Wide logical shift right.
@ ROLLOOP
A loop of single left bit rotate instructions.
@ LSLW
Wide logical shift left.
Represents one node in the SelectionDAG.
@ SELECT_CC
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
@ LSLHI
Higher 8-bit of word logical shift left.
@ ASRWN
Word arithmetic shift right N bits.
@ CMPC
Compare with carry instruction.
@ LSLLOOP
A loop of single logical shift left instructions.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
Function Alias Analysis Results
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
@ RETI_FLAG
Return from ISR.
@ LSLWN
Word logical shift left N bits.
unsigned const TargetRegisterInfo * TRI
@ CALL
Represents an abstract call instruction, which includes a bunch of information.
@ ASRW
Wide arithmetic shift right.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
@ ASR
Arithmetic shift right.
A specific AVR target MCU.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
@ SWAP
Swap Rd[7:4] <-> Rd[3:0].
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
MVT::SimpleValueType getCmpLibcallReturnType() const override
Return the ValueType for comparison libcalls.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
@ TST
Test for zero or minus instruction.
NodeType
AVR Specific DAG Nodes.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Representation of each machine instruction.
@ ASRLOOP
A loop of single arithmetic shift right instructions.
Performs target lowering for the AVR.
This is an important class for using LLVM in a threaded context.
MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
@ LSRBN
Byte logical shift right N bits.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
This structure contains all information that is necessary for lowering calls.
@ LSRWN
Word logical shift right N bits.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
AVRTargetLowering(const AVRTargetMachine &TM, const AVRSubtarget &STI)
const AVRSubtarget & Subtarget
@ BRCOND
AVR conditional branches.
@ LSR
Logical shift right.
StringRef - Represent a constant reference to a string, i.e.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ ASRBN
Byte arithmetic shift right N bits.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
Wrapper class representing virtual and physical registers.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
@ WRAPPER
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
@ RET_FLAG
Return from subroutine.
@ LSRLO
Lower 8-bit of word logical shift right.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
@ LSRLOOP
A loop of single logical shift right instructions.
@ ASRLO
Lower 8-bit of word arithmetic shift right.
@ CMP
Compare instruction.
const char LLVMTargetMachineRef TM
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const override
For most targets, an LLVM type must be broken down into multiple smaller types.
@ LSLBN
Byte logical shift left N bits.
@ RORLOOP
A loop of single right bit rotate instructions.