LLVM 17.0.0git
AVRInstrInfo.h
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1//===-- AVRInstrInfo.h - AVR Instruction Information ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AVR implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_AVR_INSTR_INFO_H
14#define LLVM_AVR_INSTR_INFO_H
15
17
18#include "AVRRegisterInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#include "AVRGenInstrInfo.inc"
22#undef GET_INSTRINFO_HEADER
23
24namespace llvm {
25
26namespace AVRCC {
27
28/// AVR specific condition codes.
29/// These correspond to `AVR_*_COND` in `AVRInstrInfo.td`.
30/// They must be kept in synch.
32 COND_EQ, //!< Equal
33 COND_NE, //!< Not equal
34 COND_GE, //!< Greater than or equal
35 COND_LT, //!< Less than
36 COND_SH, //!< Unsigned same or higher
37 COND_LO, //!< Unsigned lower
38 COND_MI, //!< Minus
39 COND_PL, //!< Plus
41};
42
43} // end of namespace AVRCC
44
45namespace AVRII {
46
47/// Specifies a target operand flag.
48enum TOF {
50
51 /// On a symbol operand, this represents the lo part.
52 MO_LO = (1 << 1),
53
54 /// On a symbol operand, this represents the hi part.
55 MO_HI = (1 << 2),
56
57 /// On a symbol operand, this represents it has to be negated.
58 MO_NEG = (1 << 3)
59};
60
61} // end of namespace AVRII
62
63/// Utilities related to the AVR instruction set.
65public:
66 explicit AVRInstrInfo();
67
68 const AVRRegisterInfo &getRegisterInfo() const { return RI; }
70 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
72 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
73
75 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
76 bool KillSrc) const override;
79 bool isKill, int FrameIndex,
80 const TargetRegisterClass *RC,
82 Register VReg) const override;
85 int FrameIndex, const TargetRegisterClass *RC,
87 Register VReg) const override;
88 unsigned isLoadFromStackSlot(const MachineInstr &MI,
89 int &FrameIndex) const override;
90 unsigned isStoreToStackSlot(const MachineInstr &MI,
91 int &FrameIndex) const override;
92
93 // Branch analysis.
97 bool AllowModify = false) const override;
100 const DebugLoc &DL,
101 int *BytesAdded = nullptr) const override;
103 int *BytesRemoved = nullptr) const override;
104 bool
106
107 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
108
109 bool isBranchOffsetInRange(unsigned BranchOpc,
110 int64_t BrOffset) const override;
111
113 MachineBasicBlock &NewDestBB,
114 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
115 int64_t BrOffset, RegScavenger *RS) const override;
116
117private:
118 const AVRRegisterInfo RI;
119};
120
121} // end namespace llvm
122
123#endif // LLVM_AVR_INSTR_INFO_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
SmallVector< MachineOperand, 4 > Cond
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:64
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const
AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
const AVRRegisterInfo & getRegisterInfo() const
Definition: AVRInstrInfo.h:68
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
Utilities relating to AVR registers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
Representation of each machine instruction.
Definition: MachineInstr.h:68
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:31
@ COND_SH
Unsigned same or higher.
Definition: AVRInstrInfo.h:36
@ COND_GE
Greater than or equal.
Definition: AVRInstrInfo.h:34
@ COND_MI
Minus.
Definition: AVRInstrInfo.h:38
@ COND_LO
Unsigned lower.
Definition: AVRInstrInfo.h:37
@ COND_LT
Less than.
Definition: AVRInstrInfo.h:35
@ COND_PL
Plus.
Definition: AVRInstrInfo.h:39
@ COND_EQ
Equal.
Definition: AVRInstrInfo.h:32
@ COND_NE
Not equal.
Definition: AVRInstrInfo.h:33
TOF
Specifies a target operand flag.
Definition: AVRInstrInfo.h:48
@ MO_HI
On a symbol operand, this represents the hi part.
Definition: AVRInstrInfo.h:55
@ MO_NEG
On a symbol operand, this represents it has to be negated.
Definition: AVRInstrInfo.h:58
@ MO_LO
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:52
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18