LLVM 20.0.0git
AVRInstrInfo.h
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1//===-- AVRInstrInfo.h - AVR Instruction Information ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the AVR implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_AVR_INSTR_INFO_H
14#define LLVM_AVR_INSTR_INFO_H
15
17
18#include "AVRRegisterInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#include "AVRGenInstrInfo.inc"
22#undef GET_INSTRINFO_HEADER
23
24namespace llvm {
25
26class AVRSubtarget;
27
28namespace AVRCC {
29
30/// AVR specific condition codes.
31/// These correspond to `AVR_*_COND` in `AVRInstrInfo.td`.
32/// They must be kept in synch.
34 COND_EQ, //!< Equal
35 COND_NE, //!< Not equal
36 COND_GE, //!< Greater than or equal
37 COND_LT, //!< Less than
38 COND_SH, //!< Unsigned same or higher
39 COND_LO, //!< Unsigned lower
40 COND_MI, //!< Minus
41 COND_PL, //!< Plus
43};
44
45} // end of namespace AVRCC
46
47namespace AVRII {
48
49/// Specifies a target operand flag.
50enum TOF {
52
53 /// On a symbol operand, this represents the lo part.
54 MO_LO = (1 << 1),
55
56 /// On a symbol operand, this represents the hi part.
57 MO_HI = (1 << 2),
58
59 /// On a symbol operand, this represents it has to be negated.
60 MO_NEG = (1 << 3)
61};
62
63} // end of namespace AVRII
64
65/// Utilities related to the AVR instruction set.
67public:
68 explicit AVRInstrInfo(AVRSubtarget &STI);
69
70 const AVRRegisterInfo &getRegisterInfo() const { return RI; }
72 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
74 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
75
77 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
78 bool KillSrc) const override;
81 bool isKill, int FrameIndex,
82 const TargetRegisterClass *RC,
84 Register VReg) const override;
87 int FrameIndex, const TargetRegisterClass *RC,
89 Register VReg) const override;
91 int &FrameIndex) const override;
93 int &FrameIndex) const override;
94
95 // Branch analysis.
99 bool AllowModify = false) const override;
102 const DebugLoc &DL,
103 int *BytesAdded = nullptr) const override;
105 int *BytesRemoved = nullptr) const override;
106 bool
108
109 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
110
111 bool isBranchOffsetInRange(unsigned BranchOpc,
112 int64_t BrOffset) const override;
113
115 MachineBasicBlock &NewDestBB,
116 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
117 int64_t BrOffset, RegScavenger *RS) const override;
118
119private:
120 const AVRRegisterInfo RI;
121
122protected:
124};
125
126} // end namespace llvm
127
128#endif // LLVM_AVR_INSTR_INFO_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:66
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const
AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const
const AVRSubtarget & STI
Definition: AVRInstrInfo.h:123
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
const AVRRegisterInfo & getRegisterInfo() const
Definition: AVRInstrInfo.h:70
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
Utilities relating to AVR registers.
A specific AVR target MCU.
Definition: AVRSubtarget.h:32
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:33
@ COND_SH
Unsigned same or higher.
Definition: AVRInstrInfo.h:38
@ COND_GE
Greater than or equal.
Definition: AVRInstrInfo.h:36
@ COND_MI
Minus.
Definition: AVRInstrInfo.h:40
@ COND_LO
Unsigned lower.
Definition: AVRInstrInfo.h:39
@ COND_LT
Less than.
Definition: AVRInstrInfo.h:37
@ COND_PL
Plus.
Definition: AVRInstrInfo.h:41
@ COND_EQ
Equal.
Definition: AVRInstrInfo.h:34
@ COND_NE
Not equal.
Definition: AVRInstrInfo.h:35
TOF
Specifies a target operand flag.
Definition: AVRInstrInfo.h:50
@ MO_HI
On a symbol operand, this represents the hi part.
Definition: AVRInstrInfo.h:57
@ MO_NEG
On a symbol operand, this represents it has to be negated.
Definition: AVRInstrInfo.h:60
@ MO_LO
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:54
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18