33#define GET_INSTRINFO_CTOR_DTOR
34#include "AVRGenInstrInfo.inc"
50 if (AVR::DREGSRegClass.
contains(DestReg, SrcReg)) {
53 if (
STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) {
57 Register DestLo, DestHi, SrcLo, SrcHi;
59 TRI.splitReg(DestReg, DestLo, DestHi);
60 TRI.splitReg(SrcReg, SrcLo, SrcHi);
67 if (DestLo == SrcHi) {
80 if (AVR::GPR8RegClass.
contains(DestReg, SrcReg)) {
82 }
else if (SrcReg == AVR::SP && AVR::DREGSRegClass.
contains(DestReg)) {
84 }
else if (DestReg == AVR::SP && AVR::DREGSRegClass.
contains(SrcReg)) {
96 int &FrameIndex)
const {
97 switch (
MI.getOpcode()) {
100 if (
MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() &&
101 MI.getOperand(2).getImm() == 0) {
102 FrameIndex =
MI.getOperand(1).getIndex();
103 return MI.getOperand(0).getReg();
115 int &FrameIndex)
const {
116 switch (
MI.getOpcode()) {
118 case AVR::STDWPtrQRr: {
119 if (
MI.getOperand(0).isFI() &&
MI.getOperand(1).isImm() &&
120 MI.getOperand(1).getImm() == 0) {
121 FrameIndex =
MI.getOperand(0).getIndex();
122 return MI.getOperand(2).getReg();
150 if (
TRI->isTypeLegalForClass(*RC, MVT::i8)) {
151 Opcode = AVR::STDPtrQRr;
152 }
else if (
TRI->isTypeLegalForClass(*RC, MVT::i16)) {
153 Opcode = AVR::STDWPtrQRr;
180 if (
TRI->isTypeLegalForClass(*RC, MVT::i8)) {
181 Opcode = AVR::LDDRdPtrQ;
182 }
else if (
TRI->isTypeLegalForClass(*RC, MVT::i16)) {
185 Opcode = AVR::LDDWRdYQ;
201 return get(AVR::BREQk);
203 return get(AVR::BRNEk);
205 return get(AVR::BRGEk);
207 return get(AVR::BRLTk);
209 return get(AVR::BRSHk);
211 return get(AVR::BRLOk);
213 return get(AVR::BRMIk);
215 return get(AVR::BRPLk);
269 bool AllowModify)
const {
275 while (
I !=
MBB.begin()) {
277 if (
I->isDebugInstr()) {
283 if (!isUnpredicatedTerminator(*
I)) {
289 if (!
I->getDesc().isBranch()) {
295 if (
I->getOpcode() == AVR::RJMPk) {
299 TBB =
I->getOperand(0).getMBB();
304 MBB.erase(std::next(
I),
MBB.end());
310 if (
MBB.isLayoutSuccessor(
I->getOperand(0).getMBB())) {
312 I->eraseFromParent();
314 UnCondBrIter =
MBB.end();
319 TBB =
I->getOperand(0).getMBB();
332 if (AllowModify && UnCondBrIter !=
MBB.end() &&
333 MBB.isLayoutSuccessor(TargetBB)) {
356 .
addMBB(UnCondBrIter->getOperand(0).getMBB());
360 OldInst->eraseFromParent();
361 UnCondBrIter->eraseFromParent();
364 UnCondBrIter =
MBB.end();
370 TBB =
I->getOperand(0).getMBB();
382 if (
TBB !=
I->getOperand(0).getMBB()) {
388 if (OldBranchCode == BranchCode) {
407 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
409 "AVR branch conditions have one component!");
412 assert(!FBB &&
"Unconditional branch with multiple successors!");
440 int *BytesRemoved)
const {
447 while (
I !=
MBB.begin()) {
449 if (
I->isDebugInstr()) {
454 if (
I->getOpcode() != AVR::RJMPk &&
462 I->eraseFromParent();
472 assert(
Cond.size() == 1 &&
"Invalid AVR branch condition!");
481 unsigned Opcode =
MI.getOpcode();
487 return Desc.getSize();
489 case TargetOpcode::EH_LABEL:
490 case TargetOpcode::IMPLICIT_DEF:
491 case TargetOpcode::KILL:
492 case TargetOpcode::DBG_VALUE:
494 case TargetOpcode::INLINEASM:
495 case TargetOpcode::INLINEASM_BR: {
502 return TII.getInlineAsmLength(
MI.getOperand(0).getSymbolName(),
510 switch (
MI.getOpcode()) {
525 return MI.getOperand(0).getMBB();
528 return MI.getOperand(1).getMBB();
538 int64_t BrOffset)
const {
548 return isIntN(13, BrOffset);
559 return isIntN(7, BrOffset);
573 if (
STI.hasJMPCALL())
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const HexagonInstrInfo * TII
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
AVRInstrInfo(AVRSubtarget &STI)
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const
AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
Contains AVR-specific information for each MachineFunction.
void setHasSpills(bool B)
Utilities relating to AVR registers.
A specific AVR target MCU.
const AVRInstrInfo * getInstrInfo() const override
const AVRRegisterInfo * getRegisterInfo() const override
A generic AVR implementation.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Describe properties that are true of each instruction in the target description file.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Wrapper class representing physical registers. Should be passed by value.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
static MachineOperand CreateImm(int64_t Val)
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CondCodes
AVR specific condition codes.
@ COND_SH
Unsigned same or higher.
@ COND_GE
Greater than or equal.
@ Undef
Value of the register doesn't matter.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
unsigned getKillRegState(bool B)
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Description of the encoding of one expression Op.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.