LLVM  16.0.0git
AVRInstrInfo.cpp
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1 //===-- AVRInstrInfo.cpp - AVR Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AVR implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AVRInstrInfo.h"
14 
15 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/IR/Constants.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/TargetRegistry.h"
24 #include "llvm/Support/Debug.h"
26 
27 #include "AVR.h"
28 #include "AVRMachineFunctionInfo.h"
29 #include "AVRRegisterInfo.h"
30 #include "AVRTargetMachine.h"
32 
33 #define GET_INSTRINFO_CTOR_DTOR
34 #include "AVRGenInstrInfo.inc"
35 
36 namespace llvm {
37 
39  : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {}
40 
43  const DebugLoc &DL, MCRegister DestReg,
44  MCRegister SrcReg, bool KillSrc) const {
45  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
46  const AVRRegisterInfo &TRI = *STI.getRegisterInfo();
47  unsigned Opc;
48 
49  if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) {
50  // If our AVR has `movw`, let's emit that; otherwise let's emit two separate
51  // `mov`s.
52  if (STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) {
53  BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)
54  .addReg(SrcReg, getKillRegState(KillSrc));
55  } else {
56  Register DestLo, DestHi, SrcLo, SrcHi;
57 
58  TRI.splitReg(DestReg, DestLo, DestHi);
59  TRI.splitReg(SrcReg, SrcLo, SrcHi);
60 
61  if (DestLo == SrcHi) {
62  BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi)
63  .addReg(SrcHi, getKillRegState(KillSrc));
64  BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo)
65  .addReg(SrcLo, getKillRegState(KillSrc));
66  } else {
67  BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo)
68  .addReg(SrcLo, getKillRegState(KillSrc));
69  BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi)
70  .addReg(SrcHi, getKillRegState(KillSrc));
71  }
72  }
73  } else {
74  if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) {
75  Opc = AVR::MOVRdRr;
76  } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) {
77  Opc = AVR::SPREAD;
78  } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) {
79  Opc = AVR::SPWRITE;
80  } else {
81  llvm_unreachable("Impossible reg-to-reg copy");
82  }
83 
84  BuildMI(MBB, MI, DL, get(Opc), DestReg)
85  .addReg(SrcReg, getKillRegState(KillSrc));
86  }
87 }
88 
90  int &FrameIndex) const {
91  switch (MI.getOpcode()) {
92  case AVR::LDDRdPtrQ:
93  case AVR::LDDWRdYQ: { //: FIXME: remove this once PR13375 gets fixed
94  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
95  MI.getOperand(2).getImm() == 0) {
96  FrameIndex = MI.getOperand(1).getIndex();
97  return MI.getOperand(0).getReg();
98  }
99  break;
100  }
101  default:
102  break;
103  }
104 
105  return 0;
106 }
107 
109  int &FrameIndex) const {
110  switch (MI.getOpcode()) {
111  case AVR::STDPtrQRr:
112  case AVR::STDWPtrQRr: {
113  if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
114  MI.getOperand(1).getImm() == 0) {
115  FrameIndex = MI.getOperand(0).getIndex();
116  return MI.getOperand(2).getReg();
117  }
118  break;
119  }
120  default:
121  break;
122  }
123 
124  return 0;
125 }
126 
129  Register SrcReg, bool isKill,
130  int FrameIndex,
131  const TargetRegisterClass *RC,
132  const TargetRegisterInfo *TRI) const {
133  MachineFunction &MF = *MBB.getParent();
135 
136  AFI->setHasSpills(true);
137 
138  const MachineFrameInfo &MFI = MF.getFrameInfo();
139 
144 
145  unsigned Opcode = 0;
146  if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
147  Opcode = AVR::STDPtrQRr;
148  } else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
149  Opcode = AVR::STDWPtrQRr;
150  } else {
151  llvm_unreachable("Cannot store this register into a stack slot!");
152  }
153 
154  BuildMI(MBB, MI, DebugLoc(), get(Opcode))
156  .addImm(0)
157  .addReg(SrcReg, getKillRegState(isKill))
158  .addMemOperand(MMO);
159 }
160 
163  Register DestReg, int FrameIndex,
164  const TargetRegisterClass *RC,
165  const TargetRegisterInfo *TRI) const {
166  MachineFunction &MF = *MBB.getParent();
167  const MachineFrameInfo &MFI = MF.getFrameInfo();
168 
173 
174  unsigned Opcode = 0;
175  if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
176  Opcode = AVR::LDDRdPtrQ;
177  } else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
178  // Opcode = AVR::LDDWRdPtrQ;
179  //: FIXME: remove this once PR13375 gets fixed
180  Opcode = AVR::LDDWRdYQ;
181  } else {
182  llvm_unreachable("Cannot load this register from a stack slot!");
183  }
184 
185  BuildMI(MBB, MI, DebugLoc(), get(Opcode), DestReg)
187  .addImm(0)
188  .addMemOperand(MMO);
189 }
190 
192  switch (CC) {
193  default:
194  llvm_unreachable("Unknown condition code!");
195  case AVRCC::COND_EQ:
196  return get(AVR::BREQk);
197  case AVRCC::COND_NE:
198  return get(AVR::BRNEk);
199  case AVRCC::COND_GE:
200  return get(AVR::BRGEk);
201  case AVRCC::COND_LT:
202  return get(AVR::BRLTk);
203  case AVRCC::COND_SH:
204  return get(AVR::BRSHk);
205  case AVRCC::COND_LO:
206  return get(AVR::BRLOk);
207  case AVRCC::COND_MI:
208  return get(AVR::BRMIk);
209  case AVRCC::COND_PL:
210  return get(AVR::BRPLk);
211  }
212 }
213 
215  switch (Opc) {
216  default:
217  return AVRCC::COND_INVALID;
218  case AVR::BREQk:
219  return AVRCC::COND_EQ;
220  case AVR::BRNEk:
221  return AVRCC::COND_NE;
222  case AVR::BRSHk:
223  return AVRCC::COND_SH;
224  case AVR::BRLOk:
225  return AVRCC::COND_LO;
226  case AVR::BRMIk:
227  return AVRCC::COND_MI;
228  case AVR::BRPLk:
229  return AVRCC::COND_PL;
230  case AVR::BRGEk:
231  return AVRCC::COND_GE;
232  case AVR::BRLTk:
233  return AVRCC::COND_LT;
234  }
235 }
236 
238  switch (CC) {
239  default:
240  llvm_unreachable("Invalid condition!");
241  case AVRCC::COND_EQ:
242  return AVRCC::COND_NE;
243  case AVRCC::COND_NE:
244  return AVRCC::COND_EQ;
245  case AVRCC::COND_SH:
246  return AVRCC::COND_LO;
247  case AVRCC::COND_LO:
248  return AVRCC::COND_SH;
249  case AVRCC::COND_GE:
250  return AVRCC::COND_LT;
251  case AVRCC::COND_LT:
252  return AVRCC::COND_GE;
253  case AVRCC::COND_MI:
254  return AVRCC::COND_PL;
255  case AVRCC::COND_PL:
256  return AVRCC::COND_MI;
257  }
258 }
259 
262  MachineBasicBlock *&FBB,
264  bool AllowModify) const {
265  // Start from the bottom of the block and work up, examining the
266  // terminator instructions.
268  MachineBasicBlock::iterator UnCondBrIter = MBB.end();
269 
270  while (I != MBB.begin()) {
271  --I;
272  if (I->isDebugInstr()) {
273  continue;
274  }
275 
276  // Working from the bottom, when we see a non-terminator
277  // instruction, we're done.
278  if (!isUnpredicatedTerminator(*I)) {
279  break;
280  }
281 
282  // A terminator that isn't a branch can't easily be handled
283  // by this analysis.
284  if (!I->getDesc().isBranch()) {
285  return true;
286  }
287 
288  // Handle unconditional branches.
289  //: TODO: add here jmp
290  if (I->getOpcode() == AVR::RJMPk) {
291  UnCondBrIter = I;
292 
293  if (!AllowModify) {
294  TBB = I->getOperand(0).getMBB();
295  continue;
296  }
297 
298  // If the block has any instructions after a JMP, delete them.
299  MBB.erase(std::next(I), MBB.end());
300 
301  Cond.clear();
302  FBB = nullptr;
303 
304  // Delete the JMP if it's equivalent to a fall-through.
305  if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
306  TBB = nullptr;
307  I->eraseFromParent();
308  I = MBB.end();
309  UnCondBrIter = MBB.end();
310  continue;
311  }
312 
313  // TBB is used to indicate the unconditinal destination.
314  TBB = I->getOperand(0).getMBB();
315  continue;
316  }
317 
318  // Handle conditional branches.
319  AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
320  if (BranchCode == AVRCC::COND_INVALID) {
321  return true; // Can't handle indirect branch.
322  }
323 
324  // Working from the bottom, handle the first conditional branch.
325  if (Cond.empty()) {
326  MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
327  if (AllowModify && UnCondBrIter != MBB.end() &&
328  MBB.isLayoutSuccessor(TargetBB)) {
329  // If we can modify the code and it ends in something like:
330  //
331  // jCC L1
332  // jmp L2
333  // L1:
334  // ...
335  // L2:
336  //
337  // Then we can change this to:
338  //
339  // jnCC L2
340  // L1:
341  // ...
342  // L2:
343  //
344  // Which is a bit more efficient.
345  // We conditionally jump to the fall-through block.
346  BranchCode = getOppositeCondition(BranchCode);
347  unsigned JNCC = getBrCond(BranchCode).getOpcode();
348  MachineBasicBlock::iterator OldInst = I;
349 
350  BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
351  .addMBB(UnCondBrIter->getOperand(0).getMBB());
352  BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(AVR::RJMPk))
353  .addMBB(TargetBB);
354 
355  OldInst->eraseFromParent();
356  UnCondBrIter->eraseFromParent();
357 
358  // Restart the analysis.
359  UnCondBrIter = MBB.end();
360  I = MBB.end();
361  continue;
362  }
363 
364  FBB = TBB;
365  TBB = I->getOperand(0).getMBB();
366  Cond.push_back(MachineOperand::CreateImm(BranchCode));
367  continue;
368  }
369 
370  // Handle subsequent conditional branches. Only handle the case where all
371  // conditional branches branch to the same destination.
372  assert(Cond.size() == 1);
373  assert(TBB);
374 
375  // Only handle the case where all conditional branches branch to
376  // the same destination.
377  if (TBB != I->getOperand(0).getMBB()) {
378  return true;
379  }
380 
381  AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm();
382  // If the conditions are the same, we can leave them alone.
383  if (OldBranchCode == BranchCode) {
384  continue;
385  }
386 
387  return true;
388  }
389 
390  return false;
391 }
392 
395  MachineBasicBlock *FBB,
397  const DebugLoc &DL, int *BytesAdded) const {
398  if (BytesAdded)
399  *BytesAdded = 0;
400 
401  // Shouldn't be a fall through.
402  assert(TBB && "insertBranch must not be told to insert a fallthrough");
403  assert((Cond.size() == 1 || Cond.size() == 0) &&
404  "AVR branch conditions have one component!");
405 
406  if (Cond.empty()) {
407  assert(!FBB && "Unconditional branch with multiple successors!");
408  auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(TBB);
409  if (BytesAdded)
410  *BytesAdded += getInstSizeInBytes(MI);
411  return 1;
412  }
413 
414  // Conditional branch.
415  unsigned Count = 0;
416  AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm();
417  auto &CondMI = *BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
418 
419  if (BytesAdded)
420  *BytesAdded += getInstSizeInBytes(CondMI);
421  ++Count;
422 
423  if (FBB) {
424  // Two-way Conditional branch. Insert the second branch.
425  auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(FBB);
426  if (BytesAdded)
427  *BytesAdded += getInstSizeInBytes(MI);
428  ++Count;
429  }
430 
431  return Count;
432 }
433 
435  int *BytesRemoved) const {
436  if (BytesRemoved)
437  *BytesRemoved = 0;
438 
440  unsigned Count = 0;
441 
442  while (I != MBB.begin()) {
443  --I;
444  if (I->isDebugInstr()) {
445  continue;
446  }
447  //: TODO: add here the missing jmp instructions once they are implemented
448  // like jmp, {e}ijmp, and other cond branches, ...
449  if (I->getOpcode() != AVR::RJMPk &&
450  getCondFromBranchOpc(I->getOpcode()) == AVRCC::COND_INVALID) {
451  break;
452  }
453 
454  // Remove the branch.
455  if (BytesRemoved)
456  *BytesRemoved += getInstSizeInBytes(*I);
457  I->eraseFromParent();
458  I = MBB.end();
459  ++Count;
460  }
461 
462  return Count;
463 }
464 
467  assert(Cond.size() == 1 && "Invalid AVR branch condition!");
468 
469  AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm());
470  Cond[0].setImm(getOppositeCondition(CC));
471 
472  return false;
473 }
474 
476  unsigned Opcode = MI.getOpcode();
477 
478  switch (Opcode) {
479  // A regular instruction
480  default: {
481  const MCInstrDesc &Desc = get(Opcode);
482  return Desc.getSize();
483  }
485  case TargetOpcode::IMPLICIT_DEF:
486  case TargetOpcode::KILL:
487  case TargetOpcode::DBG_VALUE:
488  return 0;
491  const MachineFunction &MF = *MI.getParent()->getParent();
492  const AVRTargetMachine &TM =
493  static_cast<const AVRTargetMachine &>(MF.getTarget());
494  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
495  const TargetInstrInfo &TII = *STI.getInstrInfo();
496 
497  return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
498  *TM.getMCAsmInfo());
499  }
500  }
501 }
502 
505  switch (MI.getOpcode()) {
506  default:
507  llvm_unreachable("unexpected opcode!");
508  case AVR::JMPk:
509  case AVR::CALLk:
510  case AVR::RCALLk:
511  case AVR::RJMPk:
512  case AVR::BREQk:
513  case AVR::BRNEk:
514  case AVR::BRSHk:
515  case AVR::BRLOk:
516  case AVR::BRMIk:
517  case AVR::BRPLk:
518  case AVR::BRGEk:
519  case AVR::BRLTk:
520  return MI.getOperand(0).getMBB();
521  case AVR::BRBSsk:
522  case AVR::BRBCsk:
523  return MI.getOperand(1).getMBB();
524  case AVR::SBRCRrB:
525  case AVR::SBRSRrB:
526  case AVR::SBICAb:
527  case AVR::SBISAb:
528  llvm_unreachable("unimplemented branch instructions");
529  }
530 }
531 
532 bool AVRInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
533  int64_t BrOffset) const {
534 
535  switch (BranchOp) {
536  default:
537  llvm_unreachable("unexpected opcode!");
538  case AVR::JMPk:
539  case AVR::CALLk:
540  return true;
541  case AVR::RCALLk:
542  case AVR::RJMPk:
543  return isIntN(13, BrOffset);
544  case AVR::BRBSsk:
545  case AVR::BRBCsk:
546  case AVR::BREQk:
547  case AVR::BRNEk:
548  case AVR::BRSHk:
549  case AVR::BRLOk:
550  case AVR::BRMIk:
551  case AVR::BRPLk:
552  case AVR::BRGEk:
553  case AVR::BRLTk:
554  return isIntN(7, BrOffset);
555  }
556 }
557 
559  MachineBasicBlock &NewDestBB,
560  MachineBasicBlock &RestoreBB,
561  const DebugLoc &DL, int64_t BrOffset,
562  RegScavenger *RS) const {
563  // This method inserts a *direct* branch (JMP), despite its name.
564  // LLVM calls this method to fixup unconditional branches; it never calls
565  // insertBranch or some hypothetical "insertDirectBranch".
566  // See lib/CodeGen/RegisterRelaxation.cpp for details.
567  // We end up here when a jump is too long for a RJMP instruction.
568  BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB);
569 }
570 
571 } // end of namespace llvm
llvm::AVRCC::COND_INVALID
@ COND_INVALID
Definition: AVRInstrInfo.h:40
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:223
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AVRInstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Definition: AVRInstrInfo.cpp:532
llvm::AVRInstrInfo::getBrCond
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
Definition: AVRInstrInfo.cpp:191
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::AVRTargetMachine
A generic AVR implementation.
Definition: AVRTargetMachine.h:28
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
ErrorHandling.h
llvm::AVRInstrInfo::AVRInstrInfo
AVRInstrInfo()
Definition: AVRInstrInfo.cpp:38
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:1033
llvm::AVRSubtarget::hasMOVW
bool hasMOVW() const
Definition: AVRSubtarget.h:70
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::AVRCC::COND_LT
@ COND_LT
Less than.
Definition: AVRInstrInfo.h:35
STLExtras.h
llvm::AVRInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: AVRInstrInfo.cpp:41
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::AVRCC::COND_SH
@ COND_SH
Unsigned same or higher.
Definition: AVRInstrInfo.h:36
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1025
llvm::AVRInstrInfo::getCondFromBranchOpc
AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const
Definition: AVRInstrInfo.cpp:214
llvm::AVRCC::COND_PL
@ COND_PL
Plus.
Definition: AVRInstrInfo.h:39
llvm::MCInstrDesc::getSize
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:622
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
Constants.h
AVRGenInstrInfo
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::AVRSubtarget
A specific AVR target MCU.
Definition: AVRSubtarget.h:31
MCContext.h
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
llvm::AVRInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: AVRInstrInfo.cpp:465
llvm::AVRInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: AVRInstrInfo.cpp:475
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::AVRInstrInfo::getOppositeCondition
AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const
Definition: AVRInstrInfo.cpp:237
llvm::AVRInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: AVRInstrInfo.cpp:161
llvm::AVRSubtarget::getInstrInfo
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:41
llvm::isIntN
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:427
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::AVRCC::COND_GE
@ COND_GE
Greater than or equal.
Definition: AVRInstrInfo.h:34
llvm::AVRInstrInfo::insertIndirectBranch
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
Definition: AVRInstrInfo.cpp:558
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::AVRCC::CondCodes
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:31
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:470
llvm::AVRRegisterInfo
Utilities relating to AVR registers.
Definition: AVRRegisterInfo.h:24
llvm::AVRInstrInfo::getBranchDestBlock
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
Definition: AVRInstrInfo.cpp:504
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AVRCC::COND_NE
@ COND_NE
Not equal.
Definition: AVRInstrInfo.h:33
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:484
MachineConstantPool.h
llvm::AVRMachineFunctionInfo::setHasSpills
void setHasSpills(bool B)
Definition: AVRMachineFunctionInfo.h:72
AVRTargetMachine.h
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
AVRMCTargetDesc.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::AVRCC::COND_MI
@ COND_MI
Minus.
Definition: AVRInstrInfo.h:38
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
AVRRegisterInfo.h
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:138
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
AVRMachineFunctionInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AVRInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: AVRInstrInfo.cpp:393
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:653
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::AVRInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: AVRInstrInfo.cpp:108
MachineFrameInfo.h
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1028
Function.h
llvm::AVRCC::COND_LO
@ COND_LO
Unsigned lower.
Definition: AVRInstrInfo.h:37
llvm::AVRInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: AVRInstrInfo.cpp:434
AVR.h
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::AVRCC::COND_EQ
@ COND_EQ
Equal.
Definition: AVRInstrInfo.h:32
llvm::AVRInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: AVRInstrInfo.cpp:260
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::AVRSubtarget::getRegisterInfo
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:51
llvm::AVRInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: AVRInstrInfo.cpp:89
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1019
MachineInstrBuilder.h
llvm::AVRMachineFunctionInfo
Contains AVR-specific information for each MachineFunction.
Definition: AVRMachineFunctionInfo.h:21
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
AVRInstrInfo.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:47
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstrBundleIterator< MachineInstr >
TargetRegistry.h
Debug.h
llvm::AVRInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: AVRInstrInfo.cpp:127
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24