27#define GET_INSTRINFO_CTOR_DTOR
28#include "AVRGenInstrInfo.inc"
40 bool RenamableDest,
bool RenamableSrc)
const {
44 if (AVR::DREGSRegClass.
contains(DestReg, SrcReg)) {
47 if (
STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) {
51 Register DestLo, DestHi, SrcLo, SrcHi;
53 TRI.splitReg(DestReg, DestLo, DestHi);
54 TRI.splitReg(SrcReg, SrcLo, SrcHi);
61 if (DestLo == SrcHi) {
74 if (AVR::GPR8RegClass.
contains(DestReg, SrcReg)) {
76 }
else if (SrcReg == AVR::SP && AVR::DREGSRegClass.
contains(DestReg)) {
78 }
else if (DestReg == AVR::SP && AVR::DREGSRegClass.
contains(SrcReg)) {
90 int &FrameIndex)
const {
91 switch (
MI.getOpcode()) {
94 if (
MI.getOperand(1).isFI() &&
MI.getOperand(2).isImm() &&
95 MI.getOperand(2).getImm() == 0) {
96 FrameIndex =
MI.getOperand(1).getIndex();
97 return MI.getOperand(0).getReg();
109 int &FrameIndex)
const {
110 switch (
MI.getOpcode()) {
112 case AVR::STDWPtrQRr: {
113 if (
MI.getOperand(0).isFI() &&
MI.getOperand(1).isImm() &&
114 MI.getOperand(1).getImm() == 0) {
115 FrameIndex =
MI.getOperand(0).getIndex();
116 return MI.getOperand(2).getReg();
144 if (
TRI->isTypeLegalForClass(*RC, MVT::i8)) {
145 Opcode = AVR::STDPtrQRr;
146 }
else if (
TRI->isTypeLegalForClass(*RC, MVT::i16)) {
147 Opcode = AVR::STDWPtrQRr;
174 if (
TRI->isTypeLegalForClass(*RC, MVT::i8)) {
175 Opcode = AVR::LDDRdPtrQ;
176 }
else if (
TRI->isTypeLegalForClass(*RC, MVT::i16)) {
179 Opcode = AVR::LDDWRdYQ;
195 return get(AVR::BREQk);
197 return get(AVR::BRNEk);
199 return get(AVR::BRGEk);
201 return get(AVR::BRLTk);
203 return get(AVR::BRSHk);
205 return get(AVR::BRLOk);
207 return get(AVR::BRMIk);
209 return get(AVR::BRPLk);
263 bool AllowModify)
const {
269 while (
I !=
MBB.begin()) {
271 if (
I->isDebugInstr()) {
277 if (!isUnpredicatedTerminator(*
I)) {
283 if (!
I->getDesc().isBranch()) {
289 if (
I->getOpcode() == AVR::RJMPk) {
293 TBB =
I->getOperand(0).getMBB();
298 MBB.erase(std::next(
I),
MBB.end());
304 if (
MBB.isLayoutSuccessor(
I->getOperand(0).getMBB())) {
306 I->eraseFromParent();
308 UnCondBrIter =
MBB.end();
313 TBB =
I->getOperand(0).getMBB();
326 if (AllowModify && UnCondBrIter !=
MBB.end() &&
327 MBB.isLayoutSuccessor(TargetBB)) {
350 .
addMBB(UnCondBrIter->getOperand(0).getMBB());
354 OldInst->eraseFromParent();
355 UnCondBrIter->eraseFromParent();
358 UnCondBrIter =
MBB.end();
364 TBB =
I->getOperand(0).getMBB();
376 if (
TBB !=
I->getOperand(0).getMBB()) {
382 if (OldBranchCode == BranchCode) {
401 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
403 "AVR branch conditions have one component!");
406 assert(!FBB &&
"Unconditional branch with multiple successors!");
434 int *BytesRemoved)
const {
441 while (
I !=
MBB.begin()) {
443 if (
I->isDebugInstr()) {
448 if (
I->getOpcode() != AVR::RJMPk &&
456 I->eraseFromParent();
466 assert(
Cond.size() == 1 &&
"Invalid AVR branch condition!");
475 unsigned Opcode =
MI.getOpcode();
481 return Desc.getSize();
483 case TargetOpcode::EH_LABEL:
484 case TargetOpcode::IMPLICIT_DEF:
485 case TargetOpcode::KILL:
486 case TargetOpcode::DBG_VALUE:
488 case TargetOpcode::INLINEASM:
489 case TargetOpcode::INLINEASM_BR: {
494 return TII.getInlineAsmLength(
MI.getOperand(0).getSymbolName(),
502 switch (
MI.getOpcode()) {
517 return MI.getOperand(0).getMBB();
520 return MI.getOperand(1).getMBB();
530 int64_t BrOffset)
const {
537 return STI.hasJMPCALL();
540 return isIntN(13, BrOffset);
551 return isIntN(7, BrOffset);
565 if (
STI.hasJMPCALL())
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
AVRInstrInfo(AVRSubtarget &STI)
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const
AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
Contains AVR-specific information for each MachineFunction.
void setHasSpills(bool B)
Utilities relating to AVR registers.
A specific AVR target MCU.
const AVRInstrInfo * getInstrInfo() const override
const AVRRegisterInfo * getRegisterInfo() const override
A generic AVR implementation.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Describe properties that are true of each instruction in the target description file.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Wrapper class representing physical registers. Should be passed by value.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
static MachineOperand CreateImm(int64_t Val)
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CondCodes
AVR specific condition codes.
@ COND_SH
Unsigned same or higher.
@ COND_GE
Greater than or equal.
@ Undef
Value of the register doesn't matter.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
unsigned getKillRegState(bool B)
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Description of the encoding of one expression Op.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.