LLVM  17.0.0git
CSKYISelDAGToDAG.cpp
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1 //===-- CSKYISelDAGToDAG.cpp - A dag to dag inst selector for CSKY---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines an instruction selector for the CSKY target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "CSKY.h"
14 #include "CSKYSubtarget.h"
15 #include "CSKYTargetMachine.h"
20 
21 using namespace llvm;
22 
23 #define DEBUG_TYPE "csky-isel"
24 #define PASS_NAME "CSKY DAG->DAG Pattern Instruction Selection"
25 
26 namespace {
27 class CSKYDAGToDAGISel : public SelectionDAGISel {
28  const CSKYSubtarget *Subtarget;
29 
30 public:
31  static char ID;
32 
33  explicit CSKYDAGToDAGISel(CSKYTargetMachine &TM, CodeGenOpt::Level OptLevel)
34  : SelectionDAGISel(ID, TM, OptLevel) {}
35 
36  bool runOnMachineFunction(MachineFunction &MF) override {
37  // Reset the subtarget each time through.
38  Subtarget = &MF.getSubtarget<CSKYSubtarget>();
40  return true;
41  }
42 
43  void Select(SDNode *N) override;
44  bool selectAddCarry(SDNode *N);
45  bool selectSubCarry(SDNode *N);
46  bool selectBITCAST_TO_LOHI(SDNode *N);
47  bool selectInlineAsm(SDNode *N);
48 
50 
51  bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
52  std::vector<SDValue> &OutOps) override;
53 
54 #include "CSKYGenDAGISel.inc"
55 };
56 } // namespace
57 
58 char CSKYDAGToDAGISel::ID = 0;
59 
60 INITIALIZE_PASS(CSKYDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)
61 
62 void CSKYDAGToDAGISel::Select(SDNode *N) {
63  // If we have a custom node, we have already selected
64  if (N->isMachineOpcode()) {
65  LLVM_DEBUG(dbgs() << "== "; N->dump(CurDAG); dbgs() << "\n");
66  N->setNodeId(-1);
67  return;
68  }
69 
70  SDLoc Dl(N);
71  unsigned Opcode = N->getOpcode();
72  bool IsSelected = false;
73 
74  switch (Opcode) {
75  default:
76  break;
77  case ISD::ADDCARRY:
78  IsSelected = selectAddCarry(N);
79  break;
80  case ISD::SUBCARRY:
81  IsSelected = selectSubCarry(N);
82  break;
84  Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF);
85  ReplaceNode(N, CurDAG->getRegister(GP, N->getValueType(0)).getNode());
86 
87  IsSelected = true;
88  break;
89  }
90  case ISD::FrameIndex: {
91  SDValue Imm = CurDAG->getTargetConstant(0, Dl, MVT::i32);
92  int FI = cast<FrameIndexSDNode>(N)->getIndex();
93  SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
94  ReplaceNode(N, CurDAG->getMachineNode(Subtarget->hasE2() ? CSKY::ADDI32
95  : CSKY::ADDI16XZ,
96  Dl, MVT::i32, TFI, Imm));
97 
98  IsSelected = true;
99  break;
100  }
102  IsSelected = selectBITCAST_TO_LOHI(N);
103  break;
104  case ISD::INLINEASM:
105  case ISD::INLINEASM_BR:
106  IsSelected = selectInlineAsm(N);
107  break;
108  }
109 
110  if (IsSelected)
111  return;
112 
113  // Select the default instruction.
114  SelectCode(N);
115 }
116 
117 bool CSKYDAGToDAGISel::selectInlineAsm(SDNode *N) {
118  std::vector<SDValue> AsmNodeOperands;
119  unsigned Flag, Kind;
120  bool Changed = false;
121  unsigned NumOps = N->getNumOperands();
122 
123  // Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
124  // However, some instructions (e.g. mula.s32) require GPR pair.
125  // Since there is no constraint to explicitly specify a
126  // reg pair, we use GPRPair reg class for "%r" for 64-bit data.
127 
128  SDLoc dl(N);
129  SDValue Glue =
130  N->getGluedNode() ? N->getOperand(NumOps - 1) : SDValue(nullptr, 0);
131 
132  SmallVector<bool, 8> OpChanged;
133  // Glue node will be appended late.
134  for (unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e;
135  ++i) {
136  SDValue op = N->getOperand(i);
137  AsmNodeOperands.push_back(op);
138 
140  continue;
141 
142  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
143  Flag = C->getZExtValue();
145  } else
146  continue;
147 
148  // Immediate operands to inline asm in the SelectionDAG are modeled with
149  // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
150  // the second is a constant with the value of the immediate. If we get here
151  // and we have a Kind_Imm, skip the next operand, and continue.
152  if (Kind == InlineAsm::Kind_Imm) {
153  SDValue op = N->getOperand(++i);
154  AsmNodeOperands.push_back(op);
155  continue;
156  }
157 
158  unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
159  if (NumRegs)
160  OpChanged.push_back(false);
161 
162  unsigned DefIdx = 0;
163  bool IsTiedToChangedOp = false;
164  // If it's a use that is tied with a previous def, it has no
165  // reg class constraint.
166  if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
167  IsTiedToChangedOp = OpChanged[DefIdx];
168 
169  // Memory operands to inline asm in the SelectionDAG are modeled with two
170  // operands: a constant of value InlineAsm::Kind_Mem followed by the input
171  // operand. If we get here and we have a Kind_Mem, skip the next operand (so
172  // it doesn't get misinterpreted), and continue. We do this here because
173  // it's important to update the OpChanged array correctly before moving on.
174  if (Kind == InlineAsm::Kind_Mem) {
175  SDValue op = N->getOperand(++i);
176  AsmNodeOperands.push_back(op);
177  continue;
178  }
179 
180  if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef &&
182  continue;
183 
184  unsigned RC;
185  bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
186  if ((!IsTiedToChangedOp && (!HasRC || RC != CSKY::GPRRegClassID)) ||
187  NumRegs != 2)
188  continue;
189 
190  assert((i + 2 < NumOps) && "Invalid number of operands in inline asm");
191  SDValue V0 = N->getOperand(i + 1);
192  SDValue V1 = N->getOperand(i + 2);
193  unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
194  unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
195  SDValue PairedReg;
196  MachineRegisterInfo &MRI = MF->getRegInfo();
197 
198  if (Kind == InlineAsm::Kind_RegDef ||
200  // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
201  // the original GPRs.
202 
203  Register GPVR = MRI.createVirtualRegister(&CSKY::GPRPairRegClass);
204  PairedReg = CurDAG->getRegister(GPVR, MVT::i64);
205  SDValue Chain = SDValue(N, 0);
206 
207  SDNode *GU = N->getGluedUser();
208  SDValue RegCopy =
209  CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::i64, Chain.getValue(1));
210 
211  // Extract values from a GPRPair reg and copy to the original GPR reg.
212  SDValue Sub0 =
213  CurDAG->getTargetExtractSubreg(CSKY::sub32_0, dl, MVT::i32, RegCopy);
214  SDValue Sub1 =
215  CurDAG->getTargetExtractSubreg(CSKY::sub32_32, dl, MVT::i32, RegCopy);
216  SDValue T0 =
217  CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, RegCopy.getValue(1));
218  SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
219 
220  // Update the original glue user.
221  std::vector<SDValue> Ops(GU->op_begin(), GU->op_end() - 1);
222  Ops.push_back(T1.getValue(1));
223  CurDAG->UpdateNodeOperands(GU, Ops);
224  } else {
225  // For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
226  // GPRPair and then pass the GPRPair to the inline asm.
227  SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
228 
229  // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
230  SDValue T0 =
231  CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, Chain.getValue(1));
232  SDValue T1 =
233  CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, T0.getValue(1));
234  SDValue Pair = SDValue(createGPRPairNode(MVT::i64, T0, T1), 0);
235 
236  // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
237  // i32 VRs of inline asm with it.
238  Register GPVR = MRI.createVirtualRegister(&CSKY::GPRPairRegClass);
239  PairedReg = CurDAG->getRegister(GPVR, MVT::i64);
240  Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
241 
242  AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
243  Glue = Chain.getValue(1);
244  }
245 
246  Changed = true;
247 
248  if (PairedReg.getNode()) {
249  OpChanged[OpChanged.size() - 1] = true;
250  Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
251  if (IsTiedToChangedOp)
253  else
254  Flag = InlineAsm::getFlagWordForRegClass(Flag, CSKY::GPRPairRegClassID);
255  // Replace the current flag.
256  AsmNodeOperands[AsmNodeOperands.size() - 1] =
257  CurDAG->getTargetConstant(Flag, dl, MVT::i32);
258  // Add the new register node and skip the original two GPRs.
259  AsmNodeOperands.push_back(PairedReg);
260  // Skip the next two GPRs.
261  i += 2;
262  }
263  }
264 
265  if (Glue.getNode())
266  AsmNodeOperands.push_back(Glue);
267  if (!Changed)
268  return false;
269 
270  SDValue New = CurDAG->getNode(N->getOpcode(), SDLoc(N),
271  CurDAG->getVTList(MVT::Other, MVT::Glue),
272  AsmNodeOperands);
273  New->setNodeId(-1);
274  ReplaceNode(N, New.getNode());
275  return true;
276 }
277 
278 bool CSKYDAGToDAGISel::selectBITCAST_TO_LOHI(SDNode *N) {
279  SDLoc Dl(N);
280  auto VT = N->getValueType(0);
281  auto V = N->getOperand(0);
282 
283  if (!Subtarget->hasFPUv2DoubleFloat())
284  return false;
285 
286  SDValue V1 = SDValue(CurDAG->getMachineNode(CSKY::FMFVRL_D, Dl, VT, V), 0);
287  SDValue V2 = SDValue(CurDAG->getMachineNode(CSKY::FMFVRH_D, Dl, VT, V), 0);
288 
289  ReplaceUses(SDValue(N, 0), V1);
290  ReplaceUses(SDValue(N, 1), V2);
291  CurDAG->RemoveDeadNode(N);
292 
293  return true;
294 }
295 
296 bool CSKYDAGToDAGISel::selectAddCarry(SDNode *N) {
297  MachineSDNode *NewNode = nullptr;
298  auto Type0 = N->getValueType(0);
299  auto Type1 = N->getValueType(1);
300  auto Op0 = N->getOperand(0);
301  auto Op1 = N->getOperand(1);
302  auto Op2 = N->getOperand(2);
303 
304  SDLoc Dl(N);
305 
306  if (isNullConstant(Op2)) {
307  auto *CA = CurDAG->getMachineNode(
308  Subtarget->has2E3() ? CSKY::CLRC32 : CSKY::CLRC16, Dl, Type1);
309  NewNode = CurDAG->getMachineNode(
310  Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1},
311  {Op0, Op1, SDValue(CA, 0)});
312  } else if (isOneConstant(Op2)) {
313  auto *CA = CurDAG->getMachineNode(
314  Subtarget->has2E3() ? CSKY::SETC32 : CSKY::SETC16, Dl, Type1);
315  NewNode = CurDAG->getMachineNode(
316  Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1},
317  {Op0, Op1, SDValue(CA, 0)});
318  } else {
319  NewNode = CurDAG->getMachineNode(Subtarget->has2E3() ? CSKY::ADDC32
320  : CSKY::ADDC16,
321  Dl, {Type0, Type1}, {Op0, Op1, Op2});
322  }
323  ReplaceNode(N, NewNode);
324  return true;
325 }
326 
327 static SDValue InvertCarryFlag(const CSKYSubtarget *Subtarget,
328  SelectionDAG *DAG, SDLoc Dl, SDValue OldCarry) {
329  auto NewCarryReg =
330  DAG->getMachineNode(Subtarget->has2E3() ? CSKY::MVCV32 : CSKY::MVCV16, Dl,
331  MVT::i32, OldCarry);
332  auto NewCarry =
333  DAG->getMachineNode(Subtarget->hasE2() ? CSKY::BTSTI32 : CSKY::BTSTI16,
334  Dl, OldCarry.getValueType(), SDValue(NewCarryReg, 0),
335  DAG->getTargetConstant(0, Dl, MVT::i32));
336  return SDValue(NewCarry, 0);
337 }
338 
339 bool CSKYDAGToDAGISel::selectSubCarry(SDNode *N) {
340  MachineSDNode *NewNode = nullptr;
341  auto Type0 = N->getValueType(0);
342  auto Type1 = N->getValueType(1);
343  auto Op0 = N->getOperand(0);
344  auto Op1 = N->getOperand(1);
345  auto Op2 = N->getOperand(2);
346 
347  SDLoc Dl(N);
348 
349  if (isNullConstant(Op2)) {
350  auto *CA = CurDAG->getMachineNode(
351  Subtarget->has2E3() ? CSKY::SETC32 : CSKY::SETC16, Dl, Type1);
352  NewNode = CurDAG->getMachineNode(
353  Subtarget->has2E3() ? CSKY::SUBC32 : CSKY::SUBC16, Dl, {Type0, Type1},
354  {Op0, Op1, SDValue(CA, 0)});
355  } else if (isOneConstant(Op2)) {
356  auto *CA = CurDAG->getMachineNode(
357  Subtarget->has2E3() ? CSKY::CLRC32 : CSKY::CLRC16, Dl, Type1);
358  NewNode = CurDAG->getMachineNode(
359  Subtarget->has2E3() ? CSKY::SUBC32 : CSKY::SUBC16, Dl, {Type0, Type1},
360  {Op0, Op1, SDValue(CA, 0)});
361  } else {
362  auto CarryIn = InvertCarryFlag(Subtarget, CurDAG, Dl, Op2);
363  NewNode = CurDAG->getMachineNode(Subtarget->has2E3() ? CSKY::SUBC32
364  : CSKY::SUBC16,
365  Dl, {Type0, Type1}, {Op0, Op1, CarryIn});
366  }
367  auto CarryOut = InvertCarryFlag(Subtarget, CurDAG, Dl, SDValue(NewNode, 1));
368 
369  ReplaceUses(SDValue(N, 0), SDValue(NewNode, 0));
370  ReplaceUses(SDValue(N, 1), CarryOut);
371  CurDAG->RemoveDeadNode(N);
372 
373  return true;
374 }
375 
377  SDLoc dl(V0.getNode());
378  SDValue RegClass =
379  CurDAG->getTargetConstant(CSKY::GPRPairRegClassID, dl, MVT::i32);
380  SDValue SubReg0 = CurDAG->getTargetConstant(CSKY::sub32_0, dl, MVT::i32);
381  SDValue SubReg1 = CurDAG->getTargetConstant(CSKY::sub32_32, dl, MVT::i32);
382  const SDValue Ops[] = {RegClass, V0, SubReg0, V1, SubReg1};
383  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
384 }
385 
386 bool CSKYDAGToDAGISel::SelectInlineAsmMemoryOperand(
387  const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
388  switch (ConstraintID) {
390  // We just support simple memory operands that have a single address
391  // operand and need no special handling.
392  OutOps.push_back(Op);
393  return false;
394  default:
395  break;
396  }
397 
398  return true;
399 }
400 
402  CodeGenOpt::Level OptLevel) {
403  return new CSKYDAGToDAGISel(TM, OptLevel);
404 }
i
i
Definition: README.txt:29
llvm::InlineAsm::Kind_Imm
@ Kind_Imm
Definition: InlineAsm.h:244
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1586
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
PASS_NAME
#define PASS_NAME
Definition: CSKYISelDAGToDAG.cpp:24
InvertCarryFlag
static SDValue InvertCarryFlag(const CSKYSubtarget *Subtarget, SelectionDAG *DAG, SDLoc Dl, SDValue OldCarry)
Definition: CSKYISelDAGToDAG.cpp:327
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::AArch64PACKey::ID
ID
Definition: AArch64BaseInfo.h:824
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:157
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:51
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:159
llvm::isOneConstant
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
Definition: SelectionDAG.cpp:10902
op
#define op(i)
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::MachineSDNode
An SDNode that represents everything that will be needed to construct a MachineInstr.
Definition: SelectionDAGNodes.h:2901
CSKYTargetMachine.h
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:282
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:369
CSKY.h
T1
#define T1
Definition: Mips16ISelLowering.cpp:340
llvm::InlineAsm::Kind_RegDef
@ Kind_RegDef
Definition: InlineAsm.h:241
SelectionDAG.h
llvm::InlineAsm::Kind_RegDefEarlyClobber
@ Kind_RegDefEarlyClobber
Definition: InlineAsm.h:242
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:303
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1024
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::SDNode::op_end
op_iterator op_end() const
Definition: SelectionDAGNodes.h:929
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1141
llvm::createCSKYISelDag
FunctionPass * createCSKYISelDag(CSKYTargetMachine &TM, CodeGenOpt::Level OptLevel)
Definition: CSKYISelDAGToDAG.cpp:401
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
CSKYSubtarget.h
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
llvm::ISD::GLOBAL_OFFSET_TABLE
@ GLOBAL_OFFSET_TABLE
The address of the GOT.
Definition: ISDOpcodes.h:87
llvm::InlineAsm::Op_InputChain
@ Op_InputChain
Definition: InlineAsm.h:218
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:148
DEBUG_TYPE
#define DEBUG_TYPE
Definition: CSKYISelDAGToDAG.cpp:23
llvm::CSKYSubtarget
Definition: CSKYSubtarget.h:30
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:351
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:672
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:31
llvm::InlineAsm::Op_FirstOperand
@ Op_FirstOperand
Definition: InlineAsm.h:222
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:240
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:179
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
CSKYMCTargetDesc.h
llvm::SelectionDAG::getMachineNode
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
Definition: SelectionDAG.cpp:9916
llvm::ISD::SUBCARRY
@ SUBCARRY
Definition: ISDOpcodes.h:304
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::InlineAsm::getFlagWordForRegClass
static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC)
getFlagWordForRegClass - Augment an existing flag word returned by getFlagWord with the required regi...
Definition: InlineAsm.h:325
SelectionDAGISel.h
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::InlineAsm::getFlagWord
static unsigned getFlagWord(unsigned Kind, unsigned NumOps)
Definition: InlineAsm.h:293
llvm::ms_demangle::IntrinsicFunctionKind::New
@ New
llvm::CSKYTargetMachine
Definition: CSKYTargetMachine.h:23
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::InlineAsm::getFlagWordForMatchingOp
static unsigned getFlagWordForMatchingOp(unsigned InputFlag, unsigned MatchedOperandNo)
getFlagWordForMatchingOp - Augment an existing flag word returned by getFlagWord with information ind...
Definition: InlineAsm.h:313
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:165
llvm::NVPTX::PTXLdStInstCode::V2
@ V2
Definition: NVPTX.h:124
llvm::InlineAsm::hasRegClassConstraint
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:378
llvm::isNullConstant
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
Definition: SelectionDAG.cpp:10887
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:354
MachineFrameInfo.h
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1027
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::InlineAsm::Constraint_m
@ Constraint_m
Definition: InlineAsm.h:259
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::SDNode::op_begin
op_iterator op_begin() const
Definition: SelectionDAGNodes.h:928
llvm::SelectionDAGISel
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
Definition: SelectionDAGISel.h:41
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:363
N
#define N
llvm::CSKYSubtarget::hasE2
bool hasE2() const
Definition: CSKYSubtarget.h:187
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:671
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::CodeGenOpt::Level
Level
Code generation optimization level.
Definition: CodeGen.h:57
llvm::CSKYISD::BITCAST_TO_LOHI
@ BITCAST_TO_LOHI
Definition: CSKYISelLowering.h:36
llvm::CSKYSubtarget::has2E3
bool has2E3() const
Definition: CSKYSubtarget.h:188
llvm::SelectionDAGISel::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: SelectionDAGISel.cpp:381
createGPRPairNode
static SDValue createGPRPairNode(SelectionDAG &DAG, SDValue V)
Definition: AArch64ISelLowering.cpp:22000
llvm::InlineAsm::Kind_Mem
@ Kind_Mem
Definition: InlineAsm.h:245