LLVM 17.0.0git
SparcISelLowering.cpp
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1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the interfaces that Sparc uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcISelLowering.h"
17#include "SparcRegisterInfo.h"
18#include "SparcTargetMachine.h"
31#include "llvm/IR/Function.h"
32#include "llvm/IR/Module.h"
35using namespace llvm;
36
37
38//===----------------------------------------------------------------------===//
39// Calling Convention Implementation
40//===----------------------------------------------------------------------===//
41
42static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
43 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
44 ISD::ArgFlagsTy &ArgFlags, CCState &State)
45{
46 assert (ArgFlags.isSRet());
47
48 // Assign SRet argument.
49 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
50 0,
51 LocVT, LocInfo));
52 return true;
53}
54
55static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT,
56 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
57 ISD::ArgFlagsTy &ArgFlags, CCState &State)
58{
59 static const MCPhysReg RegList[] = {
60 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
61 };
62 // Try to get first reg.
63 if (Register Reg = State.AllocateReg(RegList)) {
64 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
65 } else {
66 // Assign whole thing in stack.
68 ValNo, ValVT, State.AllocateStack(8, Align(4)), LocVT, LocInfo));
69 return true;
70 }
71
72 // Try to get second reg.
73 if (Register Reg = State.AllocateReg(RegList))
74 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
75 else
77 ValNo, ValVT, State.AllocateStack(4, Align(4)), LocVT, LocInfo));
78 return true;
79}
80
81static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT,
82 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
83 ISD::ArgFlagsTy &ArgFlags, CCState &State)
84{
85 static const MCPhysReg RegList[] = {
86 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
87 };
88
89 // Try to get first reg.
90 if (Register Reg = State.AllocateReg(RegList))
91 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
92 else
93 return false;
94
95 // Try to get second reg.
96 if (Register Reg = State.AllocateReg(RegList))
97 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
98 else
99 return false;
100
101 return true;
102}
103
104// Allocate a full-sized argument for the 64-bit ABI.
105static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT,
106 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
107 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
108 assert((LocVT == MVT::f32 || LocVT == MVT::f128
109 || LocVT.getSizeInBits() == 64) &&
110 "Can't handle non-64 bits locations");
111
112 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
113 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
114 Align alignment = (LocVT == MVT::f128) ? Align(16) : Align(8);
115 unsigned Offset = State.AllocateStack(size, alignment);
116 unsigned Reg = 0;
117
118 if (LocVT == MVT::i64 && Offset < 6*8)
119 // Promote integers to %i0-%i5.
120 Reg = SP::I0 + Offset/8;
121 else if (LocVT == MVT::f64 && Offset < 16*8)
122 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
123 Reg = SP::D0 + Offset/8;
124 else if (LocVT == MVT::f32 && Offset < 16*8)
125 // Promote floats to %f1, %f3, ...
126 Reg = SP::F1 + Offset/4;
127 else if (LocVT == MVT::f128 && Offset < 16*8)
128 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
129 Reg = SP::Q0 + Offset/16;
130
131 // Promote to register when possible, otherwise use the stack slot.
132 if (Reg) {
133 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
134 return true;
135 }
136
137 // Bail out if this is a return CC and we run out of registers to place
138 // values into.
139 if (IsReturn)
140 return false;
141
142 // This argument goes on the stack in an 8-byte slot.
143 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
144 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
145 if (LocVT == MVT::f32)
146 Offset += 4;
147
148 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
149 return true;
150}
151
152// Allocate a half-sized argument for the 64-bit ABI.
153//
154// This is used when passing { float, int } structs by value in registers.
155static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT,
156 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
157 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
158 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
159 unsigned Offset = State.AllocateStack(4, Align(4));
160
161 if (LocVT == MVT::f32 && Offset < 16*8) {
162 // Promote floats to %f0-%f31.
163 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
164 LocVT, LocInfo));
165 return true;
166 }
167
168 if (LocVT == MVT::i32 && Offset < 6*8) {
169 // Promote integers to %i0-%i5, using half the register.
170 unsigned Reg = SP::I0 + Offset/8;
171 LocVT = MVT::i64;
172 LocInfo = CCValAssign::AExt;
173
174 // Set the Custom bit if this i32 goes in the high bits of a register.
175 if (Offset % 8 == 0)
176 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
177 LocVT, LocInfo));
178 else
179 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
180 return true;
181 }
182
183 // Bail out if this is a return CC and we run out of registers to place
184 // values into.
185 if (IsReturn)
186 return false;
187
188 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
189 return true;
190}
191
192static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
193 CCValAssign::LocInfo &LocInfo,
194 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
195 return Analyze_CC_Sparc64_Full(false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
196 State);
197}
198
199static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
200 CCValAssign::LocInfo &LocInfo,
201 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
202 return Analyze_CC_Sparc64_Half(false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
203 State);
204}
205
206static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
207 CCValAssign::LocInfo &LocInfo,
208 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
209 return Analyze_CC_Sparc64_Full(true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
210 State);
211}
212
213static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
214 CCValAssign::LocInfo &LocInfo,
215 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
216 return Analyze_CC_Sparc64_Half(true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
217 State);
218}
219
220#include "SparcGenCallingConv.inc"
221
222// The calling conventions in SparcCallingConv.td are described in terms of the
223// callee's register window. This function translates registers to the
224// corresponding caller window %o register.
225static unsigned toCallerWindow(unsigned Reg) {
226 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
227 "Unexpected enum");
228 if (Reg >= SP::I0 && Reg <= SP::I7)
229 return Reg - SP::I0 + SP::O0;
230 return Reg;
231}
232
234 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
235 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
237 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
238 return CCInfo.CheckReturn(Outs, Subtarget->is64Bit() ? RetCC_Sparc64
239 : RetCC_Sparc32);
240}
241
244 bool IsVarArg,
246 const SmallVectorImpl<SDValue> &OutVals,
247 const SDLoc &DL, SelectionDAG &DAG) const {
248 if (Subtarget->is64Bit())
249 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
250 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
251}
252
255 bool IsVarArg,
257 const SmallVectorImpl<SDValue> &OutVals,
258 const SDLoc &DL, SelectionDAG &DAG) const {
260
261 // CCValAssign - represent the assignment of the return value to locations.
263
264 // CCState - Info about the registers and stack slot.
265 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
266 *DAG.getContext());
267
268 // Analyze return values.
269 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
270
271 SDValue Flag;
272 SmallVector<SDValue, 4> RetOps(1, Chain);
273 // Make room for the return address offset.
274 RetOps.push_back(SDValue());
275
276 // Copy the result values into the output registers.
277 for (unsigned i = 0, realRVLocIdx = 0;
278 i != RVLocs.size();
279 ++i, ++realRVLocIdx) {
280 CCValAssign &VA = RVLocs[i];
281 assert(VA.isRegLoc() && "Can only return in registers!");
282
283 SDValue Arg = OutVals[realRVLocIdx];
284
285 if (VA.needsCustom()) {
286 assert(VA.getLocVT() == MVT::v2i32);
287 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
288 // happen by default if this wasn't a legal type)
289
291 Arg,
294 Arg,
296
297 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag);
298 Flag = Chain.getValue(1);
299 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
300 VA = RVLocs[++i]; // skip ahead to next loc
301 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1,
302 Flag);
303 } else
304 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
305
306 // Guarantee that all emitted copies are stuck together with flags.
307 Flag = Chain.getValue(1);
308 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
309 }
310
311 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
312 // If the function returns a struct, copy the SRetReturnReg to I0
313 if (MF.getFunction().hasStructRetAttr()) {
315 Register Reg = SFI->getSRetReturnReg();
316 if (!Reg)
317 llvm_unreachable("sret virtual register not created in the entry block");
318 auto PtrVT = getPointerTy(DAG.getDataLayout());
319 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, PtrVT);
320 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
321 Flag = Chain.getValue(1);
322 RetOps.push_back(DAG.getRegister(SP::I0, PtrVT));
323 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
324 }
325
326 RetOps[0] = Chain; // Update chain.
327 RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32);
328
329 // Add the flag if we have it.
330 if (Flag.getNode())
331 RetOps.push_back(Flag);
332
333 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
334}
335
336// Lower return values for the 64-bit ABI.
337// Return values are passed the exactly the same way as function arguments.
340 bool IsVarArg,
342 const SmallVectorImpl<SDValue> &OutVals,
343 const SDLoc &DL, SelectionDAG &DAG) const {
344 // CCValAssign - represent the assignment of the return value to locations.
346
347 // CCState - Info about the registers and stack slot.
348 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
349 *DAG.getContext());
350
351 // Analyze return values.
352 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
353
354 SDValue Flag;
355 SmallVector<SDValue, 4> RetOps(1, Chain);
356
357 // The second operand on the return instruction is the return address offset.
358 // The return address is always %i7+8 with the 64-bit ABI.
359 RetOps.push_back(DAG.getConstant(8, DL, MVT::i32));
360
361 // Copy the result values into the output registers.
362 for (unsigned i = 0; i != RVLocs.size(); ++i) {
363 CCValAssign &VA = RVLocs[i];
364 assert(VA.isRegLoc() && "Can only return in registers!");
365 SDValue OutVal = OutVals[i];
366
367 // Integer return values must be sign or zero extended by the callee.
368 switch (VA.getLocInfo()) {
369 case CCValAssign::Full: break;
371 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
372 break;
374 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
375 break;
377 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
378 break;
379 default:
380 llvm_unreachable("Unknown loc info!");
381 }
382
383 // The custom bit on an i32 return value indicates that it should be passed
384 // in the high bits of the register.
385 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
386 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
387 DAG.getConstant(32, DL, MVT::i32));
388
389 // The next value may go in the low bits of the same register.
390 // Handle both at once.
391 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
392 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
393 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
394 // Skip the next value, it's already done.
395 ++i;
396 }
397 }
398
399 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
400
401 // Guarantee that all emitted copies are stuck together with flags.
402 Flag = Chain.getValue(1);
403 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
404 }
405
406 RetOps[0] = Chain; // Update chain.
407
408 // Add the flag if we have it.
409 if (Flag.getNode())
410 RetOps.push_back(Flag);
411
412 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
413}
414
416 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
417 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
418 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
419 if (Subtarget->is64Bit())
420 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
421 DL, DAG, InVals);
422 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
423 DL, DAG, InVals);
424}
425
426/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
427/// passed in either one or two GPRs, including FP values. TODO: we should
428/// pass FP values in FP registers for fastcc functions.
430 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
431 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
432 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
434 MachineRegisterInfo &RegInfo = MF.getRegInfo();
436
437 // Assign locations to all of the incoming arguments.
439 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
440 *DAG.getContext());
441 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
442
443 const unsigned StackOffset = 92;
444 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
445
446 unsigned InIdx = 0;
447 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
448 CCValAssign &VA = ArgLocs[i];
449
450 if (Ins[InIdx].Flags.isSRet()) {
451 if (InIdx != 0)
452 report_fatal_error("sparc only supports sret on the first parameter");
453 // Get SRet from [%fp+64].
454 int FrameIdx = MF.getFrameInfo().CreateFixedObject(4, 64, true);
455 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
456 SDValue Arg =
457 DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
458 InVals.push_back(Arg);
459 continue;
460 }
461
462 if (VA.isRegLoc()) {
463 if (VA.needsCustom()) {
464 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
465
466 Register VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
467 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
468 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
469
470 assert(i+1 < e);
471 CCValAssign &NextVA = ArgLocs[++i];
472
473 SDValue LoVal;
474 if (NextVA.isMemLoc()) {
475 int FrameIdx = MF.getFrameInfo().
476 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
477 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
478 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
479 } else {
480 Register loReg = MF.addLiveIn(NextVA.getLocReg(),
481 &SP::IntRegsRegClass);
482 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
483 }
484
485 if (IsLittleEndian)
486 std::swap(LoVal, HiVal);
487
488 SDValue WholeValue =
489 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
490 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue);
491 InVals.push_back(WholeValue);
492 continue;
493 }
494 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
495 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
496 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
497 if (VA.getLocVT() == MVT::f32)
498 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
499 else if (VA.getLocVT() != MVT::i32) {
501 DAG.getValueType(VA.getLocVT()));
502 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
503 }
504 InVals.push_back(Arg);
505 continue;
506 }
507
508 assert(VA.isMemLoc());
509
510 unsigned Offset = VA.getLocMemOffset()+StackOffset;
511 auto PtrVT = getPointerTy(DAG.getDataLayout());
512
513 if (VA.needsCustom()) {
514 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
515 // If it is double-word aligned, just load.
516 if (Offset % 8 == 0) {
517 int FI = MF.getFrameInfo().CreateFixedObject(8,
518 Offset,
519 true);
520 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
521 SDValue Load =
522 DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
523 InVals.push_back(Load);
524 continue;
525 }
526
527 int FI = MF.getFrameInfo().CreateFixedObject(4,
528 Offset,
529 true);
530 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
531 SDValue HiVal =
532 DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
533 int FI2 = MF.getFrameInfo().CreateFixedObject(4,
534 Offset+4,
535 true);
536 SDValue FIPtr2 = DAG.getFrameIndex(FI2, PtrVT);
537
538 SDValue LoVal =
539 DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, MachinePointerInfo());
540
541 if (IsLittleEndian)
542 std::swap(LoVal, HiVal);
543
544 SDValue WholeValue =
545 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
546 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue);
547 InVals.push_back(WholeValue);
548 continue;
549 }
550
551 int FI = MF.getFrameInfo().CreateFixedObject(4,
552 Offset,
553 true);
554 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
555 SDValue Load ;
556 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
557 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
558 } else if (VA.getValVT() == MVT::f128) {
559 report_fatal_error("SPARCv8 does not handle f128 in calls; "
560 "pass indirectly");
561 } else {
562 // We shouldn't see any other value types here.
563 llvm_unreachable("Unexpected ValVT encountered in frame lowering.");
564 }
565 InVals.push_back(Load);
566 }
567
568 if (MF.getFunction().hasStructRetAttr()) {
569 // Copy the SRet Argument to SRetReturnReg.
571 Register Reg = SFI->getSRetReturnReg();
572 if (!Reg) {
573 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
574 SFI->setSRetReturnReg(Reg);
575 }
576 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
577 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
578 }
579
580 // Store remaining ArgRegs to the stack if this is a varargs function.
581 if (isVarArg) {
582 static const MCPhysReg ArgRegs[] = {
583 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
584 };
585 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
586 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
587 unsigned ArgOffset = CCInfo.getNextStackOffset();
588 if (NumAllocated == 6)
589 ArgOffset += StackOffset;
590 else {
591 assert(!ArgOffset);
592 ArgOffset = 68+4*NumAllocated;
593 }
594
595 // Remember the vararg offset for the va_start implementation.
596 FuncInfo->setVarArgsFrameOffset(ArgOffset);
597
598 std::vector<SDValue> OutChains;
599
600 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
601 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
602 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
603 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
604
605 int FrameIdx = MF.getFrameInfo().CreateFixedObject(4, ArgOffset,
606 true);
607 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
608
609 OutChains.push_back(
610 DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, MachinePointerInfo()));
611 ArgOffset += 4;
612 }
613
614 if (!OutChains.empty()) {
615 OutChains.push_back(Chain);
616 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
617 }
618 }
619
620 return Chain;
621}
622
623// Lower formal arguments for the 64 bit ABI.
625 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
626 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
627 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
629
630 // Analyze arguments according to CC_Sparc64.
632 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
633 *DAG.getContext());
634 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
635
636 // The argument array begins at %fp+BIAS+128, after the register save area.
637 const unsigned ArgArea = 128;
638
639 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
640 CCValAssign &VA = ArgLocs[i];
641 if (VA.isRegLoc()) {
642 // This argument is passed in a register.
643 // All integer register arguments are promoted by the caller to i64.
644
645 // Create a virtual register for the promoted live-in value.
646 Register VReg = MF.addLiveIn(VA.getLocReg(),
648 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
649
650 // Get the high bits for i32 struct elements.
651 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
652 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
653 DAG.getConstant(32, DL, MVT::i32));
654
655 // The caller promoted the argument, so insert an Assert?ext SDNode so we
656 // won't promote the value again in this function.
657 switch (VA.getLocInfo()) {
660 DAG.getValueType(VA.getValVT()));
661 break;
664 DAG.getValueType(VA.getValVT()));
665 break;
666 default:
667 break;
668 }
669
670 // Truncate the register down to the argument type.
671 if (VA.isExtInLoc())
672 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
673
674 InVals.push_back(Arg);
675 continue;
676 }
677
678 // The registers are exhausted. This argument was passed on the stack.
679 assert(VA.isMemLoc());
680 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
681 // beginning of the arguments area at %fp+BIAS+128.
682 unsigned Offset = VA.getLocMemOffset() + ArgArea;
683 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
684 // Adjust offset for extended arguments, SPARC is big-endian.
685 // The caller will have written the full slot with extended bytes, but we
686 // prefer our own extending loads.
687 if (VA.isExtInLoc())
688 Offset += 8 - ValSize;
689 int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true);
690 InVals.push_back(
691 DAG.getLoad(VA.getValVT(), DL, Chain,
694 }
695
696 if (!IsVarArg)
697 return Chain;
698
699 // This function takes variable arguments, some of which may have been passed
700 // in registers %i0-%i5. Variable floating point arguments are never passed
701 // in floating point registers. They go on %i0-%i5 or on the stack like
702 // integer arguments.
703 //
704 // The va_start intrinsic needs to know the offset to the first variable
705 // argument.
706 unsigned ArgOffset = CCInfo.getNextStackOffset();
708 // Skip the 128 bytes of register save area.
709 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
710 Subtarget->getStackPointerBias());
711
712 // Save the variable arguments that were passed in registers.
713 // The caller is required to reserve stack space for 6 arguments regardless
714 // of how many arguments were actually passed.
715 SmallVector<SDValue, 8> OutChains;
716 for (; ArgOffset < 6*8; ArgOffset += 8) {
717 Register VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
718 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
719 int FI = MF.getFrameInfo().CreateFixedObject(8, ArgOffset + ArgArea, true);
720 auto PtrVT = getPointerTy(MF.getDataLayout());
721 OutChains.push_back(
722 DAG.getStore(Chain, DL, VArg, DAG.getFrameIndex(FI, PtrVT),
724 }
725
726 if (!OutChains.empty())
727 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
728
729 return Chain;
730}
731
734 SmallVectorImpl<SDValue> &InVals) const {
735 if (Subtarget->is64Bit())
736 return LowerCall_64(CLI, InVals);
737 return LowerCall_32(CLI, InVals);
738}
739
741 const CallBase *Call) {
742 if (Call)
743 return Call->hasFnAttr(Attribute::ReturnsTwice);
744
745 const Function *CalleeFn = nullptr;
746 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
747 CalleeFn = dyn_cast<Function>(G->getGlobal());
748 } else if (ExternalSymbolSDNode *E =
749 dyn_cast<ExternalSymbolSDNode>(Callee)) {
750 const Function &Fn = DAG.getMachineFunction().getFunction();
751 const Module *M = Fn.getParent();
752 const char *CalleeName = E->getSymbol();
753 CalleeFn = M->getFunction(CalleeName);
754 }
755
756 if (!CalleeFn)
757 return false;
758 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
759}
760
761/// IsEligibleForTailCallOptimization - Check whether the call is eligible
762/// for tail call optimization.
764 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const {
765
766 auto &Outs = CLI.Outs;
767 auto &Caller = MF.getFunction();
768
769 // Do not tail call opt functions with "disable-tail-calls" attribute.
770 if (Caller.getFnAttribute("disable-tail-calls").getValueAsString() == "true")
771 return false;
772
773 // Do not tail call opt if the stack is used to pass parameters.
774 // 64-bit targets have a slightly higher limit since the ABI requires
775 // to allocate some space even when all the parameters fit inside registers.
776 unsigned StackOffsetLimit = Subtarget->is64Bit() ? 48 : 0;
777 if (CCInfo.getNextStackOffset() > StackOffsetLimit)
778 return false;
779
780 // Do not tail call opt if either the callee or caller returns
781 // a struct and the other does not.
782 if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
783 return false;
784
785 // Byval parameters hand the function a pointer directly into the stack area
786 // we want to reuse during a tail call.
787 for (auto &Arg : Outs)
788 if (Arg.Flags.isByVal())
789 return false;
790
791 return true;
792}
793
794// Lower a call for the 32-bit ABI.
797 SmallVectorImpl<SDValue> &InVals) const {
798 SelectionDAG &DAG = CLI.DAG;
799 SDLoc &dl = CLI.DL;
801 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
803 SDValue Chain = CLI.Chain;
804 SDValue Callee = CLI.Callee;
805 bool &isTailCall = CLI.IsTailCall;
806 CallingConv::ID CallConv = CLI.CallConv;
807 bool isVarArg = CLI.IsVarArg;
808
809 // Analyze operands of the call, assigning locations to each operand.
811 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
812 *DAG.getContext());
813 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
814
815 isTailCall = isTailCall && IsEligibleForTailCallOptimization(
816 CCInfo, CLI, DAG.getMachineFunction());
817
818 // Get the size of the outgoing arguments stack space requirement.
819 unsigned ArgsSize = CCInfo.getNextStackOffset();
820
821 // Keep stack frames 8-byte aligned.
822 ArgsSize = (ArgsSize+7) & ~7;
823
825
826 // Create local copies for byval args.
827 SmallVector<SDValue, 8> ByValArgs;
828 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
829 ISD::ArgFlagsTy Flags = Outs[i].Flags;
830 if (!Flags.isByVal())
831 continue;
832
833 SDValue Arg = OutVals[i];
834 unsigned Size = Flags.getByValSize();
835 Align Alignment = Flags.getNonZeroByValAlign();
836
837 if (Size > 0U) {
838 int FI = MFI.CreateStackObject(Size, Alignment, false);
839 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
840 SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32);
841
842 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Alignment,
843 false, // isVolatile,
844 (Size <= 32), // AlwaysInline if size <= 32,
845 false, // isTailCall
847 ByValArgs.push_back(FIPtr);
848 }
849 else {
850 SDValue nullVal;
851 ByValArgs.push_back(nullVal);
852 }
853 }
854
855 assert(!isTailCall || ArgsSize == 0);
856
857 if (!isTailCall)
858 Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, dl);
859
861 SmallVector<SDValue, 8> MemOpChains;
862
863 const unsigned StackOffset = 92;
864 bool hasStructRetAttr = false;
865 unsigned SRetArgSize = 0;
866 // Walk the register/memloc assignments, inserting copies/loads.
867 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
868 i != e;
869 ++i, ++realArgIdx) {
870 CCValAssign &VA = ArgLocs[i];
871 SDValue Arg = OutVals[realArgIdx];
872
873 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
874
875 // Use local copy if it is a byval arg.
876 if (Flags.isByVal()) {
877 Arg = ByValArgs[byvalArgIdx++];
878 if (!Arg) {
879 continue;
880 }
881 }
882
883 // Promote the value if needed.
884 switch (VA.getLocInfo()) {
885 default: llvm_unreachable("Unknown loc info!");
886 case CCValAssign::Full: break;
888 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
889 break;
891 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
892 break;
894 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
895 break;
897 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
898 break;
899 }
900
901 if (Flags.isSRet()) {
902 assert(VA.needsCustom());
903
904 if (isTailCall)
905 continue;
906
907 // store SRet argument in %sp+64
908 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
909 SDValue PtrOff = DAG.getIntPtrConstant(64, dl);
910 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
911 MemOpChains.push_back(
912 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
913 hasStructRetAttr = true;
914 // sret only allowed on first argument
915 assert(Outs[realArgIdx].OrigArgIndex == 0);
916 SRetArgSize =
917 DAG.getDataLayout().getTypeAllocSize(CLI.getArgs()[0].IndirectType);
918 continue;
919 }
920
921 if (VA.needsCustom()) {
922 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
923
924 if (VA.isMemLoc()) {
925 unsigned Offset = VA.getLocMemOffset() + StackOffset;
926 // if it is double-word aligned, just store.
927 if (Offset % 8 == 0) {
928 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
929 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
930 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
931 MemOpChains.push_back(
932 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
933 continue;
934 }
935 }
936
937 if (VA.getLocVT() == MVT::f64) {
938 // Move from the float value from float registers into the
939 // integer registers.
940 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Arg))
941 Arg = bitcastConstantFPToInt(C, dl, DAG);
942 else
944 }
945
947 Arg,
948 DAG.getConstant(0, dl, getVectorIdxTy(DAG.getDataLayout())));
950 Arg,
951 DAG.getConstant(1, dl, getVectorIdxTy(DAG.getDataLayout())));
952
953 if (VA.isRegLoc()) {
954 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Part0));
955 assert(i+1 != e);
956 CCValAssign &NextVA = ArgLocs[++i];
957 if (NextVA.isRegLoc()) {
958 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Part1));
959 } else {
960 // Store the second part in stack.
961 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
962 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
963 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
964 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
965 MemOpChains.push_back(
966 DAG.getStore(Chain, dl, Part1, PtrOff, MachinePointerInfo()));
967 }
968 } else {
969 unsigned Offset = VA.getLocMemOffset() + StackOffset;
970 // Store the first part.
971 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
972 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
973 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
974 MemOpChains.push_back(
975 DAG.getStore(Chain, dl, Part0, PtrOff, MachinePointerInfo()));
976 // Store the second part.
977 PtrOff = DAG.getIntPtrConstant(Offset + 4, dl);
978 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
979 MemOpChains.push_back(
980 DAG.getStore(Chain, dl, Part1, PtrOff, MachinePointerInfo()));
981 }
982 continue;
983 }
984
985 // Arguments that can be passed on register must be kept at
986 // RegsToPass vector
987 if (VA.isRegLoc()) {
988 if (VA.getLocVT() != MVT::f32) {
989 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
990 continue;
991 }
992 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
993 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
994 continue;
995 }
996
997 assert(VA.isMemLoc());
998
999 // Create a store off the stack pointer for this argument.
1000 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
1002 dl);
1003 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
1004 MemOpChains.push_back(
1005 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
1006 }
1007
1008
1009 // Emit all stores, make sure the occur before any copies into physregs.
1010 if (!MemOpChains.empty())
1011 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1012
1013 // Build a sequence of copy-to-reg nodes chained together with token
1014 // chain and flag operands which copy the outgoing args into registers.
1015 // The InFlag in necessary since all emitted instructions must be
1016 // stuck together.
1017 SDValue InFlag;
1018 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1019 Register Reg = RegsToPass[i].first;
1020 if (!isTailCall)
1021 Reg = toCallerWindow(Reg);
1022 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
1023 InFlag = Chain.getValue(1);
1024 }
1025
1026 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CB);
1027
1028 // If the callee is a GlobalAddress node (quite common, every direct call is)
1029 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1030 // Likewise ExternalSymbol -> TargetExternalSymbol.
1033 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1034 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
1035 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1036 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
1037
1038 // Returns a chain & a flag for retval copy to use
1039 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1041 Ops.push_back(Chain);
1042 Ops.push_back(Callee);
1043 if (hasStructRetAttr)
1044 Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));
1045 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1046 Register Reg = RegsToPass[i].first;
1047 if (!isTailCall)
1048 Reg = toCallerWindow(Reg);
1049 Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType()));
1050 }
1051
1052 // Add a register mask operand representing the call-preserved registers.
1053 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1054 const uint32_t *Mask =
1055 ((hasReturnsTwice)
1056 ? TRI->getRTCallPreservedMask(CallConv)
1057 : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));
1058 assert(Mask && "Missing call preserved mask for calling convention");
1059 Ops.push_back(DAG.getRegisterMask(Mask));
1060
1061 if (InFlag.getNode())
1062 Ops.push_back(InFlag);
1063
1064 if (isTailCall) {
1066 return DAG.getNode(SPISD::TAIL_CALL, dl, MVT::Other, Ops);
1067 }
1068
1069 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
1070 InFlag = Chain.getValue(1);
1071
1072 Chain = DAG.getCALLSEQ_END(Chain, ArgsSize, 0, InFlag, dl);
1073 InFlag = Chain.getValue(1);
1074
1075 // Assign locations to each value returned by this call.
1077 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1078 *DAG.getContext());
1079
1080 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
1081
1082 // Copy all of the result registers out of their specified physreg.
1083 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1084 assert(RVLocs[i].isRegLoc() && "Can only return in registers!");
1085 if (RVLocs[i].getLocVT() == MVT::v2i32) {
1086 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32);
1088 Chain, dl, toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InFlag);
1089 Chain = Lo.getValue(1);
1090 InFlag = Lo.getValue(2);
1091 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo,
1092 DAG.getConstant(0, dl, MVT::i32));
1094 Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InFlag);
1095 Chain = Hi.getValue(1);
1096 InFlag = Hi.getValue(2);
1097 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,
1098 DAG.getConstant(1, dl, MVT::i32));
1099 InVals.push_back(Vec);
1100 } else {
1101 Chain =
1102 DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
1103 RVLocs[i].getValVT(), InFlag)
1104 .getValue(1);
1105 InFlag = Chain.getValue(2);
1106 InVals.push_back(Chain.getValue(0));
1107 }
1108 }
1109
1110 return Chain;
1111}
1112
1113// FIXME? Maybe this could be a TableGen attribute on some registers and
1114// this table could be generated automatically from RegInfo.
1116 const MachineFunction &MF) const {
1118 .Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3)
1119 .Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7)
1120 .Case("o0", SP::O0).Case("o1", SP::O1).Case("o2", SP::O2).Case("o3", SP::O3)
1121 .Case("o4", SP::O4).Case("o5", SP::O5).Case("o6", SP::O6).Case("o7", SP::O7)
1122 .Case("l0", SP::L0).Case("l1", SP::L1).Case("l2", SP::L2).Case("l3", SP::L3)
1123 .Case("l4", SP::L4).Case("l5", SP::L5).Case("l6", SP::L6).Case("l7", SP::L7)
1124 .Case("g0", SP::G0).Case("g1", SP::G1).Case("g2", SP::G2).Case("g3", SP::G3)
1125 .Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7", SP::G7)
1126 .Default(0);
1127
1128 if (Reg)
1129 return Reg;
1130
1131 report_fatal_error("Invalid register name global variable");
1132}
1133
1134// Fixup floating point arguments in the ... part of a varargs call.
1135//
1136// The SPARC v9 ABI requires that floating point arguments are treated the same
1137// as integers when calling a varargs function. This does not apply to the
1138// fixed arguments that are part of the function's prototype.
1139//
1140// This function post-processes a CCValAssign array created by
1141// AnalyzeCallOperands().
1144 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1145 CCValAssign &VA = ArgLocs[i];
1146 MVT ValTy = VA.getLocVT();
1147 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1148 // varargs functions.
1149 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1150 continue;
1151 // The fixed arguments to a varargs function still go in FP registers.
1152 if (Outs[VA.getValNo()].IsFixed)
1153 continue;
1154
1155 // This floating point argument should be reassigned.
1156 // Determine the offset into the argument array.
1157 Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1158 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1159 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1160 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1161
1162 if (Offset < 6*8) {
1163 // This argument should go in %i0-%i5.
1164 unsigned IReg = SP::I0 + Offset/8;
1165 if (ValTy == MVT::f64)
1166 // Full register, just bitconvert into i64.
1167 VA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), IReg, MVT::i64,
1169 else {
1170 assert(ValTy == MVT::f128 && "Unexpected type!");
1171 // Full register, just bitconvert into i128 -- We will lower this into
1172 // two i64s in LowerCall_64.
1173 VA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(), IReg,
1175 }
1176 } else {
1177 // This needs to go to memory, we're out of integer registers.
1179 VA.getLocVT(), VA.getLocInfo());
1180 }
1181 }
1182}
1183
1184// Lower a call for the 64-bit ABI.
1185SDValue
1187 SmallVectorImpl<SDValue> &InVals) const {
1188 SelectionDAG &DAG = CLI.DAG;
1189 SDLoc DL = CLI.DL;
1190 SDValue Chain = CLI.Chain;
1191 auto PtrVT = getPointerTy(DAG.getDataLayout());
1192
1193 // Analyze operands of the call, assigning locations to each operand.
1195 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1196 *DAG.getContext());
1197 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1198
1200 CCInfo, CLI, DAG.getMachineFunction());
1201
1202 // Get the size of the outgoing arguments stack space requirement.
1203 // The stack offset computed by CC_Sparc64 includes all arguments.
1204 // Called functions expect 6 argument words to exist in the stack frame, used
1205 // or not.
1206 unsigned StackReserved = 6 * 8u;
1207 unsigned ArgsSize = std::max(StackReserved, CCInfo.getNextStackOffset());
1208
1209 // Keep stack frames 16-byte aligned.
1210 ArgsSize = alignTo(ArgsSize, 16);
1211
1212 // Varargs calls require special treatment.
1213 if (CLI.IsVarArg)
1214 fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1215
1216 assert(!CLI.IsTailCall || ArgsSize == StackReserved);
1217
1218 // Adjust the stack pointer to make room for the arguments.
1219 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1220 // with more than 6 arguments.
1221 if (!CLI.IsTailCall)
1222 Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, DL);
1223
1224 // Collect the set of registers to pass to the function and their values.
1225 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1226 // instruction.
1228
1229 // Collect chains from all the memory opeations that copy arguments to the
1230 // stack. They must follow the stack pointer adjustment above and precede the
1231 // call instruction itself.
1232 SmallVector<SDValue, 8> MemOpChains;
1233
1234 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1235 const CCValAssign &VA = ArgLocs[i];
1236 SDValue Arg = CLI.OutVals[i];
1237
1238 // Promote the value if needed.
1239 switch (VA.getLocInfo()) {
1240 default:
1241 llvm_unreachable("Unknown location info!");
1242 case CCValAssign::Full:
1243 break;
1244 case CCValAssign::SExt:
1245 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1246 break;
1247 case CCValAssign::ZExt:
1248 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1249 break;
1250 case CCValAssign::AExt:
1251 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1252 break;
1253 case CCValAssign::BCvt:
1254 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1255 // SPARC does not support i128 natively. Lower it into two i64, see below.
1256 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1257 || VA.getLocVT() != MVT::i128)
1258 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1259 break;
1260 }
1261
1262 if (VA.isRegLoc()) {
1263 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1264 && VA.getLocVT() == MVT::i128) {
1265 // Store and reload into the integer register reg and reg+1.
1266 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1267 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1268 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1269 SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset, DL);
1270 HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff);
1271 SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8, DL);
1272 LoPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, LoPtrOff);
1273
1274 // Store to %sp+BIAS+128+Offset
1275 SDValue Store =
1276 DAG.getStore(Chain, DL, Arg, HiPtrOff, MachinePointerInfo());
1277 // Load into Reg and Reg+1
1278 SDValue Hi64 =
1279 DAG.getLoad(MVT::i64, DL, Store, HiPtrOff, MachinePointerInfo());
1280 SDValue Lo64 =
1281 DAG.getLoad(MVT::i64, DL, Store, LoPtrOff, MachinePointerInfo());
1282
1283 Register HiReg = VA.getLocReg();
1284 Register LoReg = VA.getLocReg() + 1;
1285 if (!CLI.IsTailCall) {
1286 HiReg = toCallerWindow(HiReg);
1287 LoReg = toCallerWindow(LoReg);
1288 }
1289
1290 RegsToPass.push_back(std::make_pair(HiReg, Hi64));
1291 RegsToPass.push_back(std::make_pair(LoReg, Lo64));
1292 continue;
1293 }
1294
1295 // The custom bit on an i32 return value indicates that it should be
1296 // passed in the high bits of the register.
1297 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1298 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1299 DAG.getConstant(32, DL, MVT::i32));
1300
1301 // The next value may go in the low bits of the same register.
1302 // Handle both at once.
1303 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1304 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1306 CLI.OutVals[i+1]);
1307 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1308 // Skip the next value, it's already done.
1309 ++i;
1310 }
1311 }
1312
1313 Register Reg = VA.getLocReg();
1314 if (!CLI.IsTailCall)
1315 Reg = toCallerWindow(Reg);
1316 RegsToPass.push_back(std::make_pair(Reg, Arg));
1317 continue;
1318 }
1319
1320 assert(VA.isMemLoc());
1321
1322 // Create a store off the stack pointer for this argument.
1323 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1324 // The argument area starts at %fp+BIAS+128 in the callee frame,
1325 // %sp+BIAS+128 in ours.
1326 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1327 Subtarget->getStackPointerBias() +
1328 128, DL);
1329 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
1330 MemOpChains.push_back(
1331 DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
1332 }
1333
1334 // Emit all stores, make sure they occur before the call.
1335 if (!MemOpChains.empty())
1336 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1337
1338 // Build a sequence of CopyToReg nodes glued together with token chain and
1339 // glue operands which copy the outgoing args into registers. The InGlue is
1340 // necessary since all emitted instructions must be stuck together in order
1341 // to pass the live physical registers.
1342 SDValue InGlue;
1343 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1344 Chain = DAG.getCopyToReg(Chain, DL,
1345 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1346 InGlue = Chain.getValue(1);
1347 }
1348
1349 // If the callee is a GlobalAddress node (quite common, every direct call is)
1350 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1351 // Likewise ExternalSymbol -> TargetExternalSymbol.
1352 SDValue Callee = CLI.Callee;
1353 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CB);
1356 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1357 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, TF);
1358 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1359 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, TF);
1360
1361 // Build the operands for the call instruction itself.
1363 Ops.push_back(Chain);
1364 Ops.push_back(Callee);
1365 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1366 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1367 RegsToPass[i].second.getValueType()));
1368
1369 // Add a register mask operand representing the call-preserved registers.
1370 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1371 const uint32_t *Mask =
1372 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv)
1373 : TRI->getCallPreservedMask(DAG.getMachineFunction(),
1374 CLI.CallConv));
1375 assert(Mask && "Missing call preserved mask for calling convention");
1376 Ops.push_back(DAG.getRegisterMask(Mask));
1377
1378 // Make sure the CopyToReg nodes are glued to the call instruction which
1379 // consumes the registers.
1380 if (InGlue.getNode())
1381 Ops.push_back(InGlue);
1382
1383 // Now the call itself.
1384 if (CLI.IsTailCall) {
1386 return DAG.getNode(SPISD::TAIL_CALL, DL, MVT::Other, Ops);
1387 }
1388 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1389 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
1390 InGlue = Chain.getValue(1);
1391
1392 // Revert the stack pointer immediately after the call.
1393 Chain = DAG.getCALLSEQ_END(Chain, ArgsSize, 0, InGlue, DL);
1394 InGlue = Chain.getValue(1);
1395
1396 // Now extract the return values. This is more or less the same as
1397 // LowerFormalArguments_64.
1398
1399 // Assign locations to each value returned by this call.
1401 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1402 *DAG.getContext());
1403
1404 // Set inreg flag manually for codegen generated library calls that
1405 // return float.
1406 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB)
1407 CLI.Ins[0].Flags.setInReg();
1408
1409 RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
1410
1411 // Copy all of the result registers out of their specified physreg.
1412 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1413 CCValAssign &VA = RVLocs[i];
1414 assert(VA.isRegLoc() && "Can only return in registers!");
1415 unsigned Reg = toCallerWindow(VA.getLocReg());
1416
1417 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1418 // reside in the same register in the high and low bits. Reuse the
1419 // CopyFromReg previous node to avoid duplicate copies.
1420 SDValue RV;
1421 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1422 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1423 RV = Chain.getValue(0);
1424
1425 // But usually we'll create a new CopyFromReg for a different register.
1426 if (!RV.getNode()) {
1427 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1428 Chain = RV.getValue(1);
1429 InGlue = Chain.getValue(2);
1430 }
1431
1432 // Get the high bits for i32 struct elements.
1433 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1434 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1435 DAG.getConstant(32, DL, MVT::i32));
1436
1437 // The callee promoted the return value, so insert an Assert?ext SDNode so
1438 // we won't promote the value again in this function.
1439 switch (VA.getLocInfo()) {
1440 case CCValAssign::SExt:
1441 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1442 DAG.getValueType(VA.getValVT()));
1443 break;
1444 case CCValAssign::ZExt:
1445 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1446 DAG.getValueType(VA.getValVT()));
1447 break;
1448 default:
1449 break;
1450 }
1451
1452 // Truncate the register down to the return value type.
1453 if (VA.isExtInLoc())
1454 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1455
1456 InVals.push_back(RV);
1457 }
1458
1459 return Chain;
1460}
1461
1462//===----------------------------------------------------------------------===//
1463// TargetLowering Implementation
1464//===----------------------------------------------------------------------===//
1465
1467 if (AI->getOperation() == AtomicRMWInst::Xchg &&
1468 AI->getType()->getPrimitiveSizeInBits() == 32)
1469 return AtomicExpansionKind::None; // Uses xchg instruction
1470
1472}
1473
1474/// intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC
1475/// rcond condition.
1477 switch (CC) {
1478 default:
1479 llvm_unreachable("Unknown/unsigned integer condition code!");
1480 case ISD::SETEQ:
1481 return SPCC::REG_Z;
1482 case ISD::SETNE:
1483 return SPCC::REG_NZ;
1484 case ISD::SETLT:
1485 return SPCC::REG_LZ;
1486 case ISD::SETGT:
1487 return SPCC::REG_GZ;
1488 case ISD::SETLE:
1489 return SPCC::REG_LEZ;
1490 case ISD::SETGE:
1491 return SPCC::REG_GEZ;
1492 }
1493}
1494
1495/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1496/// condition.
1498 switch (CC) {
1499 default: llvm_unreachable("Unknown integer condition code!");
1500 case ISD::SETEQ: return SPCC::ICC_E;
1501 case ISD::SETNE: return SPCC::ICC_NE;
1502 case ISD::SETLT: return SPCC::ICC_L;
1503 case ISD::SETGT: return SPCC::ICC_G;
1504 case ISD::SETLE: return SPCC::ICC_LE;
1505 case ISD::SETGE: return SPCC::ICC_GE;
1506 case ISD::SETULT: return SPCC::ICC_CS;
1507 case ISD::SETULE: return SPCC::ICC_LEU;
1508 case ISD::SETUGT: return SPCC::ICC_GU;
1509 case ISD::SETUGE: return SPCC::ICC_CC;
1510 }
1511}
1512
1513/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1514/// FCC condition.
1516 switch (CC) {
1517 default: llvm_unreachable("Unknown fp condition code!");
1518 case ISD::SETEQ:
1519 case ISD::SETOEQ: return SPCC::FCC_E;
1520 case ISD::SETNE:
1521 case ISD::SETUNE: return SPCC::FCC_NE;
1522 case ISD::SETLT:
1523 case ISD::SETOLT: return SPCC::FCC_L;
1524 case ISD::SETGT:
1525 case ISD::SETOGT: return SPCC::FCC_G;
1526 case ISD::SETLE:
1527 case ISD::SETOLE: return SPCC::FCC_LE;
1528 case ISD::SETGE:
1529 case ISD::SETOGE: return SPCC::FCC_GE;
1530 case ISD::SETULT: return SPCC::FCC_UL;
1531 case ISD::SETULE: return SPCC::FCC_ULE;
1532 case ISD::SETUGT: return SPCC::FCC_UG;
1533 case ISD::SETUGE: return SPCC::FCC_UGE;
1534 case ISD::SETUO: return SPCC::FCC_U;
1535 case ISD::SETO: return SPCC::FCC_O;
1536 case ISD::SETONE: return SPCC::FCC_LG;
1537 case ISD::SETUEQ: return SPCC::FCC_UE;
1538 }
1539}
1540
1542 const SparcSubtarget &STI)
1543 : TargetLowering(TM), Subtarget(&STI) {
1544 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
1545
1546 // Instructions which use registers as conditionals examine all the
1547 // bits (as does the pseudo SELECT_CC expansion). I don't think it
1548 // matters much whether it's ZeroOrOneBooleanContent, or
1549 // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
1550 // former.
1553
1554 // Set up the register classes.
1555 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1556 if (!Subtarget->useSoftFloat()) {
1557 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1558 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1559 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1560 }
1561 if (Subtarget->is64Bit()) {
1562 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1563 } else {
1564 // On 32bit sparc, we define a double-register 32bit register
1565 // class, as well. This is modeled in LLVM as a 2-vector of i32.
1566 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass);
1567
1568 // ...but almost all operations must be expanded, so set that as
1569 // the default.
1570 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
1572 }
1573 // Truncating/extending stores/loads are also not supported.
1578
1582
1585 }
1586 // However, load and store *are* legal.
1591
1592 // And we need to promote i64 loads/stores into vector load/store
1595
1596 // Sadly, this doesn't work:
1597 // AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
1598 // AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
1599 }
1600
1601 // Turn FP extload into load/fpextend
1602 for (MVT VT : MVT::fp_valuetypes()) {
1606 }
1607
1608 // Sparc doesn't have i1 sign extending load
1609 for (MVT VT : MVT::integer_valuetypes())
1611
1612 // Turn FP truncstore into trunc + store.
1619
1620 // Custom legalize GlobalAddress nodes into LO/HI parts.
1625
1626 // Sparc doesn't have sext_inreg, replace them with shl/sra
1630
1631 // Sparc has no REM or DIVREM operations.
1636
1637 // ... nor does SparcV9.
1638 if (Subtarget->is64Bit()) {
1643 }
1644
1645 // Custom expand fp<->sint
1650
1651 // Custom Expand fp<->uint
1656
1657 // Lower f16 conversion operations into library calls
1664
1667
1668 // Sparc has no select or setcc: expand to SELECT_CC.
1673
1678
1679 // Sparc doesn't have BRCOND either, it has BR_CC.
1687
1692
1697
1698 if (Subtarget->is64Bit()) {
1709
1711 Subtarget->usePopc() ? Legal : Expand);
1718 }
1719
1720 // ATOMICs.
1721 // Atomics are supported on SparcV9. 32-bit atomics are also
1722 // supported by some Leon SparcV8 variants. Otherwise, atomics
1723 // are unsupported.
1724 if (Subtarget->isV9())
1726 else if (Subtarget->hasLeonCasa())
1728 else
1730
1732
1734
1736
1737 // Custom Lower Atomic LOAD/STORE
1740
1741 if (Subtarget->is64Bit()) {
1746 }
1747
1748 if (!Subtarget->is64Bit()) {
1749 // These libcalls are not available in 32-bit.
1750 setLibcallName(RTLIB::MULO_I64, nullptr);
1751 setLibcallName(RTLIB::SHL_I128, nullptr);
1752 setLibcallName(RTLIB::SRL_I128, nullptr);
1753 setLibcallName(RTLIB::SRA_I128, nullptr);
1754 }
1755
1756 setLibcallName(RTLIB::MULO_I128, nullptr);
1757
1758 if (!Subtarget->isV9()) {
1759 // SparcV8 does not have FNEGD and FABSD.
1762 }
1763
1790
1794
1795 // Expands to [SU]MUL_LOHI.
1799
1800 if (Subtarget->useSoftMulDiv()) {
1801 // .umul works for both signed and unsigned
1804 setLibcallName(RTLIB::MUL_I32, ".umul");
1805
1807 setLibcallName(RTLIB::SDIV_I32, ".div");
1808
1810 setLibcallName(RTLIB::UDIV_I32, ".udiv");
1811
1812 setLibcallName(RTLIB::SREM_I32, ".rem");
1813 setLibcallName(RTLIB::UREM_I32, ".urem");
1814 }
1815
1816 if (Subtarget->is64Bit()) {
1821
1824
1828 }
1829
1830 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1832 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1834
1837
1838 // Use the default implementation.
1844
1846
1848 Subtarget->usePopc() ? Legal : Expand);
1849
1850 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1853 } else {
1856 }
1857
1858 if (Subtarget->hasHardQuad()) {
1866 if (Subtarget->isV9()) {
1869 } else {
1872 }
1873
1874 if (!Subtarget->is64Bit()) {
1875 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1876 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1877 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1878 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1879 }
1880
1881 } else {
1882 // Custom legalize f128 operations.
1883
1891
1895
1896 // Setup Runtime library names.
1897 if (Subtarget->is64Bit() && !Subtarget->useSoftFloat()) {
1898 setLibcallName(RTLIB::ADD_F128, "_Qp_add");
1899 setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
1900 setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
1901 setLibcallName(RTLIB::DIV_F128, "_Qp_div");
1902 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1903 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1904 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1905 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1906 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1907 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
1908 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
1909 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
1910 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
1911 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1912 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1913 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1914 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1915 } else if (!Subtarget->useSoftFloat()) {
1916 setLibcallName(RTLIB::ADD_F128, "_Q_add");
1917 setLibcallName(RTLIB::SUB_F128, "_Q_sub");
1918 setLibcallName(RTLIB::MUL_F128, "_Q_mul");
1919 setLibcallName(RTLIB::DIV_F128, "_Q_div");
1920 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1921 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1922 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1923 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1924 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1925 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1926 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1927 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1928 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1929 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1930 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1931 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1932 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1933 }
1934 }
1935
1936 if (Subtarget->fixAllFDIVSQRT()) {
1937 // Promote FDIVS and FSQRTS to FDIVD and FSQRTD instructions instead as
1938 // the former instructions generate errata on LEON processors.
1941 }
1942
1943 if (Subtarget->hasNoFMULS()) {
1945 }
1946
1947 // Custom combine bitcast between f64 and v2i32
1948 if (!Subtarget->is64Bit())
1950
1951 if (Subtarget->hasLeonCycleCounter())
1953
1955
1957
1959}
1960
1962 return Subtarget->useSoftFloat();
1963}
1964
1965const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1966 switch ((SPISD::NodeType)Opcode) {
1967 case SPISD::FIRST_NUMBER: break;
1968 case SPISD::CMPICC: return "SPISD::CMPICC";
1969 case SPISD::CMPFCC: return "SPISD::CMPFCC";
1970 case SPISD::CMPFCC_V9:
1971 return "SPISD::CMPFCC_V9";
1972 case SPISD::BRICC: return "SPISD::BRICC";
1973 case SPISD::BPICC:
1974 return "SPISD::BPICC";
1975 case SPISD::BPXCC:
1976 return "SPISD::BPXCC";
1977 case SPISD::BRFCC: return "SPISD::BRFCC";
1978 case SPISD::BRFCC_V9:
1979 return "SPISD::BRFCC_V9";
1980 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1981 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1982 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1983 case SPISD::SELECT_REG:
1984 return "SPISD::SELECT_REG";
1985 case SPISD::Hi: return "SPISD::Hi";
1986 case SPISD::Lo: return "SPISD::Lo";
1987 case SPISD::FTOI: return "SPISD::FTOI";
1988 case SPISD::ITOF: return "SPISD::ITOF";
1989 case SPISD::FTOX: return "SPISD::FTOX";
1990 case SPISD::XTOF: return "SPISD::XTOF";
1991 case SPISD::CALL: return "SPISD::CALL";
1992 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1993 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1994 case SPISD::FLUSHW: return "SPISD::FLUSHW";
1995 case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
1996 case SPISD::TLS_LD: return "SPISD::TLS_LD";
1997 case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
1998 case SPISD::TAIL_CALL: return "SPISD::TAIL_CALL";
1999 case SPISD::LOAD_GDOP: return "SPISD::LOAD_GDOP";
2000 }
2001 return nullptr;
2002}
2003
2005 EVT VT) const {
2006 if (!VT.isVector())
2007 return MVT::i32;
2009}
2010
2011/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
2012/// be zero. Op is expected to be a target specific node. Used by DAG
2013/// combiner.
2015 (const SDValue Op,
2016 KnownBits &Known,
2017 const APInt &DemandedElts,
2018 const SelectionDAG &DAG,
2019 unsigned Depth) const {
2020 KnownBits Known2;
2021 Known.resetAll();
2022
2023 switch (Op.getOpcode()) {
2024 default: break;
2025 case SPISD::SELECT_ICC:
2026 case SPISD::SELECT_XCC:
2027 case SPISD::SELECT_FCC:
2028 Known = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
2029 Known2 = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
2030
2031 // Only known if known in both the LHS and RHS.
2032 Known = KnownBits::commonBits(Known, Known2);
2033 break;
2034 }
2035}
2036
2037// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
2038// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
2039static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
2040 ISD::CondCode CC, unsigned &SPCC) {
2041 if (isNullConstant(RHS) && CC == ISD::SETNE &&
2042 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
2043 LHS.getOpcode() == SPISD::SELECT_XCC) &&
2044 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
2045 (LHS.getOpcode() == SPISD::SELECT_FCC &&
2046 (LHS.getOperand(3).getOpcode() == SPISD::CMPFCC ||
2047 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC_V9))) &&
2048 isOneConstant(LHS.getOperand(0)) && isNullConstant(LHS.getOperand(1))) {
2049 SDValue CMPCC = LHS.getOperand(3);
2050 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
2051 LHS = CMPCC.getOperand(0);
2052 RHS = CMPCC.getOperand(1);
2053 }
2054}
2055
2056// Convert to a target node and set target flags.
2058 SelectionDAG &DAG) const {
2059 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
2060 return DAG.getTargetGlobalAddress(GA->getGlobal(),
2061 SDLoc(GA),
2062 GA->getValueType(0),
2063 GA->getOffset(), TF);
2064
2065 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
2066 return DAG.getTargetConstantPool(CP->getConstVal(), CP->getValueType(0),
2067 CP->getAlign(), CP->getOffset(), TF);
2068
2069 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
2070 return DAG.getTargetBlockAddress(BA->getBlockAddress(),
2071 Op.getValueType(),
2072 0,
2073 TF);
2074
2075 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
2076 return DAG.getTargetExternalSymbol(ES->getSymbol(),
2077 ES->getValueType(0), TF);
2078
2079 llvm_unreachable("Unhandled address SDNode");
2080}
2081
2082// Split Op into high and low parts according to HiTF and LoTF.
2083// Return an ADD node combining the parts.
2085 unsigned HiTF, unsigned LoTF,
2086 SelectionDAG &DAG) const {
2087 SDLoc DL(Op);
2088 EVT VT = Op.getValueType();
2089 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
2090 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
2091 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
2092}
2093
2094// Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
2095// or ExternalSymbol SDNode.
2097 SDLoc DL(Op);
2098 EVT VT = getPointerTy(DAG.getDataLayout());
2099
2100 // Handle PIC mode first. SPARC needs a got load for every variable!
2101 if (isPositionIndependent()) {
2102 const Module *M = DAG.getMachineFunction().getFunction().getParent();
2103 PICLevel::Level picLevel = M->getPICLevel();
2104 SDValue Idx;
2105
2106 if (picLevel == PICLevel::SmallPIC) {
2107 // This is the pic13 code model, the GOT is known to be smaller than 8KiB.
2108 Idx = DAG.getNode(SPISD::Lo, DL, Op.getValueType(),
2110 } else {
2111 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
2114 }
2115
2116 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
2117 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Idx);
2118 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2119 // function has calls.
2121 MFI.setHasCalls(true);
2122 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
2124 }
2125
2126 // This is one of the absolute code models.
2127 switch(getTargetMachine().getCodeModel()) {
2128 default:
2129 llvm_unreachable("Unsupported absolute code model");
2130 case CodeModel::Small:
2131 // abs32.
2134 case CodeModel::Medium: {
2135 // abs44.
2138 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32));
2140 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
2141 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
2142 }
2143 case CodeModel::Large: {
2144 // abs64.
2147 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32));
2150 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
2151 }
2152 }
2153}
2154
2156 SelectionDAG &DAG) const {
2157 return makeAddress(Op, DAG);
2158}
2159
2161 SelectionDAG &DAG) const {
2162 return makeAddress(Op, DAG);
2163}
2164
2166 SelectionDAG &DAG) const {
2167 return makeAddress(Op, DAG);
2168}
2169
2171 SelectionDAG &DAG) const {
2172
2173 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2174 if (DAG.getTarget().useEmulatedTLS())
2175 return LowerToTLSEmulatedModel(GA, DAG);
2176
2177 SDLoc DL(GA);
2178 const GlobalValue *GV = GA->getGlobal();
2179 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2180
2182
2183 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2184 unsigned HiTF = ((model == TLSModel::GeneralDynamic)
2187 unsigned LoTF = ((model == TLSModel::GeneralDynamic)
2190 unsigned addTF = ((model == TLSModel::GeneralDynamic)
2193 unsigned callTF = ((model == TLSModel::GeneralDynamic)
2196
2197 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
2199 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
2200 withTargetFlags(Op, addTF, DAG));
2201
2202 SDValue Chain = DAG.getEntryNode();
2203 SDValue InFlag;
2204
2205 Chain = DAG.getCALLSEQ_START(Chain, 1, 0, DL);
2206 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
2207 InFlag = Chain.getValue(1);
2208 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
2209 SDValue Symbol = withTargetFlags(Op, callTF, DAG);
2210
2211 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2212 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
2214 assert(Mask && "Missing call preserved mask for calling convention");
2215 SDValue Ops[] = {Chain,
2216 Callee,
2217 Symbol,
2218 DAG.getRegister(SP::O0, PtrVT),
2219 DAG.getRegisterMask(Mask),
2220 InFlag};
2221 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
2222 InFlag = Chain.getValue(1);
2223 Chain = DAG.getCALLSEQ_END(Chain, 1, 0, InFlag, DL);
2224 InFlag = Chain.getValue(1);
2225 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
2226
2227 if (model != TLSModel::LocalDynamic)
2228 return Ret;
2229
2230 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2232 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2234 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2235 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
2237 }
2238
2239 if (model == TLSModel::InitialExec) {
2240 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX
2242
2244
2245 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2246 // function has calls.
2248 MFI.setHasCalls(true);
2249
2250 SDValue TGA = makeHiLoPair(Op,
2253 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
2255 DL, PtrVT, Ptr,
2256 withTargetFlags(Op, ldTF, DAG));
2257 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
2258 DAG.getRegister(SP::G7, PtrVT), Offset,
2259 withTargetFlags(Op,
2261 }
2262
2263 assert(model == TLSModel::LocalExec);
2264 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2266 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2268 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2269
2270 return DAG.getNode(ISD::ADD, DL, PtrVT,
2271 DAG.getRegister(SP::G7, PtrVT), Offset);
2272}
2273
2275 ArgListTy &Args, SDValue Arg,
2276 const SDLoc &DL,
2277 SelectionDAG &DAG) const {
2279 EVT ArgVT = Arg.getValueType();
2280 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2281
2282 ArgListEntry Entry;
2283 Entry.Node = Arg;
2284 Entry.Ty = ArgTy;
2285
2286 if (ArgTy->isFP128Ty()) {
2287 // Create a stack object and pass the pointer to the library function.
2288 int FI = MFI.CreateStackObject(16, Align(8), false);
2289 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2290 Chain = DAG.getStore(Chain, DL, Entry.Node, FIPtr, MachinePointerInfo(),
2291 Align(8));
2292
2293 Entry.Node = FIPtr;
2294 Entry.Ty = PointerType::getUnqual(ArgTy);
2295 }
2296 Args.push_back(Entry);
2297 return Chain;
2298}
2299
2300SDValue
2302 const char *LibFuncName,
2303 unsigned numArgs) const {
2304
2305 ArgListTy Args;
2306
2308 auto PtrVT = getPointerTy(DAG.getDataLayout());
2309
2310 SDValue Callee = DAG.getExternalSymbol(LibFuncName, PtrVT);
2311 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2312 Type *RetTyABI = RetTy;
2313 SDValue Chain = DAG.getEntryNode();
2314 SDValue RetPtr;
2315
2316 if (RetTy->isFP128Ty()) {
2317 // Create a Stack Object to receive the return value of type f128.
2318 ArgListEntry Entry;
2319 int RetFI = MFI.CreateStackObject(16, Align(8), false);
2320 RetPtr = DAG.getFrameIndex(RetFI, PtrVT);
2321 Entry.Node = RetPtr;
2322 Entry.Ty = PointerType::getUnqual(RetTy);
2323 if (!Subtarget->is64Bit()) {
2324 Entry.IsSRet = true;
2325 Entry.IndirectType = RetTy;
2326 }
2327 Entry.IsReturned = false;
2328 Args.push_back(Entry);
2329 RetTyABI = Type::getVoidTy(*DAG.getContext());
2330 }
2331
2332 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2333 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2334 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
2335 }
2337 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
2338 .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args));
2339
2340 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2341
2342 // chain is in second result.
2343 if (RetTyABI == RetTy)
2344 return CallInfo.first;
2345
2346 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2347
2348 Chain = CallInfo.second;
2349
2350 // Load RetPtr to get the return value.
2351 return DAG.getLoad(Op.getValueType(), SDLoc(Op), Chain, RetPtr,
2353}
2354
2356 unsigned &SPCC, const SDLoc &DL,
2357 SelectionDAG &DAG) const {
2358
2359 const char *LibCall = nullptr;
2360 bool is64Bit = Subtarget->is64Bit();
2361 switch(SPCC) {
2362 default: llvm_unreachable("Unhandled conditional code!");
2363 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2364 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2365 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2366 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2367 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2368 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2369 case SPCC::FCC_UL :
2370 case SPCC::FCC_ULE:
2371 case SPCC::FCC_UG :
2372 case SPCC::FCC_UGE:
2373 case SPCC::FCC_U :
2374 case SPCC::FCC_O :
2375 case SPCC::FCC_LG :
2376 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2377 }
2378
2379 auto PtrVT = getPointerTy(DAG.getDataLayout());
2382 ArgListTy Args;
2383 SDValue Chain = DAG.getEntryNode();
2384 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
2385 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
2386
2388 CLI.setDebugLoc(DL).setChain(Chain)
2389 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args));
2390
2391 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2392
2393 // result is in first, and chain is in second result.
2394 SDValue Result = CallInfo.first;
2395
2396 switch(SPCC) {
2397 default: {
2398 SDValue RHS = DAG.getConstant(0, DL, Result.getValueType());
2399 SPCC = SPCC::ICC_NE;
2400 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2401 }
2402 case SPCC::FCC_UL : {
2403 SDValue Mask = DAG.getConstant(1, DL, Result.getValueType());
2404 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2405 SDValue RHS = DAG.getConstant(0, DL, Result.getValueType());
2406 SPCC = SPCC::ICC_NE;
2407 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2408 }
2409 case SPCC::FCC_ULE: {
2410 SDValue RHS = DAG.getConstant(2, DL, Result.getValueType());
2411 SPCC = SPCC::ICC_NE;
2412 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2413 }
2414 case SPCC::FCC_UG : {
2415 SDValue RHS = DAG.getConstant(1, DL, Result.getValueType());
2416 SPCC = SPCC::ICC_G;
2417 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2418 }
2419 case SPCC::FCC_UGE: {
2420 SDValue RHS = DAG.getConstant(1, DL, Result.getValueType());
2421 SPCC = SPCC::ICC_NE;
2422 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2423 }
2424
2425 case SPCC::FCC_U : {
2426 SDValue RHS = DAG.getConstant(3, DL, Result.getValueType());
2427 SPCC = SPCC::ICC_E;
2428 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2429 }
2430 case SPCC::FCC_O : {
2431 SDValue RHS = DAG.getConstant(3, DL, Result.getValueType());
2432 SPCC = SPCC::ICC_NE;
2433 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2434 }
2435 case SPCC::FCC_LG : {
2436 SDValue Mask = DAG.getConstant(3, DL, Result.getValueType());
2437 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2438 SDValue RHS = DAG.getConstant(0, DL, Result.getValueType());
2439 SPCC = SPCC::ICC_NE;
2440 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2441 }
2442 case SPCC::FCC_UE : {
2443 SDValue Mask = DAG.getConstant(3, DL, Result.getValueType());
2444 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2445 SDValue RHS = DAG.getConstant(0, DL, Result.getValueType());
2446 SPCC = SPCC::ICC_E;
2447 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2448 }
2449 }
2450}
2451
2452static SDValue
2454 const SparcTargetLowering &TLI) {
2455
2456 if (Op.getOperand(0).getValueType() == MVT::f64)
2457 return TLI.LowerF128Op(Op, DAG,
2458 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2459
2460 if (Op.getOperand(0).getValueType() == MVT::f32)
2461 return TLI.LowerF128Op(Op, DAG,
2462 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2463
2464 llvm_unreachable("fpextend with non-float operand!");
2465 return SDValue();
2466}
2467
2468static SDValue
2470 const SparcTargetLowering &TLI) {
2471 // FP_ROUND on f64 and f32 are legal.
2472 if (Op.getOperand(0).getValueType() != MVT::f128)
2473 return Op;
2474
2475 if (Op.getValueType() == MVT::f64)
2476 return TLI.LowerF128Op(Op, DAG,
2477 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2478 if (Op.getValueType() == MVT::f32)
2479 return TLI.LowerF128Op(Op, DAG,
2480 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2481
2482 llvm_unreachable("fpround to non-float!");
2483 return SDValue();
2484}
2485
2487 const SparcTargetLowering &TLI,
2488 bool hasHardQuad) {
2489 SDLoc dl(Op);
2490 EVT VT = Op.getValueType();
2491 assert(VT == MVT::i32 || VT == MVT::i64);
2492
2493 // Expand f128 operations to fp128 abi calls.
2494 if (Op.getOperand(0).getValueType() == MVT::f128
2495 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2496 const char *libName = TLI.getLibcallName(VT == MVT::i32
2497 ? RTLIB::FPTOSINT_F128_I32
2498 : RTLIB::FPTOSINT_F128_I64);
2499 return TLI.LowerF128Op(Op, DAG, libName, 1);
2500 }
2501
2502 // Expand if the resulting type is illegal.
2503 if (!TLI.isTypeLegal(VT))
2504 return SDValue();
2505
2506 // Otherwise, Convert the fp value to integer in an FP register.
2507 if (VT == MVT::i32)
2508 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2509 else
2510 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2511
2512 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2513}
2514
2516 const SparcTargetLowering &TLI,
2517 bool hasHardQuad) {
2518 SDLoc dl(Op);
2519 EVT OpVT = Op.getOperand(0).getValueType();
2520 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2521
2522 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2523
2524 // Expand f128 operations to fp128 ABI calls.
2525 if (Op.getValueType() == MVT::f128
2526 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2527 const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2528 ? RTLIB::SINTTOFP_I32_F128
2529 : RTLIB::SINTTOFP_I64_F128);
2530 return TLI.LowerF128Op(Op, DAG, libName, 1);
2531 }
2532
2533 // Expand if the operand type is illegal.
2534 if (!TLI.isTypeLegal(OpVT))
2535 return SDValue();
2536
2537 // Otherwise, Convert the int value to FP in an FP register.
2538 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2539 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2540 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2541}
2542
2544 const SparcTargetLowering &TLI,
2545 bool hasHardQuad) {
2546 SDLoc dl(Op);
2547 EVT VT = Op.getValueType();
2548
2549 // Expand if it does not involve f128 or the target has support for
2550 // quad floating point instructions and the resulting type is legal.
2551 if (Op.getOperand(0).getValueType() != MVT::f128 ||
2552 (hasHardQuad && TLI.isTypeLegal(VT)))
2553 return SDValue();
2554
2555 assert(VT == MVT::i32 || VT == MVT::i64);
2556
2557 return TLI.LowerF128Op(Op, DAG,
2558 TLI.getLibcallName(VT == MVT::i32
2559 ? RTLIB::FPTOUINT_F128_I32
2560 : RTLIB::FPTOUINT_F128_I64),
2561 1);
2562}
2563
2565 const SparcTargetLowering &TLI,
2566 bool hasHardQuad) {
2567 SDLoc dl(Op);
2568 EVT OpVT = Op.getOperand(0).getValueType();
2569 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2570
2571 // Expand if it does not involve f128 or the target has support for
2572 // quad floating point instructions and the operand type is legal.
2573 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2574 return SDValue();
2575
2576 return TLI.LowerF128Op(Op, DAG,
2577 TLI.getLibcallName(OpVT == MVT::i32
2578 ? RTLIB::UINTTOFP_I32_F128
2579 : RTLIB::UINTTOFP_I64_F128),
2580 1);
2581}
2582
2584 const SparcTargetLowering &TLI, bool hasHardQuad,
2585 bool isV9) {
2586 SDValue Chain = Op.getOperand(0);
2587 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2588 SDValue LHS = Op.getOperand(2);
2589 SDValue RHS = Op.getOperand(3);
2590 SDValue Dest = Op.getOperand(4);
2591 SDLoc dl(Op);
2592 unsigned Opc, SPCC = ~0U;
2593
2594 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2595 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2596 LookThroughSetCC(LHS, RHS, CC, SPCC);
2597 assert(LHS.getValueType() == RHS.getValueType());
2598
2599 // Get the condition flag.
2600 SDValue CompareFlag;
2601 if (LHS.getValueType().isInteger()) {
2602 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2603 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2604 if (isV9)
2605 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2606 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BPICC : SPISD::BPXCC;
2607 else
2608 // Non-v9 targets don't have xcc.
2609 Opc = SPISD::BRICC;
2610 } else {
2611 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2612 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2613 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2614 Opc = isV9 ? SPISD::BPICC : SPISD::BRICC;
2615 } else {
2616 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2617 CompareFlag = DAG.getNode(CmpOpc, dl, MVT::Glue, LHS, RHS);
2618 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2619 Opc = isV9 ? SPISD::BRFCC_V9 : SPISD::BRFCC;
2620 }
2621 }
2622 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2623 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2624}
2625
2627 const SparcTargetLowering &TLI, bool hasHardQuad,
2628 bool isV9, bool is64Bit) {
2629 SDValue LHS = Op.getOperand(0);
2630 SDValue RHS = Op.getOperand(1);
2631 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2632 SDValue TrueVal = Op.getOperand(2);
2633 SDValue FalseVal = Op.getOperand(3);
2634 SDLoc dl(Op);
2635 unsigned Opc, SPCC = ~0U;
2636
2637 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2638 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2639 LookThroughSetCC(LHS, RHS, CC, SPCC);
2640 assert(LHS.getValueType() == RHS.getValueType());
2641
2642 SDValue CompareFlag;
2643 if (LHS.getValueType().isInteger()) {
2644 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2645 // and the RHS is zero we might be able to use a specialized select.
2646 // All SELECT_CC between any two scalar integer types are eligible for
2647 // lowering to specialized instructions. Additionally, f32 and f64 types
2648 // are also eligible, but for f128 we can only use the specialized
2649 // instruction when we have hardquad.
2650 EVT ValType = TrueVal.getValueType();
2651 bool IsEligibleType = ValType.isScalarInteger() || ValType == MVT::f32 ||
2652 ValType == MVT::f64 ||
2653 (ValType == MVT::f128 && hasHardQuad);
2654 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2655 isNullConstant(RHS) && !ISD::isUnsignedIntSetCC(CC) && IsEligibleType)
2656 return DAG.getNode(
2657 SPISD::SELECT_REG, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2659
2660 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2661 Opc = LHS.getValueType() == MVT::i32 ?
2663 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2664 } else {
2665 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2666 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2667 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2668 Opc = SPISD::SELECT_ICC;
2669 } else {
2670 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2671 CompareFlag = DAG.getNode(CmpOpc, dl, MVT::Glue, LHS, RHS);
2672 Opc = SPISD::SELECT_FCC;
2673 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2674 }
2675 }
2676 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2677 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2678}
2679
2681 const SparcTargetLowering &TLI) {
2684 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2685
2686 // Need frame address to find the address of VarArgsFrameIndex.
2688
2689 // vastart just stores the address of the VarArgsFrameIndex slot into the
2690 // memory location argument.
2691 SDLoc DL(Op);
2692 SDValue Offset =
2693 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT),
2694 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL));
2695 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2696 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2697 MachinePointerInfo(SV));
2698}
2699
2701 SDNode *Node = Op.getNode();
2702 EVT VT = Node->getValueType(0);
2703 SDValue InChain = Node->getOperand(0);
2704 SDValue VAListPtr = Node->getOperand(1);
2705 EVT PtrVT = VAListPtr.getValueType();
2706 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2707 SDLoc DL(Node);
2708 SDValue VAList =
2709 DAG.getLoad(PtrVT, DL, InChain, VAListPtr, MachinePointerInfo(SV));
2710 // Increment the pointer, VAList, to the next vaarg.
2711 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2713 DL));
2714 // Store the incremented VAList to the legalized pointer.
2715 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr, VAListPtr,
2716 MachinePointerInfo(SV));
2717 // Load the actual argument out of the pointer VAList.
2718 // We can't count on greater alignment than the word size.
2719 return DAG.getLoad(
2720 VT, DL, InChain, VAList, MachinePointerInfo(),
2721 Align(std::min(PtrVT.getFixedSizeInBits(), VT.getFixedSizeInBits()) / 8));
2722}
2723
2725 const SparcSubtarget *Subtarget) {
2726 SDValue Chain = Op.getOperand(0); // Legalize the chain.
2727 SDValue Size = Op.getOperand(1); // Legalize the size.
2728 MaybeAlign Alignment =
2729 cast<ConstantSDNode>(Op.getOperand(2))->getMaybeAlignValue();
2730 Align StackAlign = Subtarget->getFrameLowering()->getStackAlign();
2731 EVT VT = Size->getValueType(0);
2732 SDLoc dl(Op);
2733
2734 // TODO: implement over-aligned alloca. (Note: also implies
2735 // supporting support for overaligned function frames + dynamic
2736 // allocations, at all, which currently isn't supported)
2737 if (Alignment && *Alignment > StackAlign) {
2738 const MachineFunction &MF = DAG.getMachineFunction();
2739 report_fatal_error("Function \"" + Twine(MF.getName()) + "\": "
2740 "over-aligned dynamic alloca not supported.");
2741 }
2742
2743 // The resultant pointer needs to be above the register spill area
2744 // at the bottom of the stack.
2745 unsigned regSpillArea;
2746 if (Subtarget->is64Bit()) {
2747 regSpillArea = 128;
2748 } else {
2749 // On Sparc32, the size of the spill area is 92. Unfortunately,
2750 // that's only 4-byte aligned, not 8-byte aligned (the stack
2751 // pointer is 8-byte aligned). So, if the user asked for an 8-byte
2752 // aligned dynamic allocation, we actually need to add 96 to the
2753 // bottom of the stack, instead of 92, to ensure 8-byte alignment.
2754
2755 // That also means adding 4 to the size of the allocation --
2756 // before applying the 8-byte rounding. Unfortunately, we the
2757 // value we get here has already had rounding applied. So, we need
2758 // to add 8, instead, wasting a bit more memory.
2759
2760 // Further, this only actually needs to be done if the required
2761 // alignment is > 4, but, we've lost that info by this point, too,
2762 // so we always apply it.
2763
2764 // (An alternative approach would be to always reserve 96 bytes
2765 // instead of the required 92, but then we'd waste 4 extra bytes
2766 // in every frame, not just those with dynamic stack allocations)
2767
2768 // TODO: modify code in SelectionDAGBuilder to make this less sad.
2769
2770 Size = DAG.getNode(ISD::ADD, dl, VT, Size,
2771 DAG.getConstant(8, dl, VT));
2772 regSpillArea = 96;
2773 }
2774
2775 unsigned SPReg = SP::O6;
2776 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2777 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2778 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2779
2780 regSpillArea += Subtarget->getStackPointerBias();
2781
2782 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
2783 DAG.getConstant(regSpillArea, dl, VT));
2784 SDValue Ops[2] = { NewVal, Chain };
2785 return DAG.getMergeValues(Ops, dl);
2786}
2787
2788
2790 SDLoc dl(Op);
2791 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2792 dl, MVT::Other, DAG.getEntryNode());
2793 return Chain;
2794}
2795
2797 const SparcSubtarget *Subtarget,
2798 bool AlwaysFlush = false) {
2800 MFI.setFrameAddressIsTaken(true);
2801
2802 EVT VT = Op.getValueType();
2803 SDLoc dl(Op);
2804 unsigned FrameReg = SP::I6;
2805 unsigned stackBias = Subtarget->getStackPointerBias();
2806
2807 SDValue FrameAddr;
2808 SDValue Chain;
2809
2810 // flush first to make sure the windowed registers' values are in stack
2811 Chain = (depth || AlwaysFlush) ? getFLUSHW(Op, DAG) : DAG.getEntryNode();
2812
2813 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2814
2815 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2816
2817 while (depth--) {
2818 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2819 DAG.getIntPtrConstant(Offset, dl));
2820 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo());
2821 }
2822 if (Subtarget->is64Bit())
2823 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2824 DAG.getIntPtrConstant(stackBias, dl));
2825 return FrameAddr;
2826}
2827
2828
2830 const SparcSubtarget *Subtarget) {
2831
2832 uint64_t depth = Op.getConstantOperandVal(0);
2833
2834 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2835
2836}
2837
2839 const SparcTargetLowering &TLI,
2840 const SparcSubtarget *Subtarget) {
2842 MachineFrameInfo &MFI = MF.getFrameInfo();
2843 MFI.setReturnAddressIsTaken(true);
2844
2846 return SDValue();
2847
2848 EVT VT = Op.getValueType();
2849 SDLoc dl(Op);
2850 uint64_t depth = Op.getConstantOperandVal(0);
2851
2852 SDValue RetAddr;
2853 if (depth == 0) {
2854 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2855 Register RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
2856 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2857 return RetAddr;
2858 }
2859
2860 // Need frame address to find return address of the caller.
2861 SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget, true);
2862
2863 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2865 dl, VT,
2866 FrameAddr,
2867 DAG.getIntPtrConstant(Offset, dl));
2868 RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr, MachinePointerInfo());
2869
2870 return RetAddr;
2871}
2872
2873static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG,
2874 unsigned opcode) {
2875 assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2876 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2877
2878 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2879 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2880 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2881
2882 // Note: in little-endian, the floating-point value is stored in the
2883 // registers are in the opposite order, so the subreg with the sign
2884 // bit is the highest-numbered (odd), rather than the
2885 // lowest-numbered (even).
2886
2887 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2888 SrcReg64);
2889 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2890 SrcReg64);
2891
2892 if (DAG.getDataLayout().isLittleEndian())
2893 Lo32 = DAG.getNode(opcode, dl, MVT::f32, Lo32);
2894 else
2895 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2896
2897 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2898 dl, MVT::f64), 0);
2899 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2900 DstReg64, Hi32);
2901 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2902 DstReg64, Lo32);
2903 return DstReg64;
2904}
2905
2906// Lower a f128 load into two f64 loads.
2908{
2909 SDLoc dl(Op);
2910 LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
2911 assert(LdNode->getOffset().isUndef() && "Unexpected node type");
2912
2913 Align Alignment = commonAlignment(LdNode->getOriginalAlign(), 8);
2914
2915 SDValue Hi64 =
2916 DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LdNode->getBasePtr(),
2917 LdNode->getPointerInfo(), Alignment);
2918 EVT addrVT = LdNode->getBasePtr().getValueType();
2919 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2920 LdNode->getBasePtr(),
2921 DAG.getConstant(8, dl, addrVT));
2922 SDValue Lo64 = DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LoPtr,
2923 LdNode->getPointerInfo().getWithOffset(8),
2924 Alignment);
2925
2926 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2927 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2928
2929 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2930 dl, MVT::f128);
2931 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2932 MVT::f128,
2933 SDValue(InFP128, 0),
2934 Hi64,
2935 SubRegEven);
2936 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2937 MVT::f128,
2938 SDValue(InFP128, 0),
2939 Lo64,
2940 SubRegOdd);
2941 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2942 SDValue(Lo64.getNode(), 1) };
2943 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2944 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2945 return DAG.getMergeValues(Ops, dl);
2946}
2947
2949{
2950 LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
2951
2952 EVT MemVT = LdNode->getMemoryVT();
2953 if (MemVT == MVT::f128)
2954 return LowerF128Load(Op, DAG);
2955
2956 return Op;
2957}
2958
2959// Lower a f128 store into two f64 stores.
2961 SDLoc dl(Op);
2962 StoreSDNode *StNode = cast<StoreSDNode>(Op.getNode());
2963 assert(StNode->getOffset().isUndef() && "Unexpected node type");
2964
2965 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2966 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2967
2968 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2969 dl,
2970 MVT::f64,
2971 StNode->getValue(),
2972 SubRegEven);
2973 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2974 dl,
2975 MVT::f64,
2976 StNode->getValue(),
2977 SubRegOdd);
2978
2979 Align Alignment = commonAlignment(StNode->getOriginalAlign(), 8);
2980
2981 SDValue OutChains[2];
2982 OutChains[0] =
2983 DAG.getStore(StNode->getChain(), dl, SDValue(Hi64, 0),
2984 StNode->getBasePtr(), StNode->getPointerInfo(),
2985 Alignment);
2986 EVT addrVT = StNode->getBasePtr().getValueType();
2987 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2988 StNode->getBasePtr(),
2989 DAG.getConstant(8, dl, addrVT));
2990 OutChains[1] = DAG.getStore(StNode->getChain(), dl, SDValue(Lo64, 0), LoPtr,
2991 StNode->getPointerInfo().getWithOffset(8),
2992 Alignment);
2993 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2994}
2995
2997{
2998 SDLoc dl(Op);
2999 StoreSDNode *St = cast<StoreSDNode>(Op.getNode());
3000
3001 EVT MemVT = St->getMemoryVT();
3002 if (MemVT == MVT::f128)
3003 return LowerF128Store(Op, DAG);
3004
3005 if (MemVT == MVT::i64) {
3006 // Custom handling for i64 stores: turn it into a bitcast and a
3007 // v2i32 store.
3008 SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue());
3009 SDValue Chain = DAG.getStore(
3010 St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(),
3011 St->getOriginalAlign(), St->getMemOperand()->getFlags(),
3012 St->getAAInfo());
3013 return Chain;
3014 }
3015
3016 return SDValue();
3017}
3018
3019static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
3020 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
3021 && "invalid opcode");
3022
3023 SDLoc dl(Op);
3024
3025 if (Op.getValueType() == MVT::f64)
3026 return LowerF64Op(Op.getOperand(0), dl, DAG, Op.getOpcode());
3027 if (Op.getValueType() != MVT::f128)
3028 return Op;
3029
3030 // Lower fabs/fneg on f128 to fabs/fneg on f64
3031 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
3032 // (As with LowerF64Op, on little-endian, we need to negate the odd
3033 // subreg)
3034
3035 SDValue SrcReg128 = Op.getOperand(0);
3036 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
3037 SrcReg128);
3038 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
3039 SrcReg128);
3040
3041 if (DAG.getDataLayout().isLittleEndian()) {
3042 if (isV9)
3043 Lo64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Lo64);
3044 else
3045 Lo64 = LowerF64Op(Lo64, dl, DAG, Op.getOpcode());
3046 } else {
3047 if (isV9)
3048 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
3049 else
3050 Hi64 = LowerF64Op(Hi64, dl, DAG, Op.getOpcode());
3051 }
3052
3053 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
3054 dl, MVT::f128), 0);
3055 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
3056 DstReg128, Hi64);
3057 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
3058 DstReg128, Lo64);
3059 return DstReg128;
3060}
3061
3063
3064 if (Op.getValueType() != MVT::i64)
3065 return Op;
3066
3067 SDLoc dl(Op);
3068 SDValue Src1 = Op.getOperand(0);
3069 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
3070 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
3071 DAG.getConstant(32, dl, MVT::i64));
3072 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
3073
3074 SDValue Src2 = Op.getOperand(1);
3075 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
3076 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
3077 DAG.getConstant(32, dl, MVT::i64));
3078 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
3079
3080
3081 bool hasChain = false;
3082 unsigned hiOpc = Op.getOpcode();
3083 switch (Op.getOpcode()) {
3084 default: llvm_unreachable("Invalid opcode");
3085 case ISD::ADDC: hiOpc = ISD::ADDE; break;
3086 case ISD::ADDE: hasChain = true; break;
3087 case ISD::SUBC: hiOpc = ISD::SUBE; break;
3088 case ISD::SUBE: hasChain = true; break;
3089 }
3090 SDValue Lo;
3092 if (hasChain) {
3093 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
3094 Op.getOperand(2));
3095 } else {
3096 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
3097 }
3098 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
3099 SDValue Carry = Hi.getValue(1);
3100
3101 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
3102 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
3103 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
3104 DAG.getConstant(32, dl, MVT::i64));
3105
3106 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
3107 SDValue Ops[2] = { Dst, Carry };
3108 return DAG.getMergeValues(Ops, dl);
3109}
3110
3111// Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
3112// in LegalizeDAG.cpp except the order of arguments to the library function.
3114 const SparcTargetLowering &TLI)
3115{
3116 unsigned opcode = Op.getOpcode();
3117 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
3118
3119 bool isSigned = (opcode == ISD::SMULO);
3120 EVT VT = MVT::i64;
3121 EVT WideVT = MVT::i128;
3122 SDLoc dl(Op);
3123 SDValue LHS = Op.getOperand(0);
3124
3125 if (LHS.getValueType() != VT)
3126 return Op;
3127
3128 SDValue ShiftAmt = DAG.getConstant(63, dl, VT);
3129
3130 SDValue RHS = Op.getOperand(1);
3131 SDValue HiLHS, HiRHS;
3132 if (isSigned) {
3133 HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
3134 HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
3135 } else {
3136 HiLHS = DAG.getConstant(0, dl, VT);
3137 HiRHS = DAG.getConstant(0, dl, MVT::i64);
3138 }
3139
3140 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
3141
3143 CallOptions.setSExt(isSigned);
3144 SDValue MulResult = TLI.makeLibCall(DAG,
3145 RTLIB::MUL_I128, WideVT,
3146 Args, CallOptions, dl).first;
3147 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
3148 MulResult, DAG.getIntPtrConstant(0, dl));
3149 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
3150 MulResult, DAG.getIntPtrConstant(1, dl));
3151 if (isSigned) {
3152 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
3153 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
3154 } else {
3155 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT),
3156 ISD::SETNE);
3157 }
3158 // MulResult is a node with an illegal type. Because such things are not
3159 // generally permitted during this phase of legalization, ensure that
3160 // nothing is left using the node. The above EXTRACT_ELEMENT nodes should have
3161 // been folded.
3162 assert(MulResult->use_empty() && "Illegally typed node still in use!");
3163
3164 SDValue Ops[2] = { BottomHalf, TopHalf } ;
3165 return DAG.getMergeValues(Ops, dl);
3166}
3167
3169 if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getSuccessOrdering())) {
3170 // Expand with a fence.
3171 return SDValue();
3172 }
3173
3174 // Monotonic load/stores are legal.
3175 return Op;
3176}
3177
3179 SelectionDAG &DAG) const {
3180 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3181 SDLoc dl(Op);
3182 switch (IntNo) {
3183 default: return SDValue(); // Don't custom lower most intrinsics.
3184 case Intrinsic::thread_pointer: {
3185 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3186 return DAG.getRegister(SP::G7, PtrVT);
3187 }
3188 }
3189}
3190
3192LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3193
3194 bool hasHardQuad = Subtarget->hasHardQuad();
3195 bool isV9 = Subtarget->isV9();
3196 bool is64Bit = Subtarget->is64Bit();
3197
3198 switch (Op.getOpcode()) {
3199 default: llvm_unreachable("Should not custom lower this!");
3200
3201 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this,
3202 Subtarget);
3203 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
3204 Subtarget);
3205 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3206 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3207 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3208 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3209 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
3210 hasHardQuad);
3211 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
3212 hasHardQuad);
3213 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
3214 hasHardQuad);
3215 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
3216 hasHardQuad);
3217 case ISD::BR_CC:
3218 return LowerBR_CC(Op, DAG, *this, hasHardQuad, isV9);
3219 case ISD::SELECT_CC:
3220 return LowerSELECT_CC(Op, DAG, *this, hasHardQuad, isV9, is64Bit);
3221 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
3222 case ISD::VAARG: return LowerVAARG(Op, DAG);
3224 Subtarget);
3225
3226 case ISD::LOAD: return LowerLOAD(Op, DAG);
3227 case ISD::STORE: return LowerSTORE(Op, DAG);
3228 case ISD::FADD: return LowerF128Op(Op, DAG,
3229 getLibcallName(RTLIB::ADD_F128), 2);
3230 case ISD::FSUB: return LowerF128Op(Op, DAG,
3231 getLibcallName(RTLIB::SUB_F128), 2);
3232 case ISD::FMUL: return LowerF128Op(Op, DAG,
3233 getLibcallName(RTLIB::MUL_F128), 2);
3234 case ISD::FDIV: return LowerF128Op(Op, DAG,
3235 getLibcallName(RTLIB::DIV_F128), 2);
3236 case ISD::FSQRT: return LowerF128Op(Op, DAG,
3237 getLibcallName(RTLIB::SQRT_F128),1);
3238 case ISD::FABS:
3239 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
3240 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
3241 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
3242 case ISD::ADDC:
3243 case ISD::ADDE:
3244 case ISD::SUBC:
3245 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
3246 case ISD::UMULO:
3247 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
3248 case ISD::ATOMIC_LOAD:
3249 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
3251 }
3252}
3253
3255 const SDLoc &DL,
3256 SelectionDAG &DAG) const {
3257 APInt V = C->getValueAPF().bitcastToAPInt();
3259 SDValue Hi = DAG.getConstant(V.lshr(32).zextOrTrunc(32), DL, MVT::i32);
3260 if (DAG.getDataLayout().isLittleEndian())
3261 std::swap(Lo, Hi);
3262 return DAG.getBuildVector(MVT::v2i32, DL, {Hi, Lo});
3263}
3264
3266 DAGCombinerInfo &DCI) const {
3267 SDLoc dl(N);
3268 SDValue Src = N->getOperand(0);
3269
3270 if (isa<ConstantFPSDNode>(Src) && N->getSimpleValueType(0) == MVT::v2i32 &&
3271 Src.getSimpleValueType() == MVT::f64)
3272 return bitcastConstantFPToInt(cast<ConstantFPSDNode>(Src), dl, DCI.DAG);
3273
3274 return SDValue();
3275}
3276
3278 DAGCombinerInfo &DCI) const {
3279 switch (N->getOpcode()) {
3280 default:
3281 break;
3282 case ISD::BITCAST:
3283 return PerformBITCASTCombine(N, DCI);
3284 }
3285 return SDValue();
3286}
3287
3290 MachineBasicBlock *BB) const {
3291 switch (MI.getOpcode()) {
3292 default: llvm_unreachable("Unknown SELECT_CC!");
3293 case SP::SELECT_CC_Int_ICC:
3294 case SP::SELECT_CC_FP_ICC:
3295 case SP::SELECT_CC_DFP_ICC:
3296 case SP::SELECT_CC_QFP_ICC:
3297 if (Subtarget->isV9())
3298 return expandSelectCC(MI, BB, SP::BPICC);
3299 return expandSelectCC(MI, BB, SP::BCOND);
3300 case SP::SELECT_CC_Int_XCC:
3301 case SP::SELECT_CC_FP_XCC:
3302 case SP::SELECT_CC_DFP_XCC:
3303 case SP::SELECT_CC_QFP_XCC:
3304 return expandSelectCC(MI, BB, SP::BPXCC);
3305 case SP::SELECT_CC_Int_FCC:
3306 case SP::SELECT_CC_FP_FCC:
3307 case SP::SELECT_CC_DFP_FCC:
3308 case SP::SELECT_CC_QFP_FCC:
3309 if (Subtarget->isV9())
3310 return expandSelectCC(MI, BB, SP::FBCOND_V9);
3311 return expandSelectCC(MI, BB, SP::FBCOND);
3312 }
3313}
3314
3317 unsigned BROpcode) const {
3318 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
3319 DebugLoc dl = MI.getDebugLoc();
3320 unsigned CC = (SPCC::CondCodes)MI.getOperand(3).getImm();
3321
3322 // To "insert" a SELECT_CC instruction, we actually have to insert the
3323 // triangle control-flow pattern. The incoming instruction knows the
3324 // destination vreg to set, the condition code register to branch on, the
3325 // true/false values to select between, and the condition code for the branch.
3326 //
3327 // We produce the following control flow:
3328 // ThisMBB
3329 // | \
3330 // | IfFalseMBB
3331 // | /
3332 // SinkMBB
3333 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3335
3336 MachineBasicBlock *ThisMBB = BB;
3337 MachineFunction *F = BB->getParent();
3338 MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
3339 MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3340 F->insert(It, IfFalseMBB);
3341 F->insert(It, SinkMBB);
3342
3343 // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
3344 SinkMBB->splice(SinkMBB->begin(), ThisMBB,
3345 std::next(MachineBasicBlock::iterator(MI)), ThisMBB->end());
3346 SinkMBB->transferSuccessorsAndUpdatePHIs(ThisMBB);
3347
3348 // Set the new successors for ThisMBB.
3349 ThisMBB->addSuccessor(IfFalseMBB);
3350 ThisMBB->addSuccessor(SinkMBB);
3351
3352 BuildMI(ThisMBB, dl, TII.get(BROpcode))
3353 .addMBB(SinkMBB)
3354 .addImm(CC);
3355
3356 // IfFalseMBB just falls through to SinkMBB.
3357 IfFalseMBB->addSuccessor(SinkMBB);
3358
3359 // %Result = phi [ %TrueValue, ThisMBB ], [ %FalseValue, IfFalseMBB ]
3360 BuildMI(*SinkMBB, SinkMBB->begin(), dl, TII.get(SP::PHI),
3361 MI.getOperand(0).getReg())
3362 .addReg(MI.getOperand(1).getReg())
3363 .addMBB(ThisMBB)
3364 .addReg(MI.getOperand(2).getReg())
3365 .addMBB(IfFalseMBB);
3366
3367 MI.eraseFromParent(); // The pseudo instruction is gone now.
3368 return SinkMBB;
3369}
3370
3371//===----------------------------------------------------------------------===//
3372// Sparc Inline Assembly Support
3373//===----------------------------------------------------------------------===//
3374
3375/// getConstraintType - Given a constraint letter, return the type of
3376/// constraint it is for this target.
3379 if (Constraint.size() == 1) {
3380 switch (Constraint[0]) {
3381 default: break;
3382 case 'r':
3383 case 'f':
3384 case 'e':
3385 return C_RegisterClass;
3386 case 'I': // SIMM13
3387 return C_Immediate;
3388 }
3389 }
3390
3391 return TargetLowering::getConstraintType(Constraint);
3392}
3393
3396 const char *constraint) const {
3398 Value *CallOperandVal = info.CallOperandVal;
3399 // If we don't have a value, we can't do a match,
3400 // but allow it at the lowest weight.
3401 if (!CallOperandVal)
3402 return CW_Default;
3403
3404 // Look at the constraint type.
3405 switch (*constraint) {
3406 default:
3408 break;
3409 case 'I': // SIMM13
3410 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
3411 if (isInt<13>(C->getSExtValue()))
3412 weight = CW_Constant;
3413 }
3414 break;
3415 }
3416 return weight;
3417}
3418
3419/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3420/// vector. If it is invalid, don't add anything to Ops.
3423 std::string &Constraint,
3424 std::vector<SDValue> &Ops,
3425 SelectionDAG &DAG) const {
3426 SDValue Result;
3427
3428 // Only support length 1 constraints for now.
3429 if (Constraint.length() > 1)
3430 return;
3431
3432 char ConstraintLetter = Constraint[0];
3433 switch (ConstraintLetter) {
3434 default: break;
3435 case 'I':
3436 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3437 if (isInt<13>(C->getSExtValue())) {
3438 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
3439 Op.getValueType());
3440 break;
3441 }
3442 return;
3443 }
3444 }
3445
3446 if (Result.getNode()) {
3447 Ops.push_back(Result);
3448 return;
3449 }
3450 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3451}
3452
3453std::pair<unsigned, const TargetRegisterClass *>
3455 StringRef Constraint,
3456 MVT VT) const {
3457 if (Constraint.empty())
3458 return std::make_pair(0U, nullptr);
3459
3460 if (Constraint.size() == 1) {
3461 switch (Constraint[0]) {
3462 case 'r':
3463 if (VT == MVT::v2i32)
3464 return std::make_pair(0U, &SP::IntPairRegClass);
3465 else if (Subtarget->is64Bit())
3466 return std::make_pair(0U, &SP::I64RegsRegClass);
3467 else
3468 return std::make_pair(0U, &SP::IntRegsRegClass);
3469 case 'f':
3470 if (VT == MVT::f32 || VT == MVT::i32)
3471 return std::make_pair(0U, &SP::FPRegsRegClass);
3472 else if (VT == MVT::f64 || VT == MVT::i64)
3473 return std::make_pair(0U, &SP::LowDFPRegsRegClass);
3474 else if (VT == MVT::f128)
3475 return std::make_pair(0U, &SP::LowQFPRegsRegClass);
3476 // This will generate an error message
3477 return std::make_pair(0U, nullptr);
3478 case 'e':
3479 if (VT == MVT::f32 || VT == MVT::i32)
3480 return std::make_pair(0U, &SP::FPRegsRegClass);
3481 else if (VT == MVT::f64 || VT == MVT::i64 )
3482 return std::make_pair(0U, &SP::DFPRegsRegClass);
3483 else if (VT == MVT::f128)
3484 return std::make_pair(0U, &SP::QFPRegsRegClass);
3485 // This will generate an error message
3486 return std::make_pair(0U, nullptr);
3487 }
3488 }
3489
3490 if (Constraint.front() != '{')
3491 return std::make_pair(0U, nullptr);
3492
3493 assert(Constraint.back() == '}' && "Not a brace enclosed constraint?");
3494 StringRef RegName(Constraint.data() + 1, Constraint.size() - 2);
3495 if (RegName.empty())
3496 return std::make_pair(0U, nullptr);
3497
3498 unsigned long long RegNo;
3499 // Handle numbered register aliases.
3500 if (RegName[0] == 'r' &&
3501 getAsUnsignedInteger(RegName.begin() + 1, 10, RegNo)) {
3502 // r0-r7 -> g0-g7
3503 // r8-r15 -> o0-o7
3504 // r16-r23 -> l0-l7
3505 // r24-r31 -> i0-i7
3506 if (RegNo > 31)
3507 return std::make_pair(0U, nullptr);
3508 const char RegTypes[] = {'g', 'o', 'l', 'i'};
3509 char RegType = RegTypes[RegNo / 8];
3510 char RegIndex = '0' + (RegNo % 8);
3511 char Tmp[] = {'{', RegType, RegIndex, '}', 0};
3512 return getRegForInlineAsmConstraint(TRI, Tmp, VT);
3513 }
3514
3515 // Rewrite the fN constraint according to the value type if needed.
3516 if (VT != MVT::f32 && VT != MVT::Other && RegName[0] == 'f' &&
3517 getAsUnsignedInteger(RegName.begin() + 1, 10, RegNo)) {
3518 if (VT == MVT::f64 && (RegNo % 2 == 0)) {
3520 TRI, StringRef("{d" + utostr(RegNo / 2) + "}"), VT);
3521 } else if (VT == MVT::f128 && (RegNo % 4 == 0)) {
3523 TRI, StringRef("{q" + utostr(RegNo / 4) + "}"), VT);
3524 } else {
3525 return std::make_pair(0U, nullptr);
3526 }
3527 }
3528
3529 auto ResultPair =
3531 if (!ResultPair.second)
3532 return std::make_pair(0U, nullptr);
3533
3534 // Force the use of I64Regs over IntRegs for 64-bit values.
3535 if (Subtarget->is64Bit() && VT == MVT::i64) {
3536 assert(ResultPair.second == &SP::IntRegsRegClass &&
3537 "Unexpected register class");
3538 return std::make_pair(ResultPair.first, &SP::I64RegsRegClass);
3539 }
3540
3541 return ResultPair;
3542}
3543
3544bool
3546 // The Sparc target isn't yet aware of offsets.
3547 return false;
3548}
3549
3552 SelectionDAG &DAG) const {
3553
3554 SDLoc dl(N);
3555
3556 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3557
3558 switch (N->getOpcode()) {
3559 default:
3560 llvm_unreachable("Do not know how to custom type legalize this operation!");
3561
3562 case ISD::FP_TO_SINT:
3563 case ISD::FP_TO_UINT:
3564 // Custom lower only if it involves f128 or i64.
3565 if (N->getOperand(0).getValueType() != MVT::f128
3566 || N->getValueType(0) != MVT::i64)
3567 return;
3568 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3569 ? RTLIB::FPTOSINT_F128_I64
3570 : RTLIB::FPTOUINT_F128_I64);
3571
3572 Results.push_back(LowerF128Op(SDValue(N, 0),
3573 DAG,
3574 getLibcallName(libCall),
3575 1));
3576 return;
3577 case ISD::READCYCLECOUNTER: {
3578 assert(Subtarget->hasLeonCycleCounter());
3579 SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), dl, SP::ASR23, MVT::i32);
3580 SDValue Hi = DAG.getCopyFromReg(Lo, dl, SP::G0, MVT::i32);
3581 SDValue Ops[] = { Lo, Hi };
3582 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops);
3583 Results.push_back(Pair);
3584 Results.push_back(N->getOperand(0));
3585 return;
3586 }
3587 case ISD::SINT_TO_FP:
3588 case ISD::UINT_TO_FP:
3589 // Custom lower only if it involves f128 or i64.
3590 if (N->getValueType(0) != MVT::f128
3591 || N->getOperand(0).getValueType() != MVT::i64)
3592 return;
3593
3594 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3595 ? RTLIB::SINTTOFP_I64_F128
3596 : RTLIB::UINTTOFP_I64_F128);
3597
3598 Results.push_back(LowerF128Op(SDValue(N, 0),
3599 DAG,
3600 getLibcallName(libCall),
3601 1));
3602 return;
3603 case ISD::LOAD: {
3604 LoadSDNode *Ld = cast<LoadSDNode>(N);
3605 // Custom handling only for i64: turn i64 load into a v2i32 load,
3606 // and a bitcast.
3607 if (Ld->getValueType(0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64)
3608 return;
3609
3610 SDLoc dl(N);
3611 SDValue LoadRes = DAG.getExtLoad(
3612 Ld->getExtensionType(), dl, MVT::v2i32, Ld->getChain(),
3613 Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32,
3614 Ld->getOriginalAlign(), Ld->getMemOperand()->getFlags(),
3615 Ld->getAAInfo());
3616
3617 SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes);
3618 Results.push_back(Res);
3619 Results.push_back(LoadRes.getValue(1));
3620 return;
3621 }
3622 }
3623}
3624
3625// Override to enable LOAD_STACK_GUARD lowering on Linux.
3627 if (!Subtarget->isTargetLinux())
3629 return true;
3630}
3631
3632// Override to disable global variable loading on Linux.
3634 if (!Subtarget->isTargetLinux())
3636}
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Callee
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
Function Alias Analysis Results
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
static bool isSigned(unsigned int Opcode)
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define RegName(no)
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG)
lazy value info
#define F(x, y, z)
Definition: MD5.cpp:55
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
Module.h This file contains the declarations for the Module class.
LLVMContext & Context
return ToRemove size() > 0
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget, bool AlwaysFlush=false)
static unsigned toCallerWindow(unsigned Reg)
static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG)
static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC)
intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC rcond condition.
static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
static void fixupVariableFloatArgs(SmallVectorImpl< CCValAssign > &ArgLocs, ArrayRef< ISD::OutputArg > Outs)
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC)
FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC FCC condition.
static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG)
static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, const CallBase *Call)
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9)
static SDValue LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG, unsigned opcode)
static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG)
static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG)
static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)
static SDValue LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9)
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC)
static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
This file contains some functions that are useful when dealing with strings.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static bool is64Bit(const char *name)
Value * RHS
Value * LHS
Class for arbitrary precision integers.
Definition: APInt.h:75
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:994
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:839
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
BinOp getOperation() const
Definition: Instructions.h:812
LLVM Basic Block Representation.
Definition: BasicBlock.h:56
CCState - This class holds information needed while lowering arguments and return values.