62 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
88 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
110 assert((LocVT == MVT::f32 || LocVT == MVT::f128
112 "Can't handle non-64 bits locations");
115 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
120 if (LocVT == MVT::i64 &&
Offset < 6*8)
123 else if (LocVT == MVT::f64 &&
Offset < 16*8)
126 else if (LocVT == MVT::f32 &&
Offset < 16*8)
129 else if (LocVT == MVT::f128 &&
Offset < 16*8)
147 if (LocVT == MVT::f32)
163 if (LocVT == MVT::f32 &&
Offset < 16*8) {
170 if (LocVT == MVT::i32 &&
Offset < 6*8) {
172 unsigned Reg = SP::I0 +
Offset/8;
222#include "SparcGenCallingConv.inc"
228 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
230 if (Reg >= SP::I0 && Reg <= SP::I7)
231 return Reg - SP::I0 + SP::O0;
239 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
279 for (
unsigned i = 0, realRVLocIdx = 0;
281 ++i, ++realRVLocIdx) {
285 SDValue Arg = OutVals[realRVLocIdx];
313 unsigned RetAddrOffset = 8;
364 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
393 if (i+1 < RVLocs.
size() && RVLocs[i+1].getLocReg() == VA.
getLocReg()) {
449 for (
unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
452 if (Ins[InIdx].Flags.isSRet()) {
483 &SP::IntRegsRegClass);
501 else if (VA.
getLocVT() != MVT::i32) {
560 }
else if (VA.
getValVT() == MVT::f128) {
585 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
588 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
590 if (NumAllocated == 6)
594 ArgOffset = 68+4*NumAllocated;
600 std::vector<SDValue> OutChains;
602 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
616 if (!OutChains.empty()) {
617 OutChains.push_back(Chain);
639 const unsigned ArgArea = 128;
652 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
658 switch (VA.getLocInfo()) {
683 unsigned Offset = VA.getLocMemOffset() + ArgArea;
684 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
717 for (; ArgOffset < 6*8; ArgOffset += 8) {
727 if (!OutChains.
empty())
741 return TRI->isReservedReg(MF, r);
745 return TRI->isReservedReg(MF, r);
753 F, (
"SPARC doesn't support"
754 " function calls if any of the argument registers is reserved.")});
768 return Call->hasFnAttr(Attribute::ReturnsTwice);
772 CalleeFn = dyn_cast<Function>(
G->getGlobal());
774 dyn_cast<ExternalSymbolSDNode>(Callee)) {
777 const char *CalleeName = E->getSymbol();
778 CalleeFn = M->getFunction(CalleeName);
791 auto &Outs = CLI.
Outs;
795 if (Caller.getFnAttribute(
"disable-tail-calls").getValueAsString() ==
"true")
801 unsigned StackSizeLimit = Subtarget->
is64Bit() ? 48 : 0;
807 if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
812 for (
auto &Arg : Outs)
813 if (Arg.Flags.isByVal())
848 ArgsSize = (ArgsSize+7) & ~7;
854 for (
unsigned i = 0, e = Outs.
size(); i != e; ++i) {
856 if (!Flags.isByVal())
860 unsigned Size = Flags.getByValSize();
861 Align Alignment = Flags.getNonZeroByValAlign();
868 Chain = DAG.
getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Alignment,
881 assert(!isTailCall || ArgsSize == 0);
890 bool hasStructRetAttr =
false;
891 unsigned SRetArgSize = 0;
893 for (
unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.
size();
897 SDValue Arg = OutVals[realArgIdx];
902 if (Flags.isByVal()) {
903 Arg = ByValArgs[byvalArgIdx++];
927 if (Flags.isSRet()) {
939 hasStructRetAttr =
true;
941 assert(Outs[realArgIdx].OrigArgIndex == 0);
1036 if (!MemOpChains.
empty())
1044 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
1045 Register Reg = RegsToPass[i].first;
1048 Chain = DAG.
getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InGlue);
1069 if (hasStructRetAttr)
1071 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
1072 Register Reg = RegsToPass[i].first;
1082 ?
TRI->getRTCallPreservedMask(CallConv)
1088 assert(Mask &&
"Missing call preserved mask for calling convention");
1113 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
1114 assert(RVLocs[i].isRegLoc() &&
"Can only return in registers!");
1115 if (RVLocs[i].getLocVT() == MVT::v2i32) {
1118 Chain, dl,
toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InGlue);
1119 Chain =
Lo.getValue(1);
1120 InGlue =
Lo.getValue(2);
1124 Chain, dl,
toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InGlue);
1125 Chain =
Hi.getValue(1);
1126 InGlue =
Hi.getValue(2);
1133 RVLocs[i].getValVT(), InGlue)
1148 .
Case(
"i0", SP::I0).
Case(
"i1", SP::I1).
Case(
"i2", SP::I2).
Case(
"i3", SP::I3)
1149 .
Case(
"i4", SP::I4).
Case(
"i5", SP::I5).
Case(
"i6", SP::I6).
Case(
"i7", SP::I7)
1150 .
Case(
"o0", SP::O0).
Case(
"o1", SP::O1).
Case(
"o2", SP::O2).
Case(
"o3", SP::O3)
1151 .
Case(
"o4", SP::O4).
Case(
"o5", SP::O5).
Case(
"o6", SP::O6).
Case(
"o7", SP::O7)
1152 .
Case(
"l0", SP::L0).
Case(
"l1", SP::L1).
Case(
"l2", SP::L2).
Case(
"l3", SP::L3)
1153 .
Case(
"l4", SP::L4).
Case(
"l5", SP::L5).
Case(
"l6", SP::L6).
Case(
"l7", SP::L7)
1154 .
Case(
"g0", SP::G0).
Case(
"g1", SP::G1).
Case(
"g2", SP::G2).
Case(
"g3", SP::G3)
1155 .
Case(
"g4", SP::G4).
Case(
"g5", SP::G5).
Case(
"g6", SP::G6).
Case(
"g7", SP::G7)
1162 if (!
TRI->isReservedReg(MF, Reg))
1182 MVT ValTy = VA.getLocVT();
1185 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1188 if (Outs[VA.getValNo()].IsFixed)
1193 Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1194 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1195 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1196 assert(
Offset < 16*8 &&
"Offset out of range, bad register enum?");
1200 unsigned IReg = SP::I0 +
Offset/8;
1201 if (ValTy == MVT::f64)
1206 assert(ValTy == MVT::f128 &&
"Unexpected type!");
1215 VA.getLocVT(), VA.getLocInfo());
1243 unsigned StackReserved = 6 * 8u;
1244 unsigned ArgsSize = std::max<unsigned>(StackReserved, CCInfo.
getStackSize());
1247 ArgsSize =
alignTo(ArgsSize, 16);
1271 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
1327 RegsToPass.
push_back(std::make_pair(HiReg, Hi64));
1328 RegsToPass.
push_back(std::make_pair(LoReg, Lo64));
1340 if (i+1 < ArgLocs.
size() && ArgLocs[i+1].isRegLoc() &&
1341 ArgLocs[i+1].getLocReg() == VA.
getLocReg()) {
1353 RegsToPass.
push_back(std::make_pair(Reg, Arg));
1372 if (!MemOpChains.
empty())
1380 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
1382 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1402 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i)
1404 RegsToPass[i].second.getValueType()));
1409 ((hasReturnsTwice) ?
TRI->getRTCallPreservedMask(CLI.
CallConv)
1416 assert(Mask &&
"Missing call preserved mask for calling convention");
1447 if (CLI.
Ins.size() == 1 && CLI.
Ins[0].VT == MVT::f32 && !CLI.
CB)
1448 CLI.
Ins[0].Flags.setInReg();
1453 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
1597 if (!Subtarget->useSoftFloat()) {
1761 if (Subtarget->isV9()) {
1768 }
else if (Subtarget->hasLeonCasa())
1790 if (!Subtarget->isV9()) {
1832 if (Subtarget->useSoftMulDiv()) {
1879 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1887 if (Subtarget->hasHardQuad()) {
1895 if (Subtarget->isV9()) {
1926 if (Subtarget->
is64Bit() && !Subtarget->useSoftFloat()) {
1944 }
else if (!Subtarget->useSoftFloat()) {
1965 if (Subtarget->fixAllFDIVSQRT()) {
1972 if (Subtarget->hasNoFMULS()) {
1980 if (Subtarget->hasLeonCycleCounter())
1991 return Subtarget->useSoftFloat();
2000 return "SPISD::CMPFCC_V9";
2003 return "SPISD::BPICC";
2005 return "SPISD::BPXCC";
2008 return "SPISD::BRFCC_V9";
2010 return "SPISD::BR_REG";
2015 return "SPISD::SELECT_REG";
2048 const APInt &DemandedElts,
2050 unsigned Depth)
const {
2054 switch (
Op.getOpcode()) {
2081 SPCC =
LHS.getConstantOperandVal(2);
2093 GA->getValueType(0),
2094 GA->getOffset(), TF);
2098 CP->getAlign(), CP->getOffset(), TF);
2108 ES->getValueType(0), TF);
2116 unsigned HiTF,
unsigned LoTF,
2119 EVT VT =
Op.getValueType();
2245 assert(Mask &&
"Missing call preserved mask for calling convention");
2327 Args.push_back(Entry);
2333 const char *LibFuncName,
2334 unsigned numArgs)
const {
2347 if (
RetTy->isFP128Ty()) {
2352 Entry.Node = RetPtr;
2355 Entry.IsSRet =
true;
2356 Entry.IndirectType =
RetTy;
2358 Entry.IsReturned =
false;
2359 Args.push_back(Entry);
2364 for (
unsigned i = 0, e = numArgs; i != e; ++i) {
2374 if (RetTyABI ==
RetTy)
2377 assert (
RetTy->isFP128Ty() &&
"Unexpected return type!");
2387 unsigned &SPCC,
const SDLoc &
DL,
2390 const char *
LibCall =
nullptr;
2487 if (
Op.getOperand(0).getValueType() == MVT::f64)
2491 if (
Op.getOperand(0).getValueType() == MVT::f32)
2503 if (
Op.getOperand(0).getValueType() != MVT::f128)
2506 if (
Op.getValueType() == MVT::f64)
2509 if (
Op.getValueType() == MVT::f32)
2521 EVT VT =
Op.getValueType();
2522 assert(VT == MVT::i32 || VT == MVT::i64);
2525 if (
Op.getOperand(0).getValueType() == MVT::f128
2528 ? RTLIB::FPTOSINT_F128_I32
2529 : RTLIB::FPTOSINT_F128_I64);
2550 EVT OpVT =
Op.getOperand(0).getValueType();
2551 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2553 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2556 if (
Op.getValueType() == MVT::f128
2559 ? RTLIB::SINTTOFP_I32_F128
2560 : RTLIB::SINTTOFP_I64_F128);
2571 return DAG.
getNode(opcode, dl,
Op.getValueType(), Tmp);
2578 EVT VT =
Op.getValueType();
2582 if (
Op.getOperand(0).getValueType() != MVT::f128 ||
2586 assert(VT == MVT::i32 || VT == MVT::i64);
2590 ? RTLIB::FPTOUINT_F128_I32
2591 : RTLIB::FPTOUINT_F128_I64),
2599 EVT OpVT =
Op.getOperand(0).getValueType();
2600 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2604 if (
Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.
isTypeLegal(OpVT)))
2609 ? RTLIB::UINTTOFP_I32_F128
2610 : RTLIB::UINTTOFP_I64_F128),
2623 unsigned Opc, SPCC = ~0U;
2632 if (
LHS.getValueType().isInteger()) {
2635 if (
is64Bit && isV9 &&
LHS.getValueType() == MVT::i64 &&
2650 if (!hasHardQuad &&
LHS.getValueType() == MVT::f128) {
2661 return DAG.
getNode(Opc, dl, MVT::Other, Chain, Dest,
2662 DAG.
getConstant(SPCC, dl, MVT::i32), CompareFlag);
2674 unsigned Opc, SPCC = ~0U;
2682 if (
LHS.getValueType().isInteger()) {
2689 EVT ValType = TrueVal.getValueType();
2690 bool IsEligibleType = ValType.isScalarInteger() || ValType == MVT::f32 ||
2691 ValType == MVT::f64 ||
2692 (ValType == MVT::f128 && hasHardQuad);
2693 if (
is64Bit && isV9 &&
LHS.getValueType() == MVT::i64 &&
2700 Opc =
LHS.getValueType() == MVT::i32 ?
2704 if (!hasHardQuad &&
LHS.getValueType() == MVT::f128) {
2715 return DAG.
getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2716 DAG.
getConstant(SPCC, dl, MVT::i32), CompareFlag);
2734 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
2741 EVT VT =
Node->getValueType(0);
2745 const Value *SV = cast<SrcValueSDNode>(
Node->getOperand(2))->getValue();
2768 cast<ConstantSDNode>(
Op.getOperand(2))->getMaybeAlignValue();
2770 EVT VT =
Size->getValueType(0);
2776 if (Alignment && *Alignment > StackAlign) {
2779 "over-aligned dynamic alloca not supported.");
2784 unsigned regSpillArea;
2814 unsigned SPReg = SP::O6;
2823 SDValue Ops[2] = { NewVal, Chain };
2837 bool AlwaysFlush =
false) {
2841 EVT VT =
Op.getValueType();
2843 unsigned FrameReg = SP::I6;
2854 unsigned Offset = (Subtarget->
is64Bit()) ? (stackBias + 112) : 56;
2871 uint64_t depth =
Op.getConstantOperandVal(0);
2887 EVT VT =
Op.getValueType();
2889 uint64_t depth =
Op.getConstantOperandVal(0);
2932 Lo32 = DAG.
getNode(opcode, dl, MVT::f32, Lo32);
2934 Hi32 = DAG.
getNode(opcode, dl, MVT::f32, Hi32);
2992 if (MemVT == MVT::f128)
3041 if (MemVT == MVT::f128)
3044 if (MemVT == MVT::i64) {
3060 &&
"invalid opcode");
3064 if (
Op.getValueType() == MVT::f64)
3066 if (
Op.getValueType() != MVT::f128)
3082 Lo64 = DAG.
getNode(
Op.getOpcode(), dl, MVT::f64, Lo64);
3087 Hi64 = DAG.
getNode(
Op.getOpcode(), dl, MVT::f64, Hi64);
3113 unsigned IntNo =
Op.getConstantOperandVal(0);
3117 case Intrinsic::thread_pointer: {
3127 bool hasHardQuad = Subtarget->hasHardQuad();
3128 bool isV9 = Subtarget->isV9();
3131 switch (
Op.getOpcode()) {
3184 APInt V =
C->getValueAPF().bitcastToAPInt();
3197 if (isa<ConstantFPSDNode>(Src) &&
N->getSimpleValueType(0) == MVT::v2i32 &&
3198 Src.getSimpleValueType() == MVT::f64)
3206 switch (
N->getOpcode()) {
3218 switch (
MI.getOpcode()) {
3220 case SP::SELECT_CC_Int_ICC:
3221 case SP::SELECT_CC_FP_ICC:
3222 case SP::SELECT_CC_DFP_ICC:
3223 case SP::SELECT_CC_QFP_ICC:
3224 if (Subtarget->isV9())
3227 case SP::SELECT_CC_Int_XCC:
3228 case SP::SELECT_CC_FP_XCC:
3229 case SP::SELECT_CC_DFP_XCC:
3230 case SP::SELECT_CC_QFP_XCC:
3232 case SP::SELECT_CC_Int_FCC:
3233 case SP::SELECT_CC_FP_FCC:
3234 case SP::SELECT_CC_DFP_FCC:
3235 case SP::SELECT_CC_QFP_FCC:
3236 if (Subtarget->isV9())
3244 unsigned BROpcode)
const {
3267 F->insert(It, IfFalseMBB);
3268 F->insert(It, SinkMBB);
3288 MI.getOperand(0).getReg())
3294 MI.eraseFromParent();
3306 if (Constraint.
size() == 1) {
3307 switch (Constraint[0]) {
3323 const char *constraint)
const {
3325 Value *CallOperandVal =
info.CallOperandVal;
3328 if (!CallOperandVal)
3332 switch (*constraint) {
3338 if (isInt<13>(
C->getSExtValue()))
3354 if (Constraint.
size() > 1)
3357 char ConstraintLetter = Constraint[0];
3358 switch (ConstraintLetter) {
3362 if (isInt<13>(
C->getSExtValue())) {
3371 if (Result.getNode()) {
3372 Ops.push_back(Result);
3378std::pair<unsigned, const TargetRegisterClass *>
3382 if (Constraint.
empty())
3383 return std::make_pair(0U,
nullptr);
3385 if (Constraint.
size() == 1) {
3386 switch (Constraint[0]) {
3388 if (VT == MVT::v2i32)
3389 return std::make_pair(0U, &SP::IntPairRegClass);
3390 else if (Subtarget->
is64Bit())
3391 return std::make_pair(0U, &SP::I64RegsRegClass);
3393 return std::make_pair(0U, &SP::IntRegsRegClass);
3395 if (VT == MVT::f32 || VT == MVT::i32)
3396 return std::make_pair(0U, &SP::FPRegsRegClass);
3397 else if (VT == MVT::f64 || VT == MVT::i64)
3398 return std::make_pair(0U, &SP::LowDFPRegsRegClass);
3399 else if (VT == MVT::f128)
3400 return std::make_pair(0U, &SP::LowQFPRegsRegClass);
3402 return std::make_pair(0U,
nullptr);
3404 if (VT == MVT::f32 || VT == MVT::i32)
3405 return std::make_pair(0U, &SP::FPRegsRegClass);
3406 else if (VT == MVT::f64 || VT == MVT::i64 )
3407 return std::make_pair(0U, &SP::DFPRegsRegClass);
3408 else if (VT == MVT::f128)
3409 return std::make_pair(0U, &SP::QFPRegsRegClass);
3411 return std::make_pair(0U,
nullptr);
3415 if (Constraint.
front() !=
'{')
3416 return std::make_pair(0U,
nullptr);
3418 assert(Constraint.
back() ==
'}' &&
"Not a brace enclosed constraint?");
3421 return std::make_pair(0U,
nullptr);
3423 unsigned long long RegNo;
3432 return std::make_pair(0U,
nullptr);
3433 const char RegTypes[] = {
'g',
'o',
'l',
'i'};
3434 char RegType = RegTypes[RegNo / 8];
3435 char RegIndex =
'0' + (RegNo % 8);
3436 char Tmp[] = {
'{', RegType, RegIndex,
'}', 0};
3441 if (VT != MVT::f32 && VT != MVT::Other &&
RegName[0] ==
'f' &&
3443 if (VT == MVT::f64 && (RegNo % 2 == 0)) {
3446 }
else if (VT == MVT::f128 && (RegNo % 4 == 0)) {
3450 return std::make_pair(0U,
nullptr);
3456 if (!ResultPair.second)
3457 return std::make_pair(0U,
nullptr);
3460 if (Subtarget->
is64Bit() && VT == MVT::i64) {
3461 assert(ResultPair.second == &SP::IntRegsRegClass &&
3462 "Unexpected register class");
3463 return std::make_pair(ResultPair.first, &SP::I64RegsRegClass);
3483 switch (
N->getOpcode()) {
3485 llvm_unreachable(
"Do not know how to custom type legalize this operation!");
3490 if (
N->getOperand(0).getValueType() != MVT::f128
3491 ||
N->getValueType(0) != MVT::i64)
3494 ? RTLIB::FPTOSINT_F128_I64
3495 : RTLIB::FPTOUINT_F128_I64);
3503 assert(Subtarget->hasLeonCycleCounter());
3509 Results.push_back(
N->getOperand(0));
3515 if (
N->getValueType(0) != MVT::f128
3516 ||
N->getOperand(0).getValueType() != MVT::i64)
3520 ? RTLIB::SINTTOFP_I64_F128
3521 : RTLIB::UINTTOFP_I64_F128);
3565 assert(
MI.getOpcode() == SP::SUBCCrr ||
MI.getOpcode() == SP::SUBCCri);
3567 if (!Node->hasAnyUseOfValue(0))
3568 MI.getOperand(0).setReg(SP::G0);
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG)
unsigned const TargetRegisterInfo * TRI
Module.h This file contains the declarations for the Module class.
static CodeModel::Model getCodeModel(const PPCSubtarget &S, const TargetMachine &TM, const MachineOperand &MO)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget, bool AlwaysFlush=false)
static unsigned toCallerWindow(unsigned Reg)
static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG)
static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC)
intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC rcond condition.
static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
static void fixupVariableFloatArgs(SmallVectorImpl< CCValAssign > &ArgLocs, ArrayRef< ISD::OutputArg > Outs)
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC)
FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC FCC condition.
static bool isAnyArgRegReserved(const SparcRegisterInfo *TRI, const MachineFunction &MF)
static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG)
static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, const CallBase *Call)
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG, unsigned opcode)
static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)
static void emitReservedArgRegCallError(const MachineFunction &MF)
static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG)
static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)
static SDValue LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9)
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC)
static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static bool is64Bit(const char *name)
Class for arbitrary precision integers.
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
an instruction that atomically reads a memory location, combines it with another value,...
BinOp getOperation() const
LLVM Basic Block Representation.
CCState - This class holds information needed while lowering arguments and return values.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
void addLoc(const CCValAssign &V)
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
int64_t getLocMemOffset() const
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP)
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
This is the shared class of boolean and integer constants.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
A parsed version of the target data layout string in and methods for querying it.
bool isLittleEndian() const
Layout endianness...
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Diagnostic information for unsupported feature in backend.
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
const GlobalValue * getGlobal() const
Module * getParent()
Get the module that this global value is contained inside of...
This is an important class for using LLVM in a threaded context.
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
static auto integer_fixedlen_vector_valuetypes()
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
Flags getFlags() const
Return the raw flags of the source value,.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
Align getOriginalAlign() const
Returns alignment and volatility of the memory access.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
A Module instance is used to store all the information related to an LLVM module.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
LLVMContext * getContext() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.