LLVM 20.0.0git
SparcISelLowering.cpp
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1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the interfaces that Sparc uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcISelLowering.h"
18#include "SparcRegisterInfo.h"
19#include "SparcTargetMachine.h"
33#include "llvm/IR/Function.h"
34#include "llvm/IR/Module.h"
37using namespace llvm;
38
39
40//===----------------------------------------------------------------------===//
41// Calling Convention Implementation
42//===----------------------------------------------------------------------===//
43
44static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
45 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags, CCState &State)
47{
48 assert (ArgFlags.isSRet());
49
50 // Assign SRet argument.
51 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
52 0,
53 LocVT, LocInfo));
54 return true;
55}
56
57static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT,
58 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
59 ISD::ArgFlagsTy &ArgFlags, CCState &State)
60{
61 static const MCPhysReg RegList[] = {
62 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
63 };
64 // Try to get first reg.
65 if (Register Reg = State.AllocateReg(RegList)) {
66 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
67 } else {
68 // Assign whole thing in stack.
70 ValNo, ValVT, State.AllocateStack(8, Align(4)), LocVT, LocInfo));
71 return true;
72 }
73
74 // Try to get second reg.
75 if (Register Reg = State.AllocateReg(RegList))
76 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
77 else
79 ValNo, ValVT, State.AllocateStack(4, Align(4)), LocVT, LocInfo));
80 return true;
81}
82
83static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT,
84 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
85 ISD::ArgFlagsTy &ArgFlags, CCState &State)
86{
87 static const MCPhysReg RegList[] = {
88 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
89 };
90
91 // Try to get first reg.
92 if (Register Reg = State.AllocateReg(RegList))
93 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
94 else
95 return false;
96
97 // Try to get second reg.
98 if (Register Reg = State.AllocateReg(RegList))
99 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
100 else
101 return false;
102
103 return true;
104}
105
106// Allocate a full-sized argument for the 64-bit ABI.
107static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT,
108 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
109 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
110 assert((LocVT == MVT::f32 || LocVT == MVT::f128
111 || LocVT.getSizeInBits() == 64) &&
112 "Can't handle non-64 bits locations");
113
114 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
115 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
116 Align alignment = (LocVT == MVT::f128) ? Align(16) : Align(8);
117 unsigned Offset = State.AllocateStack(size, alignment);
118 unsigned Reg = 0;
119
120 if (LocVT == MVT::i64 && Offset < 6*8)
121 // Promote integers to %i0-%i5.
122 Reg = SP::I0 + Offset/8;
123 else if (LocVT == MVT::f64 && Offset < 16*8)
124 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
125 Reg = SP::D0 + Offset/8;
126 else if (LocVT == MVT::f32 && Offset < 16*8)
127 // Promote floats to %f1, %f3, ...
128 Reg = SP::F1 + Offset/4;
129 else if (LocVT == MVT::f128 && Offset < 16*8)
130 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
131 Reg = SP::Q0 + Offset/16;
132
133 // Promote to register when possible, otherwise use the stack slot.
134 if (Reg) {
135 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
136 return true;
137 }
138
139 // Bail out if this is a return CC and we run out of registers to place
140 // values into.
141 if (IsReturn)
142 return false;
143
144 // This argument goes on the stack in an 8-byte slot.
145 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
146 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
147 if (LocVT == MVT::f32)
148 Offset += 4;
149
150 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
151 return true;
152}
153
154// Allocate a half-sized argument for the 64-bit ABI.
155//
156// This is used when passing { float, int } structs by value in registers.
157static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT,
158 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
159 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
160 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
161 unsigned Offset = State.AllocateStack(4, Align(4));
162
163 if (LocVT == MVT::f32 && Offset < 16*8) {
164 // Promote floats to %f0-%f31.
165 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
166 LocVT, LocInfo));
167 return true;
168 }
169
170 if (LocVT == MVT::i32 && Offset < 6*8) {
171 // Promote integers to %i0-%i5, using half the register.
172 unsigned Reg = SP::I0 + Offset/8;
173 LocVT = MVT::i64;
174 LocInfo = CCValAssign::AExt;
175
176 // Set the Custom bit if this i32 goes in the high bits of a register.
177 if (Offset % 8 == 0)
178 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
179 LocVT, LocInfo));
180 else
181 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
182 return true;
183 }
184
185 // Bail out if this is a return CC and we run out of registers to place
186 // values into.
187 if (IsReturn)
188 return false;
189
190 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
191 return true;
192}
193
194static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
195 CCValAssign::LocInfo &LocInfo,
196 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
197 return Analyze_CC_Sparc64_Full(false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
198 State);
199}
200
201static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
202 CCValAssign::LocInfo &LocInfo,
203 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
204 return Analyze_CC_Sparc64_Half(false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
205 State);
206}
207
208static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
209 CCValAssign::LocInfo &LocInfo,
210 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
211 return Analyze_CC_Sparc64_Full(true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
212 State);
213}
214
215static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
216 CCValAssign::LocInfo &LocInfo,
217 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
218 return Analyze_CC_Sparc64_Half(true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
219 State);
220}
221
222#include "SparcGenCallingConv.inc"
223
224// The calling conventions in SparcCallingConv.td are described in terms of the
225// callee's register window. This function translates registers to the
226// corresponding caller window %o register.
227static unsigned toCallerWindow(unsigned Reg) {
228 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
229 "Unexpected enum");
230 if (Reg >= SP::I0 && Reg <= SP::I7)
231 return Reg - SP::I0 + SP::O0;
232 return Reg;
233}
234
236 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
237 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
239 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
240 return CCInfo.CheckReturn(Outs, Subtarget->is64Bit() ? RetCC_Sparc64
241 : RetCC_Sparc32);
242}
243
246 bool IsVarArg,
248 const SmallVectorImpl<SDValue> &OutVals,
249 const SDLoc &DL, SelectionDAG &DAG) const {
250 if (Subtarget->is64Bit())
251 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
252 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
253}
254
257 bool IsVarArg,
259 const SmallVectorImpl<SDValue> &OutVals,
260 const SDLoc &DL, SelectionDAG &DAG) const {
262
263 // CCValAssign - represent the assignment of the return value to locations.
265
266 // CCState - Info about the registers and stack slot.
267 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
268 *DAG.getContext());
269
270 // Analyze return values.
271 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
272
273 SDValue Glue;
274 SmallVector<SDValue, 4> RetOps(1, Chain);
275 // Make room for the return address offset.
276 RetOps.push_back(SDValue());
277
278 // Copy the result values into the output registers.
279 for (unsigned i = 0, realRVLocIdx = 0;
280 i != RVLocs.size();
281 ++i, ++realRVLocIdx) {
282 CCValAssign &VA = RVLocs[i];
283 assert(VA.isRegLoc() && "Can only return in registers!");
284
285 SDValue Arg = OutVals[realRVLocIdx];
286
287 if (VA.needsCustom()) {
288 assert(VA.getLocVT() == MVT::v2i32);
289 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
290 // happen by default if this wasn't a legal type)
291
292 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
293 Arg,
295 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
296 Arg,
298
299 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Glue);
300 Glue = Chain.getValue(1);
301 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
302 VA = RVLocs[++i]; // skip ahead to next loc
303 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1,
304 Glue);
305 } else
306 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Glue);
307
308 // Guarantee that all emitted copies are stuck together with flags.
309 Glue = Chain.getValue(1);
310 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
311 }
312
313 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
314 // If the function returns a struct, copy the SRetReturnReg to I0
315 if (MF.getFunction().hasStructRetAttr()) {
317 Register Reg = SFI->getSRetReturnReg();
318 if (!Reg)
319 llvm_unreachable("sret virtual register not created in the entry block");
320 auto PtrVT = getPointerTy(DAG.getDataLayout());
321 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, PtrVT);
322 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Glue);
323 Glue = Chain.getValue(1);
324 RetOps.push_back(DAG.getRegister(SP::I0, PtrVT));
325 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
326 }
327
328 RetOps[0] = Chain; // Update chain.
329 RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32);
330
331 // Add the glue if we have it.
332 if (Glue.getNode())
333 RetOps.push_back(Glue);
334
335 return DAG.getNode(SPISD::RET_GLUE, DL, MVT::Other, RetOps);
336}
337
338// Lower return values for the 64-bit ABI.
339// Return values are passed the exactly the same way as function arguments.
342 bool IsVarArg,
344 const SmallVectorImpl<SDValue> &OutVals,
345 const SDLoc &DL, SelectionDAG &DAG) const {
346 // CCValAssign - represent the assignment of the return value to locations.
348
349 // CCState - Info about the registers and stack slot.
350 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
351 *DAG.getContext());
352
353 // Analyze return values.
354 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
355
356 SDValue Glue;
357 SmallVector<SDValue, 4> RetOps(1, Chain);
358
359 // The second operand on the return instruction is the return address offset.
360 // The return address is always %i7+8 with the 64-bit ABI.
361 RetOps.push_back(DAG.getConstant(8, DL, MVT::i32));
362
363 // Copy the result values into the output registers.
364 for (unsigned i = 0; i != RVLocs.size(); ++i) {
365 CCValAssign &VA = RVLocs[i];
366 assert(VA.isRegLoc() && "Can only return in registers!");
367 SDValue OutVal = OutVals[i];
368
369 // Integer return values must be sign or zero extended by the callee.
370 switch (VA.getLocInfo()) {
371 case CCValAssign::Full: break;
373 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
374 break;
376 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
377 break;
379 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
380 break;
381 default:
382 llvm_unreachable("Unknown loc info!");
383 }
384
385 // The custom bit on an i32 return value indicates that it should be passed
386 // in the high bits of the register.
387 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
388 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
389 DAG.getConstant(32, DL, MVT::i32));
390
391 // The next value may go in the low bits of the same register.
392 // Handle both at once.
393 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
394 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
395 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
396 // Skip the next value, it's already done.
397 ++i;
398 }
399 }
400
401 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Glue);
402
403 // Guarantee that all emitted copies are stuck together with flags.
404 Glue = Chain.getValue(1);
405 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
406 }
407
408 RetOps[0] = Chain; // Update chain.
409
410 // Add the flag if we have it.
411 if (Glue.getNode())
412 RetOps.push_back(Glue);
413
414 return DAG.getNode(SPISD::RET_GLUE, DL, MVT::Other, RetOps);
415}
416
418 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
419 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
420 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
421 if (Subtarget->is64Bit())
422 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
423 DL, DAG, InVals);
424 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
425 DL, DAG, InVals);
426}
427
428/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
429/// passed in either one or two GPRs, including FP values. TODO: we should
430/// pass FP values in FP registers for fastcc functions.
432 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
433 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
434 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
436 MachineRegisterInfo &RegInfo = MF.getRegInfo();
438
439 // Assign locations to all of the incoming arguments.
441 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
442 *DAG.getContext());
443 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
444
445 const unsigned StackOffset = 92;
446 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
447
448 unsigned InIdx = 0;
449 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
450 CCValAssign &VA = ArgLocs[i];
451
452 if (Ins[InIdx].Flags.isSRet()) {
453 if (InIdx != 0)
454 report_fatal_error("sparc only supports sret on the first parameter");
455 // Get SRet from [%fp+64].
456 int FrameIdx = MF.getFrameInfo().CreateFixedObject(4, 64, true);
457 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
458 SDValue Arg =
459 DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
460 InVals.push_back(Arg);
461 continue;
462 }
463
464 if (VA.isRegLoc()) {
465 if (VA.needsCustom()) {
466 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
467
468 Register VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
469 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
470 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
471
472 assert(i+1 < e);
473 CCValAssign &NextVA = ArgLocs[++i];
474
475 SDValue LoVal;
476 if (NextVA.isMemLoc()) {
477 int FrameIdx = MF.getFrameInfo().
478 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
479 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
480 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
481 } else {
482 Register loReg = MF.addLiveIn(NextVA.getLocReg(),
483 &SP::IntRegsRegClass);
484 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
485 }
486
487 if (IsLittleEndian)
488 std::swap(LoVal, HiVal);
489
490 SDValue WholeValue =
491 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
492 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue);
493 InVals.push_back(WholeValue);
494 continue;
495 }
496 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
497 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
498 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
499 if (VA.getLocVT() == MVT::f32)
500 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
501 else if (VA.getLocVT() != MVT::i32) {
502 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
503 DAG.getValueType(VA.getLocVT()));
504 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
505 }
506 InVals.push_back(Arg);
507 continue;
508 }
509
510 assert(VA.isMemLoc());
511
512 unsigned Offset = VA.getLocMemOffset()+StackOffset;
513 auto PtrVT = getPointerTy(DAG.getDataLayout());
514
515 if (VA.needsCustom()) {
516 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
517 // If it is double-word aligned, just load.
518 if (Offset % 8 == 0) {
519 int FI = MF.getFrameInfo().CreateFixedObject(8,
520 Offset,
521 true);
522 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
523 SDValue Load =
524 DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
525 InVals.push_back(Load);
526 continue;
527 }
528
529 int FI = MF.getFrameInfo().CreateFixedObject(4,
530 Offset,
531 true);
532 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
533 SDValue HiVal =
534 DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
535 int FI2 = MF.getFrameInfo().CreateFixedObject(4,
536 Offset+4,
537 true);
538 SDValue FIPtr2 = DAG.getFrameIndex(FI2, PtrVT);
539
540 SDValue LoVal =
541 DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, MachinePointerInfo());
542
543 if (IsLittleEndian)
544 std::swap(LoVal, HiVal);
545
546 SDValue WholeValue =
547 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
548 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue);
549 InVals.push_back(WholeValue);
550 continue;
551 }
552
553 int FI = MF.getFrameInfo().CreateFixedObject(4,
554 Offset,
555 true);
556 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
557 SDValue Load ;
558 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
559 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
560 } else if (VA.getValVT() == MVT::f128) {
561 report_fatal_error("SPARCv8 does not handle f128 in calls; "
562 "pass indirectly");
563 } else {
564 // We shouldn't see any other value types here.
565 llvm_unreachable("Unexpected ValVT encountered in frame lowering.");
566 }
567 InVals.push_back(Load);
568 }
569
570 if (MF.getFunction().hasStructRetAttr()) {
571 // Copy the SRet Argument to SRetReturnReg.
573 Register Reg = SFI->getSRetReturnReg();
574 if (!Reg) {
575 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
576 SFI->setSRetReturnReg(Reg);
577 }
578 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
579 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
580 }
581
582 // Store remaining ArgRegs to the stack if this is a varargs function.
583 if (isVarArg) {
584 static const MCPhysReg ArgRegs[] = {
585 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
586 };
587 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
588 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
589 unsigned ArgOffset = CCInfo.getStackSize();
590 if (NumAllocated == 6)
591 ArgOffset += StackOffset;
592 else {
593 assert(!ArgOffset);
594 ArgOffset = 68+4*NumAllocated;
595 }
596
597 // Remember the vararg offset for the va_start implementation.
598 FuncInfo->setVarArgsFrameOffset(ArgOffset);
599
600 std::vector<SDValue> OutChains;
601
602 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
603 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
604 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
605 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
606
607 int FrameIdx = MF.getFrameInfo().CreateFixedObject(4, ArgOffset,
608 true);
609 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
610
611 OutChains.push_back(
612 DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, MachinePointerInfo()));
613 ArgOffset += 4;
614 }
615
616 if (!OutChains.empty()) {
617 OutChains.push_back(Chain);
618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
619 }
620 }
621
622 return Chain;
623}
624
625// Lower formal arguments for the 64 bit ABI.
627 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
628 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
629 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
631
632 // Analyze arguments according to CC_Sparc64.
634 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
635 *DAG.getContext());
636 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
637
638 // The argument array begins at %fp+BIAS+128, after the register save area.
639 const unsigned ArgArea = 128;
640
641 for (const CCValAssign &VA : ArgLocs) {
642 if (VA.isRegLoc()) {
643 // This argument is passed in a register.
644 // All integer register arguments are promoted by the caller to i64.
645
646 // Create a virtual register for the promoted live-in value.
647 Register VReg = MF.addLiveIn(VA.getLocReg(),
648 getRegClassFor(VA.getLocVT()));
649 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
650
651 // Get the high bits for i32 struct elements.
652 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
653 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
654 DAG.getConstant(32, DL, MVT::i32));
655
656 // The caller promoted the argument, so insert an Assert?ext SDNode so we
657 // won't promote the value again in this function.
658 switch (VA.getLocInfo()) {
660 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
661 DAG.getValueType(VA.getValVT()));
662 break;
664 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
665 DAG.getValueType(VA.getValVT()));
666 break;
667 default:
668 break;
669 }
670
671 // Truncate the register down to the argument type.
672 if (VA.isExtInLoc())
673 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
674
675 InVals.push_back(Arg);
676 continue;
677 }
678
679 // The registers are exhausted. This argument was passed on the stack.
680 assert(VA.isMemLoc());
681 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
682 // beginning of the arguments area at %fp+BIAS+128.
683 unsigned Offset = VA.getLocMemOffset() + ArgArea;
684 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
685 // Adjust offset for extended arguments, SPARC is big-endian.
686 // The caller will have written the full slot with extended bytes, but we
687 // prefer our own extending loads.
688 if (VA.isExtInLoc())
689 Offset += 8 - ValSize;
690 int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true);
691 InVals.push_back(
692 DAG.getLoad(VA.getValVT(), DL, Chain,
695 }
696
697 if (!IsVarArg)
698 return Chain;
699
700 // This function takes variable arguments, some of which may have been passed
701 // in registers %i0-%i5. Variable floating point arguments are never passed
702 // in floating point registers. They go on %i0-%i5 or on the stack like
703 // integer arguments.
704 //
705 // The va_start intrinsic needs to know the offset to the first variable
706 // argument.
707 unsigned ArgOffset = CCInfo.getStackSize();
709 // Skip the 128 bytes of register save area.
710 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
711 Subtarget->getStackPointerBias());
712
713 // Save the variable arguments that were passed in registers.
714 // The caller is required to reserve stack space for 6 arguments regardless
715 // of how many arguments were actually passed.
716 SmallVector<SDValue, 8> OutChains;
717 for (; ArgOffset < 6*8; ArgOffset += 8) {
718 Register VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
719 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
720 int FI = MF.getFrameInfo().CreateFixedObject(8, ArgOffset + ArgArea, true);
721 auto PtrVT = getPointerTy(MF.getDataLayout());
722 OutChains.push_back(
723 DAG.getStore(Chain, DL, VArg, DAG.getFrameIndex(FI, PtrVT),
725 }
726
727 if (!OutChains.empty())
728 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
729
730 return Chain;
731}
732
733// Check whether any of the argument registers are reserved
735 const MachineFunction &MF) {
736 // The register window design means that outgoing parameters at O*
737 // will appear in the callee as I*.
738 // Be conservative and check both sides of the register names.
739 bool Outgoing =
740 llvm::any_of(SP::GPROutgoingArgRegClass, [TRI, &MF](MCPhysReg r) {
741 return TRI->isReservedReg(MF, r);
742 });
743 bool Incoming =
744 llvm::any_of(SP::GPRIncomingArgRegClass, [TRI, &MF](MCPhysReg r) {
745 return TRI->isReservedReg(MF, r);
746 });
747 return Outgoing || Incoming;
748}
749
751 const Function &F = MF.getFunction();
752 F.getContext().diagnose(DiagnosticInfoUnsupported{
753 F, ("SPARC doesn't support"
754 " function calls if any of the argument registers is reserved.")});
755}
756
759 SmallVectorImpl<SDValue> &InVals) const {
760 if (Subtarget->is64Bit())
761 return LowerCall_64(CLI, InVals);
762 return LowerCall_32(CLI, InVals);
763}
764
765static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
766 const CallBase *Call) {
767 if (Call)
768 return Call->hasFnAttr(Attribute::ReturnsTwice);
769
770 const Function *CalleeFn = nullptr;
771 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
772 CalleeFn = dyn_cast<Function>(G->getGlobal());
773 } else if (ExternalSymbolSDNode *E =
774 dyn_cast<ExternalSymbolSDNode>(Callee)) {
775 const Function &Fn = DAG.getMachineFunction().getFunction();
776 const Module *M = Fn.getParent();
777 const char *CalleeName = E->getSymbol();
778 CalleeFn = M->getFunction(CalleeName);
779 }
780
781 if (!CalleeFn)
782 return false;
783 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
784}
785
786/// IsEligibleForTailCallOptimization - Check whether the call is eligible
787/// for tail call optimization.
789 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const {
790
791 auto &Outs = CLI.Outs;
792 auto &Caller = MF.getFunction();
793
794 // Do not tail call opt functions with "disable-tail-calls" attribute.
795 if (Caller.getFnAttribute("disable-tail-calls").getValueAsString() == "true")
796 return false;
797
798 // Do not tail call opt if the stack is used to pass parameters.
799 // 64-bit targets have a slightly higher limit since the ABI requires
800 // to allocate some space even when all the parameters fit inside registers.
801 unsigned StackSizeLimit = Subtarget->is64Bit() ? 48 : 0;
802 if (CCInfo.getStackSize() > StackSizeLimit)
803 return false;
804
805 // Do not tail call opt if either the callee or caller returns
806 // a struct and the other does not.
807 if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
808 return false;
809
810 // Byval parameters hand the function a pointer directly into the stack area
811 // we want to reuse during a tail call.
812 for (auto &Arg : Outs)
813 if (Arg.Flags.isByVal())
814 return false;
815
816 return true;
817}
818
819// Lower a call for the 32-bit ABI.
822 SmallVectorImpl<SDValue> &InVals) const {
823 SelectionDAG &DAG = CLI.DAG;
824 SDLoc &dl = CLI.DL;
826 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
828 SDValue Chain = CLI.Chain;
829 SDValue Callee = CLI.Callee;
830 bool &isTailCall = CLI.IsTailCall;
831 CallingConv::ID CallConv = CLI.CallConv;
832 bool isVarArg = CLI.IsVarArg;
834
835 // Analyze operands of the call, assigning locations to each operand.
837 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
838 *DAG.getContext());
839 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
840
841 isTailCall = isTailCall && IsEligibleForTailCallOptimization(
842 CCInfo, CLI, DAG.getMachineFunction());
843
844 // Get the size of the outgoing arguments stack space requirement.
845 unsigned ArgsSize = CCInfo.getStackSize();
846
847 // Keep stack frames 8-byte aligned.
848 ArgsSize = (ArgsSize+7) & ~7;
849
851
852 // Create local copies for byval args.
853 SmallVector<SDValue, 8> ByValArgs;
854 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
855 ISD::ArgFlagsTy Flags = Outs[i].Flags;
856 if (!Flags.isByVal())
857 continue;
858
859 SDValue Arg = OutVals[i];
860 unsigned Size = Flags.getByValSize();
861 Align Alignment = Flags.getNonZeroByValAlign();
862
863 if (Size > 0U) {
864 int FI = MFI.CreateStackObject(Size, Alignment, false);
865 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
866 SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32);
867
868 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Alignment,
869 false, // isVolatile,
870 (Size <= 32), // AlwaysInline if size <= 32,
871 /*CI=*/nullptr, std::nullopt, MachinePointerInfo(),
873 ByValArgs.push_back(FIPtr);
874 }
875 else {
876 SDValue nullVal;
877 ByValArgs.push_back(nullVal);
878 }
879 }
880
881 assert(!isTailCall || ArgsSize == 0);
882
883 if (!isTailCall)
884 Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, dl);
885
887 SmallVector<SDValue, 8> MemOpChains;
888
889 const unsigned StackOffset = 92;
890 bool hasStructRetAttr = false;
891 unsigned SRetArgSize = 0;
892 // Walk the register/memloc assignments, inserting copies/loads.
893 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
894 i != e;
895 ++i, ++realArgIdx) {
896 CCValAssign &VA = ArgLocs[i];
897 SDValue Arg = OutVals[realArgIdx];
898
899 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
900
901 // Use local copy if it is a byval arg.
902 if (Flags.isByVal()) {
903 Arg = ByValArgs[byvalArgIdx++];
904 if (!Arg) {
905 continue;
906 }
907 }
908
909 // Promote the value if needed.
910 switch (VA.getLocInfo()) {
911 default: llvm_unreachable("Unknown loc info!");
912 case CCValAssign::Full: break;
914 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
915 break;
917 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
918 break;
920 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
921 break;
923 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
924 break;
925 }
926
927 if (Flags.isSRet()) {
928 assert(VA.needsCustom());
929
930 if (isTailCall)
931 continue;
932
933 // store SRet argument in %sp+64
934 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
935 SDValue PtrOff = DAG.getIntPtrConstant(64, dl);
936 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
937 MemOpChains.push_back(
938 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
939 hasStructRetAttr = true;
940 // sret only allowed on first argument
941 assert(Outs[realArgIdx].OrigArgIndex == 0);
942 SRetArgSize =
943 DAG.getDataLayout().getTypeAllocSize(CLI.getArgs()[0].IndirectType);
944 continue;
945 }
946
947 if (VA.needsCustom()) {
948 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
949
950 if (VA.isMemLoc()) {
951 unsigned Offset = VA.getLocMemOffset() + StackOffset;
952 // if it is double-word aligned, just store.
953 if (Offset % 8 == 0) {
954 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
955 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
956 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
957 MemOpChains.push_back(
958 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
959 continue;
960 }
961 }
962
963 if (VA.getLocVT() == MVT::f64) {
964 // Move from the float value from float registers into the
965 // integer registers.
966 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Arg))
967 Arg = bitcastConstantFPToInt(C, dl, DAG);
968 else
969 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg);
970 }
971
972 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
973 Arg,
974 DAG.getConstant(0, dl, getVectorIdxTy(DAG.getDataLayout())));
975 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
976 Arg,
977 DAG.getConstant(1, dl, getVectorIdxTy(DAG.getDataLayout())));
978
979 if (VA.isRegLoc()) {
980 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Part0));
981 assert(i+1 != e);
982 CCValAssign &NextVA = ArgLocs[++i];
983 if (NextVA.isRegLoc()) {
984 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Part1));
985 } else {
986 // Store the second part in stack.
987 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
988 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
989 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
990 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
991 MemOpChains.push_back(
992 DAG.getStore(Chain, dl, Part1, PtrOff, MachinePointerInfo()));
993 }
994 } else {
995 unsigned Offset = VA.getLocMemOffset() + StackOffset;
996 // Store the first part.
997 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
998 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
999 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
1000 MemOpChains.push_back(
1001 DAG.getStore(Chain, dl, Part0, PtrOff, MachinePointerInfo()));
1002 // Store the second part.
1003 PtrOff = DAG.getIntPtrConstant(Offset + 4, dl);
1004 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
1005 MemOpChains.push_back(
1006 DAG.getStore(Chain, dl, Part1, PtrOff, MachinePointerInfo()));
1007 }
1008 continue;
1009 }
1010
1011 // Arguments that can be passed on register must be kept at
1012 // RegsToPass vector
1013 if (VA.isRegLoc()) {
1014 if (VA.getLocVT() != MVT::f32) {
1015 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1016 continue;
1017 }
1018 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
1019 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1020 continue;
1021 }
1022
1023 assert(VA.isMemLoc());
1024
1025 // Create a store off the stack pointer for this argument.
1026 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
1028 dl);
1029 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
1030 MemOpChains.push_back(
1031 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
1032 }
1033
1034
1035 // Emit all stores, make sure the occur before any copies into physregs.
1036 if (!MemOpChains.empty())
1037 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1038
1039 // Build a sequence of copy-to-reg nodes chained together with token
1040 // chain and flag operands which copy the outgoing args into registers.
1041 // The InGlue in necessary since all emitted instructions must be
1042 // stuck together.
1043 SDValue InGlue;
1044 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1045 Register Reg = RegsToPass[i].first;
1046 if (!isTailCall)
1047 Reg = toCallerWindow(Reg);
1048 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InGlue);
1049 InGlue = Chain.getValue(1);
1050 }
1051
1052 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CB);
1053
1054 // If the callee is a GlobalAddress node (quite common, every direct call is)
1055 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1056 // Likewise ExternalSymbol -> TargetExternalSymbol.
1059 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1060 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
1061 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1062 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
1063
1064 // Returns a chain & a flag for retval copy to use
1065 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1067 Ops.push_back(Chain);
1068 Ops.push_back(Callee);
1069 if (hasStructRetAttr)
1070 Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));
1071 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1072 Register Reg = RegsToPass[i].first;
1073 if (!isTailCall)
1074 Reg = toCallerWindow(Reg);
1075 Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType()));
1076 }
1077
1078 // Add a register mask operand representing the call-preserved registers.
1079 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1080 const uint32_t *Mask =
1081 ((hasReturnsTwice)
1082 ? TRI->getRTCallPreservedMask(CallConv)
1083 : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));
1084
1085 if (isAnyArgRegReserved(TRI, MF))
1087
1088 assert(Mask && "Missing call preserved mask for calling convention");
1089 Ops.push_back(DAG.getRegisterMask(Mask));
1090
1091 if (InGlue.getNode())
1092 Ops.push_back(InGlue);
1093
1094 if (isTailCall) {
1096 return DAG.getNode(SPISD::TAIL_CALL, dl, MVT::Other, Ops);
1097 }
1098
1099 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
1100 InGlue = Chain.getValue(1);
1101
1102 Chain = DAG.getCALLSEQ_END(Chain, ArgsSize, 0, InGlue, dl);
1103 InGlue = Chain.getValue(1);
1104
1105 // Assign locations to each value returned by this call.
1107 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1108 *DAG.getContext());
1109
1110 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
1111
1112 // Copy all of the result registers out of their specified physreg.
1113 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1114 assert(RVLocs[i].isRegLoc() && "Can only return in registers!");
1115 if (RVLocs[i].getLocVT() == MVT::v2i32) {
1116 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32);
1118 Chain, dl, toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InGlue);
1119 Chain = Lo.getValue(1);
1120 InGlue = Lo.getValue(2);
1121 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo,
1122 DAG.getConstant(0, dl, MVT::i32));
1124 Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InGlue);
1125 Chain = Hi.getValue(1);
1126 InGlue = Hi.getValue(2);
1127 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,
1128 DAG.getConstant(1, dl, MVT::i32));
1129 InVals.push_back(Vec);
1130 } else {
1131 Chain =
1132 DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
1133 RVLocs[i].getValVT(), InGlue)
1134 .getValue(1);
1135 InGlue = Chain.getValue(2);
1136 InVals.push_back(Chain.getValue(0));
1137 }
1138 }
1139
1140 return Chain;
1141}
1142
1143// FIXME? Maybe this could be a TableGen attribute on some registers and
1144// this table could be generated automatically from RegInfo.
1146 const MachineFunction &MF) const {
1148 .Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3)
1149 .Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7)
1150 .Case("o0", SP::O0).Case("o1", SP::O1).Case("o2", SP::O2).Case("o3", SP::O3)
1151 .Case("o4", SP::O4).Case("o5", SP::O5).Case("o6", SP::O6).Case("o7", SP::O7)
1152 .Case("l0", SP::L0).Case("l1", SP::L1).Case("l2", SP::L2).Case("l3", SP::L3)
1153 .Case("l4", SP::L4).Case("l5", SP::L5).Case("l6", SP::L6).Case("l7", SP::L7)
1154 .Case("g0", SP::G0).Case("g1", SP::G1).Case("g2", SP::G2).Case("g3", SP::G3)
1155 .Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7", SP::G7)
1156 .Default(0);
1157
1158 // If we're directly referencing register names
1159 // (e.g in GCC C extension `register int r asm("g1");`),
1160 // make sure that said register is in the reserve list.
1161 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1162 if (!TRI->isReservedReg(MF, Reg))
1163 Reg = 0;
1164
1165 if (Reg)
1166 return Reg;
1167
1168 report_fatal_error("Invalid register name global variable");
1169}
1170
1171// Fixup floating point arguments in the ... part of a varargs call.
1172//
1173// The SPARC v9 ABI requires that floating point arguments are treated the same
1174// as integers when calling a varargs function. This does not apply to the
1175// fixed arguments that are part of the function's prototype.
1176//
1177// This function post-processes a CCValAssign array created by
1178// AnalyzeCallOperands().
1181 for (CCValAssign &VA : ArgLocs) {
1182 MVT ValTy = VA.getLocVT();
1183 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1184 // varargs functions.
1185 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1186 continue;
1187 // The fixed arguments to a varargs function still go in FP registers.
1188 if (Outs[VA.getValNo()].IsFixed)
1189 continue;
1190
1191 // This floating point argument should be reassigned.
1192 // Determine the offset into the argument array.
1193 Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1194 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1195 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1196 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1197
1198 if (Offset < 6*8) {
1199 // This argument should go in %i0-%i5.
1200 unsigned IReg = SP::I0 + Offset/8;
1201 if (ValTy == MVT::f64)
1202 // Full register, just bitconvert into i64.
1203 VA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), IReg, MVT::i64,
1205 else {
1206 assert(ValTy == MVT::f128 && "Unexpected type!");
1207 // Full register, just bitconvert into i128 -- We will lower this into
1208 // two i64s in LowerCall_64.
1209 VA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(), IReg,
1210 MVT::i128, CCValAssign::BCvt);
1211 }
1212 } else {
1213 // This needs to go to memory, we're out of integer registers.
1214 VA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(), Offset,
1215 VA.getLocVT(), VA.getLocInfo());
1216 }
1217 }
1218}
1219
1220// Lower a call for the 64-bit ABI.
1221SDValue
1223 SmallVectorImpl<SDValue> &InVals) const {
1224 SelectionDAG &DAG = CLI.DAG;
1225 SDLoc DL = CLI.DL;
1226 SDValue Chain = CLI.Chain;
1227 auto PtrVT = getPointerTy(DAG.getDataLayout());
1229
1230 // Analyze operands of the call, assigning locations to each operand.
1232 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1233 *DAG.getContext());
1234 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1235
1237 CCInfo, CLI, DAG.getMachineFunction());
1238
1239 // Get the size of the outgoing arguments stack space requirement.
1240 // The stack offset computed by CC_Sparc64 includes all arguments.
1241 // Called functions expect 6 argument words to exist in the stack frame, used
1242 // or not.
1243 unsigned StackReserved = 6 * 8u;
1244 unsigned ArgsSize = std::max<unsigned>(StackReserved, CCInfo.getStackSize());
1245
1246 // Keep stack frames 16-byte aligned.
1247 ArgsSize = alignTo(ArgsSize, 16);
1248
1249 // Varargs calls require special treatment.
1250 if (CLI.IsVarArg)
1251 fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1252
1253 assert(!CLI.IsTailCall || ArgsSize == StackReserved);
1254
1255 // Adjust the stack pointer to make room for the arguments.
1256 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1257 // with more than 6 arguments.
1258 if (!CLI.IsTailCall)
1259 Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, DL);
1260
1261 // Collect the set of registers to pass to the function and their values.
1262 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1263 // instruction.
1265
1266 // Collect chains from all the memory opeations that copy arguments to the
1267 // stack. They must follow the stack pointer adjustment above and precede the
1268 // call instruction itself.
1269 SmallVector<SDValue, 8> MemOpChains;
1270
1271 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1272 const CCValAssign &VA = ArgLocs[i];
1273 SDValue Arg = CLI.OutVals[i];
1274
1275 // Promote the value if needed.
1276 switch (VA.getLocInfo()) {
1277 default:
1278 llvm_unreachable("Unknown location info!");
1279 case CCValAssign::Full:
1280 break;
1281 case CCValAssign::SExt:
1282 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1283 break;
1284 case CCValAssign::ZExt:
1285 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1286 break;
1287 case CCValAssign::AExt:
1288 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1289 break;
1290 case CCValAssign::BCvt:
1291 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1292 // SPARC does not support i128 natively. Lower it into two i64, see below.
1293 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1294 || VA.getLocVT() != MVT::i128)
1295 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1296 break;
1297 }
1298
1299 if (VA.isRegLoc()) {
1300 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1301 && VA.getLocVT() == MVT::i128) {
1302 // Store and reload into the integer register reg and reg+1.
1303 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1304 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1305 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1306 SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset, DL);
1307 HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff);
1308 SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8, DL);
1309 LoPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, LoPtrOff);
1310
1311 // Store to %sp+BIAS+128+Offset
1312 SDValue Store =
1313 DAG.getStore(Chain, DL, Arg, HiPtrOff, MachinePointerInfo());
1314 // Load into Reg and Reg+1
1315 SDValue Hi64 =
1316 DAG.getLoad(MVT::i64, DL, Store, HiPtrOff, MachinePointerInfo());
1317 SDValue Lo64 =
1318 DAG.getLoad(MVT::i64, DL, Store, LoPtrOff, MachinePointerInfo());
1319
1320 Register HiReg = VA.getLocReg();
1321 Register LoReg = VA.getLocReg() + 1;
1322 if (!CLI.IsTailCall) {
1323 HiReg = toCallerWindow(HiReg);
1324 LoReg = toCallerWindow(LoReg);
1325 }
1326
1327 RegsToPass.push_back(std::make_pair(HiReg, Hi64));
1328 RegsToPass.push_back(std::make_pair(LoReg, Lo64));
1329 continue;
1330 }
1331
1332 // The custom bit on an i32 return value indicates that it should be
1333 // passed in the high bits of the register.
1334 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1335 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1336 DAG.getConstant(32, DL, MVT::i32));
1337
1338 // The next value may go in the low bits of the same register.
1339 // Handle both at once.
1340 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1341 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1342 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1343 CLI.OutVals[i+1]);
1344 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1345 // Skip the next value, it's already done.
1346 ++i;
1347 }
1348 }
1349
1350 Register Reg = VA.getLocReg();
1351 if (!CLI.IsTailCall)
1352 Reg = toCallerWindow(Reg);
1353 RegsToPass.push_back(std::make_pair(Reg, Arg));
1354 continue;
1355 }
1356
1357 assert(VA.isMemLoc());
1358
1359 // Create a store off the stack pointer for this argument.
1360 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1361 // The argument area starts at %fp+BIAS+128 in the callee frame,
1362 // %sp+BIAS+128 in ours.
1363 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1364 Subtarget->getStackPointerBias() +
1365 128, DL);
1366 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
1367 MemOpChains.push_back(
1368 DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
1369 }
1370
1371 // Emit all stores, make sure they occur before the call.
1372 if (!MemOpChains.empty())
1373 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1374
1375 // Build a sequence of CopyToReg nodes glued together with token chain and
1376 // glue operands which copy the outgoing args into registers. The InGlue is
1377 // necessary since all emitted instructions must be stuck together in order
1378 // to pass the live physical registers.
1379 SDValue InGlue;
1380 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1381 Chain = DAG.getCopyToReg(Chain, DL,
1382 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1383 InGlue = Chain.getValue(1);
1384 }
1385
1386 // If the callee is a GlobalAddress node (quite common, every direct call is)
1387 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1388 // Likewise ExternalSymbol -> TargetExternalSymbol.
1389 SDValue Callee = CLI.Callee;
1390 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CB);
1393 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1394 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, TF);
1395 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1396 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, TF);
1397
1398 // Build the operands for the call instruction itself.
1400 Ops.push_back(Chain);
1401 Ops.push_back(Callee);
1402 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1403 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1404 RegsToPass[i].second.getValueType()));
1405
1406 // Add a register mask operand representing the call-preserved registers.
1407 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1408 const uint32_t *Mask =
1409 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv)
1410 : TRI->getCallPreservedMask(DAG.getMachineFunction(),
1411 CLI.CallConv));
1412
1413 if (isAnyArgRegReserved(TRI, MF))
1415
1416 assert(Mask && "Missing call preserved mask for calling convention");
1417 Ops.push_back(DAG.getRegisterMask(Mask));
1418
1419 // Make sure the CopyToReg nodes are glued to the call instruction which
1420 // consumes the registers.
1421 if (InGlue.getNode())
1422 Ops.push_back(InGlue);
1423
1424 // Now the call itself.
1425 if (CLI.IsTailCall) {
1427 return DAG.getNode(SPISD::TAIL_CALL, DL, MVT::Other, Ops);
1428 }
1429 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1430 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
1431 InGlue = Chain.getValue(1);
1432
1433 // Revert the stack pointer immediately after the call.
1434 Chain = DAG.getCALLSEQ_END(Chain, ArgsSize, 0, InGlue, DL);
1435 InGlue = Chain.getValue(1);
1436
1437 // Now extract the return values. This is more or less the same as
1438 // LowerFormalArguments_64.
1439
1440 // Assign locations to each value returned by this call.
1442 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1443 *DAG.getContext());
1444
1445 // Set inreg flag manually for codegen generated library calls that
1446 // return float.
1447 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB)
1448 CLI.Ins[0].Flags.setInReg();
1449
1450 RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
1451
1452 // Copy all of the result registers out of their specified physreg.
1453 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1454 CCValAssign &VA = RVLocs[i];
1455 assert(VA.isRegLoc() && "Can only return in registers!");
1456 unsigned Reg = toCallerWindow(VA.getLocReg());
1457
1458 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1459 // reside in the same register in the high and low bits. Reuse the
1460 // CopyFromReg previous node to avoid duplicate copies.
1461 SDValue RV;
1462 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1463 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1464 RV = Chain.getValue(0);
1465
1466 // But usually we'll create a new CopyFromReg for a different register.
1467 if (!RV.getNode()) {
1468 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1469 Chain = RV.getValue(1);
1470 InGlue = Chain.getValue(2);
1471 }
1472
1473 // Get the high bits for i32 struct elements.
1474 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1475 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1476 DAG.getConstant(32, DL, MVT::i32));
1477
1478 // The callee promoted the return value, so insert an Assert?ext SDNode so
1479 // we won't promote the value again in this function.
1480 switch (VA.getLocInfo()) {
1481 case CCValAssign::SExt:
1482 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1483 DAG.getValueType(VA.getValVT()));
1484 break;
1485 case CCValAssign::ZExt:
1486 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1487 DAG.getValueType(VA.getValVT()));
1488 break;
1489 default:
1490 break;
1491 }
1492
1493 // Truncate the register down to the return value type.
1494 if (VA.isExtInLoc())
1495 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1496
1497 InVals.push_back(RV);
1498 }
1499
1500 return Chain;
1501}
1502
1503//===----------------------------------------------------------------------===//
1504// TargetLowering Implementation
1505//===----------------------------------------------------------------------===//
1506
1508 if (AI->getOperation() == AtomicRMWInst::Xchg &&
1509 AI->getType()->getPrimitiveSizeInBits() == 32)
1510 return AtomicExpansionKind::None; // Uses xchg instruction
1511
1513}
1514
1515/// intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC
1516/// rcond condition.
1518 switch (CC) {
1519 default:
1520 llvm_unreachable("Unknown/unsigned integer condition code!");
1521 case ISD::SETEQ:
1522 return SPCC::REG_Z;
1523 case ISD::SETNE:
1524 return SPCC::REG_NZ;
1525 case ISD::SETLT:
1526 return SPCC::REG_LZ;
1527 case ISD::SETGT:
1528 return SPCC::REG_GZ;
1529 case ISD::SETLE:
1530 return SPCC::REG_LEZ;
1531 case ISD::SETGE:
1532 return SPCC::REG_GEZ;
1533 }
1534}
1535
1536/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1537/// condition.
1539 switch (CC) {
1540 default: llvm_unreachable("Unknown integer condition code!");
1541 case ISD::SETEQ: return SPCC::ICC_E;
1542 case ISD::SETNE: return SPCC::ICC_NE;
1543 case ISD::SETLT: return SPCC::ICC_L;
1544 case ISD::SETGT: return SPCC::ICC_G;
1545 case ISD::SETLE: return SPCC::ICC_LE;
1546 case ISD::SETGE: return SPCC::ICC_GE;
1547 case ISD::SETULT: return SPCC::ICC_CS;
1548 case ISD::SETULE: return SPCC::ICC_LEU;
1549 case ISD::SETUGT: return SPCC::ICC_GU;
1550 case ISD::SETUGE: return SPCC::ICC_CC;
1551 }
1552}
1553
1554/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1555/// FCC condition.
1557 switch (CC) {
1558 default: llvm_unreachable("Unknown fp condition code!");
1559 case ISD::SETEQ:
1560 case ISD::SETOEQ: return SPCC::FCC_E;
1561 case ISD::SETNE:
1562 case ISD::SETUNE: return SPCC::FCC_NE;
1563 case ISD::SETLT:
1564 case ISD::SETOLT: return SPCC::FCC_L;
1565 case ISD::SETGT:
1566 case ISD::SETOGT: return SPCC::FCC_G;
1567 case ISD::SETLE:
1568 case ISD::SETOLE: return SPCC::FCC_LE;
1569 case ISD::SETGE:
1570 case ISD::SETOGE: return SPCC::FCC_GE;
1571 case ISD::SETULT: return SPCC::FCC_UL;
1572 case ISD::SETULE: return SPCC::FCC_ULE;
1573 case ISD::SETUGT: return SPCC::FCC_UG;
1574 case ISD::SETUGE: return SPCC::FCC_UGE;
1575 case ISD::SETUO: return SPCC::FCC_U;
1576 case ISD::SETO: return SPCC::FCC_O;
1577 case ISD::SETONE: return SPCC::FCC_LG;
1578 case ISD::SETUEQ: return SPCC::FCC_UE;
1579 }
1580}
1581
1583 const SparcSubtarget &STI)
1584 : TargetLowering(TM), Subtarget(&STI) {
1585 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
1586
1587 // Instructions which use registers as conditionals examine all the
1588 // bits (as does the pseudo SELECT_CC expansion). I don't think it
1589 // matters much whether it's ZeroOrOneBooleanContent, or
1590 // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
1591 // former.
1594
1595 // Set up the register classes.
1596 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1597 if (!Subtarget->useSoftFloat()) {
1598 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1599 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1600 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1601 }
1602 if (Subtarget->is64Bit()) {
1603 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1604 } else {
1605 // On 32bit sparc, we define a double-register 32bit register
1606 // class, as well. This is modeled in LLVM as a 2-vector of i32.
1607 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass);
1608
1609 // ...but almost all operations must be expanded, so set that as
1610 // the default.
1611 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
1612 setOperationAction(Op, MVT::v2i32, Expand);
1613 }
1614 // Truncating/extending stores/loads are also not supported.
1616 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand);
1617 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand);
1618 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand);
1619
1620 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand);
1621 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand);
1622 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand);
1623
1624 setTruncStoreAction(VT, MVT::v2i32, Expand);
1625 setTruncStoreAction(MVT::v2i32, VT, Expand);
1626 }
1627 // However, load and store *are* legal.
1628 setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
1629 setOperationAction(ISD::STORE, MVT::v2i32, Legal);
1632
1633 // And we need to promote i64 loads/stores into vector load/store
1636
1637 // Sadly, this doesn't work:
1638 // AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
1639 // AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
1640 }
1641
1642 // Turn FP extload into load/fpextend
1643 for (MVT VT : MVT::fp_valuetypes()) {
1644 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1645 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1646 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
1647 }
1648
1649 // Sparc doesn't have i1 sign extending load
1650 for (MVT VT : MVT::integer_valuetypes())
1651 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1652
1653 // Turn FP truncstore into trunc + store.
1654 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1655 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1656 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1657 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
1658 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1659 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1660
1661 // Custom legalize GlobalAddress nodes into LO/HI parts.
1666
1667 // Sparc doesn't have sext_inreg, replace them with shl/sra
1671
1672 // Sparc has no REM or DIVREM operations.
1677
1678 // ... nor does SparcV9.
1679 if (Subtarget->is64Bit()) {
1684 }
1685
1686 // Custom expand fp<->sint
1691
1692 // Custom Expand fp<->uint
1697
1698 // Lower f16 conversion operations into library calls
1705
1708
1709 // Sparc has no select or setcc: expand to SELECT_CC.
1714
1719
1720 // Sparc doesn't have BRCOND either, it has BR_CC.
1722 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1723 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1728
1733
1738
1739 if (Subtarget->is64Bit()) {
1746
1748 Subtarget->usePopc() ? Legal : Expand);
1749 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1750 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1752 setOperationAction(ISD::ROTL , MVT::i64, Expand);
1753 setOperationAction(ISD::ROTR , MVT::i64, Expand);
1755 }
1756
1757 // ATOMICs.
1758 // Atomics are supported on SparcV9. 32-bit atomics are also
1759 // supported by some Leon SparcV8 variants. Otherwise, atomics
1760 // are unsupported.
1761 if (Subtarget->isV9()) {
1762 // TODO: we _ought_ to be able to support 64-bit atomics on 32-bit sparcv9,
1763 // but it hasn't been implemented in the backend yet.
1764 if (Subtarget->is64Bit())
1766 else
1768 } else if (Subtarget->hasLeonCasa())
1770 else
1772
1774
1776
1778
1779 // Custom Lower Atomic LOAD/STORE
1782
1783 if (Subtarget->is64Bit()) {
1788 }
1789
1790 if (!Subtarget->isV9()) {
1791 // SparcV8 does not have FNEGD and FABSD.
1794 }
1795
1796 setOperationAction(ISD::FSIN , MVT::f128, Expand);
1797 setOperationAction(ISD::FCOS , MVT::f128, Expand);
1799 setOperationAction(ISD::FREM , MVT::f128, Expand);
1800 setOperationAction(ISD::FMA , MVT::f128, Expand);
1801 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1802 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1804 setOperationAction(ISD::FREM , MVT::f64, Expand);
1805 setOperationAction(ISD::FMA , MVT::f64, Expand);
1806 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1807 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1809 setOperationAction(ISD::FREM , MVT::f32, Expand);
1810 setOperationAction(ISD::FMA , MVT::f32, Expand);
1811 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1812 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1813 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1814 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1819 setOperationAction(ISD::FPOW , MVT::f128, Expand);
1820 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1821 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1822
1826
1827 // Expands to [SU]MUL_LOHI.
1831
1832 if (Subtarget->useSoftMulDiv()) {
1833 // .umul works for both signed and unsigned
1836 setLibcallName(RTLIB::MUL_I32, ".umul");
1837
1839 setLibcallName(RTLIB::SDIV_I32, ".div");
1840
1842 setLibcallName(RTLIB::UDIV_I32, ".udiv");
1843
1844 setLibcallName(RTLIB::SREM_I32, ".rem");
1845 setLibcallName(RTLIB::UREM_I32, ".urem");
1846 }
1847
1848 if (Subtarget->is64Bit()) {
1853
1857 }
1858
1859 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1860 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1861 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1862 setOperationAction(ISD::VAARG , MVT::Other, Custom);
1863
1864 setOperationAction(ISD::TRAP , MVT::Other, Legal);
1866
1867 // Use the default implementation.
1868 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1869 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1873
1875
1877 Subtarget->usePopc() ? Legal : Expand);
1878
1879 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1880 setOperationAction(ISD::LOAD, MVT::f128, Legal);
1881 setOperationAction(ISD::STORE, MVT::f128, Legal);
1882 } else {
1883 setOperationAction(ISD::LOAD, MVT::f128, Custom);
1885 }
1886
1887 if (Subtarget->hasHardQuad()) {
1888 setOperationAction(ISD::FADD, MVT::f128, Legal);
1889 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1890 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1891 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1892 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1895 if (Subtarget->isV9()) {
1896 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1897 setOperationAction(ISD::FABS, MVT::f128, Legal);
1898 } else {
1899 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1900 setOperationAction(ISD::FABS, MVT::f128, Custom);
1901 }
1902
1903 if (!Subtarget->is64Bit()) {
1904 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1905 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1906 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1907 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1908 }
1909
1910 } else {
1911 // Custom legalize f128 operations.
1912
1913 setOperationAction(ISD::FADD, MVT::f128, Custom);
1914 setOperationAction(ISD::FSUB, MVT::f128, Custom);
1915 setOperationAction(ISD::FMUL, MVT::f128, Custom);
1916 setOperationAction(ISD::FDIV, MVT::f128, Custom);
1918 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1919 setOperationAction(ISD::FABS, MVT::f128, Custom);
1920
1924
1925 // Setup Runtime library names.
1926 if (Subtarget->is64Bit() && !Subtarget->useSoftFloat()) {
1927 setLibcallName(RTLIB::ADD_F128, "_Qp_add");
1928 setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
1929 setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
1930 setLibcallName(RTLIB::DIV_F128, "_Qp_div");
1931 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1932 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1933 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1934 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1935 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1936 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
1937 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
1938 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
1939 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
1940 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1941 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1942 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1943 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1944 } else if (!Subtarget->useSoftFloat()) {
1945 setLibcallName(RTLIB::ADD_F128, "_Q_add");
1946 setLibcallName(RTLIB::SUB_F128, "_Q_sub");
1947 setLibcallName(RTLIB::MUL_F128, "_Q_mul");
1948 setLibcallName(RTLIB::DIV_F128, "_Q_div");
1949 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1950 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1951 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1952 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1953 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1954 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1955 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1956 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1957 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1958 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1959 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1960 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1961 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1962 }
1963 }
1964
1965 if (Subtarget->fixAllFDIVSQRT()) {
1966 // Promote FDIVS and FSQRTS to FDIVD and FSQRTD instructions instead as
1967 // the former instructions generate errata on LEON processors.
1970 }
1971
1972 if (Subtarget->hasNoFMULS()) {
1974 }
1975
1976 // Custom combine bitcast between f64 and v2i32
1977 if (!Subtarget->is64Bit())
1979
1980 if (Subtarget->hasLeonCycleCounter())
1982
1984
1986
1988}
1989
1991 return Subtarget->useSoftFloat();
1992}
1993
1994const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1995 switch ((SPISD::NodeType)Opcode) {
1996 case SPISD::FIRST_NUMBER: break;
1997 case SPISD::CMPICC: return "SPISD::CMPICC";
1998 case SPISD::CMPFCC: return "SPISD::CMPFCC";
1999 case SPISD::CMPFCC_V9:
2000 return "SPISD::CMPFCC_V9";
2001 case SPISD::BRICC: return "SPISD::BRICC";
2002 case SPISD::BPICC:
2003 return "SPISD::BPICC";
2004 case SPISD::BPXCC:
2005 return "SPISD::BPXCC";
2006 case SPISD::BRFCC: return "SPISD::BRFCC";
2007 case SPISD::BRFCC_V9:
2008 return "SPISD::BRFCC_V9";
2009 case SPISD::BR_REG:
2010 return "SPISD::BR_REG";
2011 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
2012 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
2013 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
2014 case SPISD::SELECT_REG:
2015 return "SPISD::SELECT_REG";
2016 case SPISD::Hi: return "SPISD::Hi";
2017 case SPISD::Lo: return "SPISD::Lo";
2018 case SPISD::FTOI: return "SPISD::FTOI";
2019 case SPISD::ITOF: return "SPISD::ITOF";
2020 case SPISD::FTOX: return "SPISD::FTOX";
2021 case SPISD::XTOF: return "SPISD::XTOF";
2022 case SPISD::CALL: return "SPISD::CALL";
2023 case SPISD::RET_GLUE: return "SPISD::RET_GLUE";
2024 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
2025 case SPISD::FLUSHW: return "SPISD::FLUSHW";
2026 case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
2027 case SPISD::TLS_LD: return "SPISD::TLS_LD";
2028 case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
2029 case SPISD::TAIL_CALL: return "SPISD::TAIL_CALL";
2030 case SPISD::LOAD_GDOP: return "SPISD::LOAD_GDOP";
2031 }
2032 return nullptr;
2033}
2034
2036 EVT VT) const {
2037 if (!VT.isVector())
2038 return MVT::i32;
2040}
2041
2042/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
2043/// be zero. Op is expected to be a target specific node. Used by DAG
2044/// combiner.
2046 (const SDValue Op,
2047 KnownBits &Known,
2048 const APInt &DemandedElts,
2049 const SelectionDAG &DAG,
2050 unsigned Depth) const {
2051 KnownBits Known2;
2052 Known.resetAll();
2053
2054 switch (Op.getOpcode()) {
2055 default: break;
2056 case SPISD::SELECT_ICC:
2057 case SPISD::SELECT_XCC:
2058 case SPISD::SELECT_FCC:
2059 Known = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
2060 Known2 = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
2061
2062 // Only known if known in both the LHS and RHS.
2063 Known = Known.intersectWith(Known2);
2064 break;
2065 }
2066}
2067
2068// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
2069// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
2070static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
2071 ISD::CondCode CC, unsigned &SPCC) {
2072 if (isNullConstant(RHS) && CC == ISD::SETNE &&
2073 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
2074 LHS.getOpcode() == SPISD::SELECT_XCC) &&
2075 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
2076 (LHS.getOpcode() == SPISD::SELECT_FCC &&
2077 (LHS.getOperand(3).getOpcode() == SPISD::CMPFCC ||
2078 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC_V9))) &&
2079 isOneConstant(LHS.getOperand(0)) && isNullConstant(LHS.getOperand(1))) {
2080 SDValue CMPCC = LHS.getOperand(3);
2081 SPCC = LHS.getConstantOperandVal(2);
2082 LHS = CMPCC.getOperand(0);
2083 RHS = CMPCC.getOperand(1);
2084 }
2085}
2086
2087// Convert to a target node and set target flags.
2089 SelectionDAG &DAG) const {
2090 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
2091 return DAG.getTargetGlobalAddress(GA->getGlobal(),
2092 SDLoc(GA),
2093 GA->getValueType(0),
2094 GA->getOffset(), TF);
2095
2096 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
2097 return DAG.getTargetConstantPool(CP->getConstVal(), CP->getValueType(0),
2098 CP->getAlign(), CP->getOffset(), TF);
2099
2100 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
2101 return DAG.getTargetBlockAddress(BA->getBlockAddress(),
2102 Op.getValueType(),
2103 0,
2104 TF);
2105
2106 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
2107 return DAG.getTargetExternalSymbol(ES->getSymbol(),
2108 ES->getValueType(0), TF);
2109
2110 llvm_unreachable("Unhandled address SDNode");
2111}
2112
2113// Split Op into high and low parts according to HiTF and LoTF.
2114// Return an ADD node combining the parts.
2116 unsigned HiTF, unsigned LoTF,
2117 SelectionDAG &DAG) const {
2118 SDLoc DL(Op);
2119 EVT VT = Op.getValueType();
2120 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
2121 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
2122 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
2123}
2124
2125// Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
2126// or ExternalSymbol SDNode.
2128 SDLoc DL(Op);
2129 EVT VT = getPointerTy(DAG.getDataLayout());
2130
2131 // Handle PIC mode first. SPARC needs a got load for every variable!
2132 if (isPositionIndependent()) {
2133 const Module *M = DAG.getMachineFunction().getFunction().getParent();
2134 PICLevel::Level picLevel = M->getPICLevel();
2135 SDValue Idx;
2136
2137 if (picLevel == PICLevel::SmallPIC) {
2138 // This is the pic13 code model, the GOT is known to be smaller than 8KiB.
2139 Idx = DAG.getNode(SPISD::Lo, DL, Op.getValueType(),
2141 } else {
2142 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
2145 }
2146
2147 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
2148 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Idx);
2149 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2150 // function has calls.
2152 MFI.setHasCalls(true);
2153 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
2155 }
2156
2157 // This is one of the absolute code models.
2158 switch(getTargetMachine().getCodeModel()) {
2159 default:
2160 llvm_unreachable("Unsupported absolute code model");
2161 case CodeModel::Small:
2162 // abs32.
2165 case CodeModel::Medium: {
2166 // abs44.
2169 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32));
2171 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
2172 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
2173 }
2174 case CodeModel::Large: {
2175 // abs64.
2178 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32));
2181 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
2182 }
2183 }
2184}
2185
2187 SelectionDAG &DAG) const {
2188 return makeAddress(Op, DAG);
2189}
2190
2192 SelectionDAG &DAG) const {
2193 return makeAddress(Op, DAG);
2194}
2195
2197 SelectionDAG &DAG) const {
2198 return makeAddress(Op, DAG);
2199}
2200
2202 SelectionDAG &DAG) const {
2203
2204 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2205 if (DAG.getTarget().useEmulatedTLS())
2206 return LowerToTLSEmulatedModel(GA, DAG);
2207
2208 SDLoc DL(GA);
2209 const GlobalValue *GV = GA->getGlobal();
2210 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2211
2213
2214 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2215 unsigned HiTF = ((model == TLSModel::GeneralDynamic)
2218 unsigned LoTF = ((model == TLSModel::GeneralDynamic)
2221 unsigned addTF = ((model == TLSModel::GeneralDynamic)
2224 unsigned callTF = ((model == TLSModel::GeneralDynamic)
2227
2228 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
2230 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
2231 withTargetFlags(Op, addTF, DAG));
2232
2233 SDValue Chain = DAG.getEntryNode();
2234 SDValue InGlue;
2235
2236 Chain = DAG.getCALLSEQ_START(Chain, 1, 0, DL);
2237 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InGlue);
2238 InGlue = Chain.getValue(1);
2239 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
2240 SDValue Symbol = withTargetFlags(Op, callTF, DAG);
2241
2242 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2243 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
2245 assert(Mask && "Missing call preserved mask for calling convention");
2246 SDValue Ops[] = {Chain,
2247 Callee,
2248 Symbol,
2249 DAG.getRegister(SP::O0, PtrVT),
2250 DAG.getRegisterMask(Mask),
2251 InGlue};
2252 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
2253 InGlue = Chain.getValue(1);
2254 Chain = DAG.getCALLSEQ_END(Chain, 1, 0, InGlue, DL);
2255 InGlue = Chain.getValue(1);
2256 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InGlue);
2257
2258 if (model != TLSModel::LocalDynamic)
2259 return Ret;
2260
2261 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2263 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2265 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2266 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
2268 }
2269
2270 if (model == TLSModel::InitialExec) {
2271 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX
2273
2275
2276 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2277 // function has calls.
2279 MFI.setHasCalls(true);
2280
2281 SDValue TGA = makeHiLoPair(Op,
2284 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
2286 DL, PtrVT, Ptr,
2287 withTargetFlags(Op, ldTF, DAG));
2288 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
2289 DAG.getRegister(SP::G7, PtrVT), Offset,
2292 }
2293
2294 assert(model == TLSModel::LocalExec);
2295 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2297 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2299 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2300
2301 return DAG.getNode(ISD::ADD, DL, PtrVT,
2302 DAG.getRegister(SP::G7, PtrVT), Offset);
2303}
2304
2306 ArgListTy &Args, SDValue Arg,
2307 const SDLoc &DL,
2308 SelectionDAG &DAG) const {
2310 EVT ArgVT = Arg.getValueType();
2311 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2312
2313 ArgListEntry Entry;
2314 Entry.Node = Arg;
2315 Entry.Ty = ArgTy;
2316
2317 if (ArgTy->isFP128Ty()) {
2318 // Create a stack object and pass the pointer to the library function.
2319 int FI = MFI.CreateStackObject(16, Align(8), false);
2320 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2321 Chain = DAG.getStore(Chain, DL, Entry.Node, FIPtr, MachinePointerInfo(),
2322 Align(8));
2323
2324 Entry.Node = FIPtr;
2325 Entry.Ty = PointerType::getUnqual(ArgTy);
2326 }
2327 Args.push_back(Entry);
2328 return Chain;
2329}
2330
2331SDValue
2333 const char *LibFuncName,
2334 unsigned numArgs) const {
2335
2336 ArgListTy Args;
2337
2339 auto PtrVT = getPointerTy(DAG.getDataLayout());
2340
2341 SDValue Callee = DAG.getExternalSymbol(LibFuncName, PtrVT);
2342 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2343 Type *RetTyABI = RetTy;
2344 SDValue Chain = DAG.getEntryNode();
2345 SDValue RetPtr;
2346
2347 if (RetTy->isFP128Ty()) {
2348 // Create a Stack Object to receive the return value of type f128.
2349 ArgListEntry Entry;
2350 int RetFI = MFI.CreateStackObject(16, Align(8), false);
2351 RetPtr = DAG.getFrameIndex(RetFI, PtrVT);
2352 Entry.Node = RetPtr;
2353 Entry.Ty = PointerType::getUnqual(RetTy);
2354 if (!Subtarget->is64Bit()) {
2355 Entry.IsSRet = true;
2356 Entry.IndirectType = RetTy;
2357 }
2358 Entry.IsReturned = false;
2359 Args.push_back(Entry);
2360 RetTyABI = Type::getVoidTy(*DAG.getContext());
2361 }
2362
2363 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2364 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2365 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
2366 }
2368 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
2369 .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args));
2370
2371 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2372
2373 // chain is in second result.
2374 if (RetTyABI == RetTy)
2375 return CallInfo.first;
2376
2377 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2378
2379 Chain = CallInfo.second;
2380
2381 // Load RetPtr to get the return value.
2382 return DAG.getLoad(Op.getValueType(), SDLoc(Op), Chain, RetPtr,
2384}
2385
2387 unsigned &SPCC, const SDLoc &DL,
2388 SelectionDAG &DAG) const {
2389
2390 const char *LibCall = nullptr;
2391 bool is64Bit = Subtarget->is64Bit();
2392 switch(SPCC) {
2393 default: llvm_unreachable("Unhandled conditional code!");
2394 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2395 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2396 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2397 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2398 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2399 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2400 case SPCC::FCC_UL :
2401 case SPCC::FCC_ULE:
2402 case SPCC::FCC_UG :
2403 case SPCC::FCC_UGE:
2404 case SPCC::FCC_U :
2405 case SPCC::FCC_O :
2406 case SPCC::FCC_LG :
2407 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2408 }
2409
2410 auto PtrVT = getPointerTy(DAG.getDataLayout());
2411 SDValue Callee = DAG.getExternalSymbol(LibCall, PtrVT);
2413 ArgListTy Args;
2414 SDValue Chain = DAG.getEntryNode();
2415 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
2416 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
2417
2419 CLI.setDebugLoc(DL).setChain(Chain)
2420 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args));
2421
2422 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2423
2424 // result is in first, and chain is in second result.
2425 SDValue Result = CallInfo.first;
2426
2427 switch(SPCC) {
2428 default: {
2429 SDValue RHS = DAG.getConstant(0, DL, Result.getValueType());
2430 SPCC = SPCC::ICC_NE;
2431 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2432 }
2433 case SPCC::FCC_UL : {
2434 SDValue Mask = DAG.getConstant(1, DL, Result.getValueType());
2435 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2436 SDValue RHS = DAG.getConstant(0, DL, Result.getValueType());
2437 SPCC = SPCC::ICC_NE;
2438 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2439 }
2440 case SPCC::FCC_ULE: {
2441 SDValue RHS = DAG.getConstant(2, DL, Result.getValueType());
2442 SPCC = SPCC::ICC_NE;
2443 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2444 }
2445 case SPCC::FCC_UG : {
2446 SDValue RHS = DAG.getConstant(1, DL, Result.getValueType());
2447 SPCC = SPCC::ICC_G;
2448 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2449 }
2450 case SPCC::FCC_UGE: {
2451 SDValue RHS = DAG.getConstant(1, DL, Result.getValueType());
2452 SPCC = SPCC::ICC_NE;
2453 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2454 }
2455
2456 case SPCC::FCC_U : {
2457 SDValue RHS = DAG.getConstant(3, DL, Result.getValueType());
2458 SPCC = SPCC::ICC_E;
2459 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2460 }
2461 case SPCC::FCC_O : {
2462 SDValue RHS = DAG.getConstant(3, DL, Result.getValueType());
2463 SPCC = SPCC::ICC_NE;
2464 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2465 }
2466 case SPCC::FCC_LG : {
2467 SDValue Mask = DAG.getConstant(3, DL, Result.getValueType());
2468 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2469 SDValue RHS = DAG.getConstant(0, DL, Result.getValueType());
2470 SPCC = SPCC::ICC_NE;
2471 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2472 }
2473 case SPCC::FCC_UE : {
2474 SDValue Mask = DAG.getConstant(3, DL, Result.getValueType());
2475 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2476 SDValue RHS = DAG.getConstant(0, DL, Result.getValueType());
2477 SPCC = SPCC::ICC_E;
2478 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2479 }
2480 }
2481}
2482
2483static SDValue
2485 const SparcTargetLowering &TLI) {
2486
2487 if (Op.getOperand(0).getValueType() == MVT::f64)
2488 return TLI.LowerF128Op(Op, DAG,
2489 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2490
2491 if (Op.getOperand(0).getValueType() == MVT::f32)
2492 return TLI.LowerF128Op(Op, DAG,
2493 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2494
2495 llvm_unreachable("fpextend with non-float operand!");
2496 return SDValue();
2497}
2498
2499static SDValue
2501 const SparcTargetLowering &TLI) {
2502 // FP_ROUND on f64 and f32 are legal.
2503 if (Op.getOperand(0).getValueType() != MVT::f128)
2504 return Op;
2505
2506 if (Op.getValueType() == MVT::f64)
2507 return TLI.LowerF128Op(Op, DAG,
2508 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2509 if (Op.getValueType() == MVT::f32)
2510 return TLI.LowerF128Op(Op, DAG,
2511 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2512
2513 llvm_unreachable("fpround to non-float!");
2514 return SDValue();
2515}
2516
2518 const SparcTargetLowering &TLI,
2519 bool hasHardQuad) {
2520 SDLoc dl(Op);
2521 EVT VT = Op.getValueType();
2522 assert(VT == MVT::i32 || VT == MVT::i64);
2523
2524 // Expand f128 operations to fp128 abi calls.
2525 if (Op.getOperand(0).getValueType() == MVT::f128
2526 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2527 const char *libName = TLI.getLibcallName(VT == MVT::i32
2528 ? RTLIB::FPTOSINT_F128_I32
2529 : RTLIB::FPTOSINT_F128_I64);
2530 return TLI.LowerF128Op(Op, DAG, libName, 1);
2531 }
2532
2533 // Expand if the resulting type is illegal.
2534 if (!TLI.isTypeLegal(VT))
2535 return SDValue();
2536
2537 // Otherwise, Convert the fp value to integer in an FP register.
2538 if (VT == MVT::i32)
2539 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2540 else
2541 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2542
2543 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2544}
2545
2547 const SparcTargetLowering &TLI,
2548 bool hasHardQuad) {
2549 SDLoc dl(Op);
2550 EVT OpVT = Op.getOperand(0).getValueType();
2551 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2552
2553 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2554
2555 // Expand f128 operations to fp128 ABI calls.
2556 if (Op.getValueType() == MVT::f128
2557 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2558 const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2559 ? RTLIB::SINTTOFP_I32_F128
2560 : RTLIB::SINTTOFP_I64_F128);
2561 return TLI.LowerF128Op(Op, DAG, libName, 1);
2562 }
2563
2564 // Expand if the operand type is illegal.
2565 if (!TLI.isTypeLegal(OpVT))
2566 return SDValue();
2567
2568 // Otherwise, Convert the int value to FP in an FP register.
2569 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2570 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2571 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2572}
2573
2575 const SparcTargetLowering &TLI,
2576 bool hasHardQuad) {
2577 SDLoc dl(Op);
2578 EVT VT = Op.getValueType();
2579
2580 // Expand if it does not involve f128 or the target has support for
2581 // quad floating point instructions and the resulting type is legal.
2582 if (Op.getOperand(0).getValueType() != MVT::f128 ||
2583 (hasHardQuad && TLI.isTypeLegal(VT)))
2584 return SDValue();
2585
2586 assert(VT == MVT::i32 || VT == MVT::i64);
2587
2588 return TLI.LowerF128Op(Op, DAG,
2589 TLI.getLibcallName(VT == MVT::i32
2590 ? RTLIB::FPTOUINT_F128_I32
2591 : RTLIB::FPTOUINT_F128_I64),
2592 1);
2593}
2594
2596 const SparcTargetLowering &TLI,
2597 bool hasHardQuad) {
2598 SDLoc dl(Op);
2599 EVT OpVT = Op.getOperand(0).getValueType();
2600 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2601
2602 // Expand if it does not involve f128 or the target has support for
2603 // quad floating point instructions and the operand type is legal.
2604 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2605 return SDValue();
2606
2607 return TLI.LowerF128Op(Op, DAG,
2608 TLI.getLibcallName(OpVT == MVT::i32
2609 ? RTLIB::UINTTOFP_I32_F128
2610 : RTLIB::UINTTOFP_I64_F128),
2611 1);
2612}
2613
2615 const SparcTargetLowering &TLI, bool hasHardQuad,
2616 bool isV9, bool is64Bit) {
2617 SDValue Chain = Op.getOperand(0);
2618 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2619 SDValue LHS = Op.getOperand(2);
2620 SDValue RHS = Op.getOperand(3);
2621 SDValue Dest = Op.getOperand(4);
2622 SDLoc dl(Op);
2623 unsigned Opc, SPCC = ~0U;
2624
2625 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2626 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2627 LookThroughSetCC(LHS, RHS, CC, SPCC);
2628 assert(LHS.getValueType() == RHS.getValueType());
2629
2630 // Get the condition flag.
2631 SDValue CompareFlag;
2632 if (LHS.getValueType().isInteger()) {
2633 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2634 // and the RHS is zero we might be able to use a specialized branch.
2635 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2637 return DAG.getNode(SPISD::BR_REG, dl, MVT::Other, Chain, Dest,
2638 DAG.getConstant(intCondCCodeToRcond(CC), dl, MVT::i32),
2639 LHS);
2640
2641 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2642 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2643 if (isV9)
2644 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2645 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BPICC : SPISD::BPXCC;
2646 else
2647 // Non-v9 targets don't have xcc.
2648 Opc = SPISD::BRICC;
2649 } else {
2650 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2651 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2652 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2653 Opc = isV9 ? SPISD::BPICC : SPISD::BRICC;
2654 } else {
2655 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2656 CompareFlag = DAG.getNode(CmpOpc, dl, MVT::Glue, LHS, RHS);
2657 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2658 Opc = isV9 ? SPISD::BRFCC_V9 : SPISD::BRFCC;
2659 }
2660 }
2661 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2662 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2663}
2664
2666 const SparcTargetLowering &TLI, bool hasHardQuad,
2667 bool isV9, bool is64Bit) {
2668 SDValue LHS = Op.getOperand(0);
2669 SDValue RHS = Op.getOperand(1);
2670 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2671 SDValue TrueVal = Op.getOperand(2);
2672 SDValue FalseVal = Op.getOperand(3);
2673 SDLoc dl(Op);
2674 unsigned Opc, SPCC = ~0U;
2675
2676 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2677 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2678 LookThroughSetCC(LHS, RHS, CC, SPCC);
2679 assert(LHS.getValueType() == RHS.getValueType());
2680
2681 SDValue CompareFlag;
2682 if (LHS.getValueType().isInteger()) {
2683 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2684 // and the RHS is zero we might be able to use a specialized select.
2685 // All SELECT_CC between any two scalar integer types are eligible for
2686 // lowering to specialized instructions. Additionally, f32 and f64 types
2687 // are also eligible, but for f128 we can only use the specialized
2688 // instruction when we have hardquad.
2689 EVT ValType = TrueVal.getValueType();
2690 bool IsEligibleType = ValType.isScalarInteger() || ValType == MVT::f32 ||
2691 ValType == MVT::f64 ||
2692 (ValType == MVT::f128 && hasHardQuad);
2693 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2694 isNullConstant(RHS) && !ISD::isUnsignedIntSetCC(CC) && IsEligibleType)
2695 return DAG.getNode(
2696 SPISD::SELECT_REG, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2697 DAG.getConstant(intCondCCodeToRcond(CC), dl, MVT::i32), LHS);
2698
2699 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2700 Opc = LHS.getValueType() == MVT::i32 ?
2702 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2703 } else {
2704 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2705 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2706 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2707 Opc = SPISD::SELECT_ICC;
2708 } else {
2709 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2710 CompareFlag = DAG.getNode(CmpOpc, dl, MVT::Glue, LHS, RHS);
2711 Opc = SPISD::SELECT_FCC;
2712 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2713 }
2714 }
2715 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2716 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2717}
2718
2720 const SparcTargetLowering &TLI) {
2723 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2724
2725 // Need frame address to find the address of VarArgsFrameIndex.
2727
2728 // vastart just stores the address of the VarArgsFrameIndex slot into the
2729 // memory location argument.
2730 SDLoc DL(Op);
2731 SDValue Offset =
2732 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT),
2733 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL));
2734 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2735 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2736 MachinePointerInfo(SV));
2737}
2738
2740 SDNode *Node = Op.getNode();
2741 EVT VT = Node->getValueType(0);
2742 SDValue InChain = Node->getOperand(0);
2743 SDValue VAListPtr = Node->getOperand(1);
2744 EVT PtrVT = VAListPtr.getValueType();
2745 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2746 SDLoc DL(Node);
2747 SDValue VAList =
2748 DAG.getLoad(PtrVT, DL, InChain, VAListPtr, MachinePointerInfo(SV));
2749 // Increment the pointer, VAList, to the next vaarg.
2750 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2752 DL));
2753 // Store the incremented VAList to the legalized pointer.
2754 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr, VAListPtr,
2755 MachinePointerInfo(SV));
2756 // Load the actual argument out of the pointer VAList.
2757 // We can't count on greater alignment than the word size.
2758 return DAG.getLoad(
2759 VT, DL, InChain, VAList, MachinePointerInfo(),
2760 Align(std::min(PtrVT.getFixedSizeInBits(), VT.getFixedSizeInBits()) / 8));
2761}
2762
2764 const SparcSubtarget *Subtarget) {
2765 SDValue Chain = Op.getOperand(0); // Legalize the chain.
2766 SDValue Size = Op.getOperand(1); // Legalize the size.
2767 MaybeAlign Alignment =
2768 cast<ConstantSDNode>(Op.getOperand(2))->getMaybeAlignValue();
2769 Align StackAlign = Subtarget->getFrameLowering()->getStackAlign();
2770 EVT VT = Size->getValueType(0);
2771 SDLoc dl(Op);
2772
2773 // TODO: implement over-aligned alloca. (Note: also implies
2774 // supporting support for overaligned function frames + dynamic
2775 // allocations, at all, which currently isn't supported)
2776 if (Alignment && *Alignment > StackAlign) {
2777 const MachineFunction &MF = DAG.getMachineFunction();
2778 report_fatal_error("Function \"" + Twine(MF.getName()) + "\": "
2779 "over-aligned dynamic alloca not supported.");
2780 }
2781
2782 // The resultant pointer needs to be above the register spill area
2783 // at the bottom of the stack.
2784 unsigned regSpillArea;
2785 if (Subtarget->is64Bit()) {
2786 regSpillArea = 128;
2787 } else {
2788 // On Sparc32, the size of the spill area is 92. Unfortunately,
2789 // that's only 4-byte aligned, not 8-byte aligned (the stack
2790 // pointer is 8-byte aligned). So, if the user asked for an 8-byte
2791 // aligned dynamic allocation, we actually need to add 96 to the
2792 // bottom of the stack, instead of 92, to ensure 8-byte alignment.
2793
2794 // That also means adding 4 to the size of the allocation --
2795 // before applying the 8-byte rounding. Unfortunately, we the
2796 // value we get here has already had rounding applied. So, we need
2797 // to add 8, instead, wasting a bit more memory.
2798
2799 // Further, this only actually needs to be done if the required
2800 // alignment is > 4, but, we've lost that info by this point, too,
2801 // so we always apply it.
2802
2803 // (An alternative approach would be to always reserve 96 bytes
2804 // instead of the required 92, but then we'd waste 4 extra bytes
2805 // in every frame, not just those with dynamic stack allocations)
2806
2807 // TODO: modify code in SelectionDAGBuilder to make this less sad.
2808
2809 Size = DAG.getNode(ISD::ADD, dl, VT, Size,
2810 DAG.getConstant(8, dl, VT));
2811 regSpillArea = 96;
2812 }
2813
2814 unsigned SPReg = SP::O6;
2815 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2816 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2817 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2818
2819 regSpillArea += Subtarget->getStackPointerBias();
2820
2821 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
2822 DAG.getConstant(regSpillArea, dl, VT));
2823 SDValue Ops[2] = { NewVal, Chain };
2824 return DAG.getMergeValues(Ops, dl);
2825}
2826
2827
2829 SDLoc dl(Op);
2830 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2831 dl, MVT::Other, DAG.getEntryNode());
2832 return Chain;
2833}
2834
2836 const SparcSubtarget *Subtarget,
2837 bool AlwaysFlush = false) {
2839 MFI.setFrameAddressIsTaken(true);
2840
2841 EVT VT = Op.getValueType();
2842 SDLoc dl(Op);
2843 unsigned FrameReg = SP::I6;
2844 unsigned stackBias = Subtarget->getStackPointerBias();
2845
2846 SDValue FrameAddr;
2847 SDValue Chain;
2848
2849 // flush first to make sure the windowed registers' values are in stack
2850 Chain = (depth || AlwaysFlush) ? getFLUSHW(Op, DAG) : DAG.getEntryNode();
2851
2852 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2853
2854 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2855
2856 while (depth--) {
2857 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2858 DAG.getIntPtrConstant(Offset, dl));
2859 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo());
2860 }
2861 if (Subtarget->is64Bit())
2862 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2863 DAG.getIntPtrConstant(stackBias, dl));
2864 return FrameAddr;
2865}
2866
2867
2869 const SparcSubtarget *Subtarget) {
2870
2871 uint64_t depth = Op.getConstantOperandVal(0);
2872
2873 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2874
2875}
2876
2878 const SparcTargetLowering &TLI,
2879 const SparcSubtarget *Subtarget) {
2881 MachineFrameInfo &MFI = MF.getFrameInfo();
2882 MFI.setReturnAddressIsTaken(true);
2883
2885 return SDValue();
2886
2887 EVT VT = Op.getValueType();
2888 SDLoc dl(Op);
2889 uint64_t depth = Op.getConstantOperandVal(0);
2890
2891 SDValue RetAddr;
2892 if (depth == 0) {
2893 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2894 Register RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
2895 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2896 return RetAddr;
2897 }
2898
2899 // Need frame address to find return address of the caller.
2900 SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget, true);
2901
2902 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2904 dl, VT,
2905 FrameAddr,
2906 DAG.getIntPtrConstant(Offset, dl));
2907 RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr, MachinePointerInfo());
2908
2909 return RetAddr;
2910}
2911
2912static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG,
2913 unsigned opcode) {
2914 assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2915 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2916
2917 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2918 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2919 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2920
2921 // Note: in little-endian, the floating-point value is stored in the
2922 // registers are in the opposite order, so the subreg with the sign
2923 // bit is the highest-numbered (odd), rather than the
2924 // lowest-numbered (even).
2925
2926 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2927 SrcReg64);
2928 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2929 SrcReg64);
2930
2931 if (DAG.getDataLayout().isLittleEndian())
2932 Lo32 = DAG.getNode(opcode, dl, MVT::f32, Lo32);
2933 else
2934 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2935
2936 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2937 dl, MVT::f64), 0);
2938 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2939 DstReg64, Hi32);
2940 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2941 DstReg64, Lo32);
2942 return DstReg64;
2943}
2944
2945// Lower a f128 load into two f64 loads.
2947{
2948 SDLoc dl(Op);
2949 LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
2950 assert(LdNode->getOffset().isUndef() && "Unexpected node type");
2951
2952 Align Alignment = commonAlignment(LdNode->getOriginalAlign(), 8);
2953
2954 SDValue Hi64 =
2955 DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LdNode->getBasePtr(),
2956 LdNode->getPointerInfo(), Alignment);
2957 EVT addrVT = LdNode->getBasePtr().getValueType();
2958 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2959 LdNode->getBasePtr(),
2960 DAG.getConstant(8, dl, addrVT));
2961 SDValue Lo64 = DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LoPtr,
2962 LdNode->getPointerInfo().getWithOffset(8),
2963 Alignment);
2964
2965 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2966 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2967
2968 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2969 dl, MVT::f128);
2970 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2971 MVT::f128,
2972 SDValue(InFP128, 0),
2973 Hi64,
2974 SubRegEven);
2975 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2976 MVT::f128,
2977 SDValue(InFP128, 0),
2978 Lo64,
2979 SubRegOdd);
2980 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2981 SDValue(Lo64.getNode(), 1) };
2982 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2983 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2984 return DAG.getMergeValues(Ops, dl);
2985}
2986
2988{
2989 LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
2990
2991 EVT MemVT = LdNode->getMemoryVT();
2992 if (MemVT == MVT::f128)
2993 return LowerF128Load(Op, DAG);
2994
2995 return Op;
2996}
2997
2998// Lower a f128 store into two f64 stores.
3000 SDLoc dl(Op);
3001 StoreSDNode *StNode = cast<StoreSDNode>(Op.getNode());
3002 assert(StNode->getOffset().isUndef() && "Unexpected node type");
3003
3004 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
3005 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
3006
3007 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3008 dl,
3009 MVT::f64,
3010 StNode->getValue(),
3011 SubRegEven);
3012 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3013 dl,
3014 MVT::f64,
3015 StNode->getValue(),
3016 SubRegOdd);
3017
3018 Align Alignment = commonAlignment(StNode->getOriginalAlign(), 8);
3019
3020 SDValue OutChains[2];
3021 OutChains[0] =
3022 DAG.getStore(StNode->getChain(), dl, SDValue(Hi64, 0),
3023 StNode->getBasePtr(), StNode->getPointerInfo(),
3024 Alignment);
3025 EVT addrVT = StNode->getBasePtr().getValueType();
3026 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
3027 StNode->getBasePtr(),
3028 DAG.getConstant(8, dl, addrVT));
3029 OutChains[1] = DAG.getStore(StNode->getChain(), dl, SDValue(Lo64, 0), LoPtr,
3030 StNode->getPointerInfo().getWithOffset(8),
3031 Alignment);
3032 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
3033}
3034
3036{
3037 SDLoc dl(Op);
3038 StoreSDNode *St = cast<StoreSDNode>(Op.getNode());
3039
3040 EVT MemVT = St->getMemoryVT();
3041 if (MemVT == MVT::f128)
3042 return LowerF128Store(Op, DAG);
3043
3044 if (MemVT == MVT::i64) {
3045 // Custom handling for i64 stores: turn it into a bitcast and a
3046 // v2i32 store.
3047 SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue());
3048 SDValue Chain = DAG.getStore(
3049 St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(),
3050 St->getOriginalAlign(), St->getMemOperand()->getFlags(),
3051 St->getAAInfo());
3052 return Chain;
3053 }
3054
3055 return SDValue();
3056}
3057
3059 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
3060 && "invalid opcode");
3061
3062 SDLoc dl(Op);
3063
3064 if (Op.getValueType() == MVT::f64)
3065 return LowerF64Op(Op.getOperand(0), dl, DAG, Op.getOpcode());
3066 if (Op.getValueType() != MVT::f128)
3067 return Op;
3068
3069 // Lower fabs/fneg on f128 to fabs/fneg on f64
3070 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
3071 // (As with LowerF64Op, on little-endian, we need to negate the odd
3072 // subreg)
3073
3074 SDValue SrcReg128 = Op.getOperand(0);
3075 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
3076 SrcReg128);
3077 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
3078 SrcReg128);
3079
3080 if (DAG.getDataLayout().isLittleEndian()) {
3081 if (isV9)
3082 Lo64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Lo64);
3083 else
3084 Lo64 = LowerF64Op(Lo64, dl, DAG, Op.getOpcode());
3085 } else {
3086 if (isV9)
3087 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
3088 else
3089 Hi64 = LowerF64Op(Hi64, dl, DAG, Op.getOpcode());
3090 }
3091
3092 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
3093 dl, MVT::f128), 0);
3094 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
3095 DstReg128, Hi64);
3096 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
3097 DstReg128, Lo64);
3098 return DstReg128;
3099}
3100
3102 if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getSuccessOrdering())) {
3103 // Expand with a fence.
3104 return SDValue();
3105 }
3106
3107 // Monotonic load/stores are legal.
3108 return Op;
3109}
3110
3112 SelectionDAG &DAG) const {
3113 unsigned IntNo = Op.getConstantOperandVal(0);
3114 SDLoc dl(Op);
3115 switch (IntNo) {
3116 default: return SDValue(); // Don't custom lower most intrinsics.
3117 case Intrinsic::thread_pointer: {
3118 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3119 return DAG.getRegister(SP::G7, PtrVT);
3120 }
3121 }
3122}
3123
3126
3127 bool hasHardQuad = Subtarget->hasHardQuad();
3128 bool isV9 = Subtarget->isV9();
3129 bool is64Bit = Subtarget->is64Bit();
3130
3131 switch (Op.getOpcode()) {
3132 default: llvm_unreachable("Should not custom lower this!");
3133
3134 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this,
3135 Subtarget);
3136 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
3137 Subtarget);
3139 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3140 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3141 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3142 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
3143 hasHardQuad);
3144 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
3145 hasHardQuad);
3146 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
3147 hasHardQuad);
3148 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
3149 hasHardQuad);
3150 case ISD::BR_CC:
3151 return LowerBR_CC(Op, DAG, *this, hasHardQuad, isV9, is64Bit);
3152 case ISD::SELECT_CC:
3153 return LowerSELECT_CC(Op, DAG, *this, hasHardQuad, isV9, is64Bit);
3154 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
3155 case ISD::VAARG: return LowerVAARG(Op, DAG);
3157 Subtarget);
3158
3159 case ISD::LOAD: return LowerLOAD(Op, DAG);
3160 case ISD::STORE: return LowerSTORE(Op, DAG);
3161 case ISD::FADD: return LowerF128Op(Op, DAG,
3162 getLibcallName(RTLIB::ADD_F128), 2);
3163 case ISD::FSUB: return LowerF128Op(Op, DAG,
3164 getLibcallName(RTLIB::SUB_F128), 2);
3165 case ISD::FMUL: return LowerF128Op(Op, DAG,
3166 getLibcallName(RTLIB::MUL_F128), 2);
3167 case ISD::FDIV: return LowerF128Op(Op, DAG,
3168 getLibcallName(RTLIB::DIV_F128), 2);
3169 case ISD::FSQRT: return LowerF128Op(Op, DAG,
3170 getLibcallName(RTLIB::SQRT_F128),1);
3171 case ISD::FABS:
3172 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
3173 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
3174 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
3175 case ISD::ATOMIC_LOAD:
3176 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
3178 }
3179}
3180
3182 const SDLoc &DL,
3183 SelectionDAG &DAG) const {
3184 APInt V = C->getValueAPF().bitcastToAPInt();
3185 SDValue Lo = DAG.getConstant(V.zextOrTrunc(32), DL, MVT::i32);
3186 SDValue Hi = DAG.getConstant(V.lshr(32).zextOrTrunc(32), DL, MVT::i32);
3187 if (DAG.getDataLayout().isLittleEndian())
3188 std::swap(Lo, Hi);
3189 return DAG.getBuildVector(MVT::v2i32, DL, {Hi, Lo});
3190}
3191
3193 DAGCombinerInfo &DCI) const {
3194 SDLoc dl(N);
3195 SDValue Src = N->getOperand(0);
3196
3197 if (isa<ConstantFPSDNode>(Src) && N->getSimpleValueType(0) == MVT::v2i32 &&
3198 Src.getSimpleValueType() == MVT::f64)
3199 return bitcastConstantFPToInt(cast<ConstantFPSDNode>(Src), dl, DCI.DAG);
3200
3201 return SDValue();
3202}
3203
3205 DAGCombinerInfo &DCI) const {
3206 switch (N->getOpcode()) {
3207 default:
3208 break;
3209 case ISD::BITCAST:
3210 return PerformBITCASTCombine(N, DCI);
3211 }
3212 return SDValue();
3213}
3214
3217 MachineBasicBlock *BB) const {
3218 switch (MI.getOpcode()) {
3219 default: llvm_unreachable("Unknown SELECT_CC!");
3220 case SP::SELECT_CC_Int_ICC:
3221 case SP::SELECT_CC_FP_ICC:
3222 case SP::SELECT_CC_DFP_ICC:
3223 case SP::SELECT_CC_QFP_ICC:
3224 if (Subtarget->isV9())
3225 return expandSelectCC(MI, BB, SP::BPICC);
3226 return expandSelectCC(MI, BB, SP::BCOND);
3227 case SP::SELECT_CC_Int_XCC:
3228 case SP::SELECT_CC_FP_XCC:
3229 case SP::SELECT_CC_DFP_XCC:
3230 case SP::SELECT_CC_QFP_XCC:
3231 return expandSelectCC(MI, BB, SP::BPXCC);
3232 case SP::SELECT_CC_Int_FCC:
3233 case SP::SELECT_CC_FP_FCC:
3234 case SP::SELECT_CC_DFP_FCC:
3235 case SP::SELECT_CC_QFP_FCC:
3236 if (Subtarget->isV9())
3237 return expandSelectCC(MI, BB, SP::FBCOND_V9);
3238 return expandSelectCC(MI, BB, SP::FBCOND);
3239 }
3240}
3241
3244 unsigned BROpcode) const {
3245 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
3246 DebugLoc dl = MI.getDebugLoc();
3247 unsigned CC = (SPCC::CondCodes)MI.getOperand(3).getImm();
3248
3249 // To "insert" a SELECT_CC instruction, we actually have to insert the
3250 // triangle control-flow pattern. The incoming instruction knows the
3251 // destination vreg to set, the condition code register to branch on, the
3252 // true/false values to select between, and the condition code for the branch.
3253 //
3254 // We produce the following control flow:
3255 // ThisMBB
3256 // | \
3257 // | IfFalseMBB
3258 // | /
3259 // SinkMBB
3260 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3262
3263 MachineBasicBlock *ThisMBB = BB;
3264 MachineFunction *F = BB->getParent();
3265 MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
3266 MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3267 F->insert(It, IfFalseMBB);
3268 F->insert(It, SinkMBB);
3269
3270 // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
3271 SinkMBB->splice(SinkMBB->begin(), ThisMBB,
3272 std::next(MachineBasicBlock::iterator(MI)), ThisMBB->end());
3273 SinkMBB->transferSuccessorsAndUpdatePHIs(ThisMBB);
3274
3275 // Set the new successors for ThisMBB.
3276 ThisMBB->addSuccessor(IfFalseMBB);
3277 ThisMBB->addSuccessor(SinkMBB);
3278
3279 BuildMI(ThisMBB, dl, TII.get(BROpcode))
3280 .addMBB(SinkMBB)
3281 .addImm(CC);
3282
3283 // IfFalseMBB just falls through to SinkMBB.
3284 IfFalseMBB->addSuccessor(SinkMBB);
3285
3286 // %Result = phi [ %TrueValue, ThisMBB ], [ %FalseValue, IfFalseMBB ]
3287 BuildMI(*SinkMBB, SinkMBB->begin(), dl, TII.get(SP::PHI),
3288 MI.getOperand(0).getReg())
3289 .addReg(MI.getOperand(1).getReg())
3290 .addMBB(ThisMBB)
3291 .addReg(MI.getOperand(2).getReg())
3292 .addMBB(IfFalseMBB);
3293
3294 MI.eraseFromParent(); // The pseudo instruction is gone now.
3295 return SinkMBB;
3296}
3297
3298//===----------------------------------------------------------------------===//
3299// Sparc Inline Assembly Support
3300//===----------------------------------------------------------------------===//
3301
3302/// getConstraintType - Given a constraint letter, return the type of
3303/// constraint it is for this target.
3306 if (Constraint.size() == 1) {
3307 switch (Constraint[0]) {
3308 default: break;
3309 case 'r':
3310 case 'f':
3311 case 'e':
3312 return C_RegisterClass;
3313 case 'I': // SIMM13
3314 return C_Immediate;
3315 }
3316 }
3317
3318 return TargetLowering::getConstraintType(Constraint);
3319}
3320
3323 const char *constraint) const {
3325 Value *CallOperandVal = info.CallOperandVal;
3326 // If we don't have a value, we can't do a match,
3327 // but allow it at the lowest weight.
3328 if (!CallOperandVal)
3329 return CW_Default;
3330
3331 // Look at the constraint type.
3332 switch (*constraint) {
3333 default:
3335 break;
3336 case 'I': // SIMM13
3337 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
3338 if (isInt<13>(C->getSExtValue()))
3339 weight = CW_Constant;
3340 }
3341 break;
3342 }
3343 return weight;
3344}
3345
3346/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3347/// vector. If it is invalid, don't add anything to Ops.
3349 SDValue Op, StringRef Constraint, std::vector<SDValue> &Ops,
3350 SelectionDAG &DAG) const {
3351 SDValue Result;
3352
3353 // Only support length 1 constraints for now.
3354 if (Constraint.size() > 1)
3355 return;
3356
3357 char ConstraintLetter = Constraint[0];
3358 switch (ConstraintLetter) {
3359 default: break;
3360 case 'I':
3361 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3362 if (isInt<13>(C->getSExtValue())) {
3363 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
3364 Op.getValueType());
3365 break;
3366 }
3367 return;
3368 }
3369 }
3370
3371 if (Result.getNode()) {
3372 Ops.push_back(Result);
3373 return;
3374 }
3375 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3376}
3377
3378std::pair<unsigned, const TargetRegisterClass *>
3380 StringRef Constraint,
3381 MVT VT) const {
3382 if (Constraint.empty())
3383 return std::make_pair(0U, nullptr);
3384
3385 if (Constraint.size() == 1) {
3386 switch (Constraint[0]) {
3387 case 'r':
3388 if (VT == MVT::v2i32)
3389 return std::make_pair(0U, &SP::IntPairRegClass);
3390 else if (Subtarget->is64Bit())
3391 return std::make_pair(0U, &SP::I64RegsRegClass);
3392 else
3393 return std::make_pair(0U, &SP::IntRegsRegClass);
3394 case 'f':
3395 if (VT == MVT::f32 || VT == MVT::i32)
3396 return std::make_pair(0U, &SP::FPRegsRegClass);
3397 else if (VT == MVT::f64 || VT == MVT::i64)
3398 return std::make_pair(0U, &SP::LowDFPRegsRegClass);
3399 else if (VT == MVT::f128)
3400 return std::make_pair(0U, &SP::LowQFPRegsRegClass);
3401 // This will generate an error message
3402 return std::make_pair(0U, nullptr);
3403 case 'e':
3404 if (VT == MVT::f32 || VT == MVT::i32)
3405 return std::make_pair(0U, &SP::FPRegsRegClass);
3406 else if (VT == MVT::f64 || VT == MVT::i64 )
3407 return std::make_pair(0U, &SP::DFPRegsRegClass);
3408 else if (VT == MVT::f128)
3409 return std::make_pair(0U, &SP::QFPRegsRegClass);
3410 // This will generate an error message
3411 return std::make_pair(0U, nullptr);
3412 }
3413 }
3414
3415 if (Constraint.front() != '{')
3416 return std::make_pair(0U, nullptr);
3417
3418 assert(Constraint.back() == '}' && "Not a brace enclosed constraint?");
3419 StringRef RegName(Constraint.data() + 1, Constraint.size() - 2);
3420 if (RegName.empty())
3421 return std::make_pair(0U, nullptr);
3422
3423 unsigned long long RegNo;
3424 // Handle numbered register aliases.
3425 if (RegName[0] == 'r' &&
3426 getAsUnsignedInteger(RegName.begin() + 1, 10, RegNo)) {
3427 // r0-r7 -> g0-g7
3428 // r8-r15 -> o0-o7
3429 // r16-r23 -> l0-l7
3430 // r24-r31 -> i0-i7
3431 if (RegNo > 31)
3432 return std::make_pair(0U, nullptr);
3433 const char RegTypes[] = {'g', 'o', 'l', 'i'};
3434 char RegType = RegTypes[RegNo / 8];
3435 char RegIndex = '0' + (RegNo % 8);
3436 char Tmp[] = {'{', RegType, RegIndex, '}', 0};
3437 return getRegForInlineAsmConstraint(TRI, Tmp, VT);
3438 }
3439
3440 // Rewrite the fN constraint according to the value type if needed.
3441 if (VT != MVT::f32 && VT != MVT::Other && RegName[0] == 'f' &&
3442 getAsUnsignedInteger(RegName.begin() + 1, 10, RegNo)) {
3443 if (VT == MVT::f64 && (RegNo % 2 == 0)) {
3445 TRI, StringRef("{d" + utostr(RegNo / 2) + "}"), VT);
3446 } else if (VT == MVT::f128 && (RegNo % 4 == 0)) {
3448 TRI, StringRef("{q" + utostr(RegNo / 4) + "}"), VT);
3449 } else {
3450 return std::make_pair(0U, nullptr);
3451 }
3452 }
3453
3454 auto ResultPair =
3456 if (!ResultPair.second)
3457 return std::make_pair(0U, nullptr);
3458
3459 // Force the use of I64Regs over IntRegs for 64-bit values.
3460 if (Subtarget->is64Bit() && VT == MVT::i64) {
3461 assert(ResultPair.second == &SP::IntRegsRegClass &&
3462 "Unexpected register class");
3463 return std::make_pair(ResultPair.first, &SP::I64RegsRegClass);
3464 }
3465
3466 return ResultPair;
3467}
3468
3469bool
3471 // The Sparc target isn't yet aware of offsets.
3472 return false;
3473}
3474
3477 SelectionDAG &DAG) const {
3478
3479 SDLoc dl(N);
3480
3481 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3482
3483 switch (N->getOpcode()) {
3484 default:
3485 llvm_unreachable("Do not know how to custom type legalize this operation!");
3486
3487 case ISD::FP_TO_SINT:
3488 case ISD::FP_TO_UINT:
3489 // Custom lower only if it involves f128 or i64.
3490 if (N->getOperand(0).getValueType() != MVT::f128
3491 || N->getValueType(0) != MVT::i64)
3492 return;
3493 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3494 ? RTLIB::FPTOSINT_F128_I64
3495 : RTLIB::FPTOUINT_F128_I64);
3496
3497 Results.push_back(LowerF128Op(SDValue(N, 0),
3498 DAG,
3499 getLibcallName(libCall),
3500 1));
3501 return;
3502 case ISD::READCYCLECOUNTER: {
3503 assert(Subtarget->hasLeonCycleCounter());
3504 SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), dl, SP::ASR23, MVT::i32);
3505 SDValue Hi = DAG.getCopyFromReg(Lo, dl, SP::G0, MVT::i32);
3506 SDValue Ops[] = { Lo, Hi };
3507 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops);
3508 Results.push_back(Pair);
3509 Results.push_back(N->getOperand(0));
3510 return;
3511 }
3512 case ISD::SINT_TO_FP:
3513 case ISD::UINT_TO_FP:
3514 // Custom lower only if it involves f128 or i64.
3515 if (N->getValueType(0) != MVT::f128
3516 || N->getOperand(0).getValueType() != MVT::i64)
3517 return;
3518
3519 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3520 ? RTLIB::SINTTOFP_I64_F128
3521 : RTLIB::UINTTOFP_I64_F128);
3522
3523 Results.push_back(LowerF128Op(SDValue(N, 0),
3524 DAG,
3525 getLibcallName(libCall),
3526 1));
3527 return;
3528 case ISD::LOAD: {
3529 LoadSDNode *Ld = cast<LoadSDNode>(N);
3530 // Custom handling only for i64: turn i64 load into a v2i32 load,
3531 // and a bitcast.
3532 if (Ld->getValueType(0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64)
3533 return;
3534
3535 SDLoc dl(N);
3536 SDValue LoadRes = DAG.getExtLoad(
3537 Ld->getExtensionType(), dl, MVT::v2i32, Ld->getChain(),
3538 Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32,
3539 Ld->getOriginalAlign(), Ld->getMemOperand()->getFlags(),
3540 Ld->getAAInfo());
3541
3542 SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes);
3543 Results.push_back(Res);
3544 Results.push_back(LoadRes.getValue(1));
3545 return;
3546 }
3547 }
3548}
3549
3550// Override to enable LOAD_STACK_GUARD lowering on Linux.
3552 if (!Subtarget->isTargetLinux())
3554 return true;
3555}
3556
3557// Override to disable global variable loading on Linux.
3559 if (!Subtarget->isTargetLinux())
3561}
3562
3564 SDNode *Node) const {
3565 assert(MI.getOpcode() == SP::SUBCCrr || MI.getOpcode() == SP::SUBCCri);
3566 // If the result is dead, replace it with %g0.
3567 if (!Node->hasAnyUseOfValue(0))
3568 MI.getOperand(0).setReg(SP::G0);
3569}
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define RegName(no)
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG)
lazy value info
#define F(x, y, z)
Definition: MD5.cpp:55
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
Module.h This file contains the declarations for the Module class.
static CodeModel::Model getCodeModel(const PPCSubtarget &S, const TargetMachine &TM, const MachineOperand &MO)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget, bool AlwaysFlush=false)
static unsigned toCallerWindow(unsigned Reg)
static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG)
static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC)
intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC rcond condition.
static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
static void fixupVariableFloatArgs(SmallVectorImpl< CCValAssign > &ArgLocs, ArrayRef< ISD::OutputArg > Outs)
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC)
FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC FCC condition.
static bool isAnyArgRegReserved(const SparcRegisterInfo *TRI, const MachineFunction &MF)
static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG)
static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, const CallBase *Call)
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG, unsigned opcode)
static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)
static void emitReservedArgRegCallError(const MachineFunction &MF)
static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG)
static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)
static SDValue LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9)
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC)
static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
This file contains some functions that are useful when dealing with strings.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static bool is64Bit(const char *name)
Value * RHS
Value * LHS
Class for arbitrary precision integers.
Definition: APInt.h:78
This class represents an incoming formal argument to a Function.
Definition: Argument.h:31
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:696
BinOp getOperation() const
Definition: Instructions.h:787
LLVM Basic Block Representation.
Definition: BasicBlock.h:61
CCState - This class holds information needed while lowering arguments and return values.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
void addLoc(const CCValAssign &V)
CCValAssign - Represent assignment of one arg/retval to a location.
bool isRegLoc() const
Register getLocReg() const
LocInfo getLocInfo() const
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
bool needsCustom() const
bool isMemLoc() const
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
bool isExtInLoc() const
int64_t getLocMemOffset() const
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP)
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1236
This is the shared class of boolean and integer constants.
Definition: Constants.h:81
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:63
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:195
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:461
A debug info location.
Definition: DebugLoc.h:33
Diagnostic information for unsupported feature in backend.
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:686
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:743
const GlobalValue * getGlobal() const
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:656
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Machine Value Type.
static auto integer_fixedlen_vector_valuetypes()
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
Definition: MachineInstr.h:69
Flags getFlags() const
Return the raw flags of the source value,.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
Align getOriginalAlign() const
Returns alignment and volatility of the memory access.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
Definition: DerivedTypes.h:662
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool isUndef() const
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:226
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:736
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
Definition: SelectionDAG.h:567
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
Definition: SelectionDAG.h:842
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:487
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:488
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:787
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:690
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:782
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:482
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:813
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
LLVMContext * getContext() const
Definition: SelectionDAG.h:500
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:753
SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:570
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209