LLVM 17.0.0git
SparcISelLowering.h
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1//===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Sparc uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
15#define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
16
17#include "Sparc.h"
19
20namespace llvm {
21 class SparcSubtarget;
22
23 namespace SPISD {
24 enum NodeType : unsigned {
26 CMPICC, // Compare two GPR operands, set icc+xcc.
27 CMPFCC, // Compare two FP operands, set fcc.
28 CMPFCC_V9, // Compare two FP operands, set fcc (v9 variant).
29 BRICC, // Branch to dest on icc condition
30 BPICC, // Branch to dest on icc condition, with prediction (64-bit only).
31 BPXCC, // Branch to dest on xcc condition, with prediction (64-bit only).
32 BRFCC, // Branch to dest on fcc condition
33 BRFCC_V9, // Branch to dest on fcc condition (v9 variant).
34 SELECT_ICC, // Select between two values using the current ICC flags.
35 SELECT_XCC, // Select between two values using the current XCC flags.
36 SELECT_FCC, // Select between two values using the current FCC flags.
37 SELECT_REG, // Select between two values using the comparison of a register
38 // with zero.
39
41 Lo, // Hi/Lo operations, typically on a global address.
42
43 FTOI, // FP to Int within a FP register.
44 ITOF, // Int to FP within a FP register.
45 FTOX, // FP to Int64 within a FP register.
46 XTOF, // Int64 to FP within a FP register.
47
48 CALL, // A call instruction.
49 RET_FLAG, // Return with a flag operand.
50 GLOBAL_BASE_REG, // Global base reg for PIC.
51 FLUSHW, // FLUSH register windows to stack.
52
53 TAIL_CALL, // Tail call
54
55 TLS_ADD, // For Thread Local Storage (TLS).
58
59 LOAD_GDOP, // Load operation w/ gdop relocation.
60 };
61 }
62
64 const SparcSubtarget *Subtarget;
65 public:
67 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
68
69 bool useSoftFloat() const override;
70
71 /// computeKnownBitsForTargetNode - Determine which of the bits specified
72 /// in Mask are known to be either zero or one and return them in the
73 /// KnownZero/KnownOne bitsets.
75 KnownBits &Known,
76 const APInt &DemandedElts,
77 const SelectionDAG &DAG,
78 unsigned Depth = 0) const override;
79
82 MachineBasicBlock *MBB) const override;
83
84 const char *getTargetNodeName(unsigned Opcode) const override;
85
86 ConstraintType getConstraintType(StringRef Constraint) const override;
89 const char *constraint) const override;
91 std::string &Constraint,
92 std::vector<SDValue> &Ops,
93 SelectionDAG &DAG) const override;
94
95 std::pair<unsigned, const TargetRegisterClass *>
97 StringRef Constraint, MVT VT) const override;
98
99 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
100 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
101 return MVT::i32;
102 }
103
104 Register getRegisterByName(const char* RegName, LLT VT,
105 const MachineFunction &MF) const override;
106
107 /// If a physical register, this returns the register that receives the
108 /// exception address on entry to an EH pad.
110 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
111 return SP::I0;
112 }
113
114 /// If a physical register, this returns the register that receives the
115 /// exception typeid on entry to a landing pad.
117 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
118 return SP::I1;
119 }
120
121 /// Override to support customized stack guard loading.
122 bool useLoadStackGuardNode() const override;
123 void insertSSPDeclarations(Module &M) const override;
124
125 /// getSetCCResultType - Return the ISD::SETCC ValueType
127 EVT VT) const override;
128
129 SDValue
130 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
132 const SDLoc &dl, SelectionDAG &DAG,
133 SmallVectorImpl<SDValue> &InVals) const override;
135 bool isVarArg,
137 const SDLoc &dl, SelectionDAG &DAG,
138 SmallVectorImpl<SDValue> &InVals) const;
140 bool isVarArg,
142 const SDLoc &dl, SelectionDAG &DAG,
143 SmallVectorImpl<SDValue> &InVals) const;
144
145 SDValue
147 SmallVectorImpl<SDValue> &InVals) const override;
149 SmallVectorImpl<SDValue> &InVals) const;
151 SmallVectorImpl<SDValue> &InVals) const;
152
154 bool isVarArg,
156 LLVMContext &Context) const override;
157
158 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
160 const SmallVectorImpl<SDValue> &OutVals,
161 const SDLoc &dl, SelectionDAG &DAG) const override;
163 bool IsVarArg,
165 const SmallVectorImpl<SDValue> &OutVals,
166 const SDLoc &DL, SelectionDAG &DAG) const;
168 bool IsVarArg,
170 const SmallVectorImpl<SDValue> &OutVals,
171 const SDLoc &DL, SelectionDAG &DAG) const;
172
177
178 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
179 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
180 SelectionDAG &DAG) const;
181 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
182
184 const SDLoc &DL, SelectionDAG &DAG) const;
186 const char *LibFuncName,
187 unsigned numArgs) const;
189 const SDLoc &DL, SelectionDAG &DAG) const;
190
192
193 SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;
194
196 SelectionDAG &DAG) const;
197
198 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
199
201 CallLoweringInfo &CLI,
202 MachineFunction &MF) const;
203
204 bool ShouldShrinkFPConstant(EVT VT) const override {
205 // Do not shrink FP constpool if VT == MVT::f128.
206 // (ldd, call _Q_fdtoq) is more expensive than two ldds.
207 return VT != MVT::f128;
208 }
209
210 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
211 // FIXME: We insert fences for each atomics and generate
212 // sub-optimal code for PSO/TSO. (Approximately nobody uses any
213 // mode but TSO, which makes this even more silly)
214 return true;
215 }
216
218
221 SelectionDAG &DAG) const override;
222
224 unsigned BROpcode) const;
225 };
226} // end namespace llvm
227
228#endif // SPARC_ISELLOWERING_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Function Alias Analysis Results
IRTranslator LLVM IR MI
#define RegName(no)
lazy value info
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
Value * RHS
Value * LHS
Class for arbitrary precision integers.
Definition: APInt.h:75
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
CCState - This class holds information needed while lowering arguments and return values.
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:114
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:68
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
bool useSoftFloat() const override
SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL, SelectionDAG &DAG) const
MachineBasicBlock * expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, unsigned BROpcode) const
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
LowerFormalArguments32 - V8 uses a very simple ABI, where all values are passed in either one or two ...
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool IsEligibleForTailCallOptimization(CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg, const SDLoc &DL, SelectionDAG &DAG) const
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either ...
SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC, const SDLoc &DL, SelectionDAG &DAG) const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
std::vector< ArgListEntry > ArgListTy
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1311
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
#define N
Extended Value Type.
Definition: ValueTypes.h:34
This contains information for each constraint that we are lowering.
This structure contains all information that is necessary for lowering calls.