37 #define DEBUG_TYPE "msp430-lower" 41 cl::desc(
"Enable non legal immediates (for testing purposes only)"),
155 const char *
const Name;
199 { RTLIB::OEQ_F64,
"__mspabi_cmpd",
ISD::SETEQ },
200 { RTLIB::UNE_F64,
"__mspabi_cmpd",
ISD::SETNE },
201 { RTLIB::OGE_F64,
"__mspabi_cmpd",
ISD::SETGE },
202 { RTLIB::OLT_F64,
"__mspabi_cmpd",
ISD::SETLT },
203 { RTLIB::OLE_F64,
"__mspabi_cmpd",
ISD::SETLE },
204 { RTLIB::OGT_F64,
"__mspabi_cmpd",
ISD::SETGT },
205 { RTLIB::OEQ_F32,
"__mspabi_cmpf",
ISD::SETEQ },
206 { RTLIB::UNE_F32,
"__mspabi_cmpf",
ISD::SETNE },
207 { RTLIB::OGE_F32,
"__mspabi_cmpf",
ISD::SETGE },
208 { RTLIB::OLT_F32,
"__mspabi_cmpf",
ISD::SETLT },
209 { RTLIB::OLE_F32,
"__mspabi_cmpf",
ISD::SETLE },
210 { RTLIB::OGT_F32,
"__mspabi_cmpf",
ISD::SETGT },
248 for (
const auto &LC : LibraryCalls) {
257 const char *
const Name;
260 { RTLIB::MUL_I16,
"__mspabi_mpyi_hw" },
261 { RTLIB::MUL_I32,
"__mspabi_mpyl_hw" },
262 { RTLIB::MUL_I64,
"__mspabi_mpyll_hw" },
266 for (
const auto &LC : LibraryCalls) {
272 const char *
const Name;
275 { RTLIB::MUL_I16,
"__mspabi_mpyi_hw" },
276 { RTLIB::MUL_I32,
"__mspabi_mpyl_hw32" },
277 { RTLIB::MUL_I64,
"__mspabi_mpyll_hw32" },
281 for (
const auto &LC : LibraryCalls) {
287 const char *
const Name;
290 { RTLIB::MUL_I16,
"__mspabi_mpyi_f5hw" },
291 { RTLIB::MUL_I32,
"__mspabi_mpyl_f5hw" },
292 { RTLIB::MUL_I64,
"__mspabi_mpyll_f5hw" },
296 for (
const auto &LC : LibraryCalls) {
302 const char *
const Name;
305 { RTLIB::MUL_I16,
"__mspabi_mpyi" },
306 { RTLIB::MUL_I32,
"__mspabi_mpyl" },
307 { RTLIB::MUL_I64,
"__mspabi_mpyll" },
311 for (
const auto &LC : LibraryCalls) {
340 switch (
Op.getOpcode()) {
362 unsigned Amount)
const {
363 return !(Amount == 8 || Amount == 9 || Amount<=2);
370 return Immed >= -32 && Immed < 32;
382 if (Constraint.
size() == 1) {
383 switch (Constraint[0]) {
393 std::pair<unsigned, const TargetRegisterClass *>
396 if (Constraint.
size() == 1) {
398 switch (Constraint[0]) {
402 return std::make_pair(0U, &MSP430::GR8RegClass);
404 return std::make_pair(0U, &MSP430::GR16RegClass);
415 #include "MSP430GenCallingConv.inc" 419 template<
typename ArgT>
422 unsigned CurrentArgIndex;
427 CurrentArgIndex =
Args[0].OrigArgIndex;
431 if (CurrentArgIndex ==
Arg.OrigArgIndex) {
435 CurrentArgIndex =
Arg.OrigArgIndex;
454 template<
typename ArgT>
459 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
462 static const MCPhysReg BuiltinRegList[] = {
463 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
464 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
466 static const unsigned BuiltinNbRegs =
array_lengthof(BuiltinRegList);
473 RegList = BuiltinRegList;
474 NbRegs = BuiltinNbRegs;
490 "Builtin calling convention requires two arguments");
493 unsigned RegsLeft = NbRegs;
494 bool UsedStack =
false;
497 for (
unsigned i = 0,
e = ArgsParts.
size(); i !=
e; i++) {
508 else if (ArgFlags.
isZExt())
520 unsigned Parts = ArgsParts[i];
524 "Builtin calling convention requires 64-bit arguments");
527 if (!UsedStack && Parts == 2 && RegsLeft == 1) {
534 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
535 }
else if (Parts <= RegsLeft) {
536 for (
unsigned j = 0; j < Parts; j++) {
543 for (
unsigned j = 0; j < Parts; j++)
544 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
559 template<
typename ArgT>
566 SDValue MSP430TargetLowering::LowerFormalArguments(
576 return LowerCCCArguments(Chain, CallConv, isVarArg,
Ins, dl, DAG, InVals);
607 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
608 Outs, OutVals,
Ins, dl, DAG, InVals);
617 SDValue MSP430TargetLowering::LowerCCCArguments(
634 unsigned Offset = CCInfo.getNextStackOffset();
638 for (
unsigned i = 0,
e = ArgLocs.size(); i !=
e; ++i) {
647 errs() <<
"LowerFormalArguments Unhandled argument type: " 687 errs() <<
"LowerFormalArguments Unhandled argument type: " 706 for (
unsigned i = 0,
e = ArgLocs.size(); i !=
e; ++i) {
730 return CCInfo.CheckReturn(Outs, RetCC_MSP430);
760 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
769 Flag = Chain.getValue(1);
782 unsigned R12 = MSP430::R12;
785 Flag = Chain.getValue(1);
796 RetOps.push_back(
Flag);
803 SDValue MSP430TargetLowering::LowerCCCCallTo(
816 unsigned NumBytes = CCInfo.getNextStackOffset();
826 for (
unsigned i = 0,
e = ArgLocs.
size(); i !=
e; ++i) {
880 if (!MemOpChains.
empty())
887 for (
unsigned i = 0,
e = RegsToPass.
size(); i !=
e; ++i) {
888 Chain = DAG.
getCopyToReg(Chain, dl, RegsToPass[i].first,
889 RegsToPass[i].second, InFlag);
909 for (
unsigned i = 0,
e = RegsToPass.
size(); i !=
e; ++i)
911 RegsToPass[i].second.getValueType()));
926 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
Ins, dl,
933 SDValue MSP430TargetLowering::LowerCallResult(
946 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
948 RVLocs[i].getValVT(), InFlag).
getValue(1);
958 unsigned Opc =
Op.getOpcode();
960 EVT VT =
Op.getValueType();
964 if (!isa<ConstantSDNode>(
N->getOperand(1)))
967 uint64_t ShiftAmount = cast<ConstantSDNode>(
N->getOperand(1))->getZExtValue();
972 if (ShiftAmount >= 8) {
995 if (Opc ==
ISD::SRL && ShiftAmount) {
1002 while (ShiftAmount--)
1011 const GlobalValue *GV = cast<GlobalAddressSDNode>(
Op)->getGlobal();
1012 int64_t
Offset = cast<GlobalAddressSDNode>(
Op)->getOffset();
1023 const char *Sym = cast<ExternalSymbolSDNode>(
Op)->getSymbol();
1034 const BlockAddress *BA = cast<BlockAddressSDNode>(
Op)->getBlockAddress();
1071 RHS = DAG.
getConstant(
C->getSExtValue() + 1, dl,
C->getValueType(0));
1085 RHS = DAG.
getConstant(
C->getSExtValue() + 1, dl,
C->getValueType(0));
1099 RHS = DAG.
getConstant(
C->getSExtValue() + 1, dl,
C->getValueType(0));
1113 RHS = DAG.
getConstant(
C->getSExtValue() + 1, dl,
C->getValueType(0));
1138 Chain, Dest, TargetCC,
Flag);
1153 if (RHSC->isNullValue() && LHS.
hasOneUse() &&
1168 bool Invert =
false;
1170 bool Convert =
true;
1171 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
1197 EVT VT =
Op.getValueType();
1236 EVT VT =
Op.getValueType();
1250 int ReturnAddrIndex = FuncInfo->
getRAIndex();
1253 if (ReturnAddrIndex == 0) {
1272 unsigned Depth = cast<ConstantSDNode>(
Op.getOperand(0))->getZExtValue();
1296 EVT VT =
Op.getValueType();
1298 unsigned Depth = cast<ConstantSDNode>(
Op.getOperand(0))->getZExtValue();
1316 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
1334 bool MSP430TargetLowering::getPostIndexedAddressParts(
SDNode *
N,
SDNode *
Op,
1344 EVT VT =
LD->getMemoryVT();
1352 uint64_t RHSC = RHS->getZExtValue();
1353 if ((VT ==
MVT::i16 && RHSC != 2) ||
1357 Base =
Op->getOperand(0);
1430 bool ClearCarry =
false;
1432 switch (
MI.getOpcode()) {
1435 Opc = MSP430::ADD8rr;
1436 RC = &MSP430::GR8RegClass;
1439 Opc = MSP430::ADD16rr;
1440 RC = &MSP430::GR16RegClass;
1443 Opc = MSP430::RRA8r;
1444 RC = &MSP430::GR8RegClass;
1447 Opc = MSP430::RRA16r;
1448 RC = &MSP430::GR16RegClass;
1452 Opc = MSP430::RRC8r;
1453 RC = &MSP430::GR8RegClass;
1457 Opc = MSP430::RRC16r;
1458 RC = &MSP430::GR16RegClass;
1461 case MSP430::Rrcl16: {
1462 BuildMI(*BB,
MI, dl,
TII.get(MSP430::BIC16rc), MSP430::SR)
1463 .addReg(MSP430::SR).
addImm(1);
1466 unsigned RrcOpc =
MI.getOpcode() == MSP430::Rrcl16
1467 ? MSP430::RRC16r : MSP430::RRC8r;
1470 MI.eraseFromParent();
1482 F->insert(
I, LoopBB);
1483 F->insert(
I, RemBB);
1501 Register ShiftAmtSrcReg =
MI.getOperand(2).getReg();
1509 .addReg(ShiftAmtSrcReg).
addImm(0);
1519 BuildMI(LoopBB, dl,
TII.get(MSP430::PHI), ShiftReg)
1520 .addReg(SrcReg).
addMBB(BB)
1522 BuildMI(LoopBB, dl,
TII.get(MSP430::PHI), ShiftAmtReg)
1523 .addReg(ShiftAmtSrcReg).
addMBB(BB)
1526 BuildMI(LoopBB, dl,
TII.get(MSP430::BIC16rc), MSP430::SR)
1527 .addReg(MSP430::SR).
addImm(1);
1528 if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr)
1535 BuildMI(LoopBB, dl,
TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1536 .addReg(ShiftAmtReg).
addImm(1);
1544 .addReg(SrcReg).
addMBB(BB)
1547 MI.eraseFromParent();
1554 unsigned Opc =
MI.getOpcode();
1556 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1557 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1558 Opc == MSP430::Srl8 || Opc == MSP430::Srl16 ||
1559 Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16)
1565 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1566 "Unexpected instr type to insert");
1585 F->insert(
I, copy0MBB);
1586 F->insert(
I, copy1MBB);
1598 .
addImm(
MI.getOperand(3).getImm());
1613 .addReg(
MI.getOperand(2).getReg())
1618 MI.eraseFromParent();
void setFrameAddressIsTaken(bool T)
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
EVT getValueType() const
Return the ValueType of the referenced return value.
int getVarArgsFrameIndex() const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
void setRAIndex(int Index)
Return with a flag operand. Operand 0 is the chain operand.
MSP430MachineFunctionInfo - This class is derived from MachineFunction and contains private MSP430 ta...
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
BR_CC - Conditional branch.
This class represents lattice values for constants.
Register getLocReg() const
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
MSP430 conditional branches.
LLVM_NODISCARD bool empty() const
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
DADD - Decimal addition with carry TODO Nothing generates a node of this type yet.
void push_back(const T &Elt)
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Y = RRC X, rotate right via carry.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
ScalarTy getFixedSize() const
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Register getSRetReturnReg() const
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
static void AnalyzeVarArgs(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs)
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override
Return true if creating a shift of the type by the given amount is not profitable.
static void ParseFunctionArgs(const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Function & getFunction()
Return the LLVM function that this machine code represents.
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
const TargetRegisterInfo * getRegisterInfo() const override
const HexagonInstrInfo * TII
Shift and rotation operations.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void addLoc(const CCValAssign &V)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Rotate right via carry, carry gets cleared beforehand by clrc.
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
LocInfo getLocInfo() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Same as RET_FLAG, but used for returning from ISRs.
MachineFunction & getMachineFunction() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void setVarArgsFrameIndex(int Index)
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Simple integer binary arithmetic operators.
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
LLVM_NODISCARD size_t size() const
size - Get the string size.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
virtual const TargetInstrInfo * getInstrInfo() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getByValSize() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
TargetInstrInfo - Interface to description of machine instruction set.
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
void setSRetReturnReg(Register Reg)
LLVM Basic Block Representation.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed.
This is an important class for using LLVM in a threaded context.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Fast - This calling convention attempts to make calls as fast as possible (e.g.
void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, Align MinAlign, ISD::ArgFlagsTy ArgFlags)
Allocate space on the stack large enough to pass an argument by value.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
self_iterator getIterator()
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This class contains a discriminated union of information about pointers in memory operands,...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
static cl::opt< bool > MSP430NoLegalImmediate("msp430-no-legal-immediate", cl::Hidden, cl::desc("Enable non legal immediates (for testing purposes only)"), cl::init(false))
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero.
TokenFactor - This node takes multiple tokens as input and produces a single token result.
CCState - This class holds information needed while lowering arguments and return values.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
CMP - Compare instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Align getNonZeroByValAlign() const
CCValAssign - Represent assignment of one arg/retval to a location.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
BRCOND - Conditional branch.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
CallingConv::ID getCallingConv() const
Byte Swap and Counting operators.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
static void AnalyzeRetResult(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins)
amdgpu Simplify well known AMD library false FunctionCallee Callee
Select(COND, TRUEVAL, FALSEVAL).
ZERO_EXTEND - Used for integer types, zeroing the new bits.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
BR_JT - Jumptable branch.
Representation of each machine instruction.
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
MSP430_INTR - Calling convention used for MSP430 interrupt routines.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SmallVector< SDValue, 32 > OutVals
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
static void AnalyzeArguments(CCState &State, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgT > &Args)
Analyze incoming and outgoing function arguments.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Calling convention used for special MSP430 rtlib functions which have an "optimized" convention using...
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
SDValue getValue(unsigned R) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
SmallVector< MachineOperand, 4 > Cond
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Y = R{R,L}A X, rotate right (left) arithmetically.
void setReturnAddressIsTaken(bool s)
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
LLVM Value Representation.
SDValue getRegister(unsigned Reg, EVT VT)
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
SDValue getValueType(EVT)
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
SetCC operator - This evaluates to a true value iff the condition is true.
const SDValue & getOperand(unsigned i) const
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
TRUNCATE - Completely drop the high bits.
static void AnalyzeReturnValues(CCState &State, SmallVectorImpl< CCValAssign > &RVLocs, const SmallVectorImpl< ArgT > &Args)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
LLVMContext * getContext() const
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
C - The default llvm calling convention, compatible with C.
Wrapper class representing virtual and physical registers.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.