Go to the documentation of this file.
37 #define DEBUG_TYPE "msp430-lower"
41 cl::desc(
"Enable non legal immediates (for testing purposes only)"),
155 const char *
const Name;
199 { RTLIB::OEQ_F64,
"__mspabi_cmpd",
ISD::SETEQ },
200 { RTLIB::UNE_F64,
"__mspabi_cmpd",
ISD::SETNE },
201 { RTLIB::OGE_F64,
"__mspabi_cmpd",
ISD::SETGE },
202 { RTLIB::OLT_F64,
"__mspabi_cmpd",
ISD::SETLT },
203 { RTLIB::OLE_F64,
"__mspabi_cmpd",
ISD::SETLE },
204 { RTLIB::OGT_F64,
"__mspabi_cmpd",
ISD::SETGT },
205 { RTLIB::OEQ_F32,
"__mspabi_cmpf",
ISD::SETEQ },
206 { RTLIB::UNE_F32,
"__mspabi_cmpf",
ISD::SETNE },
207 { RTLIB::OGE_F32,
"__mspabi_cmpf",
ISD::SETGE },
208 { RTLIB::OLT_F32,
"__mspabi_cmpf",
ISD::SETLT },
209 { RTLIB::OLE_F32,
"__mspabi_cmpf",
ISD::SETLE },
210 { RTLIB::OGT_F32,
"__mspabi_cmpf",
ISD::SETGT },
248 for (
const auto &LC : LibraryCalls) {
257 const char *
const Name;
260 { RTLIB::MUL_I16,
"__mspabi_mpyi_hw" },
261 { RTLIB::MUL_I32,
"__mspabi_mpyl_hw" },
262 { RTLIB::MUL_I64,
"__mspabi_mpyll_hw" },
266 for (
const auto &LC : LibraryCalls) {
272 const char *
const Name;
275 { RTLIB::MUL_I16,
"__mspabi_mpyi_hw" },
276 { RTLIB::MUL_I32,
"__mspabi_mpyl_hw32" },
277 { RTLIB::MUL_I64,
"__mspabi_mpyll_hw32" },
281 for (
const auto &LC : LibraryCalls) {
287 const char *
const Name;
290 { RTLIB::MUL_I16,
"__mspabi_mpyi_f5hw" },
291 { RTLIB::MUL_I32,
"__mspabi_mpyl_f5hw" },
292 { RTLIB::MUL_I64,
"__mspabi_mpyll_f5hw" },
296 for (
const auto &LC : LibraryCalls) {
302 const char *
const Name;
305 { RTLIB::MUL_I16,
"__mspabi_mpyi" },
306 { RTLIB::MUL_I32,
"__mspabi_mpyl" },
307 { RTLIB::MUL_I64,
"__mspabi_mpyll" },
311 for (
const auto &LC : LibraryCalls) {
340 switch (
Op.getOpcode()) {
362 unsigned Amount)
const {
363 return !(Amount == 8 || Amount == 9 || Amount<=2);
370 return Immed >= -32 && Immed < 32;
382 if (Constraint.
size() == 1) {
383 switch (Constraint[0]) {
393 std::pair<unsigned, const TargetRegisterClass *>
396 if (Constraint.
size() == 1) {
398 switch (Constraint[0]) {
402 return std::make_pair(0U, &MSP430::GR8RegClass);
404 return std::make_pair(0U, &MSP430::GR16RegClass);
415 #include "MSP430GenCallingConv.inc"
419 template<
typename ArgT>
422 unsigned CurrentArgIndex;
427 CurrentArgIndex =
Args[0].OrigArgIndex;
431 if (CurrentArgIndex ==
Arg.OrigArgIndex) {
435 CurrentArgIndex =
Arg.OrigArgIndex;
454 template<
typename ArgT>
459 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
462 static const MCPhysReg BuiltinRegList[] = {
463 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
464 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
466 static const unsigned BuiltinNbRegs =
array_lengthof(BuiltinRegList);
473 RegList = BuiltinRegList;
474 NbRegs = BuiltinNbRegs;
489 assert(ArgsParts.size() == 2 &&
490 "Builtin calling convention requires two arguments");
493 unsigned RegsLeft = NbRegs;
494 bool UsedStack =
false;
497 for (
unsigned i = 0,
e = ArgsParts.size();
i !=
e;
i++) {
508 else if (ArgFlags.
isZExt())
520 unsigned Parts = ArgsParts[
i];
524 "Builtin calling convention requires 64-bit arguments");
527 if (!UsedStack && Parts == 2 && RegsLeft == 1) {
534 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
535 }
else if (Parts <= RegsLeft) {
536 for (
unsigned j = 0;
j < Parts;
j++) {
543 for (
unsigned j = 0;
j < Parts;
j++)
544 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
559 template<
typename ArgT>
566 SDValue MSP430TargetLowering::LowerFormalArguments(
576 return LowerCCCArguments(Chain, CallConv, isVarArg,
Ins, dl, DAG, InVals);
607 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
608 Outs, OutVals,
Ins, dl, DAG, InVals);
617 SDValue MSP430TargetLowering::LowerCCCArguments(
634 unsigned Offset = CCInfo.getNextStackOffset();
638 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
647 errs() <<
"LowerFormalArguments Unhandled argument type: "
670 InVals.push_back(ArgValue);
688 errs() <<
"LowerFormalArguments Unhandled argument type: "
703 InVals.push_back(InVal);
707 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
731 return CCInfo.CheckReturn(Outs, RetCC_MSP430);
761 for (
unsigned i = 0;
i != RVLocs.size(); ++
i) {
784 unsigned R12 = MSP430::R12;
798 RetOps.push_back(
Flag);
805 SDValue MSP430TargetLowering::LowerCCCCallTo(
818 unsigned NumBytes = CCInfo.getNextStackOffset();
828 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
851 RegsToPass.push_back(std::make_pair(VA.
getLocReg(),
Arg));
876 MemOpChains.push_back(
MemOp);
882 if (!MemOpChains.empty())
889 for (
unsigned i = 0,
e = RegsToPass.size();
i !=
e; ++
i) {
891 RegsToPass[
i].second, InFlag);
906 Ops.push_back(Chain);
907 Ops.push_back(Callee);
911 for (
unsigned i = 0,
e = RegsToPass.size();
i !=
e; ++
i)
913 RegsToPass[
i].second.getValueType()));
916 Ops.push_back(InFlag);
928 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
Ins, dl,
935 SDValue MSP430TargetLowering::LowerCallResult(
948 for (
unsigned i = 0;
i != RVLocs.size(); ++
i) {
950 RVLocs[
i].getValVT(), InFlag).
getValue(1);
952 InVals.push_back(Chain.
getValue(0));
960 unsigned Opc =
Op.getOpcode();
962 EVT VT =
Op.getValueType();
966 if (!isa<ConstantSDNode>(
N->getOperand(1)))
969 uint64_t ShiftAmount = cast<ConstantSDNode>(
N->getOperand(1))->getZExtValue();
974 if (ShiftAmount >= 8) {
997 if (Opc ==
ISD::SRL && ShiftAmount) {
1004 while (ShiftAmount--)
1013 const GlobalValue *GV = cast<GlobalAddressSDNode>(
Op)->getGlobal();
1014 int64_t Offset = cast<GlobalAddressSDNode>(
Op)->getOffset();
1015 EVT PtrVT =
Op.getValueType();
1025 const char *Sym = cast<ExternalSymbolSDNode>(
Op)->getSymbol();
1026 EVT PtrVT =
Op.getValueType();
1035 const BlockAddress *BA = cast<BlockAddressSDNode>(
Op)->getBlockAddress();
1036 EVT PtrVT =
Op.getValueType();
1045 assert(!
LHS.getValueType().isFloatingPoint() &&
"We don't handle FP yet");
1140 Chain, Dest, TargetCC,
Flag);
1170 bool Invert =
false;
1172 bool Convert =
true;
1173 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
1199 EVT VT =
Op.getValueType();
1238 EVT VT =
Op.getValueType();
1252 int ReturnAddrIndex = FuncInfo->
getRAIndex();
1255 if (ReturnAddrIndex == 0) {
1274 unsigned Depth = cast<ConstantSDNode>(
Op.getOperand(0))->getZExtValue();
1276 EVT PtrVT =
Op.getValueType();
1298 EVT VT =
Op.getValueType();
1300 unsigned Depth = cast<ConstantSDNode>(
Op.getOperand(0))->getZExtValue();
1315 EVT PtrVT = Ptr.getValueType();
1320 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
1330 EVT PtrVT =
Op.getValueType();
1338 bool MSP430TargetLowering::getPostIndexedAddressParts(
SDNode *
N,
SDNode *
Op,
1348 EVT VT =
LD->getMemoryVT();
1357 if ((VT ==
MVT::i16 && RHSC != 2) ||
1361 Base =
Op->getOperand(0);
1434 bool ClearCarry =
false;
1436 switch (
MI.getOpcode()) {
1439 Opc = MSP430::ADD8rr;
1440 RC = &MSP430::GR8RegClass;
1443 Opc = MSP430::ADD16rr;
1444 RC = &MSP430::GR16RegClass;
1447 Opc = MSP430::RRA8r;
1448 RC = &MSP430::GR8RegClass;
1451 Opc = MSP430::RRA16r;
1452 RC = &MSP430::GR16RegClass;
1456 Opc = MSP430::RRC8r;
1457 RC = &MSP430::GR8RegClass;
1461 Opc = MSP430::RRC16r;
1462 RC = &MSP430::GR16RegClass;
1465 case MSP430::Rrcl16: {
1470 unsigned RrcOpc =
MI.getOpcode() == MSP430::Rrcl16
1471 ? MSP430::RRC16r : MSP430::RRC8r;
1474 MI.eraseFromParent();
1486 F->insert(
I, LoopBB);
1487 F->insert(
I, RemBB);
1496 BB->addSuccessor(LoopBB);
1497 BB->addSuccessor(RemBB);
1505 Register ShiftAmtSrcReg =
MI.getOperand(2).getReg();
1523 BuildMI(LoopBB, dl,
TII.get(MSP430::PHI), ShiftReg)
1526 BuildMI(LoopBB, dl,
TII.get(MSP430::PHI), ShiftAmtReg)
1530 BuildMI(LoopBB, dl,
TII.get(MSP430::BIC16rc), MSP430::SR)
1532 if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr)
1539 BuildMI(LoopBB, dl,
TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1551 MI.eraseFromParent();
1558 unsigned Opc =
MI.getOpcode();
1560 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1561 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1562 Opc == MSP430::Srl8 || Opc == MSP430::Srl16 ||
1563 Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16)
1569 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1570 "Unexpected instr type to insert");
1589 F->insert(
I, copy0MBB);
1590 F->insert(
I, copy1MBB);
1597 BB->addSuccessor(copy0MBB);
1598 BB->addSuccessor(copy1MBB);
1602 .
addImm(
MI.getOperand(3).getImm());
1610 BB->addSuccessor(copy1MBB);
1616 BuildMI(*
BB,
BB->begin(), dl,
TII.get(MSP430::PHI),
MI.getOperand(0).getReg())
1622 MI.eraseFromParent();
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
@ RRC
Y = RRC X, rotate right via carry.
@ SETCC
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
@ CALL
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
bool hasOneUse() const
Return true if there is exactly one use of this value.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void setReturnAddressIsTaken(bool s)
@ BR_JT
BR_JT - Jumptable branch.
CCState - This class holds information needed while lowering arguments and return values.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
ScalarTy getFixedSize() const
SDNode * getNode() const
get the SDNode which holds the desired result
@ BSWAP
Byte Swap and Counting operators.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
SDValue getValueType(EVT)
void addLoc(const CCValAssign &V)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ MSP430_BUILTIN
Calling convention used for special MSP430 rtlib functions which have an "optimized" convention using...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Reg
All possible values of the reg field in the ModR/M byte.
void setVarArgsFrameIndex(int Index)
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Represents one node in the SelectionDAG.
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
This class is used to represent ISD::LOAD nodes.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
The instances of the Type class are immutable: once they are created, they are never changed.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG)
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
static void AnalyzeArguments(CCState &State, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgT > &Args)
Analyze incoming and outgoing function arguments.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
unsigned const TargetRegisterInfo * TRI
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
LLVMContext * getContext() const
@ BRCOND
BRCOND - Conditional branch.
bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override
Return true if creating a shift of the type by the given amount is not profitable.
SDValue getRegister(unsigned Reg, EVT VT)
LLVM Basic Block Representation.
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
MSP430MachineFunctionInfo - This class is derived from MachineFunction and contains private MSP430 ta...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static auto integer_valuetypes()
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
@ BR_CC
BR_CC - Conditional branch.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
static cl::opt< bool > MSP430NoLegalImmediate("msp430-no-legal-immediate", cl::Hidden, cl::desc("Enable non legal immediates (for testing purposes only)"), cl::init(false))
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
TargetInstrInfo - Interface to description of machine instruction set.
EVT getValueType() const
Return the ValueType of the referenced return value.
CCValAssign - Represent assignment of one arg/retval to a location.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
const TargetRegisterInfo * getRegisterInfo() const override
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Register getLocReg() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
(vector float) vec_cmpeq(*A, *B) C
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
static void AnalyzeReturnValues(CCState &State, SmallVectorImpl< CCValAssign > &RVLocs, const SmallVectorImpl< ArgT > &Args)
const HexagonInstrInfo * TII
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
static void AnalyzeRetResult(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
@ AND
Bitwise operators - logical and, logical or, logical xor.
LocInfo getLocInfo() const
unsigned getLocMemOffset() const
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
@ RRA
Y = R{R,L}A X, rotate right (left) arithmetically.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
bool isIntegerTy() const
True if this is an instance of IntegerType.
SmallVector< ISD::OutputArg, 32 > Outs
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
@ CMP
CMP - Compare instruction.
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
@ SELECT_CC
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
Representation of each machine instruction.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
This class contains a discriminated union of information about pointers in memory operands,...
This is an important class for using LLVM in a threaded context.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
initializer< Ty > init(const Ty &Val)
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
CallingConv::ID getCallingConv() const
int getVarArgsFrameIndex() const
SDValue getValue(unsigned R) const
This structure contains all information that is necessary for lowering calls.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
@ RET_FLAG
Return with a flag operand. Operand 0 is the chain operand.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
@ C
C - The default llvm calling convention, compatible with C.
SmallVector< ISD::InputArg, 32 > Ins
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
The address of a basic block.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
SmallVector< MachineOperand, 4 > Cond
StringRef - Represent a constant reference to a string, i.e.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
Register getSRetReturnReg() const
Wrapper class representing virtual and physical registers.
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
amdgpu Simplify well known AMD library false FunctionCallee Callee
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
@ Wrapper
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
unsigned getByValSize() const
@ RRCL
Rotate right via carry, carry gets cleared beforehand by clrc.
static void AnalyzeVarArgs(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs)
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Function & getFunction()
Return the LLVM function that this machine code represents.
Iterator for intrusive lists based on ilist_node.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
static void ParseFunctionArgs(const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
const DataLayout & getDataLayout() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
@ ZeroOrOneBooleanContent
void setSRetReturnReg(Register Reg)
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, Align MinAlign, ISD::ArgFlagsTy ArgFlags)
Allocate space on the stack large enough to pass an argument by value.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ ADD
Simple integer binary arithmetic operators.
void setRAIndex(int Index)
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
@ SHL
Shift and rotation operations.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Align getNonZeroByValAlign() const
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
@ BR_CC
MSP430 conditional branches.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
@ MSP430_INTR
MSP430_INTR - Calling convention used for MSP430 interrupt routines.
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
SmallVector< SDValue, 32 > OutVals
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const char LLVMTargetMachineRef TM
MachineFunction & getMachineFunction() const
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ RETI_FLAG
Same as RET_FLAG, but used for returning from ISRs.
void setFrameAddressIsTaken(bool T)
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
@ SIGN_EXTEND
Conversion operators.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
@ DADD
DADD - Decimal addition with carry TODO Nothing generates a node of this type yet.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
LLVM Value Representation.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.