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MSP430ISelLowering.h
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1 //===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that MSP430 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
15 #define LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
16 
17 #include "MSP430.h"
20 
21 namespace llvm {
22  namespace MSP430ISD {
23  enum NodeType : unsigned {
25 
26  /// Return with a flag operand. Operand 0 is the chain operand.
28 
29  /// Same as RET_FLAG, but used for returning from ISRs.
31 
32  /// Y = R{R,L}A X, rotate right (left) arithmetically
33  RRA, RLA,
34 
35  /// Y = RRC X, rotate right via carry
36  RRC,
37 
38  /// Rotate right via carry, carry gets cleared beforehand by clrc
40 
41  /// CALL - These operations represent an abstract call
42  /// instruction, which includes a bunch of information.
44 
45  /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
46  /// and TargetGlobalAddress.
48 
49  /// CMP - Compare instruction.
50  CMP,
51 
52  /// SetCC - Operand 0 is condition code, and operand 1 is the flag
53  /// operand produced by a CMP instruction.
55 
56  /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
57  /// is the block to branch if condition is true, operand 2 is the
58  /// condition code, and operand 3 is the flag operand produced by a CMP
59  /// instruction.
61 
62  /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
63  /// is condition code and operand 4 is flag operand.
65 
66  /// DADD - Decimal addition with carry
67  /// TODO Nothing generates a node of this type yet.
69  };
70  }
71 
72  class MSP430Subtarget;
74  public:
75  explicit MSP430TargetLowering(const TargetMachine &TM,
76  const MSP430Subtarget &STI);
77 
78  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
79  return MVT::i8;
80  }
81 
83  return MVT::i16;
84  }
85 
86  /// LowerOperation - Provide custom lowering hooks for some operations.
87  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
88 
89  /// getTargetNodeName - This method returns the name of a target specific
90  /// DAG node.
91  const char *getTargetNodeName(unsigned Opcode) const override;
92 
106 
108  getConstraintType(StringRef Constraint) const override;
109  std::pair<unsigned, const TargetRegisterClass *>
111  StringRef Constraint, MVT VT) const override;
112 
113  /// isTruncateFree - Return true if it's free to truncate a value of type
114  /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
115  /// register R15W to i8 by referencing its sub-register R15B.
116  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
117  bool isTruncateFree(EVT VT1, EVT VT2) const override;
118 
119  /// isZExtFree - Return true if any actual instruction that defines a value
120  /// of type Ty1 implicit zero-extends the value to Ty2 in the result
121  /// register. This does not necessarily include registers defined in unknown
122  /// ways, such as incoming arguments, or copies from unknown virtual
123  /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
124  /// necessarily apply to truncate instructions. e.g. on msp430, all
125  /// instructions that define 8-bit values implicit zero-extend the result
126  /// out to 16 bits.
127  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
128  bool isZExtFree(EVT VT1, EVT VT2) const override;
129  bool isZExtFree(SDValue Val, EVT VT2) const override;
130 
131  bool isLegalICmpImmediate(int64_t) const override;
132  bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override;
133 
136  MachineBasicBlock *BB) const override;
138  MachineBasicBlock *BB) const;
139 
140  private:
141  SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
142  CallingConv::ID CallConv, bool isVarArg,
143  bool isTailCall,
145  const SmallVectorImpl<SDValue> &OutVals,
147  const SDLoc &dl, SelectionDAG &DAG,
148  SmallVectorImpl<SDValue> &InVals) const;
149 
150  SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
151  bool isVarArg,
153  const SDLoc &dl, SelectionDAG &DAG,
154  SmallVectorImpl<SDValue> &InVals) const;
155 
156  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
157  CallingConv::ID CallConv, bool isVarArg,
159  const SDLoc &dl, SelectionDAG &DAG,
160  SmallVectorImpl<SDValue> &InVals) const;
161 
162  SDValue
163  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
165  const SDLoc &dl, SelectionDAG &DAG,
166  SmallVectorImpl<SDValue> &InVals) const override;
167  SDValue
168  LowerCall(TargetLowering::CallLoweringInfo &CLI,
169  SmallVectorImpl<SDValue> &InVals) const override;
170 
171  bool CanLowerReturn(CallingConv::ID CallConv,
172  MachineFunction &MF,
173  bool IsVarArg,
175  LLVMContext &Context) const override;
176 
177  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
179  const SmallVectorImpl<SDValue> &OutVals,
180  const SDLoc &dl, SelectionDAG &DAG) const override;
181 
182  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
183  SDValue &Base,
184  SDValue &Offset,
186  SelectionDAG &DAG) const override;
187  };
188 } // namespace llvm
189 
190 #endif
llvm::MSP430TargetLowering::LowerGlobalAddress
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1009
llvm::MSP430ISD::RRC
@ RRC
Y = RRC X, rotate right via carry.
Definition: MSP430ISelLowering.h:36
llvm::MSP430ISD::SETCC
@ SETCC
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction.
Definition: MSP430ISelLowering.h:54
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1315
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::MSP430ISD::CALL
@ CALL
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
Definition: MSP430ISelLowering.h:43
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1085
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4222
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::MSP430TargetLowering::LowerSIGN_EXTEND
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1233
llvm::MSP430TargetLowering::LowerVASTART
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1307
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MSP430TargetLowering::isZExtFree
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
Definition: MSP430ISelLowering.cpp:1403
llvm::MSP430TargetLowering
Definition: MSP430ISelLowering.h:73
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::MSP430TargetLowering::shouldAvoidTransformToShift
bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override
Return true if creating a shift of the type by the given amount is not profitable.
Definition: MSP430ISelLowering.cpp:361
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:33
llvm::MSP430TargetLowering::MSP430TargetLowering
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
Definition: MSP430ISelLowering.cpp:44
TargetLowering.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::MSP430TargetLowering::LowerExternalSymbol
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1020
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3254
llvm::MSP430TargetLowering::LowerSETCC
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1141
llvm::MSP430Subtarget
Definition: MSP430Subtarget.h:31
llvm::MSP430TargetLowering::EmitShiftInstr
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: MSP430ISelLowering.cpp:1422
llvm::MSP430TargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: MSP430ISelLowering.h:78
llvm::MSP430ISD::RRA
@ RRA
Y = R{R,L}A X, rotate right (left) arithmetically.
Definition: MSP430ISelLowering.h:33
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MSP430TargetLowering::getCmpLibcallReturnType
MVT::SimpleValueType getCmpLibcallReturnType() const override
Return the ValueType for comparison libcalls.
Definition: MSP430ISelLowering.h:82
llvm::MSP430ISD::CMP
@ CMP
CMP - Compare instruction.
Definition: MSP430ISelLowering.h:50
llvm::MSP430ISD::SELECT_CC
@ SELECT_CC
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
Definition: MSP430ISelLowering.h:64
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MSP430TargetLowering::LowerBlockAddress
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1030
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3812
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::MSP430TargetLowering::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: MSP430ISelLowering.cpp:1387
llvm::MSP430TargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: MSP430ISelLowering.cpp:368
llvm::MSP430TargetLowering::LowerBR_CC
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1126
llvm::MSP430ISD::RET_FLAG
@ RET_FLAG
Return with a flag operand. Operand 0 is the chain operand.
Definition: MSP430ISelLowering.h:27
llvm::MSP430TargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: MSP430ISelLowering.cpp:1552
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MSP430TargetLowering::LowerFRAMEADDR
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1291
llvm::MSP430TargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
Definition: MSP430ISelLowering.cpp:338
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MSP430ISD::RLA
@ RLA
Definition: MSP430ISelLowering.h:33
MSP430.h
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1249
llvm::MSP430TargetLowering::getReturnAddressFrameIndex
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1247
llvm::MSP430TargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
Definition: MSP430ISelLowering.cpp:1367
llvm::MSP430TargetLowering::getConstraintType
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: MSP430ISelLowering.cpp:381
llvm::MSP430ISD::Wrapper
@ Wrapper
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Definition: MSP430ISelLowering.h:47
llvm::MSP430ISD::RRCL
@ RRCL
Rotate right via carry, carry gets cleared beforehand by clrc.
Definition: MSP430ISelLowering.h:39
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::MSP430ISD::NodeType
NodeType
Definition: MSP430ISelLowering.h:23
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::MSP430TargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: MSP430ISelLowering.cpp:394
llvm::MSP430ISD::BR_CC
@ BR_CC
MSP430 conditional branches.
Definition: MSP430ISelLowering.h:60
N
#define N
llvm::MSP430TargetLowering::LowerJumpTable
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1323
llvm::MSP430TargetLowering::LowerShifts
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:956
llvm::MSP430TargetLowering::LowerSELECT_CC
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1216
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::MSP430TargetLowering::LowerRETURNADDR
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1264
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MSP430ISD::RETI_FLAG
@ RETI_FLAG
Same as RET_FLAG, but used for returning from ISRs.
Definition: MSP430ISelLowering.h:30
llvm::MSP430ISD::DADD
@ DADD
DADD - Decimal addition with carry TODO Nothing generates a node of this type yet.
Definition: MSP430ISelLowering.h:68
llvm::MSP430ISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: MSP430ISelLowering.h:24
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58