LLVM  17.0.0git
PPCFastISel.cpp
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1 //===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the PowerPC-specific support for the FastISel class. Some
10 // of the target-specific code is generated by tablegen in the file
11 // PPCGenFastISel.inc, which is #included here.
12 //
13 //===----------------------------------------------------------------------===//
14 
16 #include "PPC.h"
17 #include "PPCCCState.h"
18 #include "PPCCallingConv.h"
19 #include "PPCISelLowering.h"
20 #include "PPCMachineFunctionInfo.h"
21 #include "PPCSubtarget.h"
22 #include "PPCTargetMachine.h"
24 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/GlobalAlias.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/IR/IntrinsicInst.h"
36 #include "llvm/IR/Operator.h"
37 #include "llvm/Support/Debug.h"
39 
40 //===----------------------------------------------------------------------===//
41 //
42 // TBD:
43 // fastLowerArguments: Handle simple cases.
44 // PPCMaterializeGV: Handle TLS.
45 // SelectCall: Handle function pointers.
46 // SelectCall: Handle multi-register return values.
47 // SelectCall: Optimize away nops for local calls.
48 // processCallArgs: Handle bit-converted arguments.
49 // finishCall: Handle multi-register return values.
50 // PPCComputeAddress: Handle parameter references as FrameIndex's.
51 // PPCEmitCmp: Handle immediate as operand 1.
52 // SelectCall: Handle small byval arguments.
53 // SelectIntrinsicCall: Implement.
54 // SelectSelect: Implement.
55 // Consider factoring isTypeLegal into the base class.
56 // Implement switches and jump tables.
57 //
58 //===----------------------------------------------------------------------===//
59 using namespace llvm;
60 
61 #define DEBUG_TYPE "ppcfastisel"
62 
63 namespace {
64 
65 struct Address {
66  enum {
67  RegBase,
68  FrameIndexBase
69  } BaseType;
70 
71  union {
72  unsigned Reg;
73  int FI;
74  } Base;
75 
76  int64_t Offset;
77 
78  // Innocuous defaults for our address.
79  Address()
80  : BaseType(RegBase), Offset(0) {
81  Base.Reg = 0;
82  }
83 };
84 
85 class PPCFastISel final : public FastISel {
86 
87  const TargetMachine &TM;
88  const PPCSubtarget *Subtarget;
89  PPCFunctionInfo *PPCFuncInfo;
90  const TargetInstrInfo &TII;
91  const TargetLowering &TLI;
93 
94  public:
95  explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
96  const TargetLibraryInfo *LibInfo)
97  : FastISel(FuncInfo, LibInfo), TM(FuncInfo.MF->getTarget()),
98  Subtarget(&FuncInfo.MF->getSubtarget<PPCSubtarget>()),
99  PPCFuncInfo(FuncInfo.MF->getInfo<PPCFunctionInfo>()),
100  TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()),
101  Context(&FuncInfo.Fn->getContext()) {}
102 
103  // Backend specific FastISel code.
104  private:
105  bool fastSelectInstruction(const Instruction *I) override;
106  unsigned fastMaterializeConstant(const Constant *C) override;
107  unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
108  bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
109  const LoadInst *LI) override;
110  bool fastLowerArguments() override;
111  unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
112  unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
113  const TargetRegisterClass *RC,
114  unsigned Op0, uint64_t Imm);
115  unsigned fastEmitInst_r(unsigned MachineInstOpcode,
116  const TargetRegisterClass *RC, unsigned Op0);
117  unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
118  const TargetRegisterClass *RC,
119  unsigned Op0, unsigned Op1);
120 
121  bool fastLowerCall(CallLoweringInfo &CLI) override;
122 
123  // Instruction selection routines.
124  private:
125  bool SelectLoad(const Instruction *I);
126  bool SelectStore(const Instruction *I);
127  bool SelectBranch(const Instruction *I);
128  bool SelectIndirectBr(const Instruction *I);
129  bool SelectFPExt(const Instruction *I);
130  bool SelectFPTrunc(const Instruction *I);
131  bool SelectIToFP(const Instruction *I, bool IsSigned);
132  bool SelectFPToI(const Instruction *I, bool IsSigned);
133  bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
134  bool SelectRet(const Instruction *I);
135  bool SelectTrunc(const Instruction *I);
136  bool SelectIntExt(const Instruction *I);
137 
138  // Utility routines.
139  private:
140  bool isTypeLegal(Type *Ty, MVT &VT);
141  bool isLoadTypeLegal(Type *Ty, MVT &VT);
142  bool isValueAvailable(const Value *V) const;
143  bool isVSFRCRegClass(const TargetRegisterClass *RC) const {
144  return RC->getID() == PPC::VSFRCRegClassID;
145  }
146  bool isVSSRCRegClass(const TargetRegisterClass *RC) const {
147  return RC->getID() == PPC::VSSRCRegClassID;
148  }
149  unsigned copyRegToRegClass(const TargetRegisterClass *ToRC,
150  unsigned SrcReg, unsigned Flag = 0,
151  unsigned SubReg = 0) {
152  Register TmpReg = createResultReg(ToRC);
153  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
154  TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg);
155  return TmpReg;
156  }
157  bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
158  bool isZExt, unsigned DestReg,
159  const PPC::Predicate Pred);
160  bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
161  const TargetRegisterClass *RC, bool IsZExt = true,
162  unsigned FP64LoadOpc = PPC::LFD);
163  bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
164  bool PPCComputeAddress(const Value *Obj, Address &Addr);
165  void PPCSimplifyAddress(Address &Addr, bool &UseOffset,
166  unsigned &IndexReg);
167  bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
168  unsigned DestReg, bool IsZExt);
169  unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
170  unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
171  unsigned PPCMaterializeInt(const ConstantInt *CI, MVT VT,
172  bool UseSExt = true);
173  unsigned PPCMaterialize32BitInt(int64_t Imm,
174  const TargetRegisterClass *RC);
175  unsigned PPCMaterialize64BitInt(int64_t Imm,
176  const TargetRegisterClass *RC);
177  unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
178  unsigned SrcReg, bool IsSigned);
179  unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
180 
181  // Call handling routines.
182  private:
183  bool processCallArgs(SmallVectorImpl<Value*> &Args,
184  SmallVectorImpl<unsigned> &ArgRegs,
185  SmallVectorImpl<MVT> &ArgVTs,
187  SmallVectorImpl<unsigned> &RegArgs,
189  unsigned &NumBytes,
190  bool IsVarArg);
191  bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
192 
193  private:
194  #include "PPCGenFastISel.inc"
195 
196 };
197 
198 } // end anonymous namespace
199 
200 static std::optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
201  switch (Pred) {
202  // These are not representable with any single compare.
203  case CmpInst::FCMP_FALSE:
204  case CmpInst::FCMP_TRUE:
205  // Major concern about the following 6 cases is NaN result. The comparison
206  // result consists of 4 bits, indicating lt, eq, gt and un (unordered),
207  // only one of which will be set. The result is generated by fcmpu
208  // instruction. However, bc instruction only inspects one of the first 3
209  // bits, so when un is set, bc instruction may jump to an undesired
210  // place.
211  //
212  // More specifically, if we expect an unordered comparison and un is set, we
213  // expect to always go to true branch; in such case UEQ, UGT and ULT still
214  // give false, which are undesired; but UNE, UGE, ULE happen to give true,
215  // since they are tested by inspecting !eq, !lt, !gt, respectively.
216  //
217  // Similarly, for ordered comparison, when un is set, we always expect the
218  // result to be false. In such case OGT, OLT and OEQ is good, since they are
219  // actually testing GT, LT, and EQ respectively, which are false. OGE, OLE
220  // and ONE are tested through !lt, !gt and !eq, and these are true.
221  case CmpInst::FCMP_UEQ:
222  case CmpInst::FCMP_UGT:
223  case CmpInst::FCMP_ULT:
224  case CmpInst::FCMP_OGE:
225  case CmpInst::FCMP_OLE:
226  case CmpInst::FCMP_ONE:
227  default:
228  return std::nullopt;
229 
230  case CmpInst::FCMP_OEQ:
231  case CmpInst::ICMP_EQ:
232  return PPC::PRED_EQ;
233 
234  case CmpInst::FCMP_OGT:
235  case CmpInst::ICMP_UGT:
236  case CmpInst::ICMP_SGT:
237  return PPC::PRED_GT;
238 
239  case CmpInst::FCMP_UGE:
240  case CmpInst::ICMP_UGE:
241  case CmpInst::ICMP_SGE:
242  return PPC::PRED_GE;
243 
244  case CmpInst::FCMP_OLT:
245  case CmpInst::ICMP_ULT:
246  case CmpInst::ICMP_SLT:
247  return PPC::PRED_LT;
248 
249  case CmpInst::FCMP_ULE:
250  case CmpInst::ICMP_ULE:
251  case CmpInst::ICMP_SLE:
252  return PPC::PRED_LE;
253 
254  case CmpInst::FCMP_UNE:
255  case CmpInst::ICMP_NE:
256  return PPC::PRED_NE;
257 
258  case CmpInst::FCMP_ORD:
259  return PPC::PRED_NU;
260 
261  case CmpInst::FCMP_UNO:
262  return PPC::PRED_UN;
263  }
264 }
265 
266 // Determine whether the type Ty is simple enough to be handled by
267 // fast-isel, and return its equivalent machine type in VT.
268 // FIXME: Copied directly from ARM -- factor into base class?
269 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
270  EVT Evt = TLI.getValueType(DL, Ty, true);
271 
272  // Only handle simple types.
273  if (Evt == MVT::Other || !Evt.isSimple()) return false;
274  VT = Evt.getSimpleVT();
275 
276  // Handle all legal types, i.e. a register that will directly hold this
277  // value.
278  return TLI.isTypeLegal(VT);
279 }
280 
281 // Determine whether the type Ty is simple enough to be handled by
282 // fast-isel as a load target, and return its equivalent machine type in VT.
283 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
284  if (isTypeLegal(Ty, VT)) return true;
285 
286  // If this is a type than can be sign or zero-extended to a basic operation
287  // go ahead and accept it now.
288  if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
289  return true;
290  }
291 
292  return false;
293 }
294 
295 bool PPCFastISel::isValueAvailable(const Value *V) const {
296  if (!isa<Instruction>(V))
297  return true;
298 
299  const auto *I = cast<Instruction>(V);
300  return FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB;
301 }
302 
303 // Given a value Obj, create an Address object Addr that represents its
304 // address. Return false if we can't handle it.
305 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
306  const User *U = nullptr;
307  unsigned Opcode = Instruction::UserOp1;
308  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
309  // Don't walk into other basic blocks unless the object is an alloca from
310  // another block, otherwise it may not have a virtual register assigned.
311  if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
312  FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
313  Opcode = I->getOpcode();
314  U = I;
315  }
316  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
317  Opcode = C->getOpcode();
318  U = C;
319  }
320 
321  switch (Opcode) {
322  default:
323  break;
324  case Instruction::BitCast:
325  // Look through bitcasts.
326  return PPCComputeAddress(U->getOperand(0), Addr);
327  case Instruction::IntToPtr:
328  // Look past no-op inttoptrs.
329  if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
330  TLI.getPointerTy(DL))
331  return PPCComputeAddress(U->getOperand(0), Addr);
332  break;
333  case Instruction::PtrToInt:
334  // Look past no-op ptrtoints.
335  if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
336  return PPCComputeAddress(U->getOperand(0), Addr);
337  break;
338  case Instruction::GetElementPtr: {
339  Address SavedAddr = Addr;
340  int64_t TmpOffset = Addr.Offset;
341 
342  // Iterate through the GEP folding the constants into offsets where
343  // we can.
345  for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
346  II != IE; ++II, ++GTI) {
347  const Value *Op = *II;
348  if (StructType *STy = GTI.getStructTypeOrNull()) {
349  const StructLayout *SL = DL.getStructLayout(STy);
350  unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
351  TmpOffset += SL->getElementOffset(Idx);
352  } else {
353  uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
354  for (;;) {
355  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
356  // Constant-offset addressing.
357  TmpOffset += CI->getSExtValue() * S;
358  break;
359  }
360  if (canFoldAddIntoGEP(U, Op)) {
361  // A compatible add with a constant operand. Fold the constant.
362  ConstantInt *CI =
363  cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
364  TmpOffset += CI->getSExtValue() * S;
365  // Iterate on the other operand.
366  Op = cast<AddOperator>(Op)->getOperand(0);
367  continue;
368  }
369  // Unsupported
370  goto unsupported_gep;
371  }
372  }
373  }
374 
375  // Try to grab the base operand now.
376  Addr.Offset = TmpOffset;
377  if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
378 
379  // We failed, restore everything and try the other options.
380  Addr = SavedAddr;
381 
382  unsupported_gep:
383  break;
384  }
385  case Instruction::Alloca: {
386  const AllocaInst *AI = cast<AllocaInst>(Obj);
388  FuncInfo.StaticAllocaMap.find(AI);
389  if (SI != FuncInfo.StaticAllocaMap.end()) {
390  Addr.BaseType = Address::FrameIndexBase;
391  Addr.Base.FI = SI->second;
392  return true;
393  }
394  break;
395  }
396  }
397 
398  // FIXME: References to parameters fall through to the behavior
399  // below. They should be able to reference a frame index since
400  // they are stored to the stack, so we can get "ld rx, offset(r1)"
401  // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will
402  // just contain the parameter. Try to handle this with a FI.
403 
404  // Try to get this in a register if nothing else has worked.
405  if (Addr.Base.Reg == 0)
406  Addr.Base.Reg = getRegForValue(Obj);
407 
408  // Prevent assignment of base register to X0, which is inappropriate
409  // for loads and stores alike.
410  if (Addr.Base.Reg != 0)
411  MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
412 
413  return Addr.Base.Reg != 0;
414 }
415 
416 // Fix up some addresses that can't be used directly. For example, if
417 // an offset won't fit in an instruction field, we may need to move it
418 // into an index register.
419 void PPCFastISel::PPCSimplifyAddress(Address &Addr, bool &UseOffset,
420  unsigned &IndexReg) {
421 
422  // Check whether the offset fits in the instruction field.
423  if (!isInt<16>(Addr.Offset))
424  UseOffset = false;
425 
426  // If this is a stack pointer and the offset needs to be simplified then
427  // put the alloca address into a register, set the base type back to
428  // register and continue. This should almost never happen.
429  if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
430  Register ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
431  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ADDI8),
432  ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
433  Addr.Base.Reg = ResultReg;
434  Addr.BaseType = Address::RegBase;
435  }
436 
437  if (!UseOffset) {
438  IntegerType *OffsetTy = Type::getInt64Ty(*Context);
439  const ConstantInt *Offset = ConstantInt::getSigned(OffsetTy, Addr.Offset);
440  IndexReg = PPCMaterializeInt(Offset, MVT::i64);
441  assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
442  }
443 }
444 
445 // Emit a load instruction if possible, returning true if we succeeded,
446 // otherwise false. See commentary below for how the register class of
447 // the load is determined.
448 bool PPCFastISel::PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
449  const TargetRegisterClass *RC,
450  bool IsZExt, unsigned FP64LoadOpc) {
451  unsigned Opc;
452  bool UseOffset = true;
453  bool HasSPE = Subtarget->hasSPE();
454 
455  // If ResultReg is given, it determines the register class of the load.
456  // Otherwise, RC is the register class to use. If the result of the
457  // load isn't anticipated in this block, both may be zero, in which
458  // case we must make a conservative guess. In particular, don't assign
459  // R0 or X0 to the result register, as the result may be used in a load,
460  // store, add-immediate, or isel that won't permit this. (Though
461  // perhaps the spill and reload of live-exit values would handle this?)
462  const TargetRegisterClass *UseRC =
463  (ResultReg ? MRI.getRegClass(ResultReg) :
464  (RC ? RC :
465  (VT == MVT::f64 ? (HasSPE ? &PPC::SPERCRegClass : &PPC::F8RCRegClass) :
466  (VT == MVT::f32 ? (HasSPE ? &PPC::GPRCRegClass : &PPC::F4RCRegClass) :
467  (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
468  &PPC::GPRC_and_GPRC_NOR0RegClass)))));
469 
470  bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
471 
472  switch (VT.SimpleTy) {
473  default: // e.g., vector types not handled
474  return false;
475  case MVT::i8:
476  Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
477  break;
478  case MVT::i16:
479  Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8)
480  : (Is32BitInt ? PPC::LHA : PPC::LHA8));
481  break;
482  case MVT::i32:
483  Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8)
484  : (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
485  if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
486  UseOffset = false;
487  break;
488  case MVT::i64:
489  Opc = PPC::LD;
490  assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
491  "64-bit load with 32-bit target??");
492  UseOffset = ((Addr.Offset & 3) == 0);
493  break;
494  case MVT::f32:
495  Opc = Subtarget->hasSPE() ? PPC::SPELWZ : PPC::LFS;
496  break;
497  case MVT::f64:
498  Opc = FP64LoadOpc;
499  break;
500  }
501 
502  // If necessary, materialize the offset into a register and use
503  // the indexed form. Also handle stack pointers with special needs.
504  unsigned IndexReg = 0;
505  PPCSimplifyAddress(Addr, UseOffset, IndexReg);
506 
507  // If this is a potential VSX load with an offset of 0, a VSX indexed load can
508  // be used.
509  bool IsVSSRC = isVSSRCRegClass(UseRC);
510  bool IsVSFRC = isVSFRCRegClass(UseRC);
511  bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
512  bool Is64VSXLoad = IsVSFRC && Opc == PPC::LFD;
513  if ((Is32VSXLoad || Is64VSXLoad) &&
514  (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
515  (Addr.Offset == 0)) {
516  UseOffset = false;
517  }
518 
519  if (ResultReg == 0)
520  ResultReg = createResultReg(UseRC);
521 
522  // Note: If we still have a frame index here, we know the offset is
523  // in range, as otherwise PPCSimplifyAddress would have converted it
524  // into a RegBase.
525  if (Addr.BaseType == Address::FrameIndexBase) {
526  // VSX only provides an indexed load.
527  if (Is32VSXLoad || Is64VSXLoad) return false;
528 
529  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
530  MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
531  Addr.Offset),
532  MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
533  MFI.getObjectAlign(Addr.Base.FI));
534 
535  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
536  .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
537 
538  // Base reg with offset in range.
539  } else if (UseOffset) {
540  // VSX only provides an indexed load.
541  if (Is32VSXLoad || Is64VSXLoad) return false;
542 
543  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
544  .addImm(Addr.Offset).addReg(Addr.Base.Reg);
545 
546  // Indexed form.
547  } else {
548  // Get the RR opcode corresponding to the RI one. FIXME: It would be
549  // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
550  // is hard to get at.
551  switch (Opc) {
552  default: llvm_unreachable("Unexpected opcode!");
553  case PPC::LBZ: Opc = PPC::LBZX; break;
554  case PPC::LBZ8: Opc = PPC::LBZX8; break;
555  case PPC::LHZ: Opc = PPC::LHZX; break;
556  case PPC::LHZ8: Opc = PPC::LHZX8; break;
557  case PPC::LHA: Opc = PPC::LHAX; break;
558  case PPC::LHA8: Opc = PPC::LHAX8; break;
559  case PPC::LWZ: Opc = PPC::LWZX; break;
560  case PPC::LWZ8: Opc = PPC::LWZX8; break;
561  case PPC::LWA: Opc = PPC::LWAX; break;
562  case PPC::LWA_32: Opc = PPC::LWAX_32; break;
563  case PPC::LD: Opc = PPC::LDX; break;
564  case PPC::LFS: Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX; break;
565  case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break;
566  case PPC::EVLDD: Opc = PPC::EVLDDX; break;
567  case PPC::SPELWZ: Opc = PPC::SPELWZX; break;
568  }
569 
570  auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc),
571  ResultReg);
572 
573  // If we have an index register defined we use it in the store inst,
574  // otherwise we use X0 as base as it makes the vector instructions to
575  // use zero in the computation of the effective address regardless the
576  // content of the register.
577  if (IndexReg)
578  MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
579  else
580  MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
581  }
582 
583  return true;
584 }
585 
586 // Attempt to fast-select a load instruction.
587 bool PPCFastISel::SelectLoad(const Instruction *I) {
588  // FIXME: No atomic loads are supported.
589  if (cast<LoadInst>(I)->isAtomic())
590  return false;
591 
592  // Verify we have a legal type before going any further.
593  MVT VT;
594  if (!isLoadTypeLegal(I->getType(), VT))
595  return false;
596 
597  // See if we can handle this address.
598  Address Addr;
599  if (!PPCComputeAddress(I->getOperand(0), Addr))
600  return false;
601 
602  // Look at the currently assigned register for this instruction
603  // to determine the required register class. This is necessary
604  // to constrain RA from using R0/X0 when this is not legal.
605  Register AssignedReg = FuncInfo.ValueMap[I];
606  const TargetRegisterClass *RC =
607  AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
608 
609  Register ResultReg = 0;
610  if (!PPCEmitLoad(VT, ResultReg, Addr, RC, true,
611  Subtarget->hasSPE() ? PPC::EVLDD : PPC::LFD))
612  return false;
613  updateValueMap(I, ResultReg);
614  return true;
615 }
616 
617 // Emit a store instruction to store SrcReg at Addr.
618 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
619  assert(SrcReg && "Nothing to store!");
620  unsigned Opc;
621  bool UseOffset = true;
622 
623  const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
624  bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
625 
626  switch (VT.SimpleTy) {
627  default: // e.g., vector types not handled
628  return false;
629  case MVT::i8:
630  Opc = Is32BitInt ? PPC::STB : PPC::STB8;
631  break;
632  case MVT::i16:
633  Opc = Is32BitInt ? PPC::STH : PPC::STH8;
634  break;
635  case MVT::i32:
636  assert(Is32BitInt && "Not GPRC for i32??");
637  Opc = PPC::STW;
638  break;
639  case MVT::i64:
640  Opc = PPC::STD;
641  UseOffset = ((Addr.Offset & 3) == 0);
642  break;
643  case MVT::f32:
644  Opc = Subtarget->hasSPE() ? PPC::SPESTW : PPC::STFS;
645  break;
646  case MVT::f64:
647  Opc = Subtarget->hasSPE() ? PPC::EVSTDD : PPC::STFD;
648  break;
649  }
650 
651  // If necessary, materialize the offset into a register and use
652  // the indexed form. Also handle stack pointers with special needs.
653  unsigned IndexReg = 0;
654  PPCSimplifyAddress(Addr, UseOffset, IndexReg);
655 
656  // If this is a potential VSX store with an offset of 0, a VSX indexed store
657  // can be used.
658  bool IsVSSRC = isVSSRCRegClass(RC);
659  bool IsVSFRC = isVSFRCRegClass(RC);
660  bool Is32VSXStore = IsVSSRC && Opc == PPC::STFS;
661  bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD;
662  if ((Is32VSXStore || Is64VSXStore) &&
663  (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
664  (Addr.Offset == 0)) {
665  UseOffset = false;
666  }
667 
668  // Note: If we still have a frame index here, we know the offset is
669  // in range, as otherwise PPCSimplifyAddress would have converted it
670  // into a RegBase.
671  if (Addr.BaseType == Address::FrameIndexBase) {
672  // VSX only provides an indexed store.
673  if (Is32VSXStore || Is64VSXStore) return false;
674 
675  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
676  MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
677  Addr.Offset),
678  MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
679  MFI.getObjectAlign(Addr.Base.FI));
680 
681  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc))
682  .addReg(SrcReg)
683  .addImm(Addr.Offset)
684  .addFrameIndex(Addr.Base.FI)
685  .addMemOperand(MMO);
686 
687  // Base reg with offset in range.
688  } else if (UseOffset) {
689  // VSX only provides an indexed store.
690  if (Is32VSXStore || Is64VSXStore)
691  return false;
692 
693  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc))
694  .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
695 
696  // Indexed form.
697  } else {
698  // Get the RR opcode corresponding to the RI one. FIXME: It would be
699  // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
700  // is hard to get at.
701  switch (Opc) {
702  default: llvm_unreachable("Unexpected opcode!");
703  case PPC::STB: Opc = PPC::STBX; break;
704  case PPC::STH : Opc = PPC::STHX; break;
705  case PPC::STW : Opc = PPC::STWX; break;
706  case PPC::STB8: Opc = PPC::STBX8; break;
707  case PPC::STH8: Opc = PPC::STHX8; break;
708  case PPC::STW8: Opc = PPC::STWX8; break;
709  case PPC::STD: Opc = PPC::STDX; break;
710  case PPC::STFS: Opc = IsVSSRC ? PPC::STXSSPX : PPC::STFSX; break;
711  case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break;
712  case PPC::EVSTDD: Opc = PPC::EVSTDDX; break;
713  case PPC::SPESTW: Opc = PPC::SPESTWX; break;
714  }
715 
716  auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc))
717  .addReg(SrcReg);
718 
719  // If we have an index register defined we use it in the store inst,
720  // otherwise we use X0 as base as it makes the vector instructions to
721  // use zero in the computation of the effective address regardless the
722  // content of the register.
723  if (IndexReg)
724  MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
725  else
726  MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
727  }
728 
729  return true;
730 }
731 
732 // Attempt to fast-select a store instruction.
733 bool PPCFastISel::SelectStore(const Instruction *I) {
734  Value *Op0 = I->getOperand(0);
735  unsigned SrcReg = 0;
736 
737  // FIXME: No atomics loads are supported.
738  if (cast<StoreInst>(I)->isAtomic())
739  return false;
740 
741  // Verify we have a legal type before going any further.
742  MVT VT;
743  if (!isLoadTypeLegal(Op0->getType(), VT))
744  return false;
745 
746  // Get the value to be stored into a register.
747  SrcReg = getRegForValue(Op0);
748  if (SrcReg == 0)
749  return false;
750 
751  // See if we can handle this address.
752  Address Addr;
753  if (!PPCComputeAddress(I->getOperand(1), Addr))
754  return false;
755 
756  if (!PPCEmitStore(VT, SrcReg, Addr))
757  return false;
758 
759  return true;
760 }
761 
762 // Attempt to fast-select a branch instruction.
763 bool PPCFastISel::SelectBranch(const Instruction *I) {
764  const BranchInst *BI = cast<BranchInst>(I);
765  MachineBasicBlock *BrBB = FuncInfo.MBB;
766  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
767  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
768 
769  // For now, just try the simplest case where it's fed by a compare.
770  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
771  if (isValueAvailable(CI)) {
772  std::optional<PPC::Predicate> OptPPCPred =
773  getComparePred(CI->getPredicate());
774  if (!OptPPCPred)
775  return false;
776 
777  PPC::Predicate PPCPred = *OptPPCPred;
778 
779  // Take advantage of fall-through opportunities.
780  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
781  std::swap(TBB, FBB);
782  PPCPred = PPC::InvertPredicate(PPCPred);
783  }
784 
785  Register CondReg = createResultReg(&PPC::CRRCRegClass);
786 
787  if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
788  CondReg, PPCPred))
789  return false;
790 
791  BuildMI(*BrBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::BCC))
792  .addImm(Subtarget->hasSPE() ? PPC::PRED_SPE : PPCPred)
793  .addReg(CondReg)
794  .addMBB(TBB);
795  finishCondBranch(BI->getParent(), TBB, FBB);
796  return true;
797  }
798  } else if (const ConstantInt *CI =
799  dyn_cast<ConstantInt>(BI->getCondition())) {
800  uint64_t Imm = CI->getZExtValue();
801  MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
802  fastEmitBranch(Target, MIMD.getDL());
803  return true;
804  }
805 
806  // FIXME: ARM looks for a case where the block containing the compare
807  // has been split from the block containing the branch. If this happens,
808  // there is a vreg available containing the result of the compare. I'm
809  // not sure we can do much, as we've lost the predicate information with
810  // the compare instruction -- we have a 4-bit CR but don't know which bit
811  // to test here.
812  return false;
813 }
814 
815 // Attempt to emit a compare of the two source values. Signed and unsigned
816 // comparisons are supported. Return false if we can't handle it.
817 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
818  bool IsZExt, unsigned DestReg,
819  const PPC::Predicate Pred) {
820  Type *Ty = SrcValue1->getType();
821  EVT SrcEVT = TLI.getValueType(DL, Ty, true);
822  if (!SrcEVT.isSimple())
823  return false;
824  MVT SrcVT = SrcEVT.getSimpleVT();
825 
826  if (SrcVT == MVT::i1 && Subtarget->useCRBits())
827  return false;
828 
829  // See if operand 2 is an immediate encodeable in the compare.
830  // FIXME: Operands are not in canonical order at -O0, so an immediate
831  // operand in position 1 is a lost opportunity for now. We are
832  // similar to ARM in this regard.
833  int64_t Imm = 0;
834  bool UseImm = false;
835  const bool HasSPE = Subtarget->hasSPE();
836 
837  // Only 16-bit integer constants can be represented in compares for
838  // PowerPC. Others will be materialized into a register.
839  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
840  if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
841  SrcVT == MVT::i8 || SrcVT == MVT::i1) {
842  const APInt &CIVal = ConstInt->getValue();
843  Imm = (IsZExt) ? (int64_t)CIVal.getZExtValue() :
844  (int64_t)CIVal.getSExtValue();
845  if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
846  UseImm = true;
847  }
848  }
849 
850  Register SrcReg1 = getRegForValue(SrcValue1);
851  if (SrcReg1 == 0)
852  return false;
853 
854  unsigned SrcReg2 = 0;
855  if (!UseImm) {
856  SrcReg2 = getRegForValue(SrcValue2);
857  if (SrcReg2 == 0)
858  return false;
859  }
860 
861  unsigned CmpOpc;
862  bool NeedsExt = false;
863 
864  auto RC1 = MRI.getRegClass(SrcReg1);
865  auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr;
866 
867  switch (SrcVT.SimpleTy) {
868  default: return false;
869  case MVT::f32:
870  if (HasSPE) {
871  switch (Pred) {
872  default: return false;
873  case PPC::PRED_EQ:
874  CmpOpc = PPC::EFSCMPEQ;
875  break;
876  case PPC::PRED_LT:
877  CmpOpc = PPC::EFSCMPLT;
878  break;
879  case PPC::PRED_GT:
880  CmpOpc = PPC::EFSCMPGT;
881  break;
882  }
883  } else {
884  CmpOpc = PPC::FCMPUS;
885  if (isVSSRCRegClass(RC1))
886  SrcReg1 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg1);
887  if (RC2 && isVSSRCRegClass(RC2))
888  SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2);
889  }
890  break;
891  case MVT::f64:
892  if (HasSPE) {
893  switch (Pred) {
894  default: return false;
895  case PPC::PRED_EQ:
896  CmpOpc = PPC::EFDCMPEQ;
897  break;
898  case PPC::PRED_LT:
899  CmpOpc = PPC::EFDCMPLT;
900  break;
901  case PPC::PRED_GT:
902  CmpOpc = PPC::EFDCMPGT;
903  break;
904  }
905  } else if (isVSFRCRegClass(RC1) || (RC2 && isVSFRCRegClass(RC2))) {
906  CmpOpc = PPC::XSCMPUDP;
907  } else {
908  CmpOpc = PPC::FCMPUD;
909  }
910  break;
911  case MVT::i1:
912  case MVT::i8:
913  case MVT::i16:
914  NeedsExt = true;
915  [[fallthrough]];
916  case MVT::i32:
917  if (!UseImm)
918  CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
919  else
920  CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
921  break;
922  case MVT::i64:
923  if (!UseImm)
924  CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
925  else
926  CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
927  break;
928  }
929 
930  if (NeedsExt) {
931  Register ExtReg = createResultReg(&PPC::GPRCRegClass);
932  if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
933  return false;
934  SrcReg1 = ExtReg;
935 
936  if (!UseImm) {
937  Register ExtReg = createResultReg(&PPC::GPRCRegClass);
938  if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
939  return false;
940  SrcReg2 = ExtReg;
941  }
942  }
943 
944  if (!UseImm)
945  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(CmpOpc), DestReg)
946  .addReg(SrcReg1).addReg(SrcReg2);
947  else
948  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(CmpOpc), DestReg)
949  .addReg(SrcReg1).addImm(Imm);
950 
951  return true;
952 }
953 
954 // Attempt to fast-select a floating-point extend instruction.
955 bool PPCFastISel::SelectFPExt(const Instruction *I) {
956  Value *Src = I->getOperand(0);
957  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
958  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
959 
960  if (SrcVT != MVT::f32 || DestVT != MVT::f64)
961  return false;
962 
963  Register SrcReg = getRegForValue(Src);
964  if (!SrcReg)
965  return false;
966 
967  // No code is generated for a FP extend.
968  updateValueMap(I, SrcReg);
969  return true;
970 }
971 
972 // Attempt to fast-select a floating-point truncate instruction.
973 bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
974  Value *Src = I->getOperand(0);
975  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
976  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
977 
978  if (SrcVT != MVT::f64 || DestVT != MVT::f32)
979  return false;
980 
981  Register SrcReg = getRegForValue(Src);
982  if (!SrcReg)
983  return false;
984 
985  // Round the result to single precision.
986  unsigned DestReg;
987  auto RC = MRI.getRegClass(SrcReg);
988  if (Subtarget->hasSPE()) {
989  DestReg = createResultReg(&PPC::GPRCRegClass);
990  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::EFSCFD),
991  DestReg)
992  .addReg(SrcReg);
993  } else if (Subtarget->hasP8Vector() && isVSFRCRegClass(RC)) {
994  DestReg = createResultReg(&PPC::VSSRCRegClass);
995  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::XSRSP),
996  DestReg)
997  .addReg(SrcReg);
998  } else {
999  SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg);
1000  DestReg = createResultReg(&PPC::F4RCRegClass);
1001  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1002  TII.get(PPC::FRSP), DestReg)
1003  .addReg(SrcReg);
1004  }
1005 
1006  updateValueMap(I, DestReg);
1007  return true;
1008 }
1009 
1010 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
1011 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
1012 // those should be used instead of moving via a stack slot when the
1013 // subtarget permits.
1014 // FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte
1015 // stack slot and 4-byte store/load sequence. Or just sext the 4-byte
1016 // case to 8 bytes which produces tighter code but wastes stack space.
1017 unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
1018  bool IsSigned) {
1019 
1020  // If necessary, extend 32-bit int to 64-bit.
1021  if (SrcVT == MVT::i32) {
1022  Register TmpReg = createResultReg(&PPC::G8RCRegClass);
1023  if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
1024  return 0;
1025  SrcReg = TmpReg;
1026  }
1027 
1028  // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1029  Address Addr;
1030  Addr.BaseType = Address::FrameIndexBase;
1031  Addr.Base.FI = MFI.CreateStackObject(8, Align(8), false);
1032 
1033  // Store the value from the GPR.
1034  if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
1035  return 0;
1036 
1037  // Load the integer value into an FPR. The kind of load used depends
1038  // on a number of conditions.
1039  unsigned LoadOpc = PPC::LFD;
1040 
1041  if (SrcVT == MVT::i32) {
1042  if (!IsSigned) {
1043  LoadOpc = PPC::LFIWZX;
1044  Addr.Offset = (Subtarget->isLittleEndian()) ? 0 : 4;
1045  } else if (Subtarget->hasLFIWAX()) {
1046  LoadOpc = PPC::LFIWAX;
1047  Addr.Offset = (Subtarget->isLittleEndian()) ? 0 : 4;
1048  }
1049  }
1050 
1051  const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1052  Register ResultReg = 0;
1053  if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
1054  return 0;
1055 
1056  return ResultReg;
1057 }
1058 
1059 // Attempt to fast-select an integer-to-floating-point conversion.
1060 // FIXME: Once fast-isel has better support for VSX, conversions using
1061 // direct moves should be implemented.
1062 bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
1063  MVT DstVT;
1064  Type *DstTy = I->getType();
1065  if (!isTypeLegal(DstTy, DstVT))
1066  return false;
1067 
1068  if (DstVT != MVT::f32 && DstVT != MVT::f64)
1069  return false;
1070 
1071  Value *Src = I->getOperand(0);
1072  EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
1073  if (!SrcEVT.isSimple())
1074  return false;
1075 
1076  MVT SrcVT = SrcEVT.getSimpleVT();
1077 
1078  if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
1079  SrcVT != MVT::i32 && SrcVT != MVT::i64)
1080  return false;
1081 
1082  Register SrcReg = getRegForValue(Src);
1083  if (SrcReg == 0)
1084  return false;
1085 
1086  // Shortcut for SPE. Doesn't need to store/load, since it's all in the GPRs
1087  if (Subtarget->hasSPE()) {
1088  unsigned Opc;
1089  if (DstVT == MVT::f32)
1090  Opc = IsSigned ? PPC::EFSCFSI : PPC::EFSCFUI;
1091  else
1092  Opc = IsSigned ? PPC::EFDCFSI : PPC::EFDCFUI;
1093 
1094  Register DestReg = createResultReg(&PPC::SPERCRegClass);
1095  // Generate the convert.
1096  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
1097  .addReg(SrcReg);
1098  updateValueMap(I, DestReg);
1099  return true;
1100  }
1101 
1102  // We can only lower an unsigned convert if we have the newer
1103  // floating-point conversion operations.
1104  if (!IsSigned && !Subtarget->hasFPCVT())
1105  return false;
1106 
1107  // FIXME: For now we require the newer floating-point conversion operations
1108  // (which are present only on P7 and A2 server models) when converting
1109  // to single-precision float. Otherwise we have to generate a lot of
1110  // fiddly code to avoid double rounding. If necessary, the fiddly code
1111  // can be found in PPCTargetLowering::LowerINT_TO_FP().
1112  if (DstVT == MVT::f32 && !Subtarget->hasFPCVT())
1113  return false;
1114 
1115  // Extend the input if necessary.
1116  if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1117  Register TmpReg = createResultReg(&PPC::G8RCRegClass);
1118  if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
1119  return false;
1120  SrcVT = MVT::i64;
1121  SrcReg = TmpReg;
1122  }
1123 
1124  // Move the integer value to an FPR.
1125  unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
1126  if (FPReg == 0)
1127  return false;
1128 
1129  // Determine the opcode for the conversion.
1130  const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1131  Register DestReg = createResultReg(RC);
1132  unsigned Opc;
1133 
1134  if (DstVT == MVT::f32)
1135  Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS;
1136  else
1137  Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
1138 
1139  // Generate the convert.
1140  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
1141  .addReg(FPReg);
1142 
1143  updateValueMap(I, DestReg);
1144  return true;
1145 }
1146 
1147 // Move the floating-point value in SrcReg into an integer destination
1148 // register, and return the register (or zero if we can't handle it).
1149 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
1150 // those should be used instead of moving via a stack slot when the
1151 // subtarget permits.
1152 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
1153  unsigned SrcReg, bool IsSigned) {
1154  // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1155  // Note that if have STFIWX available, we could use a 4-byte stack
1156  // slot for i32, but this being fast-isel we'll just go with the
1157  // easiest code gen possible.
1158  Address Addr;
1159  Addr.BaseType = Address::FrameIndexBase;
1160  Addr.Base.FI = MFI.CreateStackObject(8, Align(8), false);
1161 
1162  // Store the value from the FPR.
1163  if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
1164  return 0;
1165 
1166  // Reload it into a GPR. If we want an i32 on big endian, modify the
1167  // address to have a 4-byte offset so we load from the right place.
1168  if (VT == MVT::i32)
1169  Addr.Offset = (Subtarget->isLittleEndian()) ? 0 : 4;
1170 
1171  // Look at the currently assigned register for this instruction
1172  // to determine the required register class.
1173  Register AssignedReg = FuncInfo.ValueMap[I];
1174  const TargetRegisterClass *RC =
1175  AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1176 
1177  Register ResultReg = 0;
1178  if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1179  return 0;
1180 
1181  return ResultReg;
1182 }
1183 
1184 // Attempt to fast-select a floating-point-to-integer conversion.
1185 // FIXME: Once fast-isel has better support for VSX, conversions using
1186 // direct moves should be implemented.
1187 bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
1188  MVT DstVT, SrcVT;
1189  Type *DstTy = I->getType();
1190  if (!isTypeLegal(DstTy, DstVT))
1191  return false;
1192 
1193  if (DstVT != MVT::i32 && DstVT != MVT::i64)
1194  return false;
1195 
1196  // If we don't have FCTIDUZ, or SPE, and we need it, punt to SelectionDAG.
1197  if (DstVT == MVT::i64 && !IsSigned && !Subtarget->hasFPCVT() &&
1198  !Subtarget->hasSPE())
1199  return false;
1200 
1201  Value *Src = I->getOperand(0);
1202  Type *SrcTy = Src->getType();
1203  if (!isTypeLegal(SrcTy, SrcVT))
1204  return false;
1205 
1206  if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1207  return false;
1208 
1209  Register SrcReg = getRegForValue(Src);
1210  if (SrcReg == 0)
1211  return false;
1212 
1213  // Convert f32 to f64 or convert VSSRC to VSFRC if necessary. This is just a
1214  // meaningless copy to get the register class right.
1215  const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1216  if (InRC == &PPC::F4RCRegClass)
1217  SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg);
1218  else if (InRC == &PPC::VSSRCRegClass)
1219  SrcReg = copyRegToRegClass(&PPC::VSFRCRegClass, SrcReg);
1220 
1221  // Determine the opcode for the conversion, which takes place
1222  // entirely within FPRs or VSRs.
1223  unsigned DestReg;
1224  unsigned Opc;
1225  auto RC = MRI.getRegClass(SrcReg);
1226 
1227  if (Subtarget->hasSPE()) {
1228  DestReg = createResultReg(&PPC::GPRCRegClass);
1229  if (IsSigned)
1230  Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTSIZ : PPC::EFDCTSIZ;
1231  else
1232  Opc = InRC == &PPC::GPRCRegClass ? PPC::EFSCTUIZ : PPC::EFDCTUIZ;
1233  } else if (isVSFRCRegClass(RC)) {
1234  DestReg = createResultReg(&PPC::VSFRCRegClass);
1235  if (DstVT == MVT::i32)
1236  Opc = IsSigned ? PPC::XSCVDPSXWS : PPC::XSCVDPUXWS;
1237  else
1238  Opc = IsSigned ? PPC::XSCVDPSXDS : PPC::XSCVDPUXDS;
1239  } else {
1240  DestReg = createResultReg(&PPC::F8RCRegClass);
1241  if (DstVT == MVT::i32)
1242  if (IsSigned)
1243  Opc = PPC::FCTIWZ;
1244  else
1245  Opc = Subtarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
1246  else
1247  Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
1248  }
1249 
1250  // Generate the convert.
1251  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
1252  .addReg(SrcReg);
1253 
1254  // Now move the integer value from a float register to an integer register.
1255  unsigned IntReg = Subtarget->hasSPE()
1256  ? DestReg
1257  : PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1258 
1259  if (IntReg == 0)
1260  return false;
1261 
1262  updateValueMap(I, IntReg);
1263  return true;
1264 }
1265 
1266 // Attempt to fast-select a binary integer operation that isn't already
1267 // handled automatically.
1268 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1269  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1270 
1271  // We can get here in the case when we have a binary operation on a non-legal
1272  // type and the target independent selector doesn't know how to handle it.
1273  if (DestVT != MVT::i16 && DestVT != MVT::i8)
1274  return false;
1275 
1276  // Look at the currently assigned register for this instruction
1277  // to determine the required register class. If there is no register,
1278  // make a conservative choice (don't assign R0).
1279  Register AssignedReg = FuncInfo.ValueMap[I];
1280  const TargetRegisterClass *RC =
1281  (AssignedReg ? MRI.getRegClass(AssignedReg) :
1282  &PPC::GPRC_and_GPRC_NOR0RegClass);
1283  bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1284 
1285  unsigned Opc;
1286  switch (ISDOpcode) {
1287  default: return false;
1288  case ISD::ADD:
1289  Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1290  break;
1291  case ISD::OR:
1292  Opc = IsGPRC ? PPC::OR : PPC::OR8;
1293  break;
1294  case ISD::SUB:
1295  Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1296  break;
1297  }
1298 
1299  Register ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1300  Register SrcReg1 = getRegForValue(I->getOperand(0));
1301  if (SrcReg1 == 0) return false;
1302 
1303  // Handle case of small immediate operand.
1304  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
1305  const APInt &CIVal = ConstInt->getValue();
1306  int Imm = (int)CIVal.getSExtValue();
1307  bool UseImm = true;
1308  if (isInt<16>(Imm)) {
1309  switch (Opc) {
1310  default:
1311  llvm_unreachable("Missing case!");
1312  case PPC::ADD4:
1313  Opc = PPC::ADDI;
1314  MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1315  break;
1316  case PPC::ADD8:
1317  Opc = PPC::ADDI8;
1318  MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1319  break;
1320  case PPC::OR:
1321  Opc = PPC::ORI;
1322  break;
1323  case PPC::OR8:
1324  Opc = PPC::ORI8;
1325  break;
1326  case PPC::SUBF:
1327  if (Imm == -32768)
1328  UseImm = false;
1329  else {
1330  Opc = PPC::ADDI;
1331  MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1332  Imm = -Imm;
1333  }
1334  break;
1335  case PPC::SUBF8:
1336  if (Imm == -32768)
1337  UseImm = false;
1338  else {
1339  Opc = PPC::ADDI8;
1340  MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1341  Imm = -Imm;
1342  }
1343  break;
1344  }
1345 
1346  if (UseImm) {
1347  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc),
1348  ResultReg)
1349  .addReg(SrcReg1)
1350  .addImm(Imm);
1351  updateValueMap(I, ResultReg);
1352  return true;
1353  }
1354  }
1355  }
1356 
1357  // Reg-reg case.
1358  Register SrcReg2 = getRegForValue(I->getOperand(1));
1359  if (SrcReg2 == 0) return false;
1360 
1361  // Reverse operands for subtract-from.
1362  if (ISDOpcode == ISD::SUB)
1363  std::swap(SrcReg1, SrcReg2);
1364 
1365  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
1366  .addReg(SrcReg1).addReg(SrcReg2);
1367  updateValueMap(I, ResultReg);
1368  return true;
1369 }
1370 
1371 // Handle arguments to a call that we're attempting to fast-select.
1372 // Return false if the arguments are too complex for us at the moment.
1373 bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
1374  SmallVectorImpl<unsigned> &ArgRegs,
1375  SmallVectorImpl<MVT> &ArgVTs,
1377  SmallVectorImpl<unsigned> &RegArgs,
1379  unsigned &NumBytes,
1380  bool IsVarArg) {
1382  CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context);
1383 
1384  // Reserve space for the linkage area on the stack.
1385  unsigned LinkageSize = Subtarget->getFrameLowering()->getLinkageSize();
1386  CCInfo.AllocateStack(LinkageSize, Align(8));
1387 
1388  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1389 
1390  // Bail out if we can't handle any of the arguments.
1391  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1392  CCValAssign &VA = ArgLocs[I];
1393  MVT ArgVT = ArgVTs[VA.getValNo()];
1394 
1395  // Skip vector arguments for now, as well as long double and
1396  // uint128_t, and anything that isn't passed in a register.
1397  if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
1398  !VA.isRegLoc() || VA.needsCustom())
1399  return false;
1400 
1401  // Skip bit-converted arguments for now.
1402  if (VA.getLocInfo() == CCValAssign::BCvt)
1403  return false;
1404  }
1405 
1406  // Get a count of how many bytes are to be pushed onto the stack.
1407  NumBytes = CCInfo.getNextStackOffset();
1408 
1409  // The prolog code of the callee may store up to 8 GPR argument registers to
1410  // the stack, allowing va_start to index over them in memory if its varargs.
1411  // Because we cannot tell if this is needed on the caller side, we have to
1412  // conservatively assume that it is needed. As such, make sure we have at
1413  // least enough stack space for the caller to store the 8 GPRs.
1414  // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
1415  NumBytes = std::max(NumBytes, LinkageSize + 64);
1416 
1417  // Issue CALLSEQ_START.
1418  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1419  TII.get(TII.getCallFrameSetupOpcode()))
1420  .addImm(NumBytes).addImm(0);
1421 
1422  // Prepare to assign register arguments. Every argument uses up a
1423  // GPR protocol register even if it's passed in a floating-point
1424  // register (unless we're using the fast calling convention).
1425  unsigned NextGPR = PPC::X3;
1426  unsigned NextFPR = PPC::F1;
1427 
1428  // Process arguments.
1429  for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1430  CCValAssign &VA = ArgLocs[I];
1431  unsigned Arg = ArgRegs[VA.getValNo()];
1432  MVT ArgVT = ArgVTs[VA.getValNo()];
1433 
1434  // Handle argument promotion and bitcasts.
1435  switch (VA.getLocInfo()) {
1436  default:
1437  llvm_unreachable("Unknown loc info!");
1438  case CCValAssign::Full:
1439  break;
1440  case CCValAssign::SExt: {
1441  MVT DestVT = VA.getLocVT();
1442  const TargetRegisterClass *RC =
1443  (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1444  Register TmpReg = createResultReg(RC);
1445  if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1446  llvm_unreachable("Failed to emit a sext!");
1447  ArgVT = DestVT;
1448  Arg = TmpReg;
1449  break;
1450  }
1451  case CCValAssign::AExt:
1452  case CCValAssign::ZExt: {
1453  MVT DestVT = VA.getLocVT();
1454  const TargetRegisterClass *RC =
1455  (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1456  Register TmpReg = createResultReg(RC);
1457  if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1458  llvm_unreachable("Failed to emit a zext!");
1459  ArgVT = DestVT;
1460  Arg = TmpReg;
1461  break;
1462  }
1463  case CCValAssign::BCvt: {
1464  // FIXME: Not yet handled.
1465  llvm_unreachable("Should have bailed before getting here!");
1466  break;
1467  }
1468  }
1469 
1470  // Copy this argument to the appropriate register.
1471  unsigned ArgReg;
1472  if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1473  ArgReg = NextFPR++;
1474  if (CC != CallingConv::Fast)
1475  ++NextGPR;
1476  } else
1477  ArgReg = NextGPR++;
1478 
1479  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1480  TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1481  RegArgs.push_back(ArgReg);
1482  }
1483 
1484  return true;
1485 }
1486 
1487 // For a call that we've determined we can fast-select, finish the
1488 // call sequence and generate a copy to obtain the return value (if any).
1489 bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) {
1490  CallingConv::ID CC = CLI.CallConv;
1491 
1492  // Issue CallSEQ_END.
1493  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1494  TII.get(TII.getCallFrameDestroyOpcode()))
1495  .addImm(NumBytes).addImm(0);
1496 
1497  // Next, generate a copy to obtain the return value.
1498  // FIXME: No multi-register return values yet, though I don't foresee
1499  // any real difficulties there.
1500  if (RetVT != MVT::isVoid) {
1502  CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1503  CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1504  CCValAssign &VA = RVLocs[0];
1505  assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1506  assert(VA.isRegLoc() && "Can only return in registers!");
1507 
1508  MVT DestVT = VA.getValVT();
1509  MVT CopyVT = DestVT;
1510 
1511  // Ints smaller than a register still arrive in a full 64-bit
1512  // register, so make sure we recognize this.
1513  if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1514  CopyVT = MVT::i64;
1515 
1516  unsigned SourcePhysReg = VA.getLocReg();
1517  unsigned ResultReg = 0;
1518 
1519  if (RetVT == CopyVT) {
1520  const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1521  ResultReg = copyRegToRegClass(CpyRC, SourcePhysReg);
1522 
1523  // If necessary, round the floating result to single precision.
1524  } else if (CopyVT == MVT::f64) {
1525  ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1526  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::FRSP),
1527  ResultReg).addReg(SourcePhysReg);
1528 
1529  // If only the low half of a general register is needed, generate
1530  // a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be
1531  // used along the fast-isel path (not lowered), and downstream logic
1532  // also doesn't like a direct subreg copy on a physical reg.)
1533  } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1534  // Convert physical register from G8RC to GPRC.
1535  SourcePhysReg -= PPC::X0 - PPC::R0;
1536  ResultReg = copyRegToRegClass(&PPC::GPRCRegClass, SourcePhysReg);
1537  }
1538 
1539  assert(ResultReg && "ResultReg unset!");
1540  CLI.InRegs.push_back(SourcePhysReg);
1541  CLI.ResultReg = ResultReg;
1542  CLI.NumResultRegs = 1;
1543  }
1544 
1545  return true;
1546 }
1547 
1548 bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1549  CallingConv::ID CC = CLI.CallConv;
1550  bool IsTailCall = CLI.IsTailCall;
1551  bool IsVarArg = CLI.IsVarArg;
1552  const Value *Callee = CLI.Callee;
1553  const MCSymbol *Symbol = CLI.Symbol;
1554 
1555  if (!Callee && !Symbol)
1556  return false;
1557 
1558  // Allow SelectionDAG isel to handle tail calls.
1559  if (IsTailCall)
1560  return false;
1561 
1562  // Let SDISel handle vararg functions.
1563  if (IsVarArg)
1564  return false;
1565 
1566  // If this is a PC-Rel function, let SDISel handle the call.
1567  if (Subtarget->isUsingPCRelativeCalls())
1568  return false;
1569 
1570  // Handle simple calls for now, with legal return types and
1571  // those that can be extended.
1572  Type *RetTy = CLI.RetTy;
1573  MVT RetVT;
1574  if (RetTy->isVoidTy())
1575  RetVT = MVT::isVoid;
1576  else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
1577  RetVT != MVT::i8)
1578  return false;
1579  else if (RetVT == MVT::i1 && Subtarget->useCRBits())
1580  // We can't handle boolean returns when CR bits are in use.
1581  return false;
1582 
1583  // FIXME: No multi-register return values yet.
1584  if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
1585  RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
1586  RetVT != MVT::f64) {
1588  CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1589  CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1590  if (RVLocs.size() > 1)
1591  return false;
1592  }
1593 
1594  // Bail early if more than 8 arguments, as we only currently
1595  // handle arguments passed in registers.
1596  unsigned NumArgs = CLI.OutVals.size();
1597  if (NumArgs > 8)
1598  return false;
1599 
1600  // Set up the argument vectors.
1602  SmallVector<unsigned, 8> ArgRegs;
1603  SmallVector<MVT, 8> ArgVTs;
1605 
1606  Args.reserve(NumArgs);
1607  ArgRegs.reserve(NumArgs);
1608  ArgVTs.reserve(NumArgs);
1609  ArgFlags.reserve(NumArgs);
1610 
1611  for (unsigned i = 0, ie = NumArgs; i != ie; ++i) {
1612  // Only handle easy calls for now. It would be reasonably easy
1613  // to handle <= 8-byte structures passed ByVal in registers, but we
1614  // have to ensure they are right-justified in the register.
1615  ISD::ArgFlagsTy Flags = CLI.OutFlags[i];
1616  if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal())
1617  return false;
1618 
1619  Value *ArgValue = CLI.OutVals[i];
1620  Type *ArgTy = ArgValue->getType();
1621  MVT ArgVT;
1622  if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
1623  return false;
1624 
1625  // FIXME: FastISel cannot handle non-simple types yet, including 128-bit FP
1626  // types, which is passed through vector register. Skip these types and
1627  // fallback to default SelectionDAG based selection.
1628  if (ArgVT.isVector() || ArgVT == MVT::f128)
1629  return false;
1630 
1631  Register Arg = getRegForValue(ArgValue);
1632  if (Arg == 0)
1633  return false;
1634 
1635  Args.push_back(ArgValue);
1636  ArgRegs.push_back(Arg);
1637  ArgVTs.push_back(ArgVT);
1638  ArgFlags.push_back(Flags);
1639  }
1640 
1641  // Process the arguments.
1642  SmallVector<unsigned, 8> RegArgs;
1643  unsigned NumBytes;
1644 
1645  if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1646  RegArgs, CC, NumBytes, IsVarArg))
1647  return false;
1648 
1649  MachineInstrBuilder MIB;
1650  // FIXME: No handling for function pointers yet. This requires
1651  // implementing the function descriptor (OPD) setup.
1652  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1653  if (!GV) {
1654  // patchpoints are a special case; they always dispatch to a pointer value.
1655  // However, we don't actually want to generate the indirect call sequence
1656  // here (that will be generated, as necessary, during asm printing), and
1657  // the call we generate here will be erased by FastISel::selectPatchpoint,
1658  // so don't try very hard...
1659  if (CLI.IsPatchPoint)
1660  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::NOP));
1661  else
1662  return false;
1663  } else {
1664  // Build direct call with NOP for TOC restore.
1665  // FIXME: We can and should optimize away the NOP for local calls.
1666  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1667  TII.get(PPC::BL8_NOP));
1668  // Add callee.
1669  MIB.addGlobalAddress(GV);
1670  }
1671 
1672  // Add implicit physical register uses to the call.
1673  for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
1674  MIB.addReg(RegArgs[II], RegState::Implicit);
1675 
1676  // Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live
1677  // into the call.
1678  PPCFuncInfo->setUsesTOCBasePtr();
1679  MIB.addReg(PPC::X2, RegState::Implicit);
1680 
1681  // Add a register mask with the call-preserved registers. Proper
1682  // defs for return values will be added by setPhysRegsDeadExcept().
1683  MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1684 
1685  CLI.Call = MIB;
1686 
1687  // Finish off the call including any return values.
1688  return finishCall(RetVT, CLI, NumBytes);
1689 }
1690 
1691 // Attempt to fast-select a return instruction.
1692 bool PPCFastISel::SelectRet(const Instruction *I) {
1693 
1694  if (!FuncInfo.CanLowerReturn)
1695  return false;
1696 
1697  const ReturnInst *Ret = cast<ReturnInst>(I);
1698  const Function &F = *I->getParent()->getParent();
1699 
1700  // Build a list of return value registers.
1701  SmallVector<unsigned, 4> RetRegs;
1702  CallingConv::ID CC = F.getCallingConv();
1703 
1704  if (Ret->getNumOperands() > 0) {
1706  GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1707 
1708  // Analyze operands of the call, assigning locations to each operand.
1710  CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
1711  CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
1712  const Value *RV = Ret->getOperand(0);
1713 
1714  // FIXME: Only one output register for now.
1715  if (ValLocs.size() > 1)
1716  return false;
1717 
1718  // Special case for returning a constant integer of any size - materialize
1719  // the constant as an i64 and copy it to the return register.
1720  if (const ConstantInt *CI = dyn_cast<ConstantInt>(RV)) {
1721  CCValAssign &VA = ValLocs[0];
1722 
1723  Register RetReg = VA.getLocReg();
1724  // We still need to worry about properly extending the sign. For example,
1725  // we could have only a single bit or a constant that needs zero
1726  // extension rather than sign extension. Make sure we pass the return
1727  // value extension property to integer materialization.
1728  unsigned SrcReg =
1729  PPCMaterializeInt(CI, MVT::i64, VA.getLocInfo() != CCValAssign::ZExt);
1730 
1731  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1732  TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1733 
1734  RetRegs.push_back(RetReg);
1735 
1736  } else {
1737  Register Reg = getRegForValue(RV);
1738 
1739  if (Reg == 0)
1740  return false;
1741 
1742  // Copy the result values into the output registers.
1743  for (unsigned i = 0; i < ValLocs.size(); ++i) {
1744 
1745  CCValAssign &VA = ValLocs[i];
1746  assert(VA.isRegLoc() && "Can only return in registers!");
1747  RetRegs.push_back(VA.getLocReg());
1748  unsigned SrcReg = Reg + VA.getValNo();
1749 
1750  EVT RVEVT = TLI.getValueType(DL, RV->getType());
1751  if (!RVEVT.isSimple())
1752  return false;
1753  MVT RVVT = RVEVT.getSimpleVT();
1754  MVT DestVT = VA.getLocVT();
1755 
1756  if (RVVT != DestVT && RVVT != MVT::i8 &&
1757  RVVT != MVT::i16 && RVVT != MVT::i32)
1758  return false;
1759 
1760  if (RVVT != DestVT) {
1761  switch (VA.getLocInfo()) {
1762  default:
1763  llvm_unreachable("Unknown loc info!");
1764  case CCValAssign::Full:
1765  llvm_unreachable("Full value assign but types don't match?");
1766  case CCValAssign::AExt:
1767  case CCValAssign::ZExt: {
1768  const TargetRegisterClass *RC =
1769  (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1770  Register TmpReg = createResultReg(RC);
1771  if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
1772  return false;
1773  SrcReg = TmpReg;
1774  break;
1775  }
1776  case CCValAssign::SExt: {
1777  const TargetRegisterClass *RC =
1778  (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1779  Register TmpReg = createResultReg(RC);
1780  if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
1781  return false;
1782  SrcReg = TmpReg;
1783  break;
1784  }
1785  }
1786  }
1787 
1788  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1789  TII.get(TargetOpcode::COPY), RetRegs[i])
1790  .addReg(SrcReg);
1791  }
1792  }
1793  }
1794 
1795  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1796  TII.get(PPC::BLR8));
1797 
1798  for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1799  MIB.addReg(RetRegs[i], RegState::Implicit);
1800 
1801  return true;
1802 }
1803 
1804 // Attempt to emit an integer extend of SrcReg into DestReg. Both
1805 // signed and zero extensions are supported. Return false if we
1806 // can't handle it.
1807 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1808  unsigned DestReg, bool IsZExt) {
1809  if (DestVT != MVT::i32 && DestVT != MVT::i64)
1810  return false;
1811  if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1812  return false;
1813 
1814  // Signed extensions use EXTSB, EXTSH, EXTSW.
1815  if (!IsZExt) {
1816  unsigned Opc;
1817  if (SrcVT == MVT::i8)
1818  Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1819  else if (SrcVT == MVT::i16)
1820  Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1821  else {
1822  assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1823  Opc = PPC::EXTSW_32_64;
1824  }
1825  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
1826  .addReg(SrcReg);
1827 
1828  // Unsigned 32-bit extensions use RLWINM.
1829  } else if (DestVT == MVT::i32) {
1830  unsigned MB;
1831  if (SrcVT == MVT::i8)
1832  MB = 24;
1833  else {
1834  assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1835  MB = 16;
1836  }
1837  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::RLWINM),
1838  DestReg)
1839  .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1840 
1841  // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1842  } else {
1843  unsigned MB;
1844  if (SrcVT == MVT::i8)
1845  MB = 56;
1846  else if (SrcVT == MVT::i16)
1847  MB = 48;
1848  else
1849  MB = 32;
1850  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1851  TII.get(PPC::RLDICL_32_64), DestReg)
1852  .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1853  }
1854 
1855  return true;
1856 }
1857 
1858 // Attempt to fast-select an indirect branch instruction.
1859 bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1860  Register AddrReg = getRegForValue(I->getOperand(0));
1861  if (AddrReg == 0)
1862  return false;
1863 
1864  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::MTCTR8))
1865  .addReg(AddrReg);
1866  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::BCTR8));
1867 
1868  const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1869  for (const BasicBlock *SuccBB : IB->successors())
1870  FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
1871 
1872  return true;
1873 }
1874 
1875 // Attempt to fast-select an integer truncate instruction.
1876 bool PPCFastISel::SelectTrunc(const Instruction *I) {
1877  Value *Src = I->getOperand(0);
1878  EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1879  EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1880 
1881  if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
1882  return false;
1883 
1884  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1885  return false;
1886 
1887  Register SrcReg = getRegForValue(Src);
1888  if (!SrcReg)
1889  return false;
1890 
1891  // The only interesting case is when we need to switch register classes.
1892  if (SrcVT == MVT::i64)
1893  SrcReg = copyRegToRegClass(&PPC::GPRCRegClass, SrcReg, 0, PPC::sub_32);
1894 
1895  updateValueMap(I, SrcReg);
1896  return true;
1897 }
1898 
1899 // Attempt to fast-select an integer extend instruction.
1900 bool PPCFastISel::SelectIntExt(const Instruction *I) {
1901  Type *DestTy = I->getType();
1902  Value *Src = I->getOperand(0);
1903  Type *SrcTy = Src->getType();
1904 
1905  bool IsZExt = isa<ZExtInst>(I);
1906  Register SrcReg = getRegForValue(Src);
1907  if (!SrcReg) return false;
1908 
1909  EVT SrcEVT, DestEVT;
1910  SrcEVT = TLI.getValueType(DL, SrcTy, true);
1911  DestEVT = TLI.getValueType(DL, DestTy, true);
1912  if (!SrcEVT.isSimple())
1913  return false;
1914  if (!DestEVT.isSimple())
1915  return false;
1916 
1917  MVT SrcVT = SrcEVT.getSimpleVT();
1918  MVT DestVT = DestEVT.getSimpleVT();
1919 
1920  // If we know the register class needed for the result of this
1921  // instruction, use it. Otherwise pick the register class of the
1922  // correct size that does not contain X0/R0, since we don't know
1923  // whether downstream uses permit that assignment.
1924  Register AssignedReg = FuncInfo.ValueMap[I];
1925  const TargetRegisterClass *RC =
1926  (AssignedReg ? MRI.getRegClass(AssignedReg) :
1927  (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1928  &PPC::GPRC_and_GPRC_NOR0RegClass));
1929  Register ResultReg = createResultReg(RC);
1930 
1931  if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1932  return false;
1933 
1934  updateValueMap(I, ResultReg);
1935  return true;
1936 }
1937 
1938 // Attempt to fast-select an instruction that wasn't handled by
1939 // the table-generated machinery.
1940 bool PPCFastISel::fastSelectInstruction(const Instruction *I) {
1941 
1942  switch (I->getOpcode()) {
1943  case Instruction::Load:
1944  return SelectLoad(I);
1945  case Instruction::Store:
1946  return SelectStore(I);
1947  case Instruction::Br:
1948  return SelectBranch(I);
1949  case Instruction::IndirectBr:
1950  return SelectIndirectBr(I);
1951  case Instruction::FPExt:
1952  return SelectFPExt(I);
1953  case Instruction::FPTrunc:
1954  return SelectFPTrunc(I);
1955  case Instruction::SIToFP:
1956  return SelectIToFP(I, /*IsSigned*/ true);
1957  case Instruction::UIToFP:
1958  return SelectIToFP(I, /*IsSigned*/ false);
1959  case Instruction::FPToSI:
1960  return SelectFPToI(I, /*IsSigned*/ true);
1961  case Instruction::FPToUI:
1962  return SelectFPToI(I, /*IsSigned*/ false);
1963  case Instruction::Add:
1964  return SelectBinaryIntOp(I, ISD::ADD);
1965  case Instruction::Or:
1966  return SelectBinaryIntOp(I, ISD::OR);
1967  case Instruction::Sub:
1968  return SelectBinaryIntOp(I, ISD::SUB);
1969  case Instruction::Ret:
1970  return SelectRet(I);
1971  case Instruction::Trunc:
1972  return SelectTrunc(I);
1973  case Instruction::ZExt:
1974  case Instruction::SExt:
1975  return SelectIntExt(I);
1976  // Here add other flavors of Instruction::XXX that automated
1977  // cases don't catch. For example, switches are terminators
1978  // that aren't yet handled.
1979  default:
1980  break;
1981  }
1982  return false;
1983 }
1984 
1985 // Materialize a floating-point constant into a register, and return
1986 // the register number (or zero if we failed to handle it).
1987 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1988  // If this is a PC-Rel function, let SDISel handle constant pool.
1989  if (Subtarget->isUsingPCRelativeCalls())
1990  return false;
1991 
1992  // No plans to handle long double here.
1993  if (VT != MVT::f32 && VT != MVT::f64)
1994  return 0;
1995 
1996  // All FP constants are loaded from the constant pool.
1997  Align Alignment = DL.getPrefTypeAlign(CFP->getType());
1998  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Alignment);
1999  const bool HasSPE = Subtarget->hasSPE();
2000  const TargetRegisterClass *RC;
2001  if (HasSPE)
2002  RC = ((VT == MVT::f32) ? &PPC::GPRCRegClass : &PPC::SPERCRegClass);
2003  else
2004  RC = ((VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass);
2005 
2006  Register DestReg = createResultReg(RC);
2007  CodeModel::Model CModel = TM.getCodeModel();
2008 
2009  MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
2011  MachineMemOperand::MOLoad, (VT == MVT::f32) ? 4 : 8, Alignment);
2012 
2013  unsigned Opc;
2014 
2015  if (HasSPE)
2016  Opc = ((VT == MVT::f32) ? PPC::SPELWZ : PPC::EVLDD);
2017  else
2018  Opc = ((VT == MVT::f32) ? PPC::LFS : PPC::LFD);
2019 
2020  Register TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2021 
2022  PPCFuncInfo->setUsesTOCBasePtr();
2023  // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
2024  if (CModel == CodeModel::Small) {
2025  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::LDtocCPT),
2026  TmpReg)
2027  .addConstantPoolIndex(Idx).addReg(PPC::X2);
2028  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
2029  .addImm(0).addReg(TmpReg).addMemOperand(MMO);
2030  } else {
2031  // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA8(X2, Idx)).
2032  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ADDIStocHA8),
2033  TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
2034  // But for large code model, we must generate a LDtocL followed
2035  // by the LF[SD].
2036  if (CModel == CodeModel::Large) {
2037  Register TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2038  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::LDtocL),
2039  TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
2040  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
2041  .addImm(0)
2042  .addReg(TmpReg2);
2043  } else
2044  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), DestReg)
2046  .addReg(TmpReg)
2047  .addMemOperand(MMO);
2048  }
2049 
2050  return DestReg;
2051 }
2052 
2053 // Materialize the address of a global value into a register, and return
2054 // the register number (or zero if we failed to handle it).
2055 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
2056  // If this is a PC-Rel function, let SDISel handle GV materialization.
2057  if (Subtarget->isUsingPCRelativeCalls())
2058  return false;
2059 
2060  assert(VT == MVT::i64 && "Non-address!");
2061  const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
2062  Register DestReg = createResultReg(RC);
2063 
2064  // Global values may be plain old object addresses, TLS object
2065  // addresses, constant pool entries, or jump tables. How we generate
2066  // code for these may depend on small, medium, or large code model.
2067  CodeModel::Model CModel = TM.getCodeModel();
2068 
2069  // FIXME: Jump tables are not yet required because fast-isel doesn't
2070  // handle switches; if that changes, we need them as well. For now,
2071  // what follows assumes everything's a generic (or TLS) global address.
2072 
2073  // FIXME: We don't yet handle the complexity of TLS.
2074  if (GV->isThreadLocal())
2075  return 0;
2076 
2077  // If the global has the toc-data attribute then fallback to DAG-ISEL.
2078  if (TM.getTargetTriple().isOSAIX())
2079  if (const GlobalVariable *Var = dyn_cast_or_null<GlobalVariable>(GV))
2080  if (Var->hasAttribute("toc-data"))
2081  return false;
2082 
2083  PPCFuncInfo->setUsesTOCBasePtr();
2084  // For small code model, generate a simple TOC load.
2085  if (CModel == CodeModel::Small)
2086  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::LDtoc),
2087  DestReg)
2088  .addGlobalAddress(GV)
2089  .addReg(PPC::X2);
2090  else {
2091  // If the address is an externally defined symbol, a symbol with common
2092  // or externally available linkage, a non-local function address, or a
2093  // jump table address (not yet needed), or if we are generating code
2094  // for large code model, we generate:
2095  // LDtocL(GV, ADDIStocHA8(%x2, GV))
2096  // Otherwise we generate:
2097  // ADDItocL(ADDIStocHA8(%x2, GV), GV)
2098  // Either way, start with the ADDIStocHA8:
2099  Register HighPartReg = createResultReg(RC);
2100  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ADDIStocHA8),
2101  HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
2102 
2103  if (Subtarget->isGVIndirectSymbol(GV)) {
2104  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::LDtocL),
2105  DestReg).addGlobalAddress(GV).addReg(HighPartReg);
2106  } else {
2107  // Otherwise generate the ADDItocL.
2108  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ADDItocL),
2109  DestReg).addReg(HighPartReg).addGlobalAddress(GV);
2110  }
2111  }
2112 
2113  return DestReg;
2114 }
2115 
2116 // Materialize a 32-bit integer constant into a register, and return
2117 // the register number (or zero if we failed to handle it).
2118 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
2119  const TargetRegisterClass *RC) {
2120  unsigned Lo = Imm & 0xFFFF;
2121  unsigned Hi = (Imm >> 16) & 0xFFFF;
2122 
2123  Register ResultReg = createResultReg(RC);
2124  bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
2125 
2126  if (isInt<16>(Imm))
2127  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2128  TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
2129  .addImm(Imm);
2130  else if (Lo) {
2131  // Both Lo and Hi have nonzero bits.
2132  Register TmpReg = createResultReg(RC);
2133  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2134  TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
2135  .addImm(Hi);
2136  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2137  TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
2138  .addReg(TmpReg).addImm(Lo);
2139  } else
2140  // Just Hi bits.
2141  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2142  TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
2143  .addImm(Hi);
2144 
2145  return ResultReg;
2146 }
2147 
2148 // Materialize a 64-bit integer constant into a register, and return
2149 // the register number (or zero if we failed to handle it).
2150 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
2151  const TargetRegisterClass *RC) {
2152  unsigned Remainder = 0;
2153  unsigned Shift = 0;
2154 
2155  // If the value doesn't fit in 32 bits, see if we can shift it
2156  // so that it fits in 32 bits.
2157  if (!isInt<32>(Imm)) {
2158  Shift = countTrailingZeros<uint64_t>(Imm);
2159  int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
2160 
2161  if (isInt<32>(ImmSh))
2162  Imm = ImmSh;
2163  else {
2164  Remainder = Imm;
2165  Shift = 32;
2166  Imm >>= 32;
2167  }
2168  }
2169 
2170  // Handle the high-order 32 bits (if shifted) or the whole 32 bits
2171  // (if not shifted).
2172  unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2173  if (!Shift)
2174  return TmpReg1;
2175 
2176  // If upper 32 bits were not zero, we've built them and need to shift
2177  // them into place.
2178  unsigned TmpReg2;
2179  if (Imm) {
2180  TmpReg2 = createResultReg(RC);
2181  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::RLDICR),
2182  TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
2183  } else
2184  TmpReg2 = TmpReg1;
2185 
2186  unsigned TmpReg3, Hi, Lo;
2187  if ((Hi = (Remainder >> 16) & 0xFFFF)) {
2188  TmpReg3 = createResultReg(RC);
2189  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ORIS8),
2190  TmpReg3).addReg(TmpReg2).addImm(Hi);
2191  } else
2192  TmpReg3 = TmpReg2;
2193 
2194  if ((Lo = Remainder & 0xFFFF)) {
2195  Register ResultReg = createResultReg(RC);
2196  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ORI8),
2197  ResultReg).addReg(TmpReg3).addImm(Lo);
2198  return ResultReg;
2199  }
2200 
2201  return TmpReg3;
2202 }
2203 
2204 // Materialize an integer constant into a register, and return
2205 // the register number (or zero if we failed to handle it).
2206 unsigned PPCFastISel::PPCMaterializeInt(const ConstantInt *CI, MVT VT,
2207  bool UseSExt) {
2208  // If we're using CR bit registers for i1 values, handle that as a special
2209  // case first.
2210  if (VT == MVT::i1 && Subtarget->useCRBits()) {
2211  Register ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2212  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2213  TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2214  return ImmReg;
2215  }
2216 
2217  if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 &&
2218  VT != MVT::i1)
2219  return 0;
2220 
2221  const TargetRegisterClass *RC =
2222  ((VT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass);
2223  int64_t Imm = UseSExt ? CI->getSExtValue() : CI->getZExtValue();
2224 
2225  // If the constant is in range, use a load-immediate.
2226  // Since LI will sign extend the constant we need to make sure that for
2227  // our zeroext constants that the sign extended constant fits into 16-bits -
2228  // a range of 0..0x7fff.
2229  if (isInt<16>(Imm)) {
2230  unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
2231  Register ImmReg = createResultReg(RC);
2232  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ImmReg)
2233  .addImm(Imm);
2234  return ImmReg;
2235  }
2236 
2237  // Construct the constant piecewise.
2238  if (VT == MVT::i64)
2239  return PPCMaterialize64BitInt(Imm, RC);
2240  else if (VT == MVT::i32)
2241  return PPCMaterialize32BitInt(Imm, RC);
2242 
2243  return 0;
2244 }
2245 
2246 // Materialize a constant into a register, and return the register
2247 // number (or zero if we failed to handle it).
2248 unsigned PPCFastISel::fastMaterializeConstant(const Constant *C) {
2249  EVT CEVT = TLI.getValueType(DL, C->getType(), true);
2250 
2251  // Only handle simple types.
2252  if (!CEVT.isSimple()) return 0;
2253  MVT VT = CEVT.getSimpleVT();
2254 
2255  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2256  return PPCMaterializeFP(CFP, VT);
2257  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2258  return PPCMaterializeGV(GV, VT);
2259  else if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
2260  // Note that the code in FunctionLoweringInfo::ComputePHILiveOutRegInfo
2261  // assumes that constant PHI operands will be zero extended, and failure to
2262  // match that assumption will cause problems if we sign extend here but
2263  // some user of a PHI is in a block for which we fall back to full SDAG
2264  // instruction selection.
2265  return PPCMaterializeInt(CI, VT, false);
2266 
2267  return 0;
2268 }
2269 
2270 // Materialize the address created by an alloca into a register, and
2271 // return the register number (or zero if we failed to handle it).
2272 unsigned PPCFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
2273  // Don't handle dynamic allocas.
2274  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
2275 
2276  MVT VT;
2277  if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
2278 
2280  FuncInfo.StaticAllocaMap.find(AI);
2281 
2282  if (SI != FuncInfo.StaticAllocaMap.end()) {
2283  Register ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2284  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(PPC::ADDI8),
2285  ResultReg).addFrameIndex(SI->second).addImm(0);
2286  return ResultReg;
2287  }
2288 
2289  return 0;
2290 }
2291 
2292 // Fold loads into extends when possible.
2293 // FIXME: We can have multiple redundant extend/trunc instructions
2294 // following a load. The folding only picks up one. Extend this
2295 // to check subsequent instructions for the same pattern and remove
2296 // them. Thus ResultReg should be the def reg for the last redundant
2297 // instruction in a chain, and all intervening instructions can be
2298 // removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll
2299 // to add ELF64-NOT: rldicl to the appropriate tests when this works.
2300 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2301  const LoadInst *LI) {
2302  // Verify we have a legal type before going any further.
2303  MVT VT;
2304  if (!isLoadTypeLegal(LI->getType(), VT))
2305  return false;
2306 
2307  // Combine load followed by zero- or sign-extend.
2308  bool IsZExt = false;
2309  switch(MI->getOpcode()) {
2310  default:
2311  return false;
2312 
2313  case PPC::RLDICL:
2314  case PPC::RLDICL_32_64: {
2315  IsZExt = true;
2316  unsigned MB = MI->getOperand(3).getImm();
2317  if ((VT == MVT::i8 && MB <= 56) ||
2318  (VT == MVT::i16 && MB <= 48) ||
2319  (VT == MVT::i32 && MB <= 32))
2320  break;
2321  return false;
2322  }
2323 
2324  case PPC::RLWINM:
2325  case PPC::RLWINM8: {
2326  IsZExt = true;
2327  unsigned MB = MI->getOperand(3).getImm();
2328  if ((VT == MVT::i8 && MB <= 24) ||
2329  (VT == MVT::i16 && MB <= 16))
2330  break;
2331  return false;
2332  }
2333 
2334  case PPC::EXTSB:
2335  case PPC::EXTSB8:
2336  case PPC::EXTSB8_32_64:
2337  /* There is no sign-extending load-byte instruction. */
2338  return false;
2339 
2340  case PPC::EXTSH:
2341  case PPC::EXTSH8:
2342  case PPC::EXTSH8_32_64: {
2343  if (VT != MVT::i16 && VT != MVT::i8)
2344  return false;
2345  break;
2346  }
2347 
2348  case PPC::EXTSW:
2349  case PPC::EXTSW_32:
2350  case PPC::EXTSW_32_64: {
2351  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
2352  return false;
2353  break;
2354  }
2355  }
2356 
2357  // See if we can handle this address.
2358  Address Addr;
2359  if (!PPCComputeAddress(LI->getOperand(0), Addr))
2360  return false;
2361 
2362  Register ResultReg = MI->getOperand(0).getReg();
2363 
2364  if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt,
2365  Subtarget->hasSPE() ? PPC::EVLDD : PPC::LFD))
2366  return false;
2367 
2369  removeDeadCode(I, std::next(I));
2370  return true;
2371 }
2372 
2373 // Attempt to lower call arguments in a faster way than done by
2374 // the selection DAG code.
2375 bool PPCFastISel::fastLowerArguments() {
2376  // Defer to normal argument lowering for now. It's reasonably
2377  // efficient. Consider doing something like ARM to handle the
2378  // case where all args fit in registers, no varargs, no float
2379  // or vector args.
2380  return false;
2381 }
2382 
2383 // Handle materializing integer constants into a register. This is not
2384 // automatically generated for PowerPC, so must be explicitly created here.
2385 unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
2386 
2387  if (Opc != ISD::Constant)
2388  return 0;
2389 
2390  // If we're using CR bit registers for i1 values, handle that as a special
2391  // case first.
2392  if (VT == MVT::i1 && Subtarget->useCRBits()) {
2393  Register ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2394  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2395  TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2396  return ImmReg;
2397  }
2398 
2399  if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 &&
2400  VT != MVT::i1)
2401  return 0;
2402 
2403  const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2404  &PPC::GPRCRegClass);
2405  if (VT == MVT::i64)
2406  return PPCMaterialize64BitInt(Imm, RC);
2407  else
2408  return PPCMaterialize32BitInt(Imm, RC);
2409 }
2410 
2411 // Override for ADDI and ADDI8 to set the correct register class
2412 // on RHS operand 0. The automatic infrastructure naively assumes
2413 // GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
2414 // for these cases. At the moment, none of the other automatically
2415 // generated RI instructions require special treatment. However, once
2416 // SelectSelect is implemented, "isel" requires similar handling.
2417 //
2418 // Also be conservative about the output register class. Avoid
2419 // assigning R0 or X0 to the output register for GPRC and G8RC
2420 // register classes, as any such result could be used in ADDI, etc.,
2421 // where those regs have another meaning.
2422 unsigned PPCFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
2423  const TargetRegisterClass *RC,
2424  unsigned Op0,
2425  uint64_t Imm) {
2426  if (MachineInstOpcode == PPC::ADDI)
2427  MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2428  else if (MachineInstOpcode == PPC::ADDI8)
2429  MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2430 
2431  const TargetRegisterClass *UseRC =
2432  (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2433  (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2434 
2435  return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, Op0, Imm);
2436 }
2437 
2438 // Override for instructions with one register operand to avoid use of
2439 // R0/X0. The automatic infrastructure isn't aware of the context so
2440 // we must be conservative.
2441 unsigned PPCFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
2442  const TargetRegisterClass* RC,
2443  unsigned Op0) {
2444  const TargetRegisterClass *UseRC =
2445  (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2446  (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2447 
2448  return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0);
2449 }
2450 
2451 // Override for instructions with two register operands to avoid use
2452 // of R0/X0. The automatic infrastructure isn't aware of the context
2453 // so we must be conservative.
2454 unsigned PPCFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2455  const TargetRegisterClass* RC,
2456  unsigned Op0, unsigned Op1) {
2457  const TargetRegisterClass *UseRC =
2458  (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2459  (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2460 
2461  return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op1);
2462 }
2463 
2464 namespace llvm {
2465  // Create the fast instruction selector for PowerPC64 ELF.
2467  const TargetLibraryInfo *LibInfo) {
2468  // Only available on 64-bit for now.
2469  const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
2470  if (Subtarget.isPPC64())
2471  return new PPCFastISel(FuncInfo, LibInfo);
2472  return nullptr;
2473  }
2474 }
llvm::FunctionLoweringInfo::Fn
const Function * Fn
Definition: FunctionLoweringInfo.h:54
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:130
i
i
Definition: README.txt:29
llvm::CmpInst::FCMP_ULE
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:733
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:36
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:74
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::PPC::PRED_LT
@ PRED_LT
Definition: PPCPredicates.h:27
llvm::PPCISD::FCTIDZ
@ FCTIDZ
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
Definition: PPCISelLowering.h:73
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::CmpInst::ICMP_EQ
@ ICMP_EQ
equal
Definition: InstrTypes.h:739
llvm::ReturnInst
Return a value (possibly void), from a function.
Definition: Instructions.h:3057
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::generic_gep_type_iterator
Definition: GetElementPtrTypeIterator.h:31
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:718
IntrinsicInst.h
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:168
llvm::Function
Definition: Function.h:59
llvm::PPC::PRED_GE
@ PRED_GE
Definition: PPCPredicates.h:30
llvm::MachinePointerInfo::getConstantPool
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
Definition: MachineOperand.cpp:1038
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::FunctionLoweringInfo::InsertPt
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
Definition: FunctionLoweringInfo.h:156
GetElementPtrTypeIterator.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::AllocaInst::getType
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:100
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::CallingConv::Fast
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:386
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1516
llvm::CmpInst::FCMP_ONE
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:726
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::GlobalVariable
Definition: GlobalVariable.h:39
llvm::CmpInst::ICMP_NE
@ ICMP_NE
not equal
Definition: InstrTypes.h:740
llvm::CmpInst::ICMP_SGT
@ ICMP_SGT
signed greater than
Definition: InstrTypes.h:745
getComparePred
static std::optional< PPC::Predicate > getComparePred(CmpInst::Predicate Pred)
Definition: PPCFastISel.cpp:200
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:315
Shift
bool Shift
Definition: README.txt:468
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::FunctionLoweringInfo::MBB
MachineBasicBlock * MBB
MBB - The current block.
Definition: FunctionLoweringInfo.h:153
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::PPC::InvertPredicate
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
llvm::PPCISD::FCFIDU
@ FCFIDU
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
Definition: PPCISelLowering.h:66
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:44
llvm::PPCFunctionInfo
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
Definition: PPCMachineFunctionInfo.h:24
Operator.h
llvm::CmpInst::ICMP_SLE
@ ICMP_SLE
signed less or equal
Definition: InstrTypes.h:748
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:123
llvm::PPC::PRED_GT
@ PRED_GT
Definition: PPCPredicates.h:31
llvm::CmpInst::FCMP_OGT
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:722
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::PPCISD::FCFID
@ FCFID
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
Definition: PPCISelLowering.h:62
llvm::CC_PPC64_ELF_FIS
bool CC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
F
#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:129
llvm::CmpInst::FCMP_ULT
@ FCMP_ULT
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:732
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
PPCSubtarget.h
TargetLowering.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
i64
Clang compiles this i64
Definition: README.txt:504
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:37
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
TargetMachine.h
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:76
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
FunctionLoweringInfo.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::PPCISD::LFIWZX
@ LFIWZX
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
Definition: PPCISelLowering.h:536
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:126
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:770
llvm::User
Definition: User.h:44
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::CmpInst::ICMP_ULE
@ ICMP_ULE
unsigned less or equal
Definition: InstrTypes.h:744
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:58
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3510
SI
@ SI
Definition: SIInstrInfo.cpp:7993
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::CmpInst::FCMP_UGE
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:731
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:341
PPCCCState.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MVT::isVoid
@ isVoid
Definition: MachineValueType.h:284
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:31
llvm::IntegerType
Class to represent integer types.
Definition: DerivedTypes.h:40
llvm::CmpInst::FCMP_UNO
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:728
llvm::Instruction
Definition: Instruction.h:41
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:148
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:141
llvm::PPCSubtarget::isPPC64
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
Definition: PPCSubtarget.cpp:182
llvm::APInt::getZExtValue
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1494
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:256
PPC.h
llvm::CmpInst::FCMP_OEQ
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:721
llvm::CmpInst::FCMP_OLT
@ FCMP_OLT
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:724
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:132
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::PPCSubtarget::getInstrInfo
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:145
llvm::PPC::PRED_LE
@ PRED_LE
Definition: PPCPredicates.h:28
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::generic_gep_type_iterator::getStructTypeOrNull
StructType * getStructTypeOrNull() const
Definition: GetElementPtrTypeIterator.h:116
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:120
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::PPCISD::LFIWAX
@ LFIWAX
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
Definition: PPCISelLowering.h:531
llvm::BranchInst::getCondition
Value * getCondition() const
Definition: Instructions.h:3220
llvm::CmpInst::FCMP_FALSE
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:720
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:661
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::PPCISD::FCTIWZ
@ FCTIWZ
Definition: PPCISelLowering.h:74
llvm::CodeModel::Model
Model
Definition: CodeGen.h:31
llvm::CmpInst
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:708
llvm::PPC::PRED_EQ
@ PRED_EQ
Definition: PPCPredicates.h:29
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:672
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
llvm::GlobalValue
Definition: GlobalValue.h:44
BaseType
BaseType
A given derived pointer can have multiple base pointers through phi/selects.
Definition: SafepointIRVerifier.cpp:314
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::pdb::PDB_ColorItem::Address
@ Address
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:35
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::StructLayout
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
Definition: DataLayout.h:625
uint64_t
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:31
llvm::DenseMap
Definition: DenseMap.h:714
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AArch64PACKey::IB
@ IB
Definition: AArch64BaseInfo.h:826
MachineConstantPool.h
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::PPC::PRED_NE
@ PRED_NE
Definition: PPCPredicates.h:32
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:919
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::CmpInst::FCMP_OGE
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:723
llvm::generic_gep_type_iterator::getIndexedType
Type * getIndexedType() const
Definition: GetElementPtrTypeIterator.h:70
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::CmpInst::ICMP_UGE
@ ICMP_UGE
unsigned greater or equal
Definition: InstrTypes.h:742
llvm::GlobalValue::isThreadLocal
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
Definition: GlobalValue.h:259
llvm::Type::isVoidTy
bool isVoidTy() const
Return true if this is 'void'.
Definition: Type.h:140
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::CmpInst::ICMP_SLT
@ ICMP_SLT
signed less than
Definition: InstrTypes.h:747
llvm::CCValAssign::getValNo
unsigned getValNo() const
Definition: CallingConvLower.h:117
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::PPCII::MO_TOC_LO
@ MO_TOC_LO
Definition: PPC.h:171
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::StructType
Class to represent struct types.
Definition: DerivedTypes.h:213
llvm::CmpInst::ICMP_ULT
@ ICMP_ULT
unsigned less than
Definition: InstrTypes.h:743
llvm::Offset
@ Offset
Definition: DWP.cpp:406
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::ConstantInt::isZero
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Definition: Constants.h:193
llvm::RetCC_PPC64_ELF_FIS
bool RetCC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::PPCISD::FCFIDUS
@ FCFIDUS
Definition: PPCISelLowering.h:68
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::PPC::PRED_NU
@ PRED_NU
Definition: PPCPredicates.h:34
llvm::ConstantInt::getSExtValue
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
Definition: Constants.h:147
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:177
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::FastISel::fastEmitInst_ri
Register fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm)
Emit a MachineInstr with a register operand, an immediate, and a result register in the given registe...
Definition: FastISel.cpp:1999
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:141
llvm::PPCSubtarget::getTargetLowering
const PPCTargetLowering * getTargetLowering() const override
Definition: PPCSubtarget.h:146
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
llvm::PPCISD::FCTIWUZ
@ FCTIWUZ
Definition: PPCISelLowering.h:79
CallingConv.h
llvm::CmpInst::FCMP_UGT
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:730
PPCCallingConv.h
llvm::PPC::PRED_SPE
@ PRED_SPE
Definition: PPCPredicates.h:53
llvm::Type::getInt64Ty
static IntegerType * getInt64Ty(LLVMContext &C)
Definition: Type.cpp:242
llvm::ConstantExpr
A constant value that is initialized with an expression using other constant values.
Definition: Constants.h:998
llvm::PPC::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
Definition: PPCFastISel.cpp:2466
CallingConvLower.h
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:668
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:354
llvm::StructLayout::getElementOffset
uint64_t getElementOffset(unsigned Idx) const
Definition: DataLayout.h:655
MachineFrameInfo.h
llvm::PPCISD::FCTIDUZ
@ FCTIDUZ
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
Definition: PPCISelLowering.h:78
GlobalVariable.h
llvm::MachineInstrBuilder::addConstantPoolIndex
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:158
llvm::ConstantInt::getSigned
static ConstantInt * getSigned(IntegerType *Ty, int64_t V)
Return a ConstantInt with the specified value for the specified type.
Definition: Constants.cpp:901
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:234
llvm::CmpInst::ICMP_SGE
@ ICMP_SGE
signed greater or equal
Definition: InstrTypes.h:746
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:186
PPCISelLowering.h
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::PPC::PRED_UN
@ PRED_UN
Definition: PPCPredicates.h:33
llvm::IndirectBrInst
Indirect Branch Instruction.
Definition: Instructions.h:3679
GlobalAlias.h
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:177
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:31
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
FastISel.h
llvm::FunctionLoweringInfo::MF
MachineFunction * MF
Definition: FunctionLoweringInfo.h:55
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:60
llvm::GetReturnInfo
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
Definition: TargetLoweringBase.cpp:1671
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1044
MachineInstrBuilder.h
llvm::CmpInst::ICMP_UGT
@ ICMP_UGT
unsigned greater than
Definition: InstrTypes.h:741
llvm::User::op_begin
op_iterator op_begin()
Definition: User.h:234
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:118
llvm::CmpInst::FCMP_UNE
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:734
llvm::Instruction::getParent
const BasicBlock * getParent() const
Definition: Instruction.h:90
PPCMachineFunctionInfo.h
PPC
should just be implemented with a CLZ instruction Since there are other e PPC
Definition: README.txt:709
llvm::CmpInst::FCMP_OLE
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:725
llvm::SmallVectorImpl< Value * >
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:47
llvm::omp::RTLDependInfoFields::Flags
@ Flags
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::AllocaInst
an instruction to allocate memory on the stack
Definition: Instructions.h:58
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3139
llvm::SmallVectorImpl::reserve
void reserve(size_type N)
Definition: SmallVector.h:667
PPCPredicates.h
llvm::CmpInst::FCMP_TRUE
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:735
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::FastISel::fastEmitInst_rr
Register fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1)
Emit a MachineInstr with two register operands and a result register in the given register class.
Definition: FastISel.cpp:1948
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:57
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
Debug.h
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:482
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
PPCTargetMachine.h
llvm::CCValAssign::needsCustom
bool needsCustom() const
Definition: CallingConvLower.h:124
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:57
llvm::CmpInst::FCMP_ORD
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:727
llvm::BranchInst::getSuccessor
BasicBlock * getSuccessor(unsigned i) const
Definition: Instructions.h:3232
llvm::FastISel::fastEmitInst_r
Register fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0)
Emit a MachineInstr with one register operand and a result register in the given register class.
Definition: FastISel.cpp:1927
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::CmpInst::FCMP_UEQ
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:729
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
llvm::PPCISD::FCFIDS
@ FCFIDS
Definition: PPCISelLowering.h:67
llvm::User::op_end
op_iterator op_end()
Definition: User.h:236