LLVM  14.0.0git
Public Member Functions | Static Public Member Functions | Protected Member Functions | List of all members
llvm::PPCInstrInfo Class Reference

#include "Target/PowerPC/PPCInstrInfo.h"

Inheritance diagram for llvm::PPCInstrInfo:
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Public Member Functions

 PPCInstrInfo (PPCSubtarget &STI)
 
const PPCRegisterInfogetRegisterInfo () const
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
 
bool isXFormMemOp (unsigned Opcode) const
 
bool isPrefixed (unsigned Opcode) const
 
ScheduleHazardRecognizerCreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
 CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG. More...
 
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
 CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG. More...
 
unsigned getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
 
int getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
 
int getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
 
bool hasLowDefLatency (const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
 
bool useMachineCombiner () const override
 
void genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
 When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence. More...
 
bool getFMAPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const
 Return true when there is potentially a faster code sequence for a fma chain ending in Root. More...
 
bool getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const override
 Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>. More...
 
bool shouldReduceRegisterPressure (MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const override
 On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure is high for one BB. More...
 
void finalizeInsInstrs (MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
 Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner. More...
 
bool isAssociativeAndCommutative (const MachineInstr &Inst) const override
 
int getExtendResourceLenLimit () const override
 On PowerPC, we try to reassociate FMA chain which will increase instruction size. More...
 
void setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
 This is an architecture-specific helper function of reassociateOps. More...
 
void setSpecialOperandAttr (MachineInstr &MI, uint16_t Flags) const override
 
bool isCoalescableExtInstr (const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
bool isReallyTriviallyReMaterializable (const MachineInstr &MI, AAResults *AA) const override
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
bool findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
 
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void storeRegToStackSlotNoUpd (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlotNoUpd (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
 
unsigned getStoreOpcodeForSpill (const TargetRegisterClass *RC) const
 
unsigned getLoadOpcodeForSpill (const TargetRegisterClass *RC) const
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
 
bool onlyFoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const
 
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override
 
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
 
bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
 
bool isPredicated (const MachineInstr &MI) const override
 
bool isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
 
bool PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
 
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
 
bool ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
 
bool analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
 
bool optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override
 
bool getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
 Return true if get the base operand, byte offset of an instruction and the memory width. More...
 
bool getMemOperandsWithOffsetWidth (const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
 Get the base operand and byte offset of an instruction that reads/writes memory. More...
 
bool shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
 Returns true if the two given memory operations should be scheduled adjacent. More...
 
bool areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
 Return true if two MIs access different memory addresses and false otherwise. More...
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 GetInstSize - Return the number of bytes of code the specified instruction may be. More...
 
MCInst getNop () const override
 Return the noop instruction to use for a noop. More...
 
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags () const override
 
bool expandVSXMemPseudo (MachineInstr &MI) const
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
const TargetRegisterClassupdatedRC (const TargetRegisterClass *RC) const
 
bool isTOCSaveMI (const MachineInstr &MI) const
 
bool isSignOrZeroExtended (const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
 
bool isSignExtended (const MachineInstr &MI, const unsigned depth=0) const
 Return true if the output of the instruction is always a sign-extended, i.e. More...
 
bool isZeroExtended (const MachineInstr &MI, const unsigned depth=0) const
 Return true if the output of the instruction is always zero-extended, i.e. More...
 
bool convertToImmediateForm (MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
 
bool foldFrameOffset (MachineInstr &MI) const
 
bool combineRLWINM (MachineInstr &MI, MachineInstr **ToErase=nullptr) const
 
bool isADDIInstrEligibleForFolding (MachineInstr &ADDIMI, int64_t &Imm) const
 
bool isADDInstrEligibleForFolding (MachineInstr &ADDMI) const
 
bool isImmInstrEligibleForFolding (MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const
 
bool isValidToBeChangedReg (MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const
 
void fixupIsDeadOrKill (MachineInstr *StartMI, MachineInstr *EndMI, unsigned RegNo) const
 Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI]. More...
 
void replaceInstrWithLI (MachineInstr &MI, const LoadImmediateInfo &LII) const
 
void replaceInstrOperandWithImm (MachineInstr &MI, unsigned OpNo, int64_t Imm) const
 
bool instrHasImmForm (unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
 
MachineInstrgetDefMIPostRA (unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
 
bool isBDNZ (unsigned Opcode) const
 Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). More...
 
MachineInstrfindLoopInstr (MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
 Find the hardware loop instruction used to set-up the specified loop. More...
 
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfoanalyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
 Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object. More...
 

Static Public Member Functions

static bool isSameClassPhysRegCopy (unsigned Opcode)
 
static bool isVFRegister (unsigned Reg)
 
static bool isVRRegister (unsigned Reg)
 
static int getRecordFormOpcode (unsigned Opcode)
 
static unsigned getRegNumForOperand (const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
 getRegNumForOperand - some operands use different numbering schemes for the same registers. More...
 

Protected Member Functions

MachineInstrcommuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
 Commutes the operands in the given instruction. More...
 

Detailed Description

Definition at line 191 of file PPCInstrInfo.h.

Constructor & Destructor Documentation

◆ PPCInstrInfo()

PPCInstrInfo::PPCInstrInfo ( PPCSubtarget STI)
explicit

Definition at line 90 of file PPCInstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

bool PPCInstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override

◆ analyzeCompare()

bool PPCInstrInfo::analyzeCompare ( const MachineInstr MI,
Register SrcReg,
Register SrcReg2,
int64_t &  Mask,
int64_t &  Value 
) const
override

Definition at line 2352 of file PPCInstrInfo.cpp.

References llvm::BitmaskEnumDetail::Mask(), and MI.

◆ analyzeLoopForPipelining()

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > PPCInstrInfo::analyzeLoopForPipelining ( MachineBasicBlock LoopBB) const
override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

Definition at line 5438 of file PPCInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), I, isBDNZ(), MRI, and llvm::MachineBasicBlock::pred_begin().

◆ areMemAccessesTriviallyDisjoint()

bool PPCInstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr MIa,
const MachineInstr MIb 
) const
override

◆ canInsertSelect()

bool PPCInstrInfo::canInsertSelect ( const MachineBasicBlock MBB,
ArrayRef< MachineOperand Cond,
Register  DstReg,
Register  TrueReg,
Register  FalseReg,
int CondCycles,
int TrueCycles,
int FalseCycles 
) const
override

◆ ClobbersPredicate()

bool PPCInstrInfo::ClobbersPredicate ( MachineInstr MI,
std::vector< MachineOperand > &  Pred,
bool  SkipDead 
) const
override

◆ combineRLWINM()

bool PPCInstrInfo::combineRLWINM ( MachineInstr MI,
MachineInstr **  ToErase = nullptr 
) const

◆ commuteInstructionImpl()

MachineInstr * PPCInstrInfo::commuteInstructionImpl ( MachineInstr MI,
bool  NewMI,
unsigned  OpIdx1,
unsigned  OpIdx2 
) const
overrideprotected

Commutes the operands in the given instruction.

The commutable operands are specified by their indices OpIdx1 and OpIdx2.

Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

For example, we can commute rlwimi instructions, but only if the rotate amt is zero. We also have to munge the immediates a bit.

Definition at line 1144 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::RegState::Define, llvm::getDeadRegState(), llvm::getKillRegState(), MI, and llvm::MCOI::TIED_TO.

◆ convertToImmediateForm()

bool PPCInstrInfo::convertToImmediateForm ( MachineInstr MI,
MachineInstr **  KilledDef = nullptr 
) const

◆ copyPhysReg()

void PPCInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc 
) const
override

◆ CreateTargetHazardRecognizer()

ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetHazardRecognizer ( const TargetSubtargetInfo STI,
const ScheduleDAG DAG 
) const
override

CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG.

Definition at line 99 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::CreateTargetHazardRecognizer(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, and llvm::PPC::DIR_E5500.

◆ CreateTargetPostRAHazardRecognizer()

ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData II,
const ScheduleDAG DAG 
) const
override

CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG.

Definition at line 116 of file PPCInstrInfo.cpp.

References assert(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, llvm::PPC::DIR_E5500, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::MachineFunction::getSubtarget(), llvm::ScheduleDAG::MF, and llvm::ScheduleDAG::TII.

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > PPCInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

◆ expandPostRAPseudo()

bool PPCInstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override

◆ expandVSXMemPseudo()

bool PPCInstrInfo::expandVSXMemPseudo ( MachineInstr MI) const

◆ finalizeInsInstrs()

void PPCInstrInfo::finalizeInsInstrs ( MachineInstr Root,
MachineCombinerPattern P,
SmallVectorImpl< MachineInstr * > &  InsInstrs 
) const
override

◆ findCommutedOpIndices()

bool PPCInstrInfo::findCommutedOpIndices ( const MachineInstr MI,
unsigned &  SrcOpIdx1,
unsigned &  SrcOpIdx2 
) const
override

◆ findLoopInstr()

MachineInstr * PPCInstrInfo::findLoopInstr ( MachineBasicBlock PreHeader,
SmallPtrSet< MachineBasicBlock *, 8 > &  Visited 
) const

Find the hardware loop instruction used to set-up the specified loop.

On PPC, we have two instructions used to set-up the hardware loop (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) instructions to indicate the end of a loop.

Definition at line 5458 of file PPCInstrInfo.cpp.

References I, llvm::MachineBasicBlock::instrs(), and llvm::PPCSubtarget::isPPC64().

Referenced by analyzeLoopForPipelining().

◆ fixupIsDeadOrKill()

void PPCInstrInfo::fixupIsDeadOrKill ( MachineInstr StartMI,
MachineInstr EndMI,
unsigned  RegNo 
) const

Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].

Some pre-RA or post-RA transformations may violate register killed/dead flags semantics, this function can be called to fix up. Before calling this function,

  1. Ensure that RegNo liveness is killed after instruction EndMI.
  2. Ensure that there is no new definition between (StartMI, EndMI) and possible definition for RegNo is StartMI or EndMI. For pre-RA cases, definition may be StartMI through COPY, StartMI will be adjust to true definition.
  3. We can do accurate fixup for the case when all instructions between [StartMI, EndMI] are in same basic block.
  4. For the case when StartMI and EndMI are not in same basic block, we conservatively clear kill flag for all uses of RegNo for pre-RA and for post-RA, we give an assertion as without reaching definition analysis post-RA, StartMI and EndMI are hard to keep right.

Definition at line 3337 of file PPCInstrInfo.cpp.

References assert(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::numbers::e, E, llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getVRegDef(), i, Index, llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::MachineRegisterInfo::isSSA(), llvm::MachineOperand::isUse(), llvm::Register::isVirtualRegister(), MI, MRI, llvm::MachineInstr::readsWritesVirtualRegister(), llvm::MachineBasicBlock::rend(), llvm::MachineOperand::setIsDead(), and llvm::MachineOperand::setIsKill().

◆ foldFrameOffset()

bool PPCInstrInfo::foldFrameOffset ( MachineInstr MI) const

◆ FoldImmediate()

bool PPCInstrInfo::FoldImmediate ( MachineInstr UseMI,
MachineInstr DefMI,
Register  Reg,
MachineRegisterInfo MRI 
) const
override

◆ genAlternativeCodeSequence()

void PPCInstrInfo::genAlternativeCodeSequence ( MachineInstr Root,
MachineCombinerPattern  Pattern,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
SmallVectorImpl< MachineInstr * > &  DelInstrs,
DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg 
) const
override

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.

Definition at line 774 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::REASSOC_XMM_AMM_BMM, llvm::REASSOC_XY_AMM_BMM, llvm::REASSOC_XY_BAC, and llvm::REASSOC_XY_BCA.

◆ getDefMIPostRA()

MachineInstr * PPCInstrInfo::getDefMIPostRA ( unsigned  Reg,
MachineInstr MI,
bool &  SeenIntermediateUse 
) const

Definition at line 3218 of file PPCInstrInfo.cpp.

References assert(), E, getRegisterInfo(), MI, Reg, and TRI.

Referenced by foldFrameOffset(), and isValidToBeChangedReg().

◆ getExtendResourceLenLimit()

int llvm::PPCInstrInfo::getExtendResourceLenLimit ( ) const
inlineoverride

On PowerPC, we try to reassociate FMA chain which will increase instruction size.

Set extension resource length limit to 1 for edge case. Resource Length is calculated by scaled resource usage in getCycles(). Because of the division in getCycles(), it returns different cycles due to legacy scaled resource usage. So new resource length may be same with legacy or 1 bigger than legacy. We need to execlude the 1 bigger case even the resource length is not perserved for more FMA chain reassociations on PowerPC.

Definition at line 390 of file PPCInstrInfo.h.

◆ getFMAPatterns()

bool PPCInstrInfo::getFMAPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern > &  P,
bool  DoRegPressureReduce 
) const

◆ getInstrLatency()

unsigned PPCInstrInfo::getInstrLatency ( const InstrItineraryData ItinData,
const MachineInstr MI,
unsigned *  PredCost = nullptr 
) const
override

◆ getInstSizeInBytes()

unsigned PPCInstrInfo::getInstSizeInBytes ( const MachineInstr MI) const
override

GetInstSize - Return the number of bytes of code the specified instruction may be.

This returns the maximum number of bytes.

Definition at line 2871 of file PPCInstrInfo.cpp.

References get, llvm::TargetMachine::getMCAsmInfo(), llvm::StackMapOpers::getNumPatchBytes(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::MachineFunction::getTarget(), llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, and MI.

◆ getLoadOpcodeForSpill()

unsigned PPCInstrInfo::getLoadOpcodeForSpill ( const TargetRegisterClass RC) const

Definition at line 1927 of file PPCInstrInfo.cpp.

◆ getMachineCombinerPatterns()

bool PPCInstrInfo::getMachineCombinerPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern > &  P,
bool  DoRegPressureReduce 
) const
override

Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>.

All potential patterns are output in the <Pattern> array.

Definition at line 759 of file PPCInstrInfo.cpp.

References llvm::CodeGenOpt::Aggressive, getFMAPatterns(), llvm::TargetInstrInfo::getMachineCombinerPatterns(), llvm::TargetMachine::getOptLevel(), and llvm::PPCSubtarget::getTargetMachine().

◆ getMemOperandsWithOffsetWidth()

bool PPCInstrInfo::getMemOperandsWithOffsetWidth ( const MachineInstr LdSt,
SmallVectorImpl< const MachineOperand * > &  BaseOps,
int64_t &  Offset,
bool &  OffsetIsScalable,
unsigned &  Width,
const TargetRegisterInfo TRI 
) const
override

Get the base operand and byte offset of an instruction that reads/writes memory.

Definition at line 2762 of file PPCInstrInfo.cpp.

References getMemOperandWithOffsetWidth(), Offset, and TRI.

◆ getMemOperandWithOffsetWidth()

bool PPCInstrInfo::getMemOperandWithOffsetWidth ( const MachineInstr LdSt,
const MachineOperand *&  BaseOp,
int64_t &  Offset,
unsigned &  Width,
const TargetRegisterInfo TRI 
) const

◆ getNop()

MCInst PPCInstrInfo::getNop ( ) const
override

Return the noop instruction to use for a noop.

Definition at line 1264 of file PPCInstrInfo.cpp.

References llvm::WebAssembly::Nop.

◆ getOperandLatency() [1/2]

int PPCInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
const MachineInstr DefMI,
unsigned  DefIdx,
const MachineInstr UseMI,
unsigned  UseIdx 
) const
override

◆ getOperandLatency() [2/2]

int llvm::PPCInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
SDNode DefNode,
unsigned  DefIdx,
SDNode UseNode,
unsigned  UseIdx 
) const
inlineoverride

Definition at line 324 of file PPCInstrInfo.h.

◆ getRecordFormOpcode()

int PPCInstrInfo::getRecordFormOpcode ( unsigned  Opcode)
static

Definition at line 5084 of file PPCInstrInfo.cpp.

◆ getRegisterInfo()

const PPCRegisterInfo& llvm::PPCInstrInfo::getRegisterInfo ( ) const
inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 289 of file PPCInstrInfo.h.

Referenced by areMemAccessesTriviallyDisjoint(), copyPhysReg(), finalizeInsInstrs(), fixupIsDeadOrKill(), getDefMIPostRA(), getFMAPatterns(), llvm::PPCSubtarget::getRegisterInfo(), optimizeCompareInstr(), replaceInstrOperandWithImm(), shouldClusterMemOps(), and shouldReduceRegisterPressure().

◆ getRegNumForOperand()

static unsigned llvm::PPCInstrInfo::getRegNumForOperand ( const MCInstrDesc Desc,
unsigned  Reg,
unsigned  OpNo 
)
inlinestatic

getRegNumForOperand - some operands use different numbering schemes for the same registers.

For example, a VSX instruction may have any of vs0-vs63 allocated whereas an Altivec instruction could only have vs32-vs63 allocated (numbered as v0-v31). This function returns the actual register number needed for the opcode/operand number combination. The operand number argument will be useful when we need to extend this to instructions that use both Altivec and VSX numbering (for different operands).

Definition at line 662 of file PPCInstrInfo.h.

References isVFRegister(), isVRRegister(), llvm::MCInstrDesc::OpInfo, Reg, and llvm::MCOperandInfo::RegClass.

Referenced by llvm::PPCMCCodeEmitter::getMachineOpValue(), and llvm::PPCInstPrinter::printOperand().

◆ getSerializableBitmaskMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const
override

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

◆ getStoreOpcodeForSpill()

unsigned PPCInstrInfo::getStoreOpcodeForSpill ( const TargetRegisterClass RC) const

Definition at line 1921 of file PPCInstrInfo.cpp.

◆ hasLowDefLatency()

bool llvm::PPCInstrInfo::hasLowDefLatency ( const TargetSchedModel SchedModel,
const MachineInstr DefMI,
unsigned  DefIdx 
) const
inlineoverride

Definition at line 331 of file PPCInstrInfo.h.

◆ insertBranch()

unsigned PPCInstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int BytesAdded = nullptr 
) const
override

◆ insertNoop()

void PPCInstrInfo::insertNoop ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI 
) const
override

◆ insertSelect()

void PPCInstrInfo::insertSelect ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
Register  DstReg,
ArrayRef< MachineOperand Cond,
Register  TrueReg,
Register  FalseReg 
) const
override

◆ instrHasImmForm()

bool PPCInstrInfo::instrHasImmForm ( unsigned  Opc,
bool  IsVFReg,
ImmInstrInfo III,
bool  PostRA 
) const

◆ isADDIInstrEligibleForFolding()

bool PPCInstrInfo::isADDIInstrEligibleForFolding ( MachineInstr ADDIMI,
int64_t &  Imm 
) const

◆ isADDInstrEligibleForFolding()

bool PPCInstrInfo::isADDInstrEligibleForFolding ( MachineInstr ADDMI) const

Definition at line 3570 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by foldFrameOffset().

◆ isAssociativeAndCommutative()

bool PPCInstrInfo::isAssociativeAndCommutative ( const MachineInstr Inst) const
override

◆ isBDNZ()

bool PPCInstrInfo::isBDNZ ( unsigned  Opcode) const

Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).

Definition at line 5364 of file PPCInstrInfo.cpp.

References llvm::PPCISD::BDNZ, and llvm::PPCSubtarget::isPPC64().

Referenced by analyzeLoopForPipelining().

◆ isCoalescableExtInstr()

bool PPCInstrInfo::isCoalescableExtInstr ( const MachineInstr MI,
Register SrcReg,
Register DstReg,
unsigned &  SubIdx 
) const
override

Definition at line 1054 of file PPCInstrInfo.cpp.

References MI.

◆ isImmInstrEligibleForFolding()

bool PPCInstrInfo::isImmInstrEligibleForFolding ( MachineInstr MI,
unsigned &  BaseReg,
unsigned &  XFormOpcode,
int64_t &  OffsetOfImmInstr,
ImmInstrInfo III 
) const

◆ isLoadFromStackSlot()

unsigned PPCInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
override

Definition at line 1069 of file PPCInstrInfo.cpp.

References MI.

◆ isPredicated()

bool PPCInstrInfo::isPredicated ( const MachineInstr MI) const
override

Definition at line 2163 of file PPCInstrInfo.cpp.

◆ isPrefixed()

bool llvm::PPCInstrInfo::isPrefixed ( unsigned  Opcode) const
inline

Definition at line 294 of file PPCInstrInfo.h.

References get, and llvm::PPCII::Prefixed.

Referenced by llvm::PPCMCCodeEmitter::isPrefixedInstruction().

◆ isProfitableToDupForIfCvt()

bool llvm::PPCInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
BranchProbability  Probability 
) const
inlineoverride

Definition at line 498 of file PPCInstrInfo.h.

◆ isProfitableToIfCvt() [1/2]

bool llvm::PPCInstrInfo::isProfitableToIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
unsigned  ExtraPredCycles,
BranchProbability  Probability 
) const
inlineoverride

Definition at line 486 of file PPCInstrInfo.h.

◆ isProfitableToIfCvt() [2/2]

bool PPCInstrInfo::isProfitableToIfCvt ( MachineBasicBlock TMBB,
unsigned  NumT,
unsigned  ExtraT,
MachineBasicBlock FMBB,
unsigned  NumF,
unsigned  ExtraF,
BranchProbability  Probability 
) const
override

Definition at line 2154 of file PPCInstrInfo.cpp.

References MBBDefinesCTR().

◆ isProfitableToUnpredicate()

bool llvm::PPCInstrInfo::isProfitableToUnpredicate ( MachineBasicBlock TMBB,
MachineBasicBlock FMBB 
) const
inlineoverride

Definition at line 503 of file PPCInstrInfo.h.

◆ isReallyTriviallyReMaterializable()

bool PPCInstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr MI,
AAResults AA 
) const
override

Definition at line 1089 of file PPCInstrInfo.cpp.

References llvm_unreachable, MI, and llvm::PPCISD::XXSPLTI32DX.

◆ isSameClassPhysRegCopy()

static bool llvm::PPCInstrInfo::isSameClassPhysRegCopy ( unsigned  Opcode)
inlinestatic

Definition at line 298 of file PPCInstrInfo.h.

References i, and llvm::ISD::OR.

◆ isSchedulingBoundary()

bool PPCInstrInfo::isSchedulingBoundary ( const MachineInstr MI,
const MachineBasicBlock MBB,
const MachineFunction MF 
) const
override

◆ isSignExtended()

bool llvm::PPCInstrInfo::isSignExtended ( const MachineInstr MI,
const unsigned  depth = 0 
) const
inline

Return true if the output of the instruction is always a sign-extended, i.e.

0 to 31-th bits are same as 32-th bit.

Definition at line 601 of file PPCInstrInfo.h.

References isSignOrZeroExtended(), and MI.

Referenced by optimizeCompareInstr().

◆ isSignOrZeroExtended()

bool PPCInstrInfo::isSignOrZeroExtended ( const MachineInstr MI,
bool  SignExt,
const unsigned  PhiDepth 
) const

◆ isStoreToStackSlot()

unsigned PPCInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
override

Definition at line 1128 of file PPCInstrInfo.cpp.

References MI.

◆ isTOCSaveMI()

bool PPCInstrInfo::isTOCSaveMI ( const MachineInstr MI) const

◆ isValidToBeChangedReg()

bool PPCInstrInfo::isValidToBeChangedReg ( MachineInstr ADDMI,
unsigned  Index,
MachineInstr *&  ADDIMI,
int64_t &  OffsetAddi,
int64_t  OffsetImm 
) const

◆ isVFRegister()

static bool llvm::PPCInstrInfo::isVFRegister ( unsigned  Reg)
inlinestatic

Definition at line 585 of file PPCInstrInfo.h.

References Reg.

Referenced by convertToImmediateForm(), getRegNumForOperand(), and isImmInstrEligibleForFolding().

◆ isVRRegister()

static bool llvm::PPCInstrInfo::isVRRegister ( unsigned  Reg)
inlinestatic

Definition at line 588 of file PPCInstrInfo.h.

References Reg.

Referenced by getRegNumForOperand().

◆ isXFormMemOp()

bool llvm::PPCInstrInfo::isXFormMemOp ( unsigned  Opcode) const
inline

Definition at line 291 of file PPCInstrInfo.h.

References get, and llvm::PPCII::XFormMemOp.

◆ isZeroExtended()

bool llvm::PPCInstrInfo::isZeroExtended ( const MachineInstr MI,
const unsigned  depth = 0 
) const
inline

Return true if the output of the instruction is always zero-extended, i.e.

0 to 31-th bits are all zeros

Definition at line 607 of file PPCInstrInfo.h.

References isSignOrZeroExtended(), and MI.

Referenced by optimizeCompareInstr().

◆ loadRegFromStackSlot()

void PPCInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
Register  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

Definition at line 2034 of file PPCInstrInfo.cpp.

References loadRegFromStackSlotNoUpd(), MBB, MI, TRI, and updatedRC().

◆ loadRegFromStackSlotNoUpd()

void PPCInstrInfo::loadRegFromStackSlotNoUpd ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const

◆ onlyFoldImmediate()

bool PPCInstrInfo::onlyFoldImmediate ( MachineInstr UseMI,
MachineInstr DefMI,
Register  Reg 
) const

◆ optimizeCompareInstr()

bool PPCInstrInfo::optimizeCompareInstr ( MachineInstr CmpInstr,
Register  SrcReg,
Register  SrcReg2,
int64_t  Mask,
int64_t  Value,
const MachineRegisterInfo MRI 
) const
override

Definition at line 2382 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), B, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineOperand::CreateReg(), DisableCmpOpt, llvm::numbers::e, E, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), get, llvm::MachineInstr::getFlag(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getImplicitDefs(), llvm::MCInstrDesc::getImplicitUses(), llvm::PPC::getNonRecordFormOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::PPC::getPredicate(), llvm::PPC::getPredicateCondition(), llvm::PPC::getPredicateHint(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineOperand::getSubReg(), llvm::PPC::getSwappedPredicate(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneUse(), i, I, llvm::ARM_PROC::IE, llvm::MCInstrDesc::ImplicitDefs, llvm::MCInstrDesc::ImplicitUses, llvm::HexagonISD::ISEL, llvm::PPCSubtarget::isPPC64(), isSignExtended(), llvm::Register::isVirtual(), isZeroExtended(), llvm::RegState::Kill, llvm::TargetRegisterInfo::lookThruCopyLike(), llvm::BitmaskEnumDetail::Mask(), MI, llvm::MachineInstr::modifiesRegister(), MRI, llvm::MachineInstr::NoSWrap, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::MachineInstr::readsRegister(), TRI, llvm::MachineRegisterInfo::use_empty(), llvm::MachineRegisterInfo::use_instr_begin(), llvm::MachineRegisterInfo::use_instr_end(), and UseMI.

◆ PredicateInstruction()

bool PPCInstrInfo::PredicateInstruction ( MachineInstr MI,
ArrayRef< MachineOperand Pred 
) const
override

◆ removeBranch()

unsigned PPCInstrInfo::removeBranch ( MachineBasicBlock MBB,
int BytesRemoved = nullptr 
) const
override

◆ replaceInstrOperandWithImm()

void PPCInstrInfo::replaceInstrOperandWithImm ( MachineInstr MI,
unsigned  OpNo,
int64_t  Imm 
) const

Definition at line 3164 of file PPCInstrInfo.cpp.

References assert(), getRegisterInfo(), llvm::MachineOperand::isImplicit(), MI, and TRI.

◆ replaceInstrWithLI()

void PPCInstrInfo::replaceInstrWithLI ( MachineInstr MI,
const LoadImmediateInfo LII 
) const

◆ reverseBranchCondition()

bool PPCInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 2052 of file PPCInstrInfo.cpp.

References assert(), Cond, getReg(), and llvm::PPC::InvertPredicate().

◆ setSpecialOperandAttr() [1/2]

void PPCInstrInfo::setSpecialOperandAttr ( MachineInstr MI,
uint16_t  Flags 
) const
override

Definition at line 239 of file PPCInstrInfo.cpp.

References MI.

◆ setSpecialOperandAttr() [2/2]

void PPCInstrInfo::setSpecialOperandAttr ( MachineInstr OldMI1,
MachineInstr OldMI2,
MachineInstr NewMI1,
MachineInstr NewMI2 
) const
override

This is an architecture-specific helper function of reassociateOps.

Set special operand attributes for new instructions after reassociation.

Definition at line 221 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::clearFlag(), llvm::MachineInstr::getFlags(), and llvm::MachineInstr::setFlags().

◆ shouldClusterMemOps()

bool PPCInstrInfo::shouldClusterMemOps ( ArrayRef< const MachineOperand * >  BaseOps1,
ArrayRef< const MachineOperand * >  BaseOps2,
unsigned  NumLoads,
unsigned  NumBytes 
) const
override

◆ shouldReduceRegisterPressure()

bool PPCInstrInfo::shouldReduceRegisterPressure ( MachineBasicBlock MBB,
RegisterClassInfo RegClassInfo 
) const
override

◆ storeRegToStackSlot()

void PPCInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
Register  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

Definition at line 1974 of file PPCInstrInfo.cpp.

References MBB, MI, storeRegToStackSlotNoUpd(), TRI, and updatedRC().

◆ storeRegToStackSlotNoUpd()

void PPCInstrInfo::storeRegToStackSlotNoUpd ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const

◆ SubsumesPredicate()

bool PPCInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand Pred1,
ArrayRef< MachineOperand Pred2 
) const
override

◆ updatedRC()

const TargetRegisterClass * PPCInstrInfo::updatedRC ( const TargetRegisterClass RC) const

Definition at line 5078 of file PPCInstrInfo.cpp.

References llvm::PPCSubtarget::hasVSX().

Referenced by loadRegFromStackSlot(), and storeRegToStackSlot().

◆ useMachineCombiner()

bool llvm::PPCInstrInfo::useMachineCombiner ( ) const
inlineoverride

Definition at line 340 of file PPCInstrInfo.h.


The documentation for this class was generated from the following files: