LLVM  10.0.0svn
Public Member Functions | Static Public Member Functions | Protected Member Functions | List of all members
llvm::PPCInstrInfo Class Reference

#include "Target/PowerPC/PPCInstrInfo.h"

Inheritance diagram for llvm::PPCInstrInfo:
Inheritance graph
[legend]
Collaboration diagram for llvm::PPCInstrInfo:
Collaboration graph
[legend]

Public Member Functions

 PPCInstrInfo (PPCSubtarget &STI)
 
const PPCRegisterInfogetRegisterInfo () const
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
 
bool isXFormMemOp (unsigned Opcode) const
 
ScheduleHazardRecognizerCreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
 CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG. More...
 
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
 CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG. More...
 
unsigned getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
 
int getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
 
int getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
 
bool hasLowDefLatency (const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
 
bool useMachineCombiner () const override
 
bool getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
 Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>. More...
 
bool isAssociativeAndCommutative (const MachineInstr &Inst) const override
 
bool isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
bool isReallyTriviallyReMaterializable (const MachineInstr &MI, AliasAnalysis *AA) const override
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
bool findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
 
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
unsigned getStoreOpcodeForSpill (unsigned Reg, const TargetRegisterClass *RC=nullptr) const
 
unsigned getLoadOpcodeForSpill (unsigned Reg, const TargetRegisterClass *RC=nullptr) const
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override
 
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
 
bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
 
bool isPredicated (const MachineInstr &MI) const override
 
bool isUnpredicatedTerminator (const MachineInstr &MI) const override
 
bool PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
 
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
 
bool DefinesPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
 
bool isPredicable (const MachineInstr &MI) const override
 
bool analyzeCompare (const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
 
bool optimizeCompareInstr (MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
 
bool getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
 Return true if get the base operand, byte offset of an instruction and the memory width. More...
 
bool areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
 Return true if two MIs access different memory addresses and false otherwise. More...
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 GetInstSize - Return the number of bytes of code the specified instruction may be. More...
 
void getNoop (MCInst &NopInst) const override
 Return the noop instruction to use for a noop. More...
 
std::pair< unsigned, unsigneddecomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags () const override
 
bool expandVSXMemPseudo (MachineInstr &MI) const
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
const TargetRegisterClassupdatedRC (const TargetRegisterClass *RC) const
 
bool isTOCSaveMI (const MachineInstr &MI) const
 
bool isSignOrZeroExtended (const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
 
bool isSignExtended (const MachineInstr &MI, const unsigned depth=0) const
 Return true if the output of the instruction is always a sign-extended, i.e. More...
 
bool isZeroExtended (const MachineInstr &MI, const unsigned depth=0) const
 Return true if the output of the instruction is always zero-extended, i.e. More...
 
bool convertToImmediateForm (MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
 
void fixupIsDeadOrKill (MachineInstr &StartMI, MachineInstr &EndMI, unsigned RegNo) const
 Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI]. More...
 
void replaceInstrWithLI (MachineInstr &MI, const LoadImmediateInfo &LII) const
 
void replaceInstrOperandWithImm (MachineInstr &MI, unsigned OpNo, int64_t Imm) const
 
bool instrHasImmForm (unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
 
MachineInstrgetDefMIPostRA (unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
 
bool isBDNZ (unsigned Opcode) const
 Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). More...
 
MachineInstrfindLoopInstr (MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
 Find the hardware loop instruction used to set-up the specified loop. More...
 
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfoanalyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
 Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object. More...
 

Static Public Member Functions

static bool isSameClassPhysRegCopy (unsigned Opcode)
 
static bool isVFRegister (unsigned Reg)
 
static bool isVRRegister (unsigned Reg)
 
static int getRecordFormOpcode (unsigned Opcode)
 
static unsigned getRegNumForOperand (const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
 getRegNumForOperand - some operands use different numbering schemes for the same registers. More...
 

Protected Member Functions

MachineInstrcommuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
 Commutes the operands in the given instruction. More...
 

Detailed Description

Definition at line 112 of file PPCInstrInfo.h.

Constructor & Destructor Documentation

◆ PPCInstrInfo()

PPCInstrInfo::PPCInstrInfo ( PPCSubtarget STI)
explicit

Definition at line 99 of file PPCInstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

bool PPCInstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override

Definition at line 494 of file PPCInstrInfo.cpp.

◆ analyzeCompare()

bool PPCInstrInfo::analyzeCompare ( const MachineInstr MI,
unsigned SrcReg,
unsigned SrcReg2,
int &  Mask,
int &  Value 
) const
override

◆ analyzeLoopForPipelining()

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > PPCInstrInfo::analyzeLoopForPipelining ( MachineBasicBlock LoopBB) const
override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

Definition at line 4008 of file PPCInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getUniqueVRegDef(), I, isBDNZ(), MRI, and llvm::MachineBasicBlock::pred_begin().

◆ areMemAccessesTriviallyDisjoint()

bool PPCInstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr MIa,
const MachineInstr MIb 
) const
override

◆ canInsertSelect()

bool PPCInstrInfo::canInsertSelect ( const MachineBasicBlock MBB,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg,
int &  CondCycles,
int &  TrueCycles,
int &  FalseCycles 
) const
override

Definition at line 754 of file PPCInstrInfo.cpp.

◆ commuteInstructionImpl()

MachineInstr * PPCInstrInfo::commuteInstructionImpl ( MachineInstr MI,
bool  NewMI,
unsigned  OpIdx1,
unsigned  OpIdx2 
) const
overrideprotected

Commutes the operands in the given instruction.

The commutable operands are specified by their indices OpIdx1 and OpIdx2.

Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

For example, we can commute rlwimi instructions, but only if the rotate amt is zero. We also have to munge the immediates a bit.

Definition at line 367 of file PPCInstrInfo.cpp.

References assert(), llvm::BuildMI(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::RegState::Define, llvm::getDeadRegState(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), MI, llvm::MachineOperand::setImm(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), and llvm::MCOI::TIED_TO.

◆ convertToImmediateForm()

bool PPCInstrInfo::convertToImmediateForm ( MachineInstr MI,
MachineInstr **  KilledDef = nullptr 
) const

◆ copyPhysReg()

void PPCInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override

◆ CreateTargetHazardRecognizer()

ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetHazardRecognizer ( const TargetSubtargetInfo STI,
const ScheduleDAG DAG 
) const
override

CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG.

Definition at line 108 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::CreateTargetHazardRecognizer(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, and llvm::PPC::DIR_E5500.

◆ CreateTargetPostRAHazardRecognizer()

ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData II,
const ScheduleDAG DAG 
) const
override

CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG.

Definition at line 125 of file PPCInstrInfo.cpp.

References assert(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, llvm::PPC::DIR_E5500, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::MachineFunction::getSubtarget(), llvm::ScheduleDAG::MF, and llvm::ScheduleDAG::TII.

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > PPCInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

◆ DefinesPredicate()

bool PPCInstrInfo::DefinesPredicate ( MachineInstr MI,
std::vector< MachineOperand > &  Pred 
) const
override

◆ expandPostRAPseudo()

bool PPCInstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override

◆ expandVSXMemPseudo()

bool PPCInstrInfo::expandVSXMemPseudo ( MachineInstr MI) const

◆ findCommutedOpIndices()

bool PPCInstrInfo::findCommutedOpIndices ( const MachineInstr MI,
unsigned SrcOpIdx1,
unsigned SrcOpIdx2 
) const
override

◆ findLoopInstr()

MachineInstr * PPCInstrInfo::findLoopInstr ( MachineBasicBlock PreHeader,
SmallPtrSet< MachineBasicBlock *, 8 > &  Visited 
) const

Find the hardware loop instruction used to set-up the specified loop.

On PPC, we have two instructions used to set-up the hardware loop (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) instructions to indicate the end of a loop.

Definition at line 4028 of file PPCInstrInfo.cpp.

References I, and llvm::MachineBasicBlock::instrs().

Referenced by analyzeLoopForPipelining().

◆ fixupIsDeadOrKill()

void PPCInstrInfo::fixupIsDeadOrKill ( MachineInstr StartMI,
MachineInstr EndMI,
unsigned  RegNo 
) const

Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].

Some PostRA transformations may violate register killed/dead flags semantics, this function can be called to fix up. Before calling this function,

  1. Ensure that RegNo liveness is killed after instruction EndMI.
  2. Ensure that there is no new definition between (StartMI, EndMI) and possible definition for RegNo is StartMI or EndMI.
  3. Ensure that all instructions between [StartMI, EndMI] are in same basic block.

Definition at line 2452 of file PPCInstrInfo.cpp.

References assert(), llvm::numbers::e, E, llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::MachineRegisterInfo::isSSA(), llvm::MachineOperand::isUse(), MI, MRI, llvm::MachineBasicBlock::rend(), llvm::MachineOperand::setIsDead(), and llvm::MachineOperand::setIsKill().

Referenced by convertToImmediateForm(), and swapMIOperands().

◆ FoldImmediate()

bool PPCInstrInfo::FoldImmediate ( MachineInstr UseMI,
MachineInstr DefMI,
unsigned  Reg,
MachineRegisterInfo MRI 
) const
override

◆ getDefMIPostRA()

MachineInstr * PPCInstrInfo::getDefMIPostRA ( unsigned  Reg,
MachineInstr MI,
bool SeenIntermediateUse 
) const

◆ getInstrLatency()

unsigned PPCInstrInfo::getInstrLatency ( const InstrItineraryData ItinData,
const MachineInstr MI,
unsigned PredCost = nullptr 
) const
override

◆ getInstSizeInBytes()

unsigned PPCInstrInfo::getInstSizeInBytes ( const MachineInstr MI) const
override

◆ getLoadOpcodeForSpill()

unsigned PPCInstrInfo::getLoadOpcodeForSpill ( unsigned  Reg,
const TargetRegisterClass RC = nullptr 
) const

◆ getMachineCombinerPatterns()

bool PPCInstrInfo::getMachineCombinerPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern > &  P 
) const
override

Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>.

All potential patterns are output in the <Pattern> array.

Definition at line 267 of file PPCInstrInfo.cpp.

References llvm::CodeGenOpt::Aggressive, llvm::TargetInstrInfo::getMachineCombinerPatterns(), llvm::TargetMachine::getOptLevel(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getTarget(), llvm::PPCSubtarget::getTargetMachine(), llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.

◆ getMemOperandWithOffsetWidth()

bool PPCInstrInfo::getMemOperandWithOffsetWidth ( const MachineInstr LdSt,
const MachineOperand *&  BaseOp,
int64_t &  Offset,
unsigned Width,
const TargetRegisterInfo TRI 
) const

Return true if get the base operand, byte offset of an instruction and the memory width.

Width is the size of memory that is being loaded/stored (e.g. 1, 2, 4, 8).

Definition at line 4043 of file PPCInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineInstr::mayLoadOrStore(), and llvm::MachineInstr::memoperands_begin().

Referenced by areMemAccessesTriviallyDisjoint().

◆ getNoop()

void PPCInstrInfo::getNoop ( MCInst NopInst) const
override

Return the noop instruction to use for a noop.

Definition at line 487 of file PPCInstrInfo.cpp.

References llvm::MCInst::setOpcode().

◆ getOperandLatency() [1/2]

int PPCInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
const MachineInstr DefMI,
unsigned  DefIdx,
const MachineInstr UseMI,
unsigned  UseIdx 
) const
override

◆ getOperandLatency() [2/2]

int llvm::PPCInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
SDNode DefNode,
unsigned  DefIdx,
SDNode UseNode,
unsigned  UseIdx 
) const
inlineoverride

Definition at line 216 of file PPCInstrInfo.h.

◆ getRecordFormOpcode()

int PPCInstrInfo::getRecordFormOpcode ( unsigned  Opcode)
static

Definition at line 3642 of file PPCInstrInfo.cpp.

Referenced by selectI64Imm().

◆ getRegisterInfo()

const PPCRegisterInfo& llvm::PPCInstrInfo::getRegisterInfo ( ) const
inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 185 of file PPCInstrInfo.h.

Referenced by areMemAccessesTriviallyDisjoint(), copyPhysReg(), fixupIsDeadOrKill(), getDefMIPostRA(), optimizeCompareInstr(), replaceInstrOperandWithImm(), and swapMIOperands().

◆ getRegNumForOperand()

static unsigned llvm::PPCInstrInfo::getRegNumForOperand ( const MCInstrDesc Desc,
unsigned  Reg,
unsigned  OpNo 
)
inlinestatic

getRegNumForOperand - some operands use different numbering schemes for the same registers.

For example, a VSX instruction may have any of vs0-vs63 allocated whereas an Altivec instruction could only have vs32-vs63 allocated (numbered as v0-v31). This function returns the actual register number needed for the opcode/operand number combination. The operand number argument will be useful when we need to extend this to instructions that use both Altivec and VSX numbering (for different operands).

Definition at line 457 of file PPCInstrInfo.h.

References llvm::MCInstrDesc::OpInfo, Reg, and llvm::MCOperandInfo::RegClass.

Referenced by llvm::PPCMCCodeEmitter::getMachineOpValue(), and llvm::PPCInstPrinter::printOperand().

◆ getSerializableBitmaskMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const
override

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

◆ getStoreOpcodeForSpill()

unsigned PPCInstrInfo::getStoreOpcodeForSpill ( unsigned  Reg,
const TargetRegisterClass RC = nullptr 
) const

◆ hasLowDefLatency()

bool llvm::PPCInstrInfo::hasLowDefLatency ( const TargetSchedModel SchedModel,
const MachineInstr DefMI,
unsigned  DefIdx 
) const
inlineoverride

Definition at line 223 of file PPCInstrInfo.h.

◆ insertBranch()

unsigned PPCInstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int *  BytesAdded = nullptr 
) const
override

Definition at line 701 of file PPCInstrInfo.cpp.

◆ insertNoop()

void PPCInstrInfo::insertNoop ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI 
) const
override

◆ insertSelect()

void PPCInstrInfo::insertSelect ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
unsigned  DstReg,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg 
) const
override

Definition at line 791 of file PPCInstrInfo.cpp.

◆ instrHasImmForm()

bool PPCInstrInfo::instrHasImmForm ( unsigned  Opc,
bool  IsVFReg,
ImmInstrInfo III,
bool  PostRA 
) const

◆ isAssociativeAndCommutative()

bool PPCInstrInfo::isAssociativeAndCommutative ( const MachineInstr Inst) const
override

◆ isBDNZ()

bool PPCInstrInfo::isBDNZ ( unsigned  Opcode) const

◆ isCoalescableExtInstr()

bool PPCInstrInfo::isCoalescableExtInstr ( const MachineInstr MI,
unsigned SrcReg,
unsigned DstReg,
unsigned SubIdx 
) const
override

◆ isLoadFromStackSlot()

unsigned PPCInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

Definition at line 298 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ isPredicable()

bool PPCInstrInfo::isPredicable ( const MachineInstr MI) const
override

Definition at line 1589 of file PPCInstrInfo.cpp.

References B, llvm::PPCISD::BCTRL, and llvm::MachineInstr::getOpcode().

◆ isPredicated()

bool PPCInstrInfo::isPredicated ( const MachineInstr MI) const
override

Definition at line 1414 of file PPCInstrInfo.cpp.

Referenced by isUnpredicatedTerminator().

◆ isProfitableToDupForIfCvt()

bool llvm::PPCInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
BranchProbability  Probability 
) const
inlineoverride

Definition at line 325 of file PPCInstrInfo.h.

◆ isProfitableToIfCvt() [1/2]

bool llvm::PPCInstrInfo::isProfitableToIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
unsigned  ExtraPredCycles,
BranchProbability  Probability 
) const
inlineoverride

Definition at line 313 of file PPCInstrInfo.h.

◆ isProfitableToIfCvt() [2/2]

bool PPCInstrInfo::isProfitableToIfCvt ( MachineBasicBlock TMBB,
unsigned  NumT,
unsigned  ExtraT,
MachineBasicBlock FMBB,
unsigned  NumF,
unsigned  ExtraF,
BranchProbability  Probability 
) const
override

Definition at line 1405 of file PPCInstrInfo.cpp.

References MBBDefinesCTR().

◆ isProfitableToUnpredicate()

bool llvm::PPCInstrInfo::isProfitableToUnpredicate ( MachineBasicBlock TMBB,
MachineBasicBlock FMBB 
) const
inlineoverride

◆ isReallyTriviallyReMaterializable()

bool PPCInstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr MI,
AliasAnalysis AA 
) const
override

◆ isSameClassPhysRegCopy()

static bool llvm::PPCInstrInfo::isSameClassPhysRegCopy ( unsigned  Opcode)
inlinestatic

Definition at line 190 of file PPCInstrInfo.h.

References OR, and UseMI.

◆ isSignExtended()

bool llvm::PPCInstrInfo::isSignExtended ( const MachineInstr MI,
const unsigned  depth = 0 
) const
inline

Return true if the output of the instruction is always a sign-extended, i.e.

0 to 31-th bits are same as 32-th bit.

Definition at line 413 of file PPCInstrInfo.h.

Referenced by optimizeCompareInstr().

◆ isSignOrZeroExtended()

bool PPCInstrInfo::isSignOrZeroExtended ( const MachineInstr MI,
bool  SignExt,
const unsigned  PhiDepth 
) const

◆ isStoreToStackSlot()

unsigned PPCInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override

Definition at line 351 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ isTOCSaveMI()

bool PPCInstrInfo::isTOCSaveMI ( const MachineInstr MI) const

◆ isUnpredicatedTerminator()

bool PPCInstrInfo::isUnpredicatedTerminator ( const MachineInstr MI) const
override

◆ isVFRegister()

static bool llvm::PPCInstrInfo::isVFRegister ( unsigned  Reg)
inlinestatic

Definition at line 397 of file PPCInstrInfo.h.

Referenced by convertToImmediateForm(), and getDefMIPostRA().

◆ isVRRegister()

static bool llvm::PPCInstrInfo::isVRRegister ( unsigned  Reg)
inlinestatic

Definition at line 400 of file PPCInstrInfo.h.

◆ isXFormMemOp()

bool llvm::PPCInstrInfo::isXFormMemOp ( unsigned  Opcode) const
inline

Definition at line 187 of file PPCInstrInfo.h.

References llvm::PPCII::XFormMemOp.

Referenced by getLoadOpcodeForSpill(), and storeRegToStackSlot().

◆ isZeroExtended()

bool llvm::PPCInstrInfo::isZeroExtended ( const MachineInstr MI,
const unsigned  depth = 0 
) const
inline

Return true if the output of the instruction is always zero-extended, i.e.

0 to 31-th bits are all zeros

Definition at line 419 of file PPCInstrInfo.h.

Referenced by optimizeCompareInstr().

◆ loadRegFromStackSlot()

void PPCInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ optimizeCompareInstr()

bool PPCInstrInfo::optimizeCompareInstr ( MachineInstr CmpInstr,
unsigned  SrcReg,
unsigned  SrcReg2,
int  Mask,
int  Value,
const MachineRegisterInfo MRI 
) const
override

Definition at line 1635 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), B, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineInstr::clearRegisterDeads(), llvm::MachineOperand::CreateReg(), llvm::MachineInstr::definesRegister(), DisableCmpOpt, llvm::numbers::e, E, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), first, llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getImplicitDefs(), llvm::MCInstrDesc::getImplicitUses(), llvm::PPC::getNonRecordFormOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::PPC::getPredicate(), llvm::PPC::getPredicateCondition(), llvm::PPC::getPredicateHint(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineOperand::getSubReg(), llvm::PPC::getSwappedPredicate(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneUse(), I, llvm::ARM_PROC::IE, llvm::MCInstrDesc::ImplicitDefs, llvm::MCInstrDesc::ImplicitUses, llvm::PPCSubtarget::isPPC64(), isSignExtended(), llvm::Register::isVirtualRegister(), isZeroExtended(), llvm::RegState::Kill, llvm::TargetRegisterInfo::lookThruCopyLike(), MI, llvm::MachineInstr::modifiesRegister(), llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::MachineInstr::readsRegister(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), llvm::SmallVectorBase::size(), TRI, llvm::MachineRegisterInfo::use_empty(), llvm::MachineRegisterInfo::use_instr_begin(), llvm::MachineRegisterInfo::use_instr_end(), and UseMI.

◆ PredicateInstruction()

bool PPCInstrInfo::PredicateInstruction ( MachineInstr MI,
ArrayRef< MachineOperand Pred 
) const
override

◆ removeBranch()

unsigned PPCInstrInfo::removeBranch ( MachineBasicBlock MBB,
int *  BytesRemoved = nullptr 
) const
override

◆ replaceInstrOperandWithImm()

void PPCInstrInfo::replaceInstrOperandWithImm ( MachineInstr MI,
unsigned  OpNo,
int64_t  Imm 
) const

◆ replaceInstrWithLI()

void PPCInstrInfo::replaceInstrWithLI ( MachineInstr MI,
const LoadImmediateInfo LII 
) const

◆ reverseBranchCondition()

bool PPCInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 1313 of file PPCInstrInfo.cpp.

Referenced by loadRegFromStackSlot().

◆ storeRegToStackSlot()

void PPCInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ SubsumesPredicate()

bool PPCInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand Pred1,
ArrayRef< MachineOperand Pred2 
) const
override

◆ updatedRC()

const TargetRegisterClass * PPCInstrInfo::updatedRC ( const TargetRegisterClass RC) const

Definition at line 3636 of file PPCInstrInfo.cpp.

Referenced by storeRegToStackSlot().

◆ useMachineCombiner()

bool llvm::PPCInstrInfo::useMachineCombiner ( ) const
inlineoverride

Definition at line 232 of file PPCInstrInfo.h.

References llvm::ISD::FrameIndex, and P.


The documentation for this class was generated from the following files: