48#define DEBUG_TYPE "ppc-instr-info"
50#define GET_INSTRMAP_INFO
51#define GET_INSTRINFO_CTOR_DTOR
52#include "PPCGenInstrInfo.inc"
55 "Number of spillvsrrc spilled to stack as vec");
57 "Number of spillvsrrc spilled to stack as gpr");
58STATISTIC(NumGPRtoVSRSpill,
"Number of gpr spills to spillvsrrc");
60 "Number of ISELs that depend on comparison of constants converted");
62 "Number of compare-immediate instructions fed by constants");
64 "Number of record-form rotates converted to record-form andi");
68 cl::desc(
"Disable analysis for CTR loops"));
74cl::desc(
"Causes the backend to crash instead of generating a nop VSX copy"),
79 cl::desc(
"Use the old (incorrect) instruction latency calculation"));
83 cl::desc(
"register pressure factor for the transformations."));
87 cl::desc(
"enable register pressure reduce in machine combiner pass."));
90void PPCInstrInfo::anchor() {}
95 STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
96 Subtarget(STI), RI(STI.getTargetMachine()) {}
104 static_cast<const PPCSubtarget *
>(STI)->getCPUDirective();
108 static_cast<const PPCSubtarget *
>(STI)->getInstrItineraryData();
140 unsigned *PredCost)
const {
142 return PPCGenInstrInfo::getInstrLatency(ItinData,
MI, PredCost);
152 unsigned DefClass =
MI.getDesc().getSchedClass();
153 for (
unsigned i = 0, e =
MI.getNumOperands(); i != e; ++i) {
171 unsigned UseIdx)
const {
172 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData,
DefMI, DefIdx,
175 if (!
DefMI.getParent())
182 if (Reg.isVirtual()) {
185 IsRegCR =
MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
186 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
188 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
189 PPC::CRBITRCRegClass.contains(Reg);
192 if (
UseMI.isBranch() && IsRegCR) {
292#define InfoArrayIdxFMAInst 0
293#define InfoArrayIdxFAddInst 1
294#define InfoArrayIdxFMULInst 2
295#define InfoArrayIdxAddOpIdx 3
296#define InfoArrayIdxMULOpIdx 4
297#define InfoArrayIdxFSubInst 5
308 {PPC::XSMADDADP, PPC::XSADDDP, PPC::XSMULDP, 1, 2, PPC::XSSUBDP},
309 {PPC::XSMADDASP, PPC::XSADDSP, PPC::XSMULSP, 1, 2, PPC::XSSUBSP},
310 {PPC::XVMADDADP, PPC::XVADDDP, PPC::XVMULDP, 1, 2, PPC::XVSUBDP},
311 {PPC::XVMADDASP, PPC::XVADDSP, PPC::XVMULSP, 1, 2, PPC::XVSUBSP},
312 {PPC::FMADD, PPC::FADD, PPC::FMUL, 3, 1, PPC::FSUB},
313 {PPC::FMADDS, PPC::FADDS, PPC::FMULS, 3, 1, PPC::FSUBS}};
317int16_t PPCInstrInfo::getFMAOpIdxInfo(
unsigned Opcode)
const {
374 bool DoRegPressureReduce)
const {
379 auto IsAllOpsVirtualReg = [](
const MachineInstr &Instr) {
380 for (
const auto &MO : Instr.explicit_operands())
381 if (!(MO.isReg() && MO.getReg().isVirtual()))
386 auto IsReassociableAddOrSub = [&](
const MachineInstr &Instr,
399 if (!IsAllOpsVirtualReg(Instr))
411 auto IsReassociableFMA = [&](
const MachineInstr &Instr, int16_t &AddOpIdx,
412 int16_t &MulOpIdx,
bool IsLeaf) {
424 if (!IsAllOpsVirtualReg(Instr))
444 int16_t AddOpIdx = -1;
445 int16_t MulOpIdx = -1;
447 bool IsUsedOnceL =
false;
448 bool IsUsedOnceR =
false;
452 auto IsRPReductionCandidate = [&]() {
456 if (Opcode != PPC::XSMADDASP && Opcode != PPC::XSMADDADP)
461 if (IsReassociableFMA(Root, AddOpIdx, MulOpIdx,
true)) {
462 assert((MulOpIdx >= 0) &&
"mul operand index not right!");
463 Register MULRegL =
TRI->lookThruSingleUseCopyChain(
465 Register MULRegR =
TRI->lookThruSingleUseCopyChain(
467 if (!MULRegL && !MULRegR)
470 if (MULRegL && !MULRegR) {
474 }
else if (!MULRegL && MULRegR) {
486 MULInstrL =
MRI->getVRegDef(MULRegL);
487 MULInstrR =
MRI->getVRegDef(MULRegR);
494 if (DoRegPressureReduce && IsRPReductionCandidate()) {
495 assert((MULInstrL && MULInstrR) &&
"wrong register preduction candidate!");
516 if (!IsReassociableFMA(Root, AddOpIdx, MulOpIdx,
false))
519 assert((AddOpIdx >= 0) &&
"add operand index not right!");
526 if (!IsReassociableFMA(*Prev, AddOpIdx, MulOpIdx,
false))
529 assert((AddOpIdx >= 0) &&
"add operand index not right!");
534 if (IsReassociableFMA(*Leaf, AddOpIdx, MulOpIdx,
true)) {
550 assert(!InsInstrs.
empty() &&
"Instructions set to be inserted is empty!");
583 assert(isa<llvm::ConstantFP>(
C) &&
"not a valid constant!");
586 APFloat F1((dyn_cast<ConstantFP>(
C))->getValueAPF());
596 for (
auto *Inst : InsInstrs) {
598 assert(Operand.isReg() &&
"Invalid instruction in InsInstrs!");
599 if (Operand.getReg() == PPC::ZERO8) {
600 Placeholder = &Operand;
606 assert(Placeholder &&
"Placeholder does not exist!");
611 generateLoadForNewConst(ConstPoolIdx, &Root,
C->getType(), InsInstrs);
614 Placeholder->setReg(LoadNewConst);
635 if (!(Subtarget.
isPPC64() && Subtarget.hasP9Vector() &&
643 auto GetMBBPressure =
653 if (
MI.isDebugValue() ||
MI.isDebugLabel())
659 RPTracker.
recede(RegOpers);
669 unsigned VSSRCLimit =
TRI->getRegPressureSetLimit(
673 return GetMBBPressure(
MBB)[PPC::RegisterPressureSets::VSSRC] >
679 if (!
I->hasOneMemOperand())
683 return Op->isLoad() && Op->getPseudoValue() &&
687Register PPCInstrInfo::generateLoadForNewConst(
695 "Target not supported!\n");
701 Register VReg1 =
MRI->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
703 BuildMI(*MF,
MI->getDebugLoc(),
get(PPC::ADDIStocHA8), VReg1)
708 "Only float and double are supported!");
713 LoadOpcode = PPC::DFLOADf32;
715 LoadOpcode = PPC::DFLOADf64;
745 assert(
I->mayLoad() &&
"Should be a load instruction.\n");
746 for (
auto MO :
I->uses()) {
750 if (Reg == 0 || !Reg.isVirtual())
756 return (MCP->
getConstants())[MO2.getIndex()].Val.ConstVal;
763 bool DoRegPressureReduce)
const {
773 DoRegPressureReduce);
786 reassociateFMA(Root,
Pattern, InsInstrs, DelInstrs, InstrIdxForVirtReg);
791 DelInstrs, InstrIdxForVirtReg);
796void PPCInstrInfo::reassociateFMA(
807 MRI.constrainRegClass(RegC, RC);
810 int16_t
Idx = getFMAOpIdxInfo(FmaOp);
811 assert(
Idx >= 0 &&
"Root must be a FMA instruction");
813 bool IsILPReassociate =
833 Leaf =
MRI.getVRegDef(MULReg);
839 Leaf =
MRI.getVRegDef(MULReg);
845 if (IsILPReassociate)
853 MRI.constrainRegClass(Reg, RC);
854 KillFlag = Operand.
isKill();
859 bool &MulOp1KillFlag,
bool &MulOp2KillFlag,
860 bool &AddOpKillFlag) {
861 GetOperandInfo(Instr.
getOperand(FirstMulOpIdx), MulOp1, MulOp1KillFlag);
862 GetOperandInfo(Instr.
getOperand(FirstMulOpIdx + 1), MulOp2, MulOp2KillFlag);
863 GetOperandInfo(Instr.
getOperand(AddOpIdx), AddOp, AddOpKillFlag);
866 Register RegM11, RegM12, RegX, RegY, RegM21, RegM22, RegM31, RegM32, RegA11,
868 bool KillX =
false, KillY =
false, KillM11 =
false, KillM12 =
false,
869 KillM21 =
false, KillM22 =
false, KillM31 =
false, KillM32 =
false,
870 KillA11 =
false, KillA21 =
false, KillB =
false;
872 GetFMAInstrInfo(Root, RegM31, RegM32, RegB, KillM31, KillM32, KillB);
874 if (IsILPReassociate)
875 GetFMAInstrInfo(*Prev, RegM21, RegM22, RegA21, KillM21, KillM22, KillA21);
878 GetFMAInstrInfo(*Leaf, RegM11, RegM12, RegA11, KillM11, KillM12, KillA11);
879 GetOperandInfo(Leaf->
getOperand(AddOpIdx), RegX, KillX);
881 GetOperandInfo(Leaf->
getOperand(1), RegX, KillX);
882 GetOperandInfo(Leaf->
getOperand(2), RegY, KillY);
885 GetOperandInfo(Leaf->
getOperand(1), RegX, KillX);
886 GetOperandInfo(Leaf->
getOperand(2), RegY, KillY);
896 InstrIdxForVirtReg.
insert(std::make_pair(NewVRA, 0));
899 if (IsILPReassociate) {
900 NewVRB =
MRI.createVirtualRegister(RC);
901 InstrIdxForVirtReg.
insert(std::make_pair(NewVRB, 1));
906 NewVRD =
MRI.createVirtualRegister(RC);
907 InstrIdxForVirtReg.
insert(std::make_pair(NewVRD, 2));
912 Register RegMul2,
bool KillRegMul2) {
913 MI->getOperand(AddOpIdx).setReg(RegAdd);
914 MI->getOperand(AddOpIdx).setIsKill(KillAdd);
915 MI->getOperand(FirstMulOpIdx).setReg(RegMul1);
916 MI->getOperand(FirstMulOpIdx).setIsKill(KillRegMul1);
917 MI->getOperand(FirstMulOpIdx + 1).setReg(RegMul2);
918 MI->getOperand(FirstMulOpIdx + 1).setIsKill(KillRegMul2);
939 AdjustOperandOrder(MINewB, RegX, KillX, RegM21, KillM21, RegM22, KillM22);
940 AdjustOperandOrder(MINewA, RegY, KillY, RegM31, KillM31, RegM32, KillM32);
961 assert(NewVRD &&
"new FMA register not created!");
980 AdjustOperandOrder(MINewB, RegX, KillX, RegM21, KillM21, RegM22, KillM22);
981 AdjustOperandOrder(MINewD, NewVRA,
true, RegM31, KillM31, RegM32,
1007 bool KillVarReg =
false;
1010 KillVarReg = KillM31;
1013 KillVarReg = KillM32;
1037 if (!IsILPReassociate) {
1046 "Insertion instructions set should not be empty!");
1050 if (IsILPReassociate)
1058 unsigned &SubIdx)
const {
1059 switch (
MI.getOpcode()) {
1060 default:
return false;
1063 case PPC::EXTSW_32_64:
1064 SrcReg =
MI.getOperand(1).getReg();
1065 DstReg =
MI.getOperand(0).getReg();
1066 SubIdx = PPC::sub_32;
1072 int &FrameIndex)
const {
1076 if (
MI.getOperand(1).isImm() && !
MI.getOperand(1).getImm() &&
1077 MI.getOperand(2).isFI()) {
1078 FrameIndex =
MI.getOperand(2).getIndex();
1079 return MI.getOperand(0).getReg();
1089 switch (
MI.getOpcode()) {
1101 case PPC::ADDIStocHA:
1102 case PPC::ADDIStocHA8:
1104 case PPC::LOAD_STACK_GUARD:
1106 case PPC::XXLXORspz:
1107 case PPC::XXLXORdpz:
1108 case PPC::XXLEQVOnes:
1109 case PPC::XXSPLTI32DX:
1111 case PPC::XXSPLTIDP:
1115 case PPC::V_SETALLONESB:
1116 case PPC::V_SETALLONESH:
1117 case PPC::V_SETALLONES:
1120 case PPC::XXSETACCZ:
1121 case PPC::XXSETACCZW:
1128 int &FrameIndex)
const {
1130 if (
MI.getOperand(1).isImm() && !
MI.getOperand(1).getImm() &&
1131 MI.getOperand(2).isFI()) {
1132 FrameIndex =
MI.getOperand(2).getIndex();
1133 return MI.getOperand(0).getReg();
1141 unsigned OpIdx2)
const {
1145 if (
MI.getOpcode() != PPC::RLWIMI &&
MI.getOpcode() != PPC::RLWIMI_rec)
1153 if (
MI.getOperand(3).getImm() != 0)
1164 assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
1165 "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMI_rec.");
1169 unsigned SubReg1 =
MI.getOperand(1).getSubReg();
1170 unsigned SubReg2 =
MI.getOperand(2).getSubReg();
1171 bool Reg1IsKill =
MI.getOperand(1).isKill();
1172 bool Reg2IsKill =
MI.getOperand(2).isKill();
1173 bool ChangeReg0 =
false;
1179 "Expecting a two-address instruction!");
1180 assert(
MI.getOperand(0).getSubReg() == SubReg1 &&
"Tied subreg mismatch");
1186 unsigned MB =
MI.getOperand(4).getImm();
1187 unsigned ME =
MI.getOperand(5).getImm();
1191 if (MB == 0 && ME == 31)
1196 Register Reg0 = ChangeReg0 ? Reg2 :
MI.getOperand(0).getReg();
1197 bool Reg0IsDead =
MI.getOperand(0).isDead();
1198 return BuildMI(MF,
MI.getDebugLoc(),
MI.getDesc())
1207 MI.getOperand(0).setReg(Reg2);
1208 MI.getOperand(0).setSubReg(SubReg2);
1210 MI.getOperand(2).setReg(Reg1);
1211 MI.getOperand(1).setReg(Reg2);
1212 MI.getOperand(2).setSubReg(SubReg1);
1213 MI.getOperand(1).setSubReg(SubReg2);
1214 MI.getOperand(2).setIsKill(Reg1IsKill);
1215 MI.getOperand(1).setIsKill(Reg2IsKill);
1218 MI.getOperand(4).setImm((ME + 1) & 31);
1219 MI.getOperand(5).setImm((MB - 1) & 31);
1224 unsigned &SrcOpIdx1,
1225 unsigned &SrcOpIdx2)
const {
1236 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
1246 default: Opcode = PPC::NOP;
break;
1272 bool AllowModify)
const {
1273 bool isPPC64 = Subtarget.
isPPC64();
1280 if (!isUnpredicatedTerminator(*
I))
1286 if (
I->getOpcode() == PPC::B &&
1288 I->eraseFromParent();
1292 if (
I ==
MBB.
end() || !isUnpredicatedTerminator(*
I))
1301 if (
I ==
MBB.
begin() || !isUnpredicatedTerminator(*--
I)) {
1307 }
else if (LastInst.
getOpcode() == PPC::BCC) {
1315 }
else if (LastInst.
getOpcode() == PPC::BC) {
1323 }
else if (LastInst.
getOpcode() == PPC::BCn) {
1331 }
else if (LastInst.
getOpcode() == PPC::BDNZ8 ||
1342 }
else if (LastInst.
getOpcode() == PPC::BDZ8 ||
1363 if (
I !=
MBB.
begin() && isUnpredicatedTerminator(*--
I))
1367 if (SecondLastInst.
getOpcode() == PPC::BCC &&
1377 }
else if (SecondLastInst.
getOpcode() == PPC::BC &&
1387 }
else if (SecondLastInst.
getOpcode() == PPC::BCn &&
1397 }
else if ((SecondLastInst.
getOpcode() == PPC::BDNZ8 ||
1398 SecondLastInst.
getOpcode() == PPC::BDNZ) &&
1411 }
else if ((SecondLastInst.
getOpcode() == PPC::BDZ8 ||
1412 SecondLastInst.
getOpcode() == PPC::BDZ) &&
1435 I->eraseFromParent();
1444 int *BytesRemoved)
const {
1445 assert(!BytesRemoved &&
"code size not handled");
1451 if (
I->getOpcode() != PPC::B &&
I->getOpcode() != PPC::BCC &&
1452 I->getOpcode() != PPC::BC &&
I->getOpcode() != PPC::BCn &&
1453 I->getOpcode() != PPC::BDNZ8 &&
I->getOpcode() != PPC::BDNZ &&
1454 I->getOpcode() != PPC::BDZ8 &&
I->getOpcode() != PPC::BDZ)
1458 I->eraseFromParent();
1464 if (
I->getOpcode() != PPC::BCC &&
1465 I->getOpcode() != PPC::BC &&
I->getOpcode() != PPC::BCn &&
1466 I->getOpcode() != PPC::BDNZ8 &&
I->getOpcode() != PPC::BDNZ &&
1467 I->getOpcode() != PPC::BDZ8 &&
I->getOpcode() != PPC::BDZ)
1471 I->eraseFromParent();
1480 int *BytesAdded)
const {
1482 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
1484 "PPC branch conditions have two components!");
1485 assert(!BytesAdded &&
"code size not handled");
1487 bool isPPC64 = Subtarget.
isPPC64();
1495 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1496 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).
addMBB(
TBB);
1512 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1513 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).
addMBB(
TBB);
1531 Register FalseReg,
int &CondCycles,
1532 int &TrueCycles,
int &FalseCycles)
const {
1533 if (
Cond.size() != 2)
1549 RI.getCommonSubClass(
MRI.getRegClass(TrueReg),
MRI.getRegClass(FalseReg));
1554 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
1555 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
1556 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
1557 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
1577 "PPC branch conditions have two components!");
1582 RI.getCommonSubClass(
MRI.getRegClass(TrueReg),
MRI.getRegClass(FalseReg));
1583 assert(RC &&
"TrueReg and FalseReg must have overlapping register classes");
1585 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
1586 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
1588 PPC::GPRCRegClass.hasSubClassEq(RC) ||
1589 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
1590 "isel is for regular integer GPRs only");
1592 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
1595 unsigned SubIdx = 0;
1596 bool SwapOps =
false;
1597 switch (SelectPred) {
1601 SubIdx = PPC::sub_eq; SwapOps =
false;
break;
1605 SubIdx = PPC::sub_eq; SwapOps =
true;
break;
1609 SubIdx = PPC::sub_lt; SwapOps =
false;
break;
1613 SubIdx = PPC::sub_lt; SwapOps =
true;
break;
1617 SubIdx = PPC::sub_gt; SwapOps =
false;
break;
1621 SubIdx = PPC::sub_gt; SwapOps =
true;
break;
1625 SubIdx = PPC::sub_un; SwapOps =
false;
break;
1629 SubIdx = PPC::sub_un; SwapOps =
true;
break;
1634 Register FirstReg = SwapOps ? FalseReg : TrueReg,
1635 SecondReg = SwapOps ? TrueReg : FalseReg;
1640 if (
MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
1641 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
1643 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
1644 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
1646 FirstReg =
MRI.createVirtualRegister(FirstRC);
1658 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
1659 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
1660 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
1661 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
1663 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
1664 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
1665 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
1666 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
1668 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
1669 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
1670 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
1671 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
1673 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
1674 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
1675 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
1676 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
1679 assert(Ret != 4 &&
"Invalid CR bit register");
1690 if (PPC::F8RCRegClass.
contains(DestReg) &&
1691 PPC::VSRCRegClass.
contains(SrcReg)) {
1693 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
1699 }
else if (PPC::F8RCRegClass.
contains(SrcReg) &&
1700 PPC::VSRCRegClass.
contains(DestReg)) {
1702 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
1711 if (PPC::CRBITRCRegClass.
contains(SrcReg) &&
1712 PPC::GPRCRegClass.
contains(DestReg)) {
1724 }
else if (PPC::CRRCRegClass.
contains(SrcReg) &&
1725 (PPC::G8RCRegClass.
contains(DestReg) ||
1726 PPC::GPRCRegClass.
contains(DestReg))) {
1727 bool Is64Bit = PPC::G8RCRegClass.contains(DestReg);
1728 unsigned MvCode = Is64Bit ? PPC::MFOCRF8 : PPC::MFOCRF;
1729 unsigned ShCode = Is64Bit ? PPC::RLWINM8 : PPC::RLWINM;
1730 unsigned CRNum =
TRI->getEncodingValue(SrcReg);
1742 }
else if (PPC::G8RCRegClass.
contains(SrcReg) &&
1743 PPC::VSFRCRegClass.
contains(DestReg)) {
1744 assert(Subtarget.hasDirectMove() &&
1745 "Subtarget doesn't support directmove, don't know how to copy.");
1750 }
else if (PPC::VSFRCRegClass.
contains(SrcReg) &&
1751 PPC::G8RCRegClass.
contains(DestReg)) {
1752 assert(Subtarget.hasDirectMove() &&
1753 "Subtarget doesn't support directmove, don't know how to copy.");
1757 }
else if (PPC::SPERCRegClass.
contains(SrcReg) &&
1758 PPC::GPRCRegClass.
contains(DestReg)) {
1762 }
else if (PPC::GPRCRegClass.
contains(SrcReg) &&
1763 PPC::SPERCRegClass.
contains(DestReg)) {
1770 if (PPC::GPRCRegClass.
contains(DestReg, SrcReg))
1772 else if (PPC::G8RCRegClass.
contains(DestReg, SrcReg))
1774 else if (PPC::F4RCRegClass.
contains(DestReg, SrcReg))
1776 else if (PPC::CRRCRegClass.
contains(DestReg, SrcReg))
1778 else if (PPC::VRRCRegClass.
contains(DestReg, SrcReg))
1780 else if (PPC::VSRCRegClass.
contains(DestReg, SrcReg))
1790 else if (PPC::VSFRCRegClass.
contains(DestReg, SrcReg) ||
1791 PPC::VSSRCRegClass.
contains(DestReg, SrcReg))
1792 Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
1793 else if (Subtarget.pairedVectorMemops() &&
1794 PPC::VSRpRCRegClass.contains(DestReg, SrcReg)) {
1795 if (SrcReg > PPC::VSRp15)
1796 SrcReg = PPC::V0 + (SrcReg - PPC::VSRp16) * 2;
1798 SrcReg = PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2;
1799 if (DestReg > PPC::VSRp15)
1800 DestReg = PPC::V0 + (DestReg - PPC::VSRp16) * 2;
1802 DestReg = PPC::VSL0 + (DestReg - PPC::VSRp0) * 2;
1809 else if (PPC::CRBITRCRegClass.
contains(DestReg, SrcReg))
1811 else if (PPC::SPERCRegClass.
contains(DestReg, SrcReg))
1813 else if ((PPC::ACCRCRegClass.
contains(DestReg) ||
1814 PPC::UACCRCRegClass.
contains(DestReg)) &&
1815 (PPC::ACCRCRegClass.
contains(SrcReg) ||
1816 PPC::UACCRCRegClass.
contains(SrcReg))) {
1822 bool DestPrimed = PPC::ACCRCRegClass.contains(DestReg);
1823 bool SrcPrimed = PPC::ACCRCRegClass.contains(SrcReg);
1825 PPC::VSL0 + (SrcReg - (SrcPrimed ? PPC::ACC0 : PPC::UACC0)) * 4;
1827 PPC::VSL0 + (DestReg - (DestPrimed ? PPC::ACC0 : PPC::UACC0)) * 4;
1836 if (SrcPrimed && !KillSrc)
1839 }
else if (PPC::G8pRCRegClass.
contains(DestReg) &&
1840 PPC::G8pRCRegClass.
contains(SrcReg)) {
1842 unsigned DestRegIdx = DestReg - PPC::G8p0;
1843 MCRegister DestRegSub0 = PPC::X0 + 2 * DestRegIdx;
1844 MCRegister DestRegSub1 = PPC::X0 + 2 * DestRegIdx + 1;
1845 unsigned SrcRegIdx = SrcReg - PPC::G8p0;
1846 MCRegister SrcRegSub0 = PPC::X0 + 2 * SrcRegIdx;
1847 MCRegister SrcRegSub1 = PPC::X0 + 2 * SrcRegIdx + 1;
1869 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1870 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1872 }
else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1873 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1875 }
else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1877 }
else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1879 }
else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1881 }
else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1883 }
else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1885 }
else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1887 }
else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1889 }
else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1891 }
else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1893 }
else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1895 }
else if (PPC::ACCRCRegClass.hasSubClassEq(RC)) {
1896 assert(Subtarget.pairedVectorMemops() &&
1897 "Register unexpected when paired memops are disabled.");
1899 }
else if (PPC::UACCRCRegClass.hasSubClassEq(RC)) {
1900 assert(Subtarget.pairedVectorMemops() &&
1901 "Register unexpected when paired memops are disabled.");
1903 }
else if (PPC::WACCRCRegClass.hasSubClassEq(RC)) {
1904 assert(Subtarget.pairedVectorMemops() &&
1905 "Register unexpected when paired memops are disabled.");
1907 }
else if (PPC::VSRpRCRegClass.hasSubClassEq(RC)) {
1908 assert(Subtarget.pairedVectorMemops() &&
1909 "Register unexpected when paired memops are disabled.");
1911 }
else if (PPC::G8pRCRegClass.hasSubClassEq(RC)) {
1922 return OpcodesForSpill[getSpillIndex(RC)];
1928 return OpcodesForSpill[getSpillIndex(RC)];
1931void PPCInstrInfo::StoreRegToStackSlot(
1945 if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1946 PPC::CRBITRCRegClass.hasSubClassEq(RC))
1960 StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1962 for (
unsigned i = 0, e = NewMIs.
size(); i != e; ++i)
1970 NewMIs.
back()->addMemOperand(MF, MMO);
1989 unsigned DestReg,
int FrameIdx,
1998 if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1999 PPC::CRBITRCRegClass.hasSubClassEq(RC))
2018 LoadRegFromStackSlot(MF,
DL, DestReg, FrameIdx, RC, NewMIs);
2020 for (
unsigned i = 0, e = NewMIs.
size(); i != e; ++i)
2028 NewMIs.
back()->addMemOperand(MF, MMO);
2051 assert(
Cond.size() == 2 &&
"Invalid PPC branch opcode!");
2053 Cond[0].setImm(
Cond[0].getImm() == 0 ? 1 : 0);
2066 unsigned DefOpc =
DefMI.getOpcode();
2067 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
2069 if (!
DefMI.getOperand(1).isImm())
2071 if (
DefMI.getOperand(1).getImm() != 0)
2087 for (UseIdx = 0; UseIdx <
UseMI.getNumOperands(); ++UseIdx)
2088 if (
UseMI.getOperand(UseIdx).isReg() &&
2092 assert(UseIdx <
UseMI.getNumOperands() &&
"Cannot find Reg in UseMI");
2103 if (UseInfo->
RegClass != PPC::GPRC_NOR0RegClassID &&
2104 UseInfo->
RegClass != PPC::G8RC_NOX0RegClassID)
2116 bool isPPC64 = Subtarget.
isPPC64();
2117 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
2119 ZeroReg = UseInfo->
RegClass == PPC::G8RC_NOX0RegClassID ?
2120 PPC::ZERO8 : PPC::ZERO;
2125 UseMI.getOperand(UseIdx).setReg(ZeroReg);
2137 if (
MRI->use_nodbg_empty(Reg))
2138 DefMI.eraseFromParent();
2144 if (
MI.definesRegister(PPC::CTR) ||
MI.definesRegister(PPC::CTR8))
2156 unsigned NumT,
unsigned ExtraT,
2158 unsigned NumF,
unsigned ExtraF,
2181 if (
MI.getOpcode() == PPC::MFFS ||
MI.getOpcode() == PPC::MTFSF)
2188 unsigned OpC =
MI.getOpcode();
2189 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
2190 if (Pred[1].
getReg() == PPC::CTR8 || Pred[1].
getReg() == PPC::CTR) {
2191 bool isPPC64 = Subtarget.
isPPC64();
2192 MI.setDesc(
get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
2193 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
2199 MI.setDesc(
get(PPC::BCLR));
2202 MI.setDesc(
get(PPC::BCLRn));
2205 MI.setDesc(
get(PPC::BCCLR));
2207 .
addImm(Pred[0].getImm())
2212 }
else if (OpC == PPC::B) {
2213 if (Pred[1].
getReg() == PPC::CTR8 || Pred[1].
getReg() == PPC::CTR) {
2214 bool isPPC64 = Subtarget.
isPPC64();
2215 MI.setDesc(
get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
2216 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
2223 MI.removeOperand(0);
2225 MI.setDesc(
get(PPC::BC));
2231 MI.removeOperand(0);
2233 MI.setDesc(
get(PPC::BCn));
2239 MI.removeOperand(0);
2241 MI.setDesc(
get(PPC::BCC));
2243 .
addImm(Pred[0].getImm())
2249 }
else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL ||
2250 OpC == PPC::BCTRL8 || OpC == PPC::BCTRL_RM ||
2251 OpC == PPC::BCTRL8_RM) {
2252 if (Pred[1].
getReg() == PPC::CTR8 || Pred[1].
getReg() == PPC::CTR)
2255 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8 ||
2256 OpC == PPC::BCTRL_RM || OpC == PPC::BCTRL8_RM;
2257 bool isPPC64 = Subtarget.
isPPC64();
2260 MI.setDesc(
get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
2261 : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
2264 MI.setDesc(
get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
2265 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
2268 MI.setDesc(
get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
2269 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
2271 .
addImm(Pred[0].getImm())
2280 if (OpC == PPC::BCTRL_RM || OpC == PPC::BCTRL8_RM)
2292 assert(Pred1.
size() == 2 &&
"Invalid PPC first predicate");
2293 assert(Pred2.
size() == 2 &&
"Invalid PPC second predicate");
2295 if (Pred1[1].
getReg() == PPC::CTR8 || Pred1[1].
getReg() == PPC::CTR)
2297 if (Pred2[1].
getReg() == PPC::CTR8 || Pred2[1].
getReg() == PPC::CTR)
2322 std::vector<MachineOperand> &Pred,
2323 bool SkipDead)
const {
2331 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
2332 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
2336 for (
unsigned c = 0; c < std::size(RCs) && !Found; ++c) {
2339 if (MO.isDef() && RC->
contains(MO.getReg())) {
2343 }
else if (MO.isRegMask()) {
2345 if (MO.clobbersPhysReg(R)) {
2358 int64_t &
Value)
const {
2359 unsigned Opc =
MI.getOpcode();
2362 default:
return false;
2367 SrcReg =
MI.getOperand(1).getReg();
2369 Value =
MI.getOperand(2).getImm();
2378 SrcReg =
MI.getOperand(1).getReg();
2379 SrcReg2 =
MI.getOperand(2).getReg();
2398 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
2410 bool isPPC64 = Subtarget.
isPPC64();
2411 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
2412 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
2413 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
2422 if (!
MI)
return false;
2424 bool equalityOnly =
false;
2427 if (is32BitSignedCompare) {
2433 }
else if (is32BitUnsignedCompare) {
2438 equalityOnly =
true;
2442 equalityOnly = is64BitUnsignedCompare;
2444 equalityOnly = is32BitUnsignedCompare;
2450 I =
MRI->use_instr_begin(CRReg), IE =
MRI->use_instr_end();
2462 if (SubIdx != PPC::sub_eq)
2474 bool FoundUse =
false;
2476 J =
MRI->use_instr_begin(CRReg), JE =
MRI->use_instr_end();
2503 else if (
Value != 0) {
2512 if (equalityOnly || !
MRI->hasOneUse(CRReg))
2522 int16_t Immed = (int16_t)
Value;
2556 for (;
I !=
E && !noSub; --
I) {
2570 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
2571 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
2572 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
2594 int MIOpC =
MI->getOpcode();
2595 if (MIOpC == PPC::ANDI_rec || MIOpC == PPC::ANDI8_rec ||
2596 MIOpC == PPC::ANDIS_rec || MIOpC == PPC::ANDIS8_rec)
2599 NewOpC = PPC::getRecordFormOpcode(MIOpC);
2617 if (!equalityOnly && (NewOpC == PPC::SUBF_rec || NewOpC == PPC::SUBF8_rec) &&
2627 bool ShouldSwap =
false;
2628 if (Sub &&
Value == 0) {
2634 ShouldSwap = !ShouldSwap;
2639 I =
MRI->use_instr_begin(CRReg), IE =
MRI->use_instr_end();
2647 "Invalid predicate for equality-only optimization");
2654 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
2655 "Invalid CR bit for equality-only optimization");
2657 if (NewSubReg == PPC::sub_lt)
2658 NewSubReg = PPC::sub_gt;
2659 else if (NewSubReg == PPC::sub_gt)
2660 NewSubReg = PPC::sub_lt;
2668 "Non-zero immediate support and ShouldSwap"
2669 "may conflict in updating predicate");
2677 BuildMI(*
MI->getParent(), std::next(MII),
MI->getDebugLoc(),
2678 get(TargetOpcode::COPY), CRReg)
2683 MI->clearRegisterDeads(PPC::CR0);
2685 if (MIOpC != NewOpC) {
2695 if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
2696 Register GPRRes =
MI->getOperand(0).getReg();
2697 int64_t SH =
MI->getOperand(2).getImm();
2698 int64_t MB =
MI->getOperand(3).getImm();
2699 int64_t ME =
MI->getOperand(4).getImm();
2702 bool MBInLoHWord = MB >= 16;
2703 bool MEInLoHWord = ME >= 16;
2706 if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
2707 Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2709 Mask >>= MBInLoHWord ? 0 : 16;
2710 NewOpC = MIOpC == PPC::RLWINM
2711 ? (MBInLoHWord ? PPC::ANDI_rec : PPC::ANDIS_rec)
2712 : (MBInLoHWord ? PPC::ANDI8_rec : PPC::ANDIS8_rec);
2713 }
else if (
MRI->use_empty(GPRRes) && (ME == 31) &&
2714 (ME - MB + 1 == SH) && (MB >= 16)) {
2718 Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
2720 NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIS_rec : PPC::ANDIS8_rec;
2723 if (Mask != ~0LLU) {
2724 MI->removeOperand(4);
2725 MI->removeOperand(3);
2726 MI->getOperand(2).setImm(Mask);
2727 NumRcRotatesConvertedToRcAnd++;
2729 }
else if (MIOpC == PPC::RLDICL &&
MI->getOperand(2).getImm() == 0) {
2730 int64_t MB =
MI->getOperand(3).getImm();
2732 uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2733 NewOpC = PPC::ANDI8_rec;
2734 MI->removeOperand(3);
2735 MI->getOperand(2).setImm(Mask);
2736 NumRcRotatesConvertedToRcAnd++;
2741 MI->setDesc(NewDesc);
2744 if (!
MI->definesRegister(ImpDef)) {
2745 MI->addOperand(*
MI->getParent()->getParent(),
2750 if (!
MI->readsRegister(ImpUse)) {
2751 MI->addOperand(*
MI->getParent()->getParent(),
2756 assert(
MI->definesRegister(PPC::CR0) &&
2757 "Record-form instruction does not define cr0?");
2762 for (
unsigned i = 0, e = PredsToUpdate.
size(); i < e; i++)
2763 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
2765 for (
unsigned i = 0, e = SubRegsToUpdate.
size(); i < e; i++)
2766 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
2777 int64_t CmpMask, CmpValue;
2782 if (CmpValue || !CmpMask || SrcReg2)
2790 if (Opc == PPC::CMPLWI || Opc == PPC::CMPLDI)
2797 if (Subtarget.
isPPC64() && Opc == PPC::CMPWI)
2804 bool SrcRegHasOtherUse =
false;
2811 if (CRReg != PPC::CR0)
2815 bool SeenUseOfCRReg =
false;
2816 bool IsCRRegKilled =
false;
2817 if (!isRegElgibleForForwarding(RegMO, *SrcMI, CmpMI,
false, IsCRRegKilled,
2823 int NewOpC = PPC::getRecordFormOpcode(SrcMIOpc);
2841 "Record-form instruction does not define cr0?");
2852 int64_t &
Offset,
bool &OffsetIsScalable,
unsigned &Width,
2855 OffsetIsScalable =
false;
2890 case PPC::DFSTOREf64:
2891 return FirstOpc == SecondOpc;
2897 return SecondOpc == PPC::STW || SecondOpc == PPC::STW8;
2904 unsigned NumBytes)
const {
2910 "Only base registers and frame indices are supported.");
2928 unsigned FirstOpc = FirstLdSt.
getOpcode();
2929 unsigned SecondOpc = SecondLdSt.
getOpcode();
2941 int64_t Offset1 = 0, Offset2 = 0;
2942 unsigned Width1 = 0, Width2 = 0;
2949 assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 &&
2950 "getMemOperandWithOffsetWidth return incorrect base op");
2952 assert(Offset1 <= Offset2 &&
"Caller should have ordered offsets.");
2953 return Offset1 + Width1 == Offset2;
2960 unsigned Opcode =
MI.getOpcode();
2962 if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) {
2964 const char *AsmStr =
MI.getOperand(0).getSymbolName();
2966 }
else if (Opcode == TargetOpcode::STACKMAP) {
2969 }
else if (Opcode == TargetOpcode::PATCHPOINT) {
2973 return get(Opcode).getSize();
2977std::pair<unsigned, unsigned>
2980 return std::make_pair(TF & Mask, TF & ~Mask);
2985 using namespace PPCII;
2986 static const std::pair<unsigned, const char *> TargetFlags[] = {
2989 {MO_TPREL_LO,
"ppc-tprel-lo"},
2990 {MO_TPREL_HA,
"ppc-tprel-ha"},
2991 {MO_DTPREL_LO,
"ppc-dtprel-lo"},
2992 {MO_TLSLD_LO,
"ppc-tlsld-lo"},
2993 {MO_TOC_LO,
"ppc-toc-lo"},
2994 {MO_TLS,
"ppc-tls"}};
3000 using namespace PPCII;
3001 static const std::pair<unsigned, const char *> TargetFlags[] = {
3002 {MO_PLT,
"ppc-plt"},
3003 {MO_PIC_FLAG,
"ppc-pic"},
3004 {MO_PCREL_FLAG,
"ppc-pcrel"},
3005 {MO_GOT_FLAG,
"ppc-got"},
3006 {MO_PCREL_OPT_FLAG,
"ppc-opt-pcrel"},
3007 {MO_TLSGD_FLAG,
"ppc-tlsgd"},
3008 {MO_TLSLD_FLAG,
"ppc-tlsld"},
3009 {MO_TPREL_FLAG,
"ppc-tprel"},
3010 {MO_TLSGDM_FLAG,
"ppc-tlsgdm"},
3011 {MO_GOT_TLSGD_PCREL_FLAG,
"ppc-got-tlsgd-pcrel"},
3012 {MO_GOT_TLSLD_PCREL_FLAG,
"ppc-got-tlsld-pcrel"},
3013 {MO_GOT_TPREL_PCREL_FLAG,
"ppc-got-tprel-pcrel"}};
3024 unsigned UpperOpcode, LowerOpcode;
3025 switch (
MI.getOpcode()) {
3026 case PPC::DFLOADf32:
3027 UpperOpcode = PPC::LXSSP;
3028 LowerOpcode = PPC::LFS;
3030 case PPC::DFLOADf64:
3031 UpperOpcode = PPC::LXSD;
3032 LowerOpcode = PPC::LFD;
3034 case PPC::DFSTOREf32:
3035 UpperOpcode = PPC::STXSSP;
3036 LowerOpcode = PPC::STFS;
3038 case PPC::DFSTOREf64:
3039 UpperOpcode = PPC::STXSD;
3040 LowerOpcode = PPC::STFD;
3042 case PPC::XFLOADf32:
3043 UpperOpcode = PPC::LXSSPX;
3044 LowerOpcode = PPC::LFSX;
3046 case PPC::XFLOADf64:
3047 UpperOpcode = PPC::LXSDX;
3048 LowerOpcode = PPC::LFDX;
3050 case PPC::XFSTOREf32:
3051 UpperOpcode = PPC::STXSSPX;
3052 LowerOpcode = PPC::STFSX;
3054 case PPC::XFSTOREf64:
3055 UpperOpcode = PPC::STXSDX;
3056 LowerOpcode = PPC::STFDX;
3059 UpperOpcode = PPC::LXSIWAX;
3060 LowerOpcode = PPC::LFIWAX;
3063 UpperOpcode = PPC::LXSIWZX;
3064 LowerOpcode = PPC::LFIWZX;
3067 UpperOpcode = PPC::STXSIWX;
3068 LowerOpcode = PPC::STFIWX;
3074 Register TargetReg =
MI.getOperand(0).getReg();
3076 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
3077 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
3078 Opcode = LowerOpcode;
3080 Opcode = UpperOpcode;
3081 MI.setDesc(
get(Opcode));
3090 auto &
MBB = *
MI.getParent();
3091 auto DL =
MI.getDebugLoc();
3093 switch (
MI.getOpcode()) {
3094 case PPC::BUILD_UACC: {
3097 if (ACC - PPC::ACC0 != UACC - PPC::UACC0) {
3098 MCRegister SrcVSR = PPC::VSL0 + (UACC - PPC::UACC0) * 4;
3099 MCRegister DstVSR = PPC::VSL0 + (ACC - PPC::ACC0) * 4;
3103 for (
int VecNo = 0; VecNo < 4; VecNo++)
3105 .addReg(SrcVSR + VecNo)
3113 case PPC::KILL_PAIR: {
3114 MI.setDesc(
get(PPC::UNENCODED_NOP));
3115 MI.removeOperand(1);
3116 MI.removeOperand(0);
3119 case TargetOpcode::LOAD_STACK_GUARD: {
3121 "Only Linux target is expected to contain LOAD_STACK_GUARD");
3122 const int64_t
Offset = Subtarget.
isPPC64() ? -0x7010 : -0x7008;
3123 const unsigned Reg = Subtarget.
isPPC64() ? PPC::X13 : PPC::R2;
3124 MI.setDesc(
get(Subtarget.
isPPC64() ? PPC::LD : PPC::LWZ));
3130 case PPC::DFLOADf32:
3131 case PPC::DFLOADf64:
3132 case PPC::DFSTOREf32:
3133 case PPC::DFSTOREf64: {
3134 assert(Subtarget.hasP9Vector() &&
3135 "Invalid D-Form Pseudo-ops on Pre-P9 target.");
3138 "D-form op must have register and immediate operands");
3141 case PPC::XFLOADf32:
3142 case PPC::XFSTOREf32:
3146 assert(Subtarget.hasP8Vector() &&
3147 "Invalid X-Form Pseudo-ops on Pre-P8 target.");
3148 assert(
MI.getOperand(2).isReg() &&
MI.getOperand(1).isReg() &&
3149 "X-form op must have register and register operands");
3152 case PPC::XFLOADf64:
3153 case PPC::XFSTOREf64: {
3154 assert(Subtarget.hasVSX() &&
3155 "Invalid X-Form Pseudo-ops on target that has no VSX.");
3156 assert(
MI.getOperand(2).isReg() &&
MI.getOperand(1).isReg() &&
3157 "X-form op must have register and register operands");
3160 case PPC::SPILLTOVSR_LD: {
3161 Register TargetReg =
MI.getOperand(0).getReg();
3162 if (PPC::VSFRCRegClass.
contains(TargetReg)) {
3163 MI.setDesc(
get(PPC::DFLOADf64));
3167 MI.setDesc(
get(PPC::LD));
3170 case PPC::SPILLTOVSR_ST: {
3172 if (PPC::VSFRCRegClass.
contains(SrcReg)) {
3173 NumStoreSPILLVSRRCAsVec++;
3174 MI.setDesc(
get(PPC::DFSTOREf64));
3177 NumStoreSPILLVSRRCAsGpr++;
3178 MI.setDesc(
get(PPC::STD));
3182 case PPC::SPILLTOVSR_LDX: {
3183 Register TargetReg =
MI.getOperand(0).getReg();
3184 if (PPC::VSFRCRegClass.
contains(TargetReg))
3185 MI.setDesc(
get(PPC::LXSDX));
3187 MI.setDesc(
get(PPC::LDX));
3190 case PPC::SPILLTOVSR_STX: {
3192 if (PPC::VSFRCRegClass.
contains(SrcReg)) {
3193 NumStoreSPILLVSRRCAsVec++;
3194 MI.setDesc(
get(PPC::STXSDX));
3196 NumStoreSPILLVSRRCAsGpr++;
3197 MI.setDesc(
get(PPC::STDX));
3203 case PPC::CFENCE8: {
3204 auto Val =
MI.getOperand(0).getReg();
3210 MI.setDesc(
get(PPC::ISYNC));
3211 MI.removeOperand(0);
3222static unsigned selectReg(int64_t Imm1, int64_t Imm2,
unsigned CompareOpc,
3223 unsigned TrueReg,
unsigned FalseReg,
3224 unsigned CRSubReg) {
3226 if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
3230 return Imm1 < Imm2 ? TrueReg : FalseReg;
3232 return Imm1 > Imm2 ? TrueReg : FalseReg;
3234 return Imm1 == Imm2 ? TrueReg : FalseReg;
3238 else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
3246 return Imm1 == Imm2 ? TrueReg : FalseReg;
3249 return PPC::NoRegister;
3254 int64_t Imm)
const {
3255 assert(
MI.getOperand(OpNo).isReg() &&
"Operand must be a REG");
3257 Register InUseReg =
MI.getOperand(OpNo).getReg();
3258 MI.getOperand(OpNo).ChangeToImmediate(Imm);
3266 int UseOpIdx =
MI.findRegisterUseOperandIdx(InUseReg,
false,
TRI);
3286 int OperandToKeep = LII.
SetCR ? 1 : 0;
3287 for (
int i =
MI.getNumOperands() - 1; i > OperandToKeep; i--)
3288 MI.removeOperand(i);
3292 MI.setDesc(
get(LII.
Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec));
3307 bool &SeenIntermediateUse)
const {
3308 assert(!
MI.getParent()->getParent()->getRegInfo().isSSA() &&
3309 "Should be called after register allocation.");
3313 SeenIntermediateUse =
false;
3314 for (; It !=
E; ++It) {
3315 if (It->modifiesRegister(Reg,
TRI))
3317 if (It->readsRegister(Reg,
TRI))
3318 SeenIntermediateUse =
true;
3326 int64_t Imm)
const {
3328 "Register should be in non-SSA form after RA");
3329 bool isPPC64 = Subtarget.
isPPC64();
3333 if (isInt<16>(Imm)) {
3335 }
else if (isInt<32>(Imm)) {
3343 assert(isPPC64 &&
"Materializing 64-bit immediate to single register is "
3344 "only supported in PPC64");
3346 if ((Imm >> 32) & 0xFFFF)
3349 .
addImm((Imm >> 32) & 0xFFFF);
3356 .
addImm((Imm >> 16) & 0xFFFF);
3366 unsigned &OpNoForForwarding,
3367 bool &SeenIntermediateUse)
const {
3368 OpNoForForwarding = ~0U;
3376 for (
int i = 1, e =
MI.getNumOperands(); i < e; i++) {
3377 if (!
MI.getOperand(i).isReg())
3380 if (!Reg.isVirtual())
3385 if (DefMIForTrueReg->
getOpcode() == PPC::LI ||
3386 DefMIForTrueReg->
getOpcode() == PPC::LI8 ||
3387 DefMIForTrueReg->
getOpcode() == PPC::ADDI ||
3388 DefMIForTrueReg->
getOpcode() == PPC::ADDI8) {
3389 OpNoForForwarding = i;
3390 DefMI = DefMIForTrueReg;
3405 unsigned Opc =
MI.getOpcode();
3406 bool ConvertibleImmForm =
3407 Opc == PPC::CMPWI || Opc == PPC::CMPLWI || Opc == PPC::CMPDI ||
3408 Opc == PPC::CMPLDI || Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
3409 Opc == PPC::ORI || Opc == PPC::ORI8 || Opc == PPC::XORI ||
3410 Opc == PPC::XORI8 || Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec ||
3411 Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
3412 Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8 ||
3413 Opc == PPC::RLWINM8_rec;
3414 bool IsVFReg = (
MI.getNumOperands() &&
MI.getOperand(0).isReg())
3421 if ((Opc == PPC::OR || Opc == PPC::OR8) &&
3422 MI.getOperand(1).getReg() ==
MI.getOperand(2).getReg())
3424 for (
int i = 1, e =
MI.getNumOperands(); i <
e; i++) {
3426 SeenIntermediateUse =
false;
3443 OpNoForForwarding = i;
3450 return OpNoForForwarding == ~0
U ? nullptr :
DefMI;
3453unsigned PPCInstrInfo::getSpillTarget()
const {
3456 bool IsP10Variant = Subtarget.isISA3_1() || Subtarget.pairedVectorMemops();
3457 return Subtarget.isISAFuture() ? 3 : IsP10Variant ?
3458 2 : Subtarget.hasP9Vector() ?
3471 unsigned RegNo)
const {
3478 MRI.clearKillFlags(RegNo);
3484 "Instructions are not in same basic block");
3493 "Must be a virtual register");
3495 StartMI =
MRI.getVRegDef(RegNo);
3499 bool IsKillSet =
false;
3512 if (UseIndex != -1) {
3520 clearOperandKillInfo(*EndMI, i);
3529 for (; It !=
E; ++It) {
3531 if (It->isDebugInstr() || It->isPosition())
3537 for (
int i = 0, e = It->getNumOperands(); i != e; ++i)
3538 clearOperandKillInfo(*It, i);
3543 if ((MO = It->findRegisterUseOperand(RegNo,
false, &
getRegisterInfo()))) {
3548 }
else if ((MO = It->findRegisterDefOperand(RegNo,
false,
true,
3551 assert(&*It == StartMI &&
"No new def between StartMI and EndMI.");
3557 if ((&*It) == StartMI)
3562 "RegNo should be killed or dead");
3592 bool PostRA = !
MRI->isSSA();
3598 unsigned ToBeDeletedReg = 0;
3599 int64_t OffsetImm = 0;
3600 unsigned XFormOpcode = 0;
3608 bool OtherIntermediateUse =
false;
3612 if (OtherIntermediateUse || !ADDMI)
3619 unsigned ScaleRegIdx = 0;
3620 int64_t OffsetAddi = 0;
3634 assert(ADDIMI &&
"There should be ADDIMI for valid ToBeChangedReg.");
3639 for (
auto It = ++Start; It !=
End; It++)
3648 (ScaleReg == PPC::R0 || ScaleReg == PPC::X0))
3653 if (NewDefFor(ToBeChangedReg, *ADDMI,
MI) || NewDefFor(ScaleReg, *ADDMI,
MI))
3669 MI.setDesc(
get(XFormOpcode));
3671 .ChangeToRegister(ScaleReg,
false,
false,
3675 .ChangeToRegister(ToBeChangedReg,
false,
false,
true);
3687 int64_t &Imm)
const {
3691 if (Opc != PPC::ADDI && Opc != PPC::ADDI8)
3707 return Opc == PPC::ADD4 || Opc == PPC::ADD8;
3711 unsigned &ToBeDeletedReg,
3712 unsigned &XFormOpcode,
3716 if (!
MI.mayLoadOrStore())
3719 unsigned Opc =
MI.getOpcode();
3724 if (XFormOpcode == PPC::INSTRUCTION_LIST_END)
3738 if (!ImmOperand.
isImm())
3741 assert(RegOperand.
isReg() &&
"Instruction format is not right");
3744 if (!RegOperand.
isKill())
3747 ToBeDeletedReg = RegOperand.
getReg();
3748 OffsetImm = ImmOperand.
getImm();
3755 int64_t &OffsetAddi,
3756 int64_t OffsetImm)
const {
3763 bool OtherIntermediateUse =
false;
3784 if (OtherIntermediateUse || !ADDIMI)
3790 if (isInt<16>(OffsetAddi + OffsetImm))
3802 bool PostRA = !
MRI->isSSA();
3803 bool SeenIntermediateUse =
true;
3804 unsigned ForwardingOperand = ~0U;
3806 SeenIntermediateUse);
3809 assert(ForwardingOperand <
MI.getNumOperands() &&
3810 "The forwarding operand needs to be valid at this point");
3811 bool IsForwardingOperandKilled =
MI.getOperand(ForwardingOperand).isKill();
3812 bool KillFwdDefMI = !SeenIntermediateUse && IsForwardingOperandKilled;
3813 if (KilledDef && KillFwdDefMI)
3819 PPC::INSTRUCTION_LIST_END &&
3820 transformToNewImmFormFedByAdd(
MI, *
DefMI, ForwardingOperand))
3824 bool IsVFReg =
MI.getOperand(0).isReg()
3832 transformToImmFormFedByAdd(
MI, III, ForwardingOperand, *
DefMI,
3839 transformToImmFormFedByLI(
MI, III, ForwardingOperand, *
DefMI))
3844 if (!HasImmForm && simplifyToLI(
MI, *
DefMI, ForwardingOperand, KilledDef))
3853 Register FoldingReg =
MI.getOperand(1).getReg();
3857 if (SrcMI->
getOpcode() != PPC::RLWINM &&
3858 SrcMI->
getOpcode() != PPC::RLWINM_rec &&
3862 assert((
MI.getOperand(2).isImm() &&
MI.getOperand(3).isImm() &&
3865 "Invalid PPC::RLWINM Instruction!");
3873 assert((MEMI < 32 && MESrc < 32 && MBMI < 32 && MBSrc < 32) &&
3874 "Invalid PPC::RLWINM Instruction!");
3896 bool SrcMaskFull = (MBSrc - MESrc == 1) || (MBSrc == 0 && MESrc == 31);
3899 if ((MBMI > MEMI) && !SrcMaskFull)
3909 APInt RotatedSrcMask = MaskSrc.
rotl(SHMI);
3910 APInt FinalMask = RotatedSrcMask & MaskMI;
3912 bool Simplified =
false;
3915 if (FinalMask.
isZero()) {
3917 (
MI.getOpcode() == PPC::RLWINM8 ||
MI.getOpcode() == PPC::RLWINM8_rec);
3922 if (
MI.getOpcode() == PPC::RLWINM ||
MI.getOpcode() == PPC::RLWINM8) {
3924 MI.removeOperand(4);
3925 MI.removeOperand(3);
3926 MI.removeOperand(2);
3927 MI.getOperand(1).ChangeToImmediate(0);
3928 MI.setDesc(
get(Is64Bit ? PPC::LI8 : PPC::LI));
3931 MI.removeOperand(4);
3932 MI.removeOperand(3);
3933 MI.getOperand(2).setImm(0);
3934 MI.setDesc(
get(Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec));
3937 MI.getOperand(1).setIsKill(
true);
3941 MI.getOperand(1).setIsKill(
false);
3957 uint16_t NewSH = (SHSrc + SHMI) % 32;
3958 MI.getOperand(2).setImm(NewSH);
3961 MI.getOperand(3).setImm(NewMB);
3962 MI.getOperand(4).setImm(NewME);
3966 MI.getOperand(1).setIsKill(
true);
3970 MI.getOperand(1).setIsKill(
false);
3975 if (Simplified &
MRI->use_nodbg_empty(FoldingReg) &&
4000 default:
return false;
4008 III.
ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
4017 III.
ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
4033 III.
ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
4041 III.
ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
4049 III.
ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
4069 case PPC::OR: III.
ImmOpcode = PPC::ORI;
break;
4070 case PPC::OR8: III.
ImmOpcode = PPC::ORI8;
break;
4071 case PPC::XOR: III.
ImmOpcode = PPC::XORI;
break;
4072 case PPC::XOR8: III.
ImmOpcode = PPC::XORI8;
break;
4077 case PPC::RLWNM_rec:
4078 case PPC::RLWNM8_rec:
4098 if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 || Opc == PPC::RLWNM_rec ||
4099 Opc == PPC::RLWNM8_rec)
4105 case PPC::RLWNM: III.
ImmOpcode = PPC::RLWINM;
break;
4106 case PPC::RLWNM8: III.
ImmOpcode = PPC::RLWINM8;
break;
4107 case PPC::RLWNM_rec:
4110 case PPC::RLWNM8_rec:
4113 case PPC::SLW: III.
ImmOpcode = PPC::RLWINM;
break;
4114 case PPC::SLW8: III.
ImmOpcode = PPC::RLWINM8;
break;
4121 case PPC::SRW: III.
ImmOpcode = PPC::RLWINM;
break;
4122 case PPC::SRW8: III.
ImmOpcode = PPC::RLWINM8;
break;
4142 case PPC::RLDCL_rec:
4144 case PPC::RLDCR_rec:
4160 if (Opc == PPC::RLDCL || Opc == PPC::RLDCL_rec || Opc == PPC::RLDCR ||
4161 Opc == PPC::RLDCR_rec)
4167 case PPC::RLDCL: III.
ImmOpcode = PPC::RLDICL;
break;
4168 case PPC::RLDCL_rec:
4171 case PPC::RLDCR: III.
ImmOpcode = PPC::RLDICR;
break;
4172 case PPC::RLDCR_rec:
4175 case PPC::SLD: III.
ImmOpcode = PPC::RLDICR;
break;
4179 case PPC::SRD: III.
ImmOpcode = PPC::RLDICL;
break;
4226 case PPC::LBZX: III.
ImmOpcode = PPC::LBZ;
break;
4227 case PPC::LBZX8: III.
ImmOpcode = PPC::LBZ8;
break;
4228 case PPC::LHZX: III.
ImmOpcode = PPC::LHZ;
break;
4229 case PPC::LHZX8: III.
ImmOpcode = PPC::LHZ8;
break;
4230 case PPC::LHAX: III.
ImmOpcode = PPC::LHA;
break;
4231 case PPC::LHAX8: III.
ImmOpcode = PPC::LHA8;
break;
4232 case PPC::LWZX: III.
ImmOpcode = PPC::LWZ;
break;
4233 case PPC::LWZX8: III.
ImmOpcode = PPC::LWZ8;
break;
4239 case PPC::LFSX: III.
ImmOpcode = PPC::LFS;
break;
4240 case PPC::LFDX: III.
ImmOpcode = PPC::LFD;
break;
4241 case PPC::STBX: III.
ImmOpcode = PPC::STB;
break;
4242 case PPC::STBX8: III.
ImmOpcode = PPC::STB8;
break;
4243 case PPC::STHX: III.
ImmOpcode = PPC::STH;
break;
4244 case PPC::STHX8: III.
ImmOpcode = PPC::STH8;
break;
4245 case PPC::STWX: III.
ImmOpcode = PPC::STW;
break;
4246 case PPC::STWX8: III.
ImmOpcode = PPC::STW8;
break;
4251 case PPC::STFSX: III.
ImmOpcode = PPC::STFS;
break;
4252 case PPC::STFDX: III.
ImmOpcode = PPC::STFD;
break;
4284 case PPC::LBZUX: III.
ImmOpcode = PPC::LBZU;
break;
4285 case PPC::LBZUX8: III.
ImmOpcode = PPC::LBZU8;
break;
4286 case PPC::LHZUX: III.
ImmOpcode = PPC::LHZU;
break;
4287 case PPC::LHZUX8: III.
ImmOpcode = PPC::LHZU8;
break;
4288 case PPC::LHAUX: III.
ImmOpcode = PPC::LHAU;
break;
4289 case PPC::LHAUX8: III.
ImmOpcode = PPC::LHAU8;
break;
4290 case PPC::LWZUX: III.
ImmOpcode = PPC::LWZU;
break;
4291 case PPC::LWZUX8: III.
ImmOpcode = PPC::LWZU8;
break;
4296 case PPC::LFSUX: III.
ImmOpcode = PPC::LFSU;
break;
4297 case PPC::LFDUX: III.
ImmOpcode = PPC::LFDU;
break;
4298 case PPC::STBUX: III.
ImmOpcode = PPC::STBU;
break;
4299 case PPC::STBUX8: III.
ImmOpcode = PPC::STBU8;
break;
4300 case PPC::STHUX: III.
ImmOpcode = PPC::STHU;
break;
4301 case PPC::STHUX8: III.
ImmOpcode = PPC::STHU8;
break;
4302 case PPC::STWUX: III.
ImmOpcode = PPC::STWU;
break;
4303 case PPC::STWUX8: III.
ImmOpcode = PPC::STWU8;
break;
4308 case PPC::STFSUX: III.
ImmOpcode = PPC::STFSU;
break;
4309 case PPC::STFDUX: III.
ImmOpcode = PPC::STFDU;
break;
4322 case PPC::XFLOADf32:
4323 case PPC::XFLOADf64:
4324 case PPC::XFSTOREf32:
4325 case PPC::XFSTOREf64:
4326 if (!Subtarget.hasP9Vector())
4353 case PPC::XFLOADf32:
4367 case PPC::XFLOADf64:
4385 case PPC::XFSTOREf32:
4399 case PPC::XFSTOREf64:
4410 assert(Op1 != Op2 &&
"Cannot swap operand with itself.");
4412 unsigned MaxOp = std::max(Op1, Op2);
4413 unsigned MinOp = std::min(Op1, Op2);
4416 MI.removeOperand(std::max(Op1, Op2));
4417 MI.removeOperand(std::min(Op1, Op2));
4421 if (MaxOp - MinOp == 1 &&
MI.getNumOperands() == MinOp) {
4422 MI.addOperand(MOp2);
4423 MI.addOperand(MOp1);
4428 unsigned TotalOps =
MI.getNumOperands() + 2;
4429 for (
unsigned i =
MI.getNumOperands() - 1; i >= MinOp; i--) {
4431 MI.removeOperand(i);
4434 MI.addOperand(MOp2);
4436 for (
unsigned i =
MI.getNumOperands(); i < TotalOps; i++) {
4438 MI.addOperand(MOp1);
4440 MI.addOperand(MOps.
back());
4451 unsigned OpNoForForwarding
4491 unsigned Opc =
DefMI.getOpcode();
4492 if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
4496 "Add inst must have at least three operands");
4497 RegMO = &
DefMI.getOperand(1);
4498 ImmMO = &
DefMI.getOperand(2);
4501 if (!RegMO->
isReg())
4510bool PPCInstrInfo::isRegElgibleForForwarding(
4513 bool &IsFwdFeederRegKilled,
bool &SeenIntermediateUse)
const {
4530 for (; It !=
E; ++It) {
4534 IsFwdFeederRegKilled =
true;
4536 SeenIntermediateUse =
true;
4538 if ((&*It) == &
DefMI)
4551bool PPCInstrInfo::isImmElgibleForForwarding(
const MachineOperand &ImmMO,
4555 int64_t BaseImm)
const {
4557 if (
DefMI.getOpcode() == PPC::ADDItocL) {
4578 if (ImmMO.
isImm()) {
4583 APInt ActualValue(64, ImmMO.
getImm() + BaseImm,
true);
4588 Imm = SignExtend64<16>(ImmMO.
getImm() + BaseImm);
4604 unsigned OpNoForForwarding,
4606 if ((
DefMI.getOpcode() != PPC::LI &&
DefMI.getOpcode() != PPC::LI8) ||
4607 !
DefMI.getOperand(1).isImm())
4612 bool PostRA = !
MRI->isSSA();
4614 int64_t Immediate =
DefMI.getOperand(1).getImm();
4616 int64_t SExtImm = SignExtend64<16>(Immediate);
4618 bool IsForwardingOperandKilled =
MI.getOperand(OpNoForForwarding).isKill();
4619 Register ForwardingOperandReg =
MI.getOperand(OpNoForForwarding).getReg();
4621 bool ReplaceWithLI =
false;
4622 bool Is64BitLI =
false;
4625 unsigned Opc =
MI.getOpcode();
4646 bool Changed =
false;
4648 int64_t Comparand =
MI.getOperand(2).getImm();
4649 int64_t SExtComparand = ((
uint64_t)Comparand & ~0x7FFFuLL) != 0
4650 ? (Comparand | 0xFFFFFFFFFFFF0000)
4653 for (
auto &CompareUseMI :
MRI->use_instructions(DefReg)) {
4654 unsigned UseOpc = CompareUseMI.getOpcode();
4655 if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
4657 unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
4658 Register TrueReg = CompareUseMI.getOperand(1).getReg();
4659 Register FalseReg = CompareUseMI.getOperand(2).getReg();
4660 unsigned RegToCopy =
4661 selectReg(SExtImm, SExtComparand, Opc, TrueReg, FalseReg, CRSubReg);
4662 if (RegToCopy == PPC::NoRegister)
4665 if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
4666 CompareUseMI.setDesc(
get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
4668 CompareUseMI.removeOperand(3);
4669 CompareUseMI.removeOperand(2);
4673 dbgs() <<
"Found LI -> CMPI -> ISEL, replacing with a copy.\n");
4677 CompareUseMI.setDesc(
get(PPC::COPY));
4678 CompareUseMI.removeOperand(3);
4679 CompareUseMI.removeOperand(RegToCopy == TrueReg ? 2 : 1);
4680 CmpIselsConverted++;