LLVM  9.0.0svn
PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCInstrInfo.h"
15 #include "PPC.h"
16 #include "PPCHazardRecognizers.h"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Statistic.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/Debug.h"
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "ppc-instr-info"
43 
44 #define GET_INSTRMAP_INFO
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "PPCGenInstrInfo.inc"
47 
48 STATISTIC(NumStoreSPILLVSRRCAsVec,
49  "Number of spillvsrrc spilled to stack as vec");
50 STATISTIC(NumStoreSPILLVSRRCAsGpr,
51  "Number of spillvsrrc spilled to stack as gpr");
52 STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc");
53 STATISTIC(CmpIselsConverted,
54  "Number of ISELs that depend on comparison of constants converted");
55 STATISTIC(MissedConvertibleImmediateInstrs,
56  "Number of compare-immediate instructions fed by constants");
57 STATISTIC(NumRcRotatesConvertedToRcAnd,
58  "Number of record-form rotates converted to record-form andi");
59 
60 static cl::
61 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
62  cl::desc("Disable analysis for CTR loops"));
63 
64 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
65 cl::desc("Disable compare instruction optimization"), cl::Hidden);
66 
67 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
68 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
69 cl::Hidden);
70 
71 static cl::opt<bool>
72 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
73  cl::desc("Use the old (incorrect) instruction latency calculation"));
74 
75 // Index into the OpcodesForSpill array.
94  SOK_LastOpcodeSpill // This must be last on the enum.
95 };
96 
97 // Pin the vtable to this file.
98 void PPCInstrInfo::anchor() {}
99 
101  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
102  /* CatchRetOpcode */ -1,
103  STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
104  Subtarget(STI), RI(STI.getTargetMachine()) {}
105 
106 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
107 /// this target when scheduling the DAG.
110  const ScheduleDAG *DAG) const {
111  unsigned Directive =
112  static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
113  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
114  Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
115  const InstrItineraryData *II =
116  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
117  return new ScoreboardHazardRecognizer(II, DAG);
118  }
119 
121 }
122 
123 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
124 /// to use for this target when scheduling the DAG.
127  const ScheduleDAG *DAG) const {
128  unsigned Directive =
129  DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
130 
131  // FIXME: Leaving this as-is until we have POWER9 scheduling info
132  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
133  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
134 
135  // Most subtargets use a PPC970 recognizer.
136  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
137  Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
138  assert(DAG->TII && "No InstrInfo?");
139 
140  return new PPCHazardRecognizer970(*DAG);
141  }
142 
143  return new ScoreboardHazardRecognizer(II, DAG);
144 }
145 
147  const MachineInstr &MI,
148  unsigned *PredCost) const {
149  if (!ItinData || UseOldLatencyCalc)
150  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
151 
152  // The default implementation of getInstrLatency calls getStageLatency, but
153  // getStageLatency does not do the right thing for us. While we have
154  // itinerary, most cores are fully pipelined, and so the itineraries only
155  // express the first part of the pipeline, not every stage. Instead, we need
156  // to use the listed output operand cycle number (using operand 0 here, which
157  // is an output).
158 
159  unsigned Latency = 1;
160  unsigned DefClass = MI.getDesc().getSchedClass();
161  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
162  const MachineOperand &MO = MI.getOperand(i);
163  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
164  continue;
165 
166  int Cycle = ItinData->getOperandCycle(DefClass, i);
167  if (Cycle < 0)
168  continue;
169 
170  Latency = std::max(Latency, (unsigned) Cycle);
171  }
172 
173  return Latency;
174 }
175 
177  const MachineInstr &DefMI, unsigned DefIdx,
178  const MachineInstr &UseMI,
179  unsigned UseIdx) const {
180  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
181  UseMI, UseIdx);
182 
183  if (!DefMI.getParent())
184  return Latency;
185 
186  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
187  unsigned Reg = DefMO.getReg();
188 
189  bool IsRegCR;
191  const MachineRegisterInfo *MRI =
192  &DefMI.getParent()->getParent()->getRegInfo();
193  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
194  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
195  } else {
196  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
197  PPC::CRBITRCRegClass.contains(Reg);
198  }
199 
200  if (UseMI.isBranch() && IsRegCR) {
201  if (Latency < 0)
202  Latency = getInstrLatency(ItinData, DefMI);
203 
204  // On some cores, there is an additional delay between writing to a condition
205  // register, and using it from a branch.
206  unsigned Directive = Subtarget.getDarwinDirective();
207  switch (Directive) {
208  default: break;
209  case PPC::DIR_7400:
210  case PPC::DIR_750:
211  case PPC::DIR_970:
212  case PPC::DIR_E5500:
213  case PPC::DIR_PWR4:
214  case PPC::DIR_PWR5:
215  case PPC::DIR_PWR5X:
216  case PPC::DIR_PWR6:
217  case PPC::DIR_PWR6X:
218  case PPC::DIR_PWR7:
219  case PPC::DIR_PWR8:
220  // FIXME: Is this needed for POWER9?
221  Latency += 2;
222  break;
223  }
224  }
225 
226  return Latency;
227 }
228 
229 // This function does not list all associative and commutative operations, but
230 // only those worth feeding through the machine combiner in an attempt to
231 // reduce the critical path. Mostly, this means floating-point operations,
232 // because they have high latencies (compared to other operations, such and
233 // and/or, which are also associative and commutative, but have low latencies).
235  switch (Inst.getOpcode()) {
236  // FP Add:
237  case PPC::FADD:
238  case PPC::FADDS:
239  // FP Multiply:
240  case PPC::FMUL:
241  case PPC::FMULS:
242  // Altivec Add:
243  case PPC::VADDFP:
244  // VSX Add:
245  case PPC::XSADDDP:
246  case PPC::XVADDDP:
247  case PPC::XVADDSP:
248  case PPC::XSADDSP:
249  // VSX Multiply:
250  case PPC::XSMULDP:
251  case PPC::XVMULDP:
252  case PPC::XVMULSP:
253  case PPC::XSMULSP:
254  // QPX Add:
255  case PPC::QVFADD:
256  case PPC::QVFADDS:
257  case PPC::QVFADDSs:
258  // QPX Multiply:
259  case PPC::QVFMUL:
260  case PPC::QVFMULS:
261  case PPC::QVFMULSs:
262  return true;
263  default:
264  return false;
265  }
266 }
267 
269  MachineInstr &Root,
270  SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
271  // Using the machine combiner in this way is potentially expensive, so
272  // restrict to when aggressive optimizations are desired.
274  return false;
275 
276  // FP reassociation is only legal when we don't need strict IEEE semantics.
278  return false;
279 
280  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
281 }
282 
283 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
285  unsigned &SrcReg, unsigned &DstReg,
286  unsigned &SubIdx) const {
287  switch (MI.getOpcode()) {
288  default: return false;
289  case PPC::EXTSW:
290  case PPC::EXTSW_32:
291  case PPC::EXTSW_32_64:
292  SrcReg = MI.getOperand(1).getReg();
293  DstReg = MI.getOperand(0).getReg();
294  SubIdx = PPC::sub_32;
295  return true;
296  }
297 }
298 
300  int &FrameIndex) const {
301  unsigned Opcode = MI.getOpcode();
302  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
303  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
304 
305  if (End != std::find(OpcodesForSpill, End, Opcode)) {
306  // Check for the operands added by addFrameReference (the immediate is the
307  // offset which defaults to 0).
308  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
309  MI.getOperand(2).isFI()) {
310  FrameIndex = MI.getOperand(2).getIndex();
311  return MI.getOperand(0).getReg();
312  }
313  }
314  return 0;
315 }
316 
317 // For opcodes with the ReMaterializable flag set, this function is called to
318 // verify the instruction is really rematable.
320  AliasAnalysis *AA) const {
321  switch (MI.getOpcode()) {
322  default:
323  // This function should only be called for opcodes with the ReMaterializable
324  // flag set.
325  llvm_unreachable("Unknown rematerializable operation!");
326  break;
327  case PPC::LI:
328  case PPC::LI8:
329  case PPC::LIS:
330  case PPC::LIS8:
331  case PPC::QVGPCI:
332  case PPC::ADDIStocHA:
333  case PPC::ADDItocL:
334  case PPC::LOAD_STACK_GUARD:
335  case PPC::XXLXORz:
336  case PPC::XXLXORspz:
337  case PPC::XXLXORdpz:
338  case PPC::V_SET0B:
339  case PPC::V_SET0H:
340  case PPC::V_SET0:
341  case PPC::V_SETALLONESB:
342  case PPC::V_SETALLONESH:
343  case PPC::V_SETALLONES:
344  return true;
345  }
346  return false;
347 }
348 
350  int &FrameIndex) const {
351  unsigned Opcode = MI.getOpcode();
352  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
353  const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
354 
355  if (End != std::find(OpcodesForSpill, End, Opcode)) {
356  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
357  MI.getOperand(2).isFI()) {
358  FrameIndex = MI.getOperand(2).getIndex();
359  return MI.getOperand(0).getReg();
360  }
361  }
362  return 0;
363 }
364 
366  unsigned OpIdx1,
367  unsigned OpIdx2) const {
368  MachineFunction &MF = *MI.getParent()->getParent();
369 
370  // Normal instructions can be commuted the obvious way.
371  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
372  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
373  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
374  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
375  // changing the relative order of the mask operands might change what happens
376  // to the high-bits of the mask (and, thus, the result).
377 
378  // Cannot commute if it has a non-zero rotate count.
379  if (MI.getOperand(3).getImm() != 0)
380  return nullptr;
381 
382  // If we have a zero rotate count, we have:
383  // M = mask(MB,ME)
384  // Op0 = (Op1 & ~M) | (Op2 & M)
385  // Change this to:
386  // M = mask((ME+1)&31, (MB-1)&31)
387  // Op0 = (Op2 & ~M) | (Op1 & M)
388 
389  // Swap op1/op2
390  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
391  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
392  unsigned Reg0 = MI.getOperand(0).getReg();
393  unsigned Reg1 = MI.getOperand(1).getReg();
394  unsigned Reg2 = MI.getOperand(2).getReg();
395  unsigned SubReg1 = MI.getOperand(1).getSubReg();
396  unsigned SubReg2 = MI.getOperand(2).getSubReg();
397  bool Reg1IsKill = MI.getOperand(1).isKill();
398  bool Reg2IsKill = MI.getOperand(2).isKill();
399  bool ChangeReg0 = false;
400  // If machine instrs are no longer in two-address forms, update
401  // destination register as well.
402  if (Reg0 == Reg1) {
403  // Must be two address instruction!
405  "Expecting a two-address instruction!");
406  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
407  Reg2IsKill = false;
408  ChangeReg0 = true;
409  }
410 
411  // Masks.
412  unsigned MB = MI.getOperand(4).getImm();
413  unsigned ME = MI.getOperand(5).getImm();
414 
415  // We can't commute a trivial mask (there is no way to represent an all-zero
416  // mask).
417  if (MB == 0 && ME == 31)
418  return nullptr;
419 
420  if (NewMI) {
421  // Create a new instruction.
422  unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
423  bool Reg0IsDead = MI.getOperand(0).isDead();
424  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
425  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
426  .addReg(Reg2, getKillRegState(Reg2IsKill))
427  .addReg(Reg1, getKillRegState(Reg1IsKill))
428  .addImm((ME + 1) & 31)
429  .addImm((MB - 1) & 31);
430  }
431 
432  if (ChangeReg0) {
433  MI.getOperand(0).setReg(Reg2);
434  MI.getOperand(0).setSubReg(SubReg2);
435  }
436  MI.getOperand(2).setReg(Reg1);
437  MI.getOperand(1).setReg(Reg2);
438  MI.getOperand(2).setSubReg(SubReg1);
439  MI.getOperand(1).setSubReg(SubReg2);
440  MI.getOperand(2).setIsKill(Reg1IsKill);
441  MI.getOperand(1).setIsKill(Reg2IsKill);
442 
443  // Swap the mask around.
444  MI.getOperand(4).setImm((ME + 1) & 31);
445  MI.getOperand(5).setImm((MB - 1) & 31);
446  return &MI;
447 }
448 
450  unsigned &SrcOpIdx2) const {
451  // For VSX A-Type FMA instructions, it is the first two operands that can be
452  // commuted, however, because the non-encoded tied input operand is listed
453  // first, the operands to swap are actually the second and third.
454 
455  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
456  if (AltOpc == -1)
457  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
458 
459  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
460  // and SrcOpIdx2.
461  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
462 }
463 
466  // This function is used for scheduling, and the nop wanted here is the type
467  // that terminates dispatch groups on the POWER cores.
468  unsigned Directive = Subtarget.getDarwinDirective();
469  unsigned Opcode;
470  switch (Directive) {
471  default: Opcode = PPC::NOP; break;
472  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
473  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
474  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
475  // FIXME: Update when POWER9 scheduling model is ready.
476  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
477  }
478 
479  DebugLoc DL;
480  BuildMI(MBB, MI, DL, get(Opcode));
481 }
482 
483 /// Return the noop instruction to use for a noop.
484 void PPCInstrInfo::getNoop(MCInst &NopInst) const {
485  NopInst.setOpcode(PPC::NOP);
486 }
487 
488 // Branch analysis.
489 // Note: If the condition register is set to CTR or CTR8 then this is a
490 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
492  MachineBasicBlock *&TBB,
493  MachineBasicBlock *&FBB,
495  bool AllowModify) const {
496  bool isPPC64 = Subtarget.isPPC64();
497 
498  // If the block has no terminators, it just falls into the block after it.
500  if (I == MBB.end())
501  return false;
502 
503  if (!isUnpredicatedTerminator(*I))
504  return false;
505 
506  if (AllowModify) {
507  // If the BB ends with an unconditional branch to the fallthrough BB,
508  // we eliminate the branch instruction.
509  if (I->getOpcode() == PPC::B &&
510  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
511  I->eraseFromParent();
512 
513  // We update iterator after deleting the last branch.
514  I = MBB.getLastNonDebugInstr();
515  if (I == MBB.end() || !isUnpredicatedTerminator(*I))
516  return false;
517  }
518  }
519 
520  // Get the last instruction in the block.
521  MachineInstr &LastInst = *I;
522 
523  // If there is only one terminator instruction, process it.
524  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
525  if (LastInst.getOpcode() == PPC::B) {
526  if (!LastInst.getOperand(0).isMBB())
527  return true;
528  TBB = LastInst.getOperand(0).getMBB();
529  return false;
530  } else if (LastInst.getOpcode() == PPC::BCC) {
531  if (!LastInst.getOperand(2).isMBB())
532  return true;
533  // Block ends with fall-through condbranch.
534  TBB = LastInst.getOperand(2).getMBB();
535  Cond.push_back(LastInst.getOperand(0));
536  Cond.push_back(LastInst.getOperand(1));
537  return false;
538  } else if (LastInst.getOpcode() == PPC::BC) {
539  if (!LastInst.getOperand(1).isMBB())
540  return true;
541  // Block ends with fall-through condbranch.
542  TBB = LastInst.getOperand(1).getMBB();
544  Cond.push_back(LastInst.getOperand(0));
545  return false;
546  } else if (LastInst.getOpcode() == PPC::BCn) {
547  if (!LastInst.getOperand(1).isMBB())
548  return true;
549  // Block ends with fall-through condbranch.
550  TBB = LastInst.getOperand(1).getMBB();
552  Cond.push_back(LastInst.getOperand(0));
553  return false;
554  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
555  LastInst.getOpcode() == PPC::BDNZ) {
556  if (!LastInst.getOperand(0).isMBB())
557  return true;
558  if (DisableCTRLoopAnal)
559  return true;
560  TBB = LastInst.getOperand(0).getMBB();
562  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
563  true));
564  return false;
565  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
566  LastInst.getOpcode() == PPC::BDZ) {
567  if (!LastInst.getOperand(0).isMBB())
568  return true;
569  if (DisableCTRLoopAnal)
570  return true;
571  TBB = LastInst.getOperand(0).getMBB();
573  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
574  true));
575  return false;
576  }
577 
578  // Otherwise, don't know what this is.
579  return true;
580  }
581 
582  // Get the instruction before it if it's a terminator.
583  MachineInstr &SecondLastInst = *I;
584 
585  // If there are three terminators, we don't know what sort of block this is.
586  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
587  return true;
588 
589  // If the block ends with PPC::B and PPC:BCC, handle it.
590  if (SecondLastInst.getOpcode() == PPC::BCC &&
591  LastInst.getOpcode() == PPC::B) {
592  if (!SecondLastInst.getOperand(2).isMBB() ||
593  !LastInst.getOperand(0).isMBB())
594  return true;
595  TBB = SecondLastInst.getOperand(2).getMBB();
596  Cond.push_back(SecondLastInst.getOperand(0));
597  Cond.push_back(SecondLastInst.getOperand(1));
598  FBB = LastInst.getOperand(0).getMBB();
599  return false;
600  } else if (SecondLastInst.getOpcode() == PPC::BC &&
601  LastInst.getOpcode() == PPC::B) {
602  if (!SecondLastInst.getOperand(1).isMBB() ||
603  !LastInst.getOperand(0).isMBB())
604  return true;
605  TBB = SecondLastInst.getOperand(1).getMBB();
607  Cond.push_back(SecondLastInst.getOperand(0));
608  FBB = LastInst.getOperand(0).getMBB();
609  return false;
610  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
611  LastInst.getOpcode() == PPC::B) {
612  if (!SecondLastInst.getOperand(1).isMBB() ||
613  !LastInst.getOperand(0).isMBB())
614  return true;
615  TBB = SecondLastInst.getOperand(1).getMBB();
617  Cond.push_back(SecondLastInst.getOperand(0));
618  FBB = LastInst.getOperand(0).getMBB();
619  return false;
620  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
621  SecondLastInst.getOpcode() == PPC::BDNZ) &&
622  LastInst.getOpcode() == PPC::B) {
623  if (!SecondLastInst.getOperand(0).isMBB() ||
624  !LastInst.getOperand(0).isMBB())
625  return true;
626  if (DisableCTRLoopAnal)
627  return true;
628  TBB = SecondLastInst.getOperand(0).getMBB();
630  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
631  true));
632  FBB = LastInst.getOperand(0).getMBB();
633  return false;
634  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
635  SecondLastInst.getOpcode() == PPC::BDZ) &&
636  LastInst.getOpcode() == PPC::B) {
637  if (!SecondLastInst.getOperand(0).isMBB() ||
638  !LastInst.getOperand(0).isMBB())
639  return true;
640  if (DisableCTRLoopAnal)
641  return true;
642  TBB = SecondLastInst.getOperand(0).getMBB();
644  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
645  true));
646  FBB = LastInst.getOperand(0).getMBB();
647  return false;
648  }
649 
650  // If the block ends with two PPC:Bs, handle it. The second one is not
651  // executed, so remove it.
652  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
653  if (!SecondLastInst.getOperand(0).isMBB())
654  return true;
655  TBB = SecondLastInst.getOperand(0).getMBB();
656  I = LastInst;
657  if (AllowModify)
658  I->eraseFromParent();
659  return false;
660  }
661 
662  // Otherwise, can't handle this.
663  return true;
664 }
665 
667  int *BytesRemoved) const {
668  assert(!BytesRemoved && "code size not handled");
669 
671  if (I == MBB.end())
672  return 0;
673 
674  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
675  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
676  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
677  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
678  return 0;
679 
680  // Remove the branch.
681  I->eraseFromParent();
682 
683  I = MBB.end();
684 
685  if (I == MBB.begin()) return 1;
686  --I;
687  if (I->getOpcode() != PPC::BCC &&
688  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
689  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
690  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
691  return 1;
692 
693  // Remove the branch.
694  I->eraseFromParent();
695  return 2;
696 }
697 
699  MachineBasicBlock *TBB,
700  MachineBasicBlock *FBB,
702  const DebugLoc &DL,
703  int *BytesAdded) const {
704  // Shouldn't be a fall through.
705  assert(TBB && "insertBranch must not be told to insert a fallthrough");
706  assert((Cond.size() == 2 || Cond.size() == 0) &&
707  "PPC branch conditions have two components!");
708  assert(!BytesAdded && "code size not handled");
709 
710  bool isPPC64 = Subtarget.isPPC64();
711 
712  // One-way branch.
713  if (!FBB) {
714  if (Cond.empty()) // Unconditional branch
715  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
716  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
717  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
718  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
719  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
720  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
721  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
722  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
723  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
724  else // Conditional branch
725  BuildMI(&MBB, DL, get(PPC::BCC))
726  .addImm(Cond[0].getImm())
727  .add(Cond[1])
728  .addMBB(TBB);
729  return 1;
730  }
731 
732  // Two-way Conditional Branch.
733  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
734  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
735  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
736  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
737  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
738  BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
739  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
740  BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
741  else
742  BuildMI(&MBB, DL, get(PPC::BCC))
743  .addImm(Cond[0].getImm())
744  .add(Cond[1])
745  .addMBB(TBB);
746  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
747  return 2;
748 }
749 
750 // Select analysis.
753  unsigned TrueReg, unsigned FalseReg,
754  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
755  if (Cond.size() != 2)
756  return false;
757 
758  // If this is really a bdnz-like condition, then it cannot be turned into a
759  // select.
760  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
761  return false;
762 
763  // Check register classes.
764  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
765  const TargetRegisterClass *RC =
766  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
767  if (!RC)
768  return false;
769 
770  // isel is for regular integer GPRs only.
771  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
772  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
773  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
774  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
775  return false;
776 
777  // FIXME: These numbers are for the A2, how well they work for other cores is
778  // an open question. On the A2, the isel instruction has a 2-cycle latency
779  // but single-cycle throughput. These numbers are used in combination with
780  // the MispredictPenalty setting from the active SchedMachineModel.
781  CondCycles = 1;
782  TrueCycles = 1;
783  FalseCycles = 1;
784 
785  return true;
786 }
787 
790  const DebugLoc &dl, unsigned DestReg,
791  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
792  unsigned FalseReg) const {
793  assert(Cond.size() == 2 &&
794  "PPC branch conditions have two components!");
795 
796  // Get the register classes.
798  const TargetRegisterClass *RC =
799  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
800  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
801 
802  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
803  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
804  assert((Is64Bit ||
805  PPC::GPRCRegClass.hasSubClassEq(RC) ||
806  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
807  "isel is for regular integer GPRs only");
808 
809  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
810  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
811 
812  unsigned SubIdx = 0;
813  bool SwapOps = false;
814  switch (SelectPred) {
815  case PPC::PRED_EQ:
816  case PPC::PRED_EQ_MINUS:
817  case PPC::PRED_EQ_PLUS:
818  SubIdx = PPC::sub_eq; SwapOps = false; break;
819  case PPC::PRED_NE:
820  case PPC::PRED_NE_MINUS:
821  case PPC::PRED_NE_PLUS:
822  SubIdx = PPC::sub_eq; SwapOps = true; break;
823  case PPC::PRED_LT:
824  case PPC::PRED_LT_MINUS:
825  case PPC::PRED_LT_PLUS:
826  SubIdx = PPC::sub_lt; SwapOps = false; break;
827  case PPC::PRED_GE:
828  case PPC::PRED_GE_MINUS:
829  case PPC::PRED_GE_PLUS:
830  SubIdx = PPC::sub_lt; SwapOps = true; break;
831  case PPC::PRED_GT:
832  case PPC::PRED_GT_MINUS:
833  case PPC::PRED_GT_PLUS:
834  SubIdx = PPC::sub_gt; SwapOps = false; break;
835  case PPC::PRED_LE:
836  case PPC::PRED_LE_MINUS:
837  case PPC::PRED_LE_PLUS:
838  SubIdx = PPC::sub_gt; SwapOps = true; break;
839  case PPC::PRED_UN:
840  case PPC::PRED_UN_MINUS:
841  case PPC::PRED_UN_PLUS:
842  SubIdx = PPC::sub_un; SwapOps = false; break;
843  case PPC::PRED_NU:
844  case PPC::PRED_NU_MINUS:
845  case PPC::PRED_NU_PLUS:
846  SubIdx = PPC::sub_un; SwapOps = true; break;
847  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
848  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
849  }
850 
851  unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
852  SecondReg = SwapOps ? TrueReg : FalseReg;
853 
854  // The first input register of isel cannot be r0. If it is a member
855  // of a register class that can be r0, then copy it first (the
856  // register allocator should eliminate the copy).
857  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
858  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
859  const TargetRegisterClass *FirstRC =
860  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
861  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
862  unsigned OldFirstReg = FirstReg;
863  FirstReg = MRI.createVirtualRegister(FirstRC);
864  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
865  .addReg(OldFirstReg);
866  }
867 
868  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
869  .addReg(FirstReg).addReg(SecondReg)
870  .addReg(Cond[1].getReg(), 0, SubIdx);
871 }
872 
873 static unsigned getCRBitValue(unsigned CRBit) {
874  unsigned Ret = 4;
875  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
876  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
877  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
878  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
879  Ret = 3;
880  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
881  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
882  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
883  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
884  Ret = 2;
885  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
886  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
887  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
888  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
889  Ret = 1;
890  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
891  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
892  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
893  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
894  Ret = 0;
895 
896  assert(Ret != 4 && "Invalid CR bit register");
897  return Ret;
898 }
899 
902  const DebugLoc &DL, unsigned DestReg,
903  unsigned SrcReg, bool KillSrc) const {
904  // We can end up with self copies and similar things as a result of VSX copy
905  // legalization. Promote them here.
907  if (PPC::F8RCRegClass.contains(DestReg) &&
908  PPC::VSRCRegClass.contains(SrcReg)) {
909  unsigned SuperReg =
910  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
911 
912  if (VSXSelfCopyCrash && SrcReg == SuperReg)
913  llvm_unreachable("nop VSX copy");
914 
915  DestReg = SuperReg;
916  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
917  PPC::VSRCRegClass.contains(DestReg)) {
918  unsigned SuperReg =
919  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
920 
921  if (VSXSelfCopyCrash && DestReg == SuperReg)
922  llvm_unreachable("nop VSX copy");
923 
924  SrcReg = SuperReg;
925  }
926 
927  // Different class register copy
928  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
929  PPC::GPRCRegClass.contains(DestReg)) {
930  unsigned CRReg = getCRFromCRBit(SrcReg);
931  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
932  getKillRegState(KillSrc);
933  // Rotate the CR bit in the CR fields to be the least significant bit and
934  // then mask with 0x1 (MB = ME = 31).
935  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
936  .addReg(DestReg, RegState::Kill)
937  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
938  .addImm(31)
939  .addImm(31);
940  return;
941  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
942  PPC::G8RCRegClass.contains(DestReg)) {
943  BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
944  getKillRegState(KillSrc);
945  return;
946  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
947  PPC::GPRCRegClass.contains(DestReg)) {
948  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
949  getKillRegState(KillSrc);
950  return;
951  } else if (PPC::G8RCRegClass.contains(SrcReg) &&
952  PPC::VSFRCRegClass.contains(DestReg)) {
953  assert(Subtarget.hasDirectMove() &&
954  "Subtarget doesn't support directmove, don't know how to copy.");
955  BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
956  NumGPRtoVSRSpill++;
957  getKillRegState(KillSrc);
958  return;
959  } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
960  PPC::G8RCRegClass.contains(DestReg)) {
961  assert(Subtarget.hasDirectMove() &&
962  "Subtarget doesn't support directmove, don't know how to copy.");
963  BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
964  getKillRegState(KillSrc);
965  return;
966  } else if (PPC::SPERCRegClass.contains(SrcReg) &&
967  PPC::SPE4RCRegClass.contains(DestReg)) {
968  BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
969  getKillRegState(KillSrc);
970  return;
971  } else if (PPC::SPE4RCRegClass.contains(SrcReg) &&
972  PPC::SPERCRegClass.contains(DestReg)) {
973  BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
974  getKillRegState(KillSrc);
975  return;
976  }
977 
978  unsigned Opc;
979  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
980  Opc = PPC::OR;
981  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
982  Opc = PPC::OR8;
983  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
984  Opc = PPC::FMR;
985  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
986  Opc = PPC::MCRF;
987  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
988  Opc = PPC::VOR;
989  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
990  // There are two different ways this can be done:
991  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
992  // issue in VSU pipeline 0.
993  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
994  // can go to either pipeline.
995  // We'll always use xxlor here, because in practically all cases where
996  // copies are generated, they are close enough to some use that the
997  // lower-latency form is preferable.
998  Opc = PPC::XXLOR;
999  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
1000  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
1001  Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
1002  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
1003  Opc = PPC::QVFMR;
1004  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
1005  Opc = PPC::QVFMRs;
1006  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
1007  Opc = PPC::QVFMRb;
1008  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
1009  Opc = PPC::CROR;
1010  else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
1011  Opc = PPC::EVOR;
1012  else
1013  llvm_unreachable("Impossible reg-to-reg copy");
1014 
1015  const MCInstrDesc &MCID = get(Opc);
1016  if (MCID.getNumOperands() == 3)
1017  BuildMI(MBB, I, DL, MCID, DestReg)
1018  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1019  else
1020  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1021 }
1022 
1024  const TargetRegisterClass *RC)
1025  const {
1026  const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1027  int OpcodeIndex = 0;
1028 
1029  if (RC != nullptr) {
1030  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1031  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1032  OpcodeIndex = SOK_Int4Spill;
1033  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1034  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1035  OpcodeIndex = SOK_Int8Spill;
1036  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1037  OpcodeIndex = SOK_Float8Spill;
1038  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1039  OpcodeIndex = SOK_Float4Spill;
1040  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1041  OpcodeIndex = SOK_SPESpill;
1042  } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1043  OpcodeIndex = SOK_SPE4Spill;
1044  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1045  OpcodeIndex = SOK_CRSpill;
1046  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1047  OpcodeIndex = SOK_CRBitSpill;
1048  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1049  OpcodeIndex = SOK_VRVectorSpill;
1050  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1051  OpcodeIndex = SOK_VSXVectorSpill;
1052  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1053  OpcodeIndex = SOK_VectorFloat8Spill;
1054  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1055  OpcodeIndex = SOK_VectorFloat4Spill;
1056  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1057  OpcodeIndex = SOK_VRSaveSpill;
1058  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1059  OpcodeIndex = SOK_QuadFloat8Spill;
1060  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1061  OpcodeIndex = SOK_QuadFloat4Spill;
1062  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1063  OpcodeIndex = SOK_QuadBitSpill;
1064  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1065  OpcodeIndex = SOK_SpillToVSR;
1066  } else {
1067  llvm_unreachable("Unknown regclass!");
1068  }
1069  } else {
1070  if (PPC::GPRCRegClass.contains(Reg) ||
1071  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1072  OpcodeIndex = SOK_Int4Spill;
1073  } else if (PPC::G8RCRegClass.contains(Reg) ||
1074  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1075  OpcodeIndex = SOK_Int8Spill;
1076  } else if (PPC::F8RCRegClass.contains(Reg)) {
1077  OpcodeIndex = SOK_Float8Spill;
1078  } else if (PPC::F4RCRegClass.contains(Reg)) {
1079  OpcodeIndex = SOK_Float4Spill;
1080  } else if (PPC::SPERCRegClass.contains(Reg)) {
1081  OpcodeIndex = SOK_SPESpill;
1082  } else if (PPC::SPE4RCRegClass.contains(Reg)) {
1083  OpcodeIndex = SOK_SPE4Spill;
1084  } else if (PPC::CRRCRegClass.contains(Reg)) {
1085  OpcodeIndex = SOK_CRSpill;
1086  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1087  OpcodeIndex = SOK_CRBitSpill;
1088  } else if (PPC::VRRCRegClass.contains(Reg)) {
1089  OpcodeIndex = SOK_VRVectorSpill;
1090  } else if (PPC::VSRCRegClass.contains(Reg)) {
1091  OpcodeIndex = SOK_VSXVectorSpill;
1092  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1093  OpcodeIndex = SOK_VectorFloat8Spill;
1094  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1095  OpcodeIndex = SOK_VectorFloat4Spill;
1096  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1097  OpcodeIndex = SOK_VRSaveSpill;
1098  } else if (PPC::QFRCRegClass.contains(Reg)) {
1099  OpcodeIndex = SOK_QuadFloat8Spill;
1100  } else if (PPC::QSRCRegClass.contains(Reg)) {
1101  OpcodeIndex = SOK_QuadFloat4Spill;
1102  } else if (PPC::QBRCRegClass.contains(Reg)) {
1103  OpcodeIndex = SOK_QuadBitSpill;
1104  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1105  OpcodeIndex = SOK_SpillToVSR;
1106  } else {
1107  llvm_unreachable("Unknown regclass!");
1108  }
1109  }
1110  return OpcodesForSpill[OpcodeIndex];
1111 }
1112 
1113 unsigned
1115  const TargetRegisterClass *RC) const {
1116  const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1117  int OpcodeIndex = 0;
1118 
1119  if (RC != nullptr) {
1120  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1121  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1122  OpcodeIndex = SOK_Int4Spill;
1123  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1124  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1125  OpcodeIndex = SOK_Int8Spill;
1126  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1127  OpcodeIndex = SOK_Float8Spill;
1128  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1129  OpcodeIndex = SOK_Float4Spill;
1130  } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1131  OpcodeIndex = SOK_SPESpill;
1132  } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1133  OpcodeIndex = SOK_SPE4Spill;
1134  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1135  OpcodeIndex = SOK_CRSpill;
1136  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1137  OpcodeIndex = SOK_CRBitSpill;
1138  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1139  OpcodeIndex = SOK_VRVectorSpill;
1140  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1141  OpcodeIndex = SOK_VSXVectorSpill;
1142  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1143  OpcodeIndex = SOK_VectorFloat8Spill;
1144  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1145  OpcodeIndex = SOK_VectorFloat4Spill;
1146  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1147  OpcodeIndex = SOK_VRSaveSpill;
1148  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1149  OpcodeIndex = SOK_QuadFloat8Spill;
1150  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1151  OpcodeIndex = SOK_QuadFloat4Spill;
1152  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1153  OpcodeIndex = SOK_QuadBitSpill;
1154  } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1155  OpcodeIndex = SOK_SpillToVSR;
1156  } else {
1157  llvm_unreachable("Unknown regclass!");
1158  }
1159  } else {
1160  if (PPC::GPRCRegClass.contains(Reg) ||
1161  PPC::GPRC_NOR0RegClass.contains(Reg)) {
1162  OpcodeIndex = SOK_Int4Spill;
1163  } else if (PPC::G8RCRegClass.contains(Reg) ||
1164  PPC::G8RC_NOX0RegClass.contains(Reg)) {
1165  OpcodeIndex = SOK_Int8Spill;
1166  } else if (PPC::F8RCRegClass.contains(Reg)) {
1167  OpcodeIndex = SOK_Float8Spill;
1168  } else if (PPC::F4RCRegClass.contains(Reg)) {
1169  OpcodeIndex = SOK_Float4Spill;
1170  } else if (PPC::SPERCRegClass.contains(Reg)) {
1171  OpcodeIndex = SOK_SPESpill;
1172  } else if (PPC::SPE4RCRegClass.contains(Reg)) {
1173  OpcodeIndex = SOK_SPE4Spill;
1174  } else if (PPC::CRRCRegClass.contains(Reg)) {
1175  OpcodeIndex = SOK_CRSpill;
1176  } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1177  OpcodeIndex = SOK_CRBitSpill;
1178  } else if (PPC::VRRCRegClass.contains(Reg)) {
1179  OpcodeIndex = SOK_VRVectorSpill;
1180  } else if (PPC::VSRCRegClass.contains(Reg)) {
1181  OpcodeIndex = SOK_VSXVectorSpill;
1182  } else if (PPC::VSFRCRegClass.contains(Reg)) {
1183  OpcodeIndex = SOK_VectorFloat8Spill;
1184  } else if (PPC::VSSRCRegClass.contains(Reg)) {
1185  OpcodeIndex = SOK_VectorFloat4Spill;
1186  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1187  OpcodeIndex = SOK_VRSaveSpill;
1188  } else if (PPC::QFRCRegClass.contains(Reg)) {
1189  OpcodeIndex = SOK_QuadFloat8Spill;
1190  } else if (PPC::QSRCRegClass.contains(Reg)) {
1191  OpcodeIndex = SOK_QuadFloat4Spill;
1192  } else if (PPC::QBRCRegClass.contains(Reg)) {
1193  OpcodeIndex = SOK_QuadBitSpill;
1194  } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1195  OpcodeIndex = SOK_SpillToVSR;
1196  } else {
1197  llvm_unreachable("Unknown regclass!");
1198  }
1199  }
1200  return OpcodesForSpill[OpcodeIndex];
1201 }
1202 
1203 void PPCInstrInfo::StoreRegToStackSlot(
1204  MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1205  const TargetRegisterClass *RC,
1206  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1207  unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC);
1208  DebugLoc DL;
1209 
1210  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1211  FuncInfo->setHasSpills();
1212 
1214  BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1215  FrameIdx));
1216 
1217  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1218  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1219  FuncInfo->setSpillsCR();
1220 
1221  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1222  FuncInfo->setSpillsVRSAVE();
1223 
1224  if (isXFormMemOp(Opcode))
1225  FuncInfo->setHasNonRISpills();
1226 }
1227 
1230  unsigned SrcReg, bool isKill,
1231  int FrameIdx,
1232  const TargetRegisterClass *RC,
1233  const TargetRegisterInfo *TRI) const {
1234  MachineFunction &MF = *MBB.getParent();
1236 
1237  // We need to avoid a situation in which the value from a VRRC register is
1238  // spilled using an Altivec instruction and reloaded into a VSRC register
1239  // using a VSX instruction. The issue with this is that the VSX
1240  // load/store instructions swap the doublewords in the vector and the Altivec
1241  // ones don't. The register classes on the spill/reload may be different if
1242  // the register is defined using an Altivec instruction and is then used by a
1243  // VSX instruction.
1244  RC = updatedRC(RC);
1245 
1246  StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1247 
1248  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1249  MBB.insert(MI, NewMIs[i]);
1250 
1251  const MachineFrameInfo &MFI = MF.getFrameInfo();
1253  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1255  MFI.getObjectAlignment(FrameIdx));
1256  NewMIs.back()->addMemOperand(MF, MMO);
1257 }
1258 
1259 void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1260  unsigned DestReg, int FrameIdx,
1261  const TargetRegisterClass *RC,
1263  const {
1264  unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC);
1265  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1266  FrameIdx));
1267  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1268 
1269  if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1270  PPC::CRBITRCRegClass.hasSubClassEq(RC))
1271  FuncInfo->setSpillsCR();
1272 
1273  if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1274  FuncInfo->setSpillsVRSAVE();
1275 
1276  if (isXFormMemOp(Opcode))
1277  FuncInfo->setHasNonRISpills();
1278 }
1279 
1280 void
1283  unsigned DestReg, int FrameIdx,
1284  const TargetRegisterClass *RC,
1285  const TargetRegisterInfo *TRI) const {
1286  MachineFunction &MF = *MBB.getParent();
1288  DebugLoc DL;
1289  if (MI != MBB.end()) DL = MI->getDebugLoc();
1290 
1291  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1292  FuncInfo->setHasSpills();
1293 
1294  // We need to avoid a situation in which the value from a VRRC register is
1295  // spilled using an Altivec instruction and reloaded into a VSRC register
1296  // using a VSX instruction. The issue with this is that the VSX
1297  // load/store instructions swap the doublewords in the vector and the Altivec
1298  // ones don't. The register classes on the spill/reload may be different if
1299  // the register is defined using an Altivec instruction and is then used by a
1300  // VSX instruction.
1301  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1302  RC = &PPC::VSRCRegClass;
1303 
1304  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1305 
1306  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1307  MBB.insert(MI, NewMIs[i]);
1308 
1309  const MachineFrameInfo &MFI = MF.getFrameInfo();
1311  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1313  MFI.getObjectAlignment(FrameIdx));
1314  NewMIs.back()->addMemOperand(MF, MMO);
1315 }
1316 
1317 bool PPCInstrInfo::
1319  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1320  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1321  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1322  else
1323  // Leave the CR# the same, but invert the condition.
1324  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1325  return false;
1326 }
1327 
1329  unsigned Reg, MachineRegisterInfo *MRI) const {
1330  // For some instructions, it is legal to fold ZERO into the RA register field.
1331  // A zero immediate should always be loaded with a single li.
1332  unsigned DefOpc = DefMI.getOpcode();
1333  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1334  return false;
1335  if (!DefMI.getOperand(1).isImm())
1336  return false;
1337  if (DefMI.getOperand(1).getImm() != 0)
1338  return false;
1339 
1340  // Note that we cannot here invert the arguments of an isel in order to fold
1341  // a ZERO into what is presented as the second argument. All we have here
1342  // is the condition bit, and that might come from a CR-logical bit operation.
1343 
1344  const MCInstrDesc &UseMCID = UseMI.getDesc();
1345 
1346  // Only fold into real machine instructions.
1347  if (UseMCID.isPseudo())
1348  return false;
1349 
1350  unsigned UseIdx;
1351  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1352  if (UseMI.getOperand(UseIdx).isReg() &&
1353  UseMI.getOperand(UseIdx).getReg() == Reg)
1354  break;
1355 
1356  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1357  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1358 
1359  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1360 
1361  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1362  // register (which might also be specified as a pointer class kind).
1363  if (UseInfo->isLookupPtrRegClass()) {
1364  if (UseInfo->RegClass /* Kind */ != 1)
1365  return false;
1366  } else {
1367  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1368  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1369  return false;
1370  }
1371 
1372  // Make sure this is not tied to an output register (or otherwise
1373  // constrained). This is true for ST?UX registers, for example, which
1374  // are tied to their output registers.
1375  if (UseInfo->Constraints != 0)
1376  return false;
1377 
1378  unsigned ZeroReg;
1379  if (UseInfo->isLookupPtrRegClass()) {
1380  bool isPPC64 = Subtarget.isPPC64();
1381  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1382  } else {
1383  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1384  PPC::ZERO8 : PPC::ZERO;
1385  }
1386 
1387  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1388  UseMI.getOperand(UseIdx).setReg(ZeroReg);
1389 
1390  if (DeleteDef)
1391  DefMI.eraseFromParent();
1392 
1393  return true;
1394 }
1395 
1397  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1398  I != IE; ++I)
1399  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1400  return true;
1401  return false;
1402 }
1403 
1404 // We should make sure that, if we're going to predicate both sides of a
1405 // condition (a diamond), that both sides don't define the counter register. We
1406 // can predicate counter-decrement-based branches, but while that predicates
1407 // the branching, it does not predicate the counter decrement. If we tried to
1408 // merge the triangle into one predicated block, we'd decrement the counter
1409 // twice.
1411  unsigned NumT, unsigned ExtraT,
1412  MachineBasicBlock &FMBB,
1413  unsigned NumF, unsigned ExtraF,
1414  BranchProbability Probability) const {
1415  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1416 }
1417 
1418 
1420  // The predicated branches are identified by their type, not really by the
1421  // explicit presence of a predicate. Furthermore, some of them can be
1422  // predicated more than once. Because if conversion won't try to predicate
1423  // any instruction which already claims to be predicated (by returning true
1424  // here), always return false. In doing so, we let isPredicable() be the
1425  // final word on whether not the instruction can be (further) predicated.
1426 
1427  return false;
1428 }
1429 
1431  if (!MI.isTerminator())
1432  return false;
1433 
1434  // Conditional branch is a special case.
1435  if (MI.isBranch() && !MI.isBarrier())
1436  return true;
1437 
1438  return !isPredicated(MI);
1439 }
1440 
1442  ArrayRef<MachineOperand> Pred) const {
1443  unsigned OpC = MI.getOpcode();
1444  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1445  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1446  bool isPPC64 = Subtarget.isPPC64();
1447  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1448  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1449  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1450  MI.setDesc(get(PPC::BCLR));
1451  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1452  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1453  MI.setDesc(get(PPC::BCLRn));
1454  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1455  } else {
1456  MI.setDesc(get(PPC::BCCLR));
1458  .addImm(Pred[0].getImm())
1459  .add(Pred[1]);
1460  }
1461 
1462  return true;
1463  } else if (OpC == PPC::B) {
1464  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1465  bool isPPC64 = Subtarget.isPPC64();
1466  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1467  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1468  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1469  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1470  MI.RemoveOperand(0);
1471 
1472  MI.setDesc(get(PPC::BC));
1474  .add(Pred[1])
1475  .addMBB(MBB);
1476  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1477  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1478  MI.RemoveOperand(0);
1479 
1480  MI.setDesc(get(PPC::BCn));
1482  .add(Pred[1])
1483  .addMBB(MBB);
1484  } else {
1485  MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1486  MI.RemoveOperand(0);
1487 
1488  MI.setDesc(get(PPC::BCC));
1490  .addImm(Pred[0].getImm())
1491  .add(Pred[1])
1492  .addMBB(MBB);
1493  }
1494 
1495  return true;
1496  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL ||
1497  OpC == PPC::BCTRL8) {
1498  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1499  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1500 
1501  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1502  bool isPPC64 = Subtarget.isPPC64();
1503 
1504  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1505  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1506  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1507  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1508  return true;
1509  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1510  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1511  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1512  MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1513  return true;
1514  }
1515 
1516  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1517  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1519  .addImm(Pred[0].getImm())
1520  .add(Pred[1]);
1521  return true;
1522  }
1523 
1524  return false;
1525 }
1526 
1528  ArrayRef<MachineOperand> Pred2) const {
1529  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1530  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1531 
1532  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1533  return false;
1534  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1535  return false;
1536 
1537  // P1 can only subsume P2 if they test the same condition register.
1538  if (Pred1[1].getReg() != Pred2[1].getReg())
1539  return false;
1540 
1541  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1542  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1543 
1544  if (P1 == P2)
1545  return true;
1546 
1547  // Does P1 subsume P2, e.g. GE subsumes GT.
1548  if (P1 == PPC::PRED_LE &&
1549  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1550  return true;
1551  if (P1 == PPC::PRED_GE &&
1552  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1553  return true;
1554 
1555  return false;
1556 }
1557 
1559  std::vector<MachineOperand> &Pred) const {
1560  // Note: At the present time, the contents of Pred from this function is
1561  // unused by IfConversion. This implementation follows ARM by pushing the
1562  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1563  // predicate, instructions defining CTR or CTR8 are also included as
1564  // predicate-defining instructions.
1565 
1566  const TargetRegisterClass *RCs[] =
1567  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1568  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1569 
1570  bool Found = false;
1571  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1572  const MachineOperand &MO = MI.getOperand(i);
1573  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1574  const TargetRegisterClass *RC = RCs[c];
1575  if (MO.isReg()) {
1576  if (MO.isDef() && RC->contains(MO.getReg())) {
1577  Pred.push_back(MO);
1578  Found = true;
1579  }
1580  } else if (MO.isRegMask()) {
1581  for (TargetRegisterClass::iterator I = RC->begin(),
1582  IE = RC->end(); I != IE; ++I)
1583  if (MO.clobbersPhysReg(*I)) {
1584  Pred.push_back(MO);
1585  Found = true;
1586  }
1587  }
1588  }
1589  }
1590 
1591  return Found;
1592 }
1593 
1595  unsigned OpC = MI.getOpcode();
1596  switch (OpC) {
1597  default:
1598  return false;
1599  case PPC::B:
1600  case PPC::BLR:
1601  case PPC::BLR8:
1602  case PPC::BCTR:
1603  case PPC::BCTR8:
1604  case PPC::BCTRL:
1605  case PPC::BCTRL8:
1606  return true;
1607  }
1608 }
1609 
1610 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1611  unsigned &SrcReg2, int &Mask,
1612  int &Value) const {
1613  unsigned Opc = MI.getOpcode();
1614 
1615  switch (Opc) {
1616  default: return false;
1617  case PPC::CMPWI:
1618  case PPC::CMPLWI:
1619  case PPC::CMPDI:
1620  case PPC::CMPLDI:
1621  SrcReg = MI.getOperand(1).getReg();
1622  SrcReg2 = 0;
1623  Value = MI.getOperand(2).getImm();
1624  Mask = 0xFFFF;
1625  return true;
1626  case PPC::CMPW:
1627  case PPC::CMPLW:
1628  case PPC::CMPD:
1629  case PPC::CMPLD:
1630  case PPC::FCMPUS:
1631  case PPC::FCMPUD:
1632  SrcReg = MI.getOperand(1).getReg();
1633  SrcReg2 = MI.getOperand(2).getReg();
1634  Value = 0;
1635  Mask = 0;
1636  return true;
1637  }
1638 }
1639 
1640 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1641  unsigned SrcReg2, int Mask, int Value,
1642  const MachineRegisterInfo *MRI) const {
1643  if (DisableCmpOpt)
1644  return false;
1645 
1646  int OpC = CmpInstr.getOpcode();
1647  unsigned CRReg = CmpInstr.getOperand(0).getReg();
1648 
1649  // FP record forms set CR1 based on the exception status bits, not a
1650  // comparison with zero.
1651  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1652  return false;
1653 
1654  // The record forms set the condition register based on a signed comparison
1655  // with zero (so says the ISA manual). This is not as straightforward as it
1656  // seems, however, because this is always a 64-bit comparison on PPC64, even
1657  // for instructions that are 32-bit in nature (like slw for example).
1658  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1659  // for equality checks (as those don't depend on the sign). On PPC64,
1660  // we are restricted to equality for unsigned 64-bit comparisons and for
1661  // signed 32-bit comparisons the applicability is more restricted.
1662  bool isPPC64 = Subtarget.isPPC64();
1663  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1664  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1665  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1666 
1667  // Get the unique definition of SrcReg.
1668  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1669  if (!MI) return false;
1670 
1671  bool equalityOnly = false;
1672  bool noSub = false;
1673  if (isPPC64) {
1674  if (is32BitSignedCompare) {
1675  // We can perform this optimization only if MI is sign-extending.
1676  if (isSignExtended(*MI))
1677  noSub = true;
1678  else
1679  return false;
1680  } else if (is32BitUnsignedCompare) {
1681  // We can perform this optimization, equality only, if MI is
1682  // zero-extending.
1683  if (isZeroExtended(*MI)) {
1684  noSub = true;
1685  equalityOnly = true;
1686  } else
1687  return false;
1688  } else
1689  equalityOnly = is64BitUnsignedCompare;
1690  } else
1691  equalityOnly = is32BitUnsignedCompare;
1692 
1693  if (equalityOnly) {
1694  // We need to check the uses of the condition register in order to reject
1695  // non-equality comparisons.
1697  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1698  I != IE; ++I) {
1699  MachineInstr *UseMI = &*I;
1700  if (UseMI->getOpcode() == PPC::BCC) {
1701  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1702  unsigned PredCond = PPC::getPredicateCondition(Pred);
1703  // We ignore hint bits when checking for non-equality comparisons.
1704  if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1705  return false;
1706  } else if (UseMI->getOpcode() == PPC::ISEL ||
1707  UseMI->getOpcode() == PPC::ISEL8) {
1708  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1709  if (SubIdx != PPC::sub_eq)
1710  return false;
1711  } else
1712  return false;
1713  }
1714  }
1715 
1716  MachineBasicBlock::iterator I = CmpInstr;
1717 
1718  // Scan forward to find the first use of the compare.
1719  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1720  ++I) {
1721  bool FoundUse = false;
1723  J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1724  J != JE; ++J)
1725  if (&*J == &*I) {
1726  FoundUse = true;
1727  break;
1728  }
1729 
1730  if (FoundUse)
1731  break;
1732  }
1733 
1736 
1737  // There are two possible candidates which can be changed to set CR[01].
1738  // One is MI, the other is a SUB instruction.
1739  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1740  MachineInstr *Sub = nullptr;
1741  if (SrcReg2 != 0)
1742  // MI is not a candidate for CMPrr.
1743  MI = nullptr;
1744  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1745  // same BB as the comparison. This is to allow the check below to avoid calls
1746  // (and other explicit clobbers); instead we should really check for these
1747  // more explicitly (in at least a few predecessors).
1748  else if (MI->getParent() != CmpInstr.getParent())
1749  return false;
1750  else if (Value != 0) {
1751  // The record-form instructions set CR bit based on signed comparison
1752  // against 0. We try to convert a compare against 1 or -1 into a compare
1753  // against 0 to exploit record-form instructions. For example, we change
1754  // the condition "greater than -1" into "greater than or equal to 0"
1755  // and "less than 1" into "less than or equal to 0".
1756 
1757  // Since we optimize comparison based on a specific branch condition,
1758  // we don't optimize if condition code is used by more than once.
1759  if (equalityOnly || !MRI->hasOneUse(CRReg))
1760  return false;
1761 
1762  MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1763  if (UseMI->getOpcode() != PPC::BCC)
1764  return false;
1765 
1766  PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1767  PPC::Predicate NewPred = Pred;
1768  unsigned PredCond = PPC::getPredicateCondition(Pred);
1769  unsigned PredHint = PPC::getPredicateHint(Pred);
1770  int16_t Immed = (int16_t)Value;
1771 
1772  // When modifying the condition in the predicate, we propagate hint bits
1773  // from the original predicate to the new one.
1774  if (Immed == -1 && PredCond == PPC::PRED_GT)
1775  // We convert "greater than -1" into "greater than or equal to 0",
1776  // since we are assuming signed comparison by !equalityOnly
1777  NewPred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1778  else if (Immed == -1 && PredCond == PPC::PRED_LE)
1779  // We convert "less than or equal to -1" into "less than 0".
1780  NewPred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1781  else if (Immed == 1 && PredCond == PPC::PRED_LT)
1782  // We convert "less than 1" into "less than or equal to 0".
1783  NewPred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1784  else if (Immed == 1 && PredCond == PPC::PRED_GE)
1785  // We convert "greater than or equal to 1" into "greater than 0".
1786  NewPred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1787  else
1788  return false;
1789 
1790  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1791  NewPred));
1792  }
1793 
1794  // Search for Sub.
1796  --I;
1797 
1798  // Get ready to iterate backward from CmpInstr.
1799  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1800 
1801  for (; I != E && !noSub; --I) {
1802  const MachineInstr &Instr = *I;
1803  unsigned IOpC = Instr.getOpcode();
1804 
1805  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1806  Instr.readsRegister(PPC::CR0, TRI)))
1807  // This instruction modifies or uses the record condition register after
1808  // the one we want to change. While we could do this transformation, it
1809  // would likely not be profitable. This transformation removes one
1810  // instruction, and so even forcing RA to generate one move probably
1811  // makes it unprofitable.
1812  return false;
1813 
1814  // Check whether CmpInstr can be made redundant by the current instruction.
1815  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1816  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1817  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1818  ((Instr.getOperand(1).getReg() == SrcReg &&
1819  Instr.getOperand(2).getReg() == SrcReg2) ||
1820  (Instr.getOperand(1).getReg() == SrcReg2 &&
1821  Instr.getOperand(2).getReg() == SrcReg))) {
1822  Sub = &*I;
1823  break;
1824  }
1825 
1826  if (I == B)
1827  // The 'and' is below the comparison instruction.
1828  return false;
1829  }
1830 
1831  // Return false if no candidates exist.
1832  if (!MI && !Sub)
1833  return false;
1834 
1835  // The single candidate is called MI.
1836  if (!MI) MI = Sub;
1837 
1838  int NewOpC = -1;
1839  int MIOpC = MI->getOpcode();
1840  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 ||
1841  MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8)
1842  NewOpC = MIOpC;
1843  else {
1844  NewOpC = PPC::getRecordFormOpcode(MIOpC);
1845  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1846  NewOpC = MIOpC;
1847  }
1848 
1849  // FIXME: On the non-embedded POWER architectures, only some of the record
1850  // forms are fast, and we should use only the fast ones.
1851 
1852  // The defining instruction has a record form (or is already a record
1853  // form). It is possible, however, that we'll need to reverse the condition
1854  // code of the users.
1855  if (NewOpC == -1)
1856  return false;
1857 
1858  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1859  // needs to be updated to be based on SUB. Push the condition code
1860  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1861  // condition code of these operands will be modified.
1862  // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1863  // comparison against 0, which may modify predicate.
1864  bool ShouldSwap = false;
1865  if (Sub && Value == 0) {
1866  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1867  Sub->getOperand(2).getReg() == SrcReg;
1868 
1869  // The operands to subf are the opposite of sub, so only in the fixed-point
1870  // case, invert the order.
1871  ShouldSwap = !ShouldSwap;
1872  }
1873 
1874  if (ShouldSwap)
1876  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1877  I != IE; ++I) {
1878  MachineInstr *UseMI = &*I;
1879  if (UseMI->getOpcode() == PPC::BCC) {
1880  PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1881  unsigned PredCond = PPC::getPredicateCondition(Pred);
1882  assert((!equalityOnly ||
1883  PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&
1884  "Invalid predicate for equality-only optimization");
1885  (void)PredCond; // To suppress warning in release build.
1886  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1887  PPC::getSwappedPredicate(Pred)));
1888  } else if (UseMI->getOpcode() == PPC::ISEL ||
1889  UseMI->getOpcode() == PPC::ISEL8) {
1890  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1891  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1892  "Invalid CR bit for equality-only optimization");
1893 
1894  if (NewSubReg == PPC::sub_lt)
1895  NewSubReg = PPC::sub_gt;
1896  else if (NewSubReg == PPC::sub_gt)
1897  NewSubReg = PPC::sub_lt;
1898 
1899  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1900  NewSubReg));
1901  } else // We need to abort on a user we don't understand.
1902  return false;
1903  }
1904  assert(!(Value != 0 && ShouldSwap) &&
1905  "Non-zero immediate support and ShouldSwap"
1906  "may conflict in updating predicate");
1907 
1908  // Create a new virtual register to hold the value of the CR set by the
1909  // record-form instruction. If the instruction was not previously in
1910  // record form, then set the kill flag on the CR.
1911  CmpInstr.eraseFromParent();
1912 
1914  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1915  get(TargetOpcode::COPY), CRReg)
1916  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1917 
1918  // Even if CR0 register were dead before, it is alive now since the
1919  // instruction we just built uses it.
1920  MI->clearRegisterDeads(PPC::CR0);
1921 
1922  if (MIOpC != NewOpC) {
1923  // We need to be careful here: we're replacing one instruction with
1924  // another, and we need to make sure that we get all of the right
1925  // implicit uses and defs. On the other hand, the caller may be holding
1926  // an iterator to this instruction, and so we can't delete it (this is
1927  // specifically the case if this is the instruction directly after the
1928  // compare).
1929 
1930  // Rotates are expensive instructions. If we're emitting a record-form
1931  // rotate that can just be an andi/andis, we should just emit that.
1932  if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
1933  unsigned GPRRes = MI->getOperand(0).getReg();
1934  int64_t SH = MI->getOperand(2).getImm();
1935  int64_t MB = MI->getOperand(3).getImm();
1936  int64_t ME = MI->getOperand(4).getImm();
1937  // We can only do this if both the start and end of the mask are in the
1938  // same halfword.
1939  bool MBInLoHWord = MB >= 16;
1940  bool MEInLoHWord = ME >= 16;
1941  uint64_t Mask = ~0LLU;
1942 
1943  if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
1944  Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
1945  // The mask value needs to shift right 16 if we're emitting andis.
1946  Mask >>= MBInLoHWord ? 0 : 16;
1947  NewOpC = MIOpC == PPC::RLWINM ?
1948  (MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) :
1949  (MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8);
1950  } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
1951  (ME - MB + 1 == SH) && (MB >= 16)) {
1952  // If we are rotating by the exact number of bits as are in the mask
1953  // and the mask is in the least significant bits of the register,
1954  // that's just an andis. (as long as the GPR result has no uses).
1955  Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
1956  Mask >>= 16;
1957  NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8;
1958  }
1959  // If we've set the mask, we can transform.
1960  if (Mask != ~0LLU) {
1961  MI->RemoveOperand(4);
1962  MI->RemoveOperand(3);
1963  MI->getOperand(2).setImm(Mask);
1964  NumRcRotatesConvertedToRcAnd++;
1965  }
1966  } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
1967  int64_t MB = MI->getOperand(3).getImm();
1968  if (MB >= 48) {
1969  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
1970  NewOpC = PPC::ANDIo8;
1971  MI->RemoveOperand(3);
1972  MI->getOperand(2).setImm(Mask);
1973  NumRcRotatesConvertedToRcAnd++;
1974  }
1975  }
1976 
1977  const MCInstrDesc &NewDesc = get(NewOpC);
1978  MI->setDesc(NewDesc);
1979 
1980  if (NewDesc.ImplicitDefs)
1981  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1982  *ImpDefs; ++ImpDefs)
1983  if (!MI->definesRegister(*ImpDefs))
1984  MI->addOperand(*MI->getParent()->getParent(),
1985  MachineOperand::CreateReg(*ImpDefs, true, true));
1986  if (NewDesc.ImplicitUses)
1987  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1988  *ImpUses; ++ImpUses)
1989  if (!MI->readsRegister(*ImpUses))
1990  MI->addOperand(*MI->getParent()->getParent(),
1991  MachineOperand::CreateReg(*ImpUses, false, true));
1992  }
1993  assert(MI->definesRegister(PPC::CR0) &&
1994  "Record-form instruction does not define cr0?");
1995 
1996  // Modify the condition code of operands in OperandsToUpdate.
1997  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1998  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1999  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
2000  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
2001 
2002  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
2003  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
2004 
2005  return true;
2006 }
2007 
2008 /// GetInstSize - Return the number of bytes of code the specified
2009 /// instruction may be. This returns the maximum number of bytes.
2010 ///
2012  unsigned Opcode = MI.getOpcode();
2013 
2014  if (Opcode == PPC::INLINEASM) {
2015  const MachineFunction *MF = MI.getParent()->getParent();
2016  const char *AsmStr = MI.getOperand(0).getSymbolName();
2017  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
2018  } else if (Opcode == TargetOpcode::STACKMAP) {
2019  StackMapOpers Opers(&MI);
2020  return Opers.getNumPatchBytes();
2021  } else if (Opcode == TargetOpcode::PATCHPOINT) {
2022  PatchPointOpers Opers(&MI);
2023  return Opers.getNumPatchBytes();
2024  } else {
2025  return get(Opcode).getSize();
2026  }
2027 }
2028 
2029 std::pair<unsigned, unsigned>
2031  const unsigned Mask = PPCII::MO_ACCESS_MASK;
2032  return std::make_pair(TF & Mask, TF & ~Mask);
2033 }
2034 
2037  using namespace PPCII;
2038  static const std::pair<unsigned, const char *> TargetFlags[] = {
2039  {MO_LO, "ppc-lo"},
2040  {MO_HA, "ppc-ha"},
2041  {MO_TPREL_LO, "ppc-tprel-lo"},
2042  {MO_TPREL_HA, "ppc-tprel-ha"},
2043  {MO_DTPREL_LO, "ppc-dtprel-lo"},
2044  {MO_TLSLD_LO, "ppc-tlsld-lo"},
2045  {MO_TOC_LO, "ppc-toc-lo"},
2046  {MO_TLS, "ppc-tls"}};
2047  return makeArrayRef(TargetFlags);
2048 }
2049 
2052  using namespace PPCII;
2053  static const std::pair<unsigned, const char *> TargetFlags[] = {
2054  {MO_PLT, "ppc-plt"},
2055  {MO_PIC_FLAG, "ppc-pic"},
2056  {MO_NLP_FLAG, "ppc-nlp"},
2057  {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
2058  return makeArrayRef(TargetFlags);
2059 }
2060 
2061 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2062 // The VSX versions have the advantage of a full 64-register target whereas
2063 // the FP ones have the advantage of lower latency and higher throughput. So
2064 // what we are after is using the faster instructions in low register pressure
2065 // situations and using the larger register file in high register pressure
2066 // situations.
2068  unsigned UpperOpcode, LowerOpcode;
2069  switch (MI.getOpcode()) {
2070  case PPC::DFLOADf32:
2071  UpperOpcode = PPC::LXSSP;
2072  LowerOpcode = PPC::LFS;
2073  break;
2074  case PPC::DFLOADf64:
2075  UpperOpcode = PPC::LXSD;
2076  LowerOpcode = PPC::LFD;
2077  break;
2078  case PPC::DFSTOREf32:
2079  UpperOpcode = PPC::STXSSP;
2080  LowerOpcode = PPC::STFS;
2081  break;
2082  case PPC::DFSTOREf64:
2083  UpperOpcode = PPC::STXSD;
2084  LowerOpcode = PPC::STFD;
2085  break;
2086  case PPC::XFLOADf32:
2087  UpperOpcode = PPC::LXSSPX;
2088  LowerOpcode = PPC::LFSX;
2089  break;
2090  case PPC::XFLOADf64:
2091  UpperOpcode = PPC::LXSDX;
2092  LowerOpcode = PPC::LFDX;
2093  break;
2094  case PPC::XFSTOREf32:
2095  UpperOpcode = PPC::STXSSPX;
2096  LowerOpcode = PPC::STFSX;
2097  break;
2098  case PPC::XFSTOREf64:
2099  UpperOpcode = PPC::STXSDX;
2100  LowerOpcode = PPC::STFDX;
2101  break;
2102  case PPC::LIWAX:
2103  UpperOpcode = PPC::LXSIWAX;
2104  LowerOpcode = PPC::LFIWAX;
2105  break;
2106  case PPC::LIWZX:
2107  UpperOpcode = PPC::LXSIWZX;
2108  LowerOpcode = PPC::LFIWZX;
2109  break;
2110  case PPC::STIWX:
2111  UpperOpcode = PPC::STXSIWX;
2112  LowerOpcode = PPC::STFIWX;
2113  break;
2114  default:
2115  llvm_unreachable("Unknown Operation!");
2116  }
2117 
2118  unsigned TargetReg = MI.getOperand(0).getReg();
2119  unsigned Opcode;
2120  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2121  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2122  Opcode = LowerOpcode;
2123  else
2124  Opcode = UpperOpcode;
2125  MI.setDesc(get(Opcode));
2126  return true;
2127 }
2128 
2129 static bool isAnImmediateOperand(const MachineOperand &MO) {
2130  return MO.isCPI() || MO.isGlobal() || MO.isImm();
2131 }
2132 
2134  auto &MBB = *MI.getParent();
2135  auto DL = MI.getDebugLoc();
2136 
2137  switch (MI.getOpcode()) {
2138  case TargetOpcode::LOAD_STACK_GUARD: {
2139  assert(Subtarget.isTargetLinux() &&
2140  "Only Linux target is expected to contain LOAD_STACK_GUARD");
2141  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2142  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2143  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2145  .addImm(Offset)
2146  .addReg(Reg);
2147  return true;
2148  }
2149  case PPC::DFLOADf32:
2150  case PPC::DFLOADf64:
2151  case PPC::DFSTOREf32:
2152  case PPC::DFSTOREf64: {
2153  assert(Subtarget.hasP9Vector() &&
2154  "Invalid D-Form Pseudo-ops on Pre-P9 target.");
2155  assert(MI.getOperand(2).isReg() &&
2157  "D-form op must have register and immediate operands");
2158  return expandVSXMemPseudo(MI);
2159  }
2160  case PPC::XFLOADf32:
2161  case PPC::XFSTOREf32:
2162  case PPC::LIWAX:
2163  case PPC::LIWZX:
2164  case PPC::STIWX: {
2165  assert(Subtarget.hasP8Vector() &&
2166  "Invalid X-Form Pseudo-ops on Pre-P8 target.");
2167  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2168  "X-form op must have register and register operands");
2169  return expandVSXMemPseudo(MI);
2170  }
2171  case PPC::XFLOADf64:
2172  case PPC::XFSTOREf64: {
2173  assert(Subtarget.hasVSX() &&
2174  "Invalid X-Form Pseudo-ops on target that has no VSX.");
2175  assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2176  "X-form op must have register and register operands");
2177  return expandVSXMemPseudo(MI);
2178  }
2179  case PPC::SPILLTOVSR_LD: {
2180  unsigned TargetReg = MI.getOperand(0).getReg();
2181  if (PPC::VSFRCRegClass.contains(TargetReg)) {
2182  MI.setDesc(get(PPC::DFLOADf64));
2183  return expandPostRAPseudo(MI);
2184  }
2185  else
2186  MI.setDesc(get(PPC::LD));
2187  return true;
2188  }
2189  case PPC::SPILLTOVSR_ST: {
2190  unsigned SrcReg = MI.getOperand(0).getReg();
2191  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2192  NumStoreSPILLVSRRCAsVec++;
2193  MI.setDesc(get(PPC::DFSTOREf64));
2194  return expandPostRAPseudo(MI);
2195  } else {
2196  NumStoreSPILLVSRRCAsGpr++;
2197  MI.setDesc(get(PPC::STD));
2198  }
2199  return true;
2200  }
2201  case PPC::SPILLTOVSR_LDX: {
2202  unsigned TargetReg = MI.getOperand(0).getReg();
2203  if (PPC::VSFRCRegClass.contains(TargetReg))
2204  MI.setDesc(get(PPC::LXSDX));
2205  else
2206  MI.setDesc(get(PPC::LDX));
2207  return true;
2208  }
2209  case PPC::SPILLTOVSR_STX: {
2210  unsigned SrcReg = MI.getOperand(0).getReg();
2211  if (PPC::VSFRCRegClass.contains(SrcReg)) {
2212  NumStoreSPILLVSRRCAsVec++;
2213  MI.setDesc(get(PPC::STXSDX));
2214  } else {
2215  NumStoreSPILLVSRRCAsGpr++;
2216  MI.setDesc(get(PPC::STDX));
2217  }
2218  return true;
2219  }
2220 
2221  case PPC::CFENCE8: {
2222  auto Val = MI.getOperand(0).getReg();
2223  BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2224  BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2226  .addReg(PPC::CR7)
2227  .addImm(1);
2228  MI.setDesc(get(PPC::ISYNC));
2229  MI.RemoveOperand(0);
2230  return true;
2231  }
2232  }
2233  return false;
2234 }
2235 
2236 // Essentially a compile-time implementation of a compare->isel sequence.
2237 // It takes two constants to compare, along with the true/false registers
2238 // and the comparison type (as a subreg to a CR field) and returns one
2239 // of the true/false registers, depending on the comparison results.
2240 static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
2241  unsigned TrueReg, unsigned FalseReg,
2242  unsigned CRSubReg) {
2243  // Signed comparisons. The immediates are assumed to be sign-extended.
2244  if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
2245  switch (CRSubReg) {
2246  default: llvm_unreachable("Unknown integer comparison type.");
2247  case PPC::sub_lt:
2248  return Imm1 < Imm2 ? TrueReg : FalseReg;
2249  case PPC::sub_gt:
2250  return Imm1 > Imm2 ? TrueReg : FalseReg;
2251  case PPC::sub_eq:
2252  return Imm1 == Imm2 ? TrueReg : FalseReg;
2253  }
2254  }
2255  // Unsigned comparisons.
2256  else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
2257  switch (CRSubReg) {
2258  default: llvm_unreachable("Unknown integer comparison type.");
2259  case PPC::sub_lt:
2260  return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
2261  case PPC::sub_gt:
2262  return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
2263  case PPC::sub_eq:
2264  return Imm1 == Imm2 ? TrueReg : FalseReg;
2265  }
2266  }
2267  return PPC::NoRegister;
2268 }
2269 
2271  unsigned OpNo,
2272  int64_t Imm) const {
2273  assert(MI.getOperand(OpNo).isReg() && "Operand must be a REG");
2274  // Replace the REG with the Immediate.
2275  unsigned InUseReg = MI.getOperand(OpNo).getReg();
2276  MI.getOperand(OpNo).ChangeToImmediate(Imm);
2277 
2278  if (empty(MI.implicit_operands()))
2279  return;
2280 
2281  // We need to make sure that the MI didn't have any implicit use
2282  // of this REG any more.
2284  int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI);
2285  if (UseOpIdx >= 0) {
2286  MachineOperand &MO = MI.getOperand(UseOpIdx);
2287  if (MO.isImplicit())
2288  // The operands must always be in the following order:
2289  // - explicit reg defs,
2290  // - other explicit operands (reg uses, immediates, etc.),
2291  // - implicit reg defs
2292  // - implicit reg uses
2293  // Therefore, removing the implicit operand won't change the explicit
2294  // operands layout.
2295  MI.RemoveOperand(UseOpIdx);
2296  }
2297 }
2298 
2299 // Replace an instruction with one that materializes a constant (and sets
2300 // CR0 if the original instruction was a record-form instruction).
2302  const LoadImmediateInfo &LII) const {
2303  // Remove existing operands.
2304  int OperandToKeep = LII.SetCR ? 1 : 0;
2305  for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
2306  MI.RemoveOperand(i);
2307 
2308  // Replace the instruction.
2309  if (LII.SetCR) {
2310  MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2311  // Set the immediate.
2313  .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2314  return;
2315  }
2316  else
2317  MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2318 
2319  // Set the immediate.
2321  .addImm(LII.Imm);
2322 }
2323 
2324 MachineInstr *PPCInstrInfo::getForwardingDefMI(
2325  MachineInstr &MI,
2326  unsigned &OpNoForForwarding,
2327  bool &SeenIntermediateUse) const {
2328  OpNoForForwarding = ~0U;
2329  MachineInstr *DefMI = nullptr;
2332  // If we're in SSA, get the defs through the MRI. Otherwise, only look
2333  // within the basic block to see if the register is defined using an LI/LI8.
2334  if (MRI->isSSA()) {
2335  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2336  if (!MI.getOperand(i).isReg())
2337  continue;
2338  unsigned Reg = MI.getOperand(i).getReg();
2340  continue;
2341  unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
2343  DefMI = MRI->getVRegDef(TrueReg);
2344  if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
2345  OpNoForForwarding = i;
2346  break;
2347  }
2348  }
2349  }
2350  } else {
2351  // Looking back through the definition for each operand could be expensive,
2352  // so exit early if this isn't an instruction that either has an immediate
2353  // form or is already an immediate form that we can handle.
2354  ImmInstrInfo III;
2355  unsigned Opc = MI.getOpcode();
2356  bool ConvertibleImmForm =
2357  Opc == PPC::CMPWI || Opc == PPC::CMPLWI ||
2358  Opc == PPC::CMPDI || Opc == PPC::CMPLDI ||
2359  Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
2360  Opc == PPC::ORI || Opc == PPC::ORI8 ||
2361  Opc == PPC::XORI || Opc == PPC::XORI8 ||
2362  Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
2363  Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
2364  Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
2365  Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2366  if (!instrHasImmForm(MI, III, true) && !ConvertibleImmForm)
2367  return nullptr;
2368 
2369  // Don't convert or %X, %Y, %Y since that's just a register move.
2370  if ((Opc == PPC::OR || Opc == PPC::OR8) &&
2371  MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2372  return nullptr;
2373  for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2374  MachineOperand &MO = MI.getOperand(i);
2375  SeenIntermediateUse = false;
2376  if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2378  It++;
2379  unsigned Reg = MI.getOperand(i).getReg();
2380 
2381  // Is this register defined by some form of add-immediate (including
2382  // load-immediate) within this basic block?
2383  for ( ; It != E; ++It) {
2384  if (It->modifiesRegister(Reg, &getRegisterInfo())) {
2385  switch (It->getOpcode()) {
2386  default: break;
2387  case PPC::LI:
2388  case PPC::LI8:
2389  case PPC::ADDItocL:
2390  case PPC::ADDI:
2391  case PPC::ADDI8:
2392  OpNoForForwarding = i;
2393  return &*It;
2394  }
2395  break;
2396  } else if (It->readsRegister(Reg, &getRegisterInfo()))
2397  // If we see another use of this reg between the def and the MI,
2398  // we want to flat it so the def isn't deleted.
2399  SeenIntermediateUse = true;
2400  }
2401  }
2402  }
2403  }
2404  return OpNoForForwarding == ~0U ? nullptr : DefMI;
2405 }
2406 
2407 const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
2408  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2409  // Power 8
2410  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2411  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
2412  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2413  PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW},
2414  // Power 9
2415  {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2416  PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
2417  PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2418  PPC::SPILLTOVSR_ST}};
2419 
2420  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2421 }
2422 
2423 const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
2424  static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2425  // Power 8
2426  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2427  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
2428  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2429  PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ},
2430  // Power 9
2431  {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2432  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
2433  PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2434  PPC::SPILLTOVSR_LD}};
2435 
2436  return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2437 }
2438 
2440  unsigned RegNo) const {
2441  const MachineRegisterInfo &MRI =
2442  StartMI.getParent()->getParent()->getRegInfo();
2443  if (MRI.isSSA())
2444  return;
2445 
2446  // Instructions between [StartMI, EndMI] should be in same basic block.
2447  assert((StartMI.getParent() == EndMI.getParent()) &&
2448  "Instructions are not in same basic block");
2449 
2450  bool IsKillSet = false;
2451 
2452  auto clearOperandKillInfo = [=] (MachineInstr &MI, unsigned Index) {
2453  MachineOperand &MO = MI.getOperand(Index);
2454  if (MO.isReg() && MO.isUse() && MO.isKill() &&
2455  getRegisterInfo().regsOverlap(MO.getReg(), RegNo))
2456  MO.setIsKill(false);
2457  };
2458 
2459  // Set killed flag for EndMI.
2460  // No need to do anything if EndMI defines RegNo.
2461  int UseIndex =
2462  EndMI.findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
2463  if (UseIndex != -1) {
2464  EndMI.getOperand(UseIndex).setIsKill(true);
2465  IsKillSet = true;
2466  // Clear killed flag for other EndMI operands related to RegNo. In some
2467  // upexpected cases, killed may be set multiple times for same register
2468  // operand in same MI.
2469  for (int i = 0, e = EndMI.getNumOperands(); i != e; ++i)
2470  if (i != UseIndex)
2471  clearOperandKillInfo(EndMI, i);
2472  }
2473 
2474  // Walking the inst in reverse order (EndMI -> StartMI].
2477  // EndMI has been handled above, skip it here.
2478  It++;
2479  MachineOperand *MO = nullptr;
2480  for (; It != E; ++It) {
2481  // Skip insturctions which could not be a def/use of RegNo.
2482  if (It->isDebugInstr() || It->isPosition())
2483  continue;
2484 
2485  // Clear killed flag for all It operands related to RegNo. In some
2486  // upexpected cases, killed may be set multiple times for same register
2487  // operand in same MI.
2488  for (int i = 0, e = It->getNumOperands(); i != e; ++i)
2489  clearOperandKillInfo(*It, i);
2490 
2491  // If killed is not set, set killed for its last use or set dead for its def
2492  // if no use found.
2493  if (!IsKillSet) {
2494  if ((MO = It->findRegisterUseOperand(RegNo, false, &getRegisterInfo()))) {
2495  // Use found, set it killed.
2496  IsKillSet = true;
2497  MO->setIsKill(true);
2498  continue;
2499  } else if ((MO = It->findRegisterDefOperand(RegNo, false, true,
2500  &getRegisterInfo()))) {
2501  // No use found, set dead for its def.
2502  assert(&*It == &StartMI && "No new def between StartMI and EndMI.");
2503  MO->setIsDead(true);
2504  break;
2505  }
2506  }
2507 
2508  if ((&*It) == &StartMI)
2509  break;
2510  }
2511  // Ensure RegMo liveness is killed after EndMI.
2512  assert((IsKillSet || (MO && MO->isDead())) &&
2513  "RegNo should be killed or dead");
2514 }
2515 
2516 // If this instruction has an immediate form and one of its operands is a
2517 // result of a load-immediate or an add-immediate, convert it to
2518 // the immediate form if the constant is in range.
2520  MachineInstr **KilledDef) const {
2521  MachineFunction *MF = MI.getParent()->getParent();
2523  bool PostRA = !MRI->isSSA();
2524  bool SeenIntermediateUse = true;
2525  unsigned ForwardingOperand = ~0U;
2526  MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
2527  SeenIntermediateUse);
2528  if (!DefMI)
2529  return false;
2530  assert(ForwardingOperand < MI.getNumOperands() &&
2531  "The forwarding operand needs to be valid at this point");
2532  bool IsForwardingOperandKilled = MI.getOperand(ForwardingOperand).isKill();
2533  bool KillFwdDefMI = !SeenIntermediateUse && IsForwardingOperandKilled;
2534  unsigned ForwardingOperandReg = MI.getOperand(ForwardingOperand).getReg();
2535  if (KilledDef && KillFwdDefMI)
2536  *KilledDef = DefMI;
2537 
2538  ImmInstrInfo III;
2539  bool HasImmForm = instrHasImmForm(MI, III, PostRA);
2540  // If this is a reg+reg instruction that has a reg+imm form,
2541  // and one of the operands is produced by an add-immediate,
2542  // try to convert it.
2543  if (HasImmForm &&
2544  transformToImmFormFedByAdd(MI, III, ForwardingOperand, *DefMI,
2545  KillFwdDefMI))
2546  return true;
2547 
2548  if ((DefMI->getOpcode() != PPC::LI && DefMI->getOpcode() != PPC::LI8) ||
2549  !DefMI->getOperand(1).isImm())
2550  return false;
2551 
2552  int64_t Immediate = DefMI->getOperand(1).getImm();
2553  // Sign-extend to 64-bits.
2554  int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
2555  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
2556 
2557  // If this is a reg+reg instruction that has a reg+imm form,
2558  // and one of the operands is produced by LI, convert it now.
2559  if (HasImmForm)
2560  return transformToImmFormFedByLI(MI, III, ForwardingOperand, *DefMI, SExtImm);
2561 
2562  bool ReplaceWithLI = false;
2563  bool Is64BitLI = false;
2564  int64_t NewImm = 0;
2565  bool SetCR = false;
2566  unsigned Opc = MI.getOpcode();
2567  switch (Opc) {
2568  default: return false;
2569 
2570  // FIXME: Any branches conditional on such a comparison can be made
2571  // unconditional. At this time, this happens too infrequently to be worth
2572  // the implementation effort, but if that ever changes, we could convert
2573  // such a pattern here.
2574  case PPC::CMPWI:
2575  case PPC::CMPLWI:
2576  case PPC::CMPDI:
2577  case PPC::CMPLDI: {
2578  // Doing this post-RA would require dataflow analysis to reliably find uses
2579  // of the CR register set by the compare.
2580  // No need to fixup killed/dead flag since this transformation is only valid
2581  // before RA.
2582  if (PostRA)
2583  return false;
2584  // If a compare-immediate is fed by an immediate and is itself an input of
2585  // an ISEL (the most common case) into a COPY of the correct register.
2586  bool Changed = false;
2587  unsigned DefReg = MI.getOperand(0).getReg();
2588  int64_t Comparand = MI.getOperand(2).getImm();
2589  int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0 ?
2590  (Comparand | 0xFFFFFFFFFFFF0000) : Comparand;
2591 
2592  for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
2593  unsigned UseOpc = CompareUseMI.getOpcode();
2594  if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
2595  continue;
2596  unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2597  unsigned TrueReg = CompareUseMI.getOperand(1).getReg();
2598  unsigned FalseReg = CompareUseMI.getOperand(2).getReg();
2599  unsigned RegToCopy = selectReg(SExtImm, SExtComparand, Opc, TrueReg,
2600  FalseReg, CRSubReg);
2601  if (RegToCopy == PPC::NoRegister)
2602  continue;
2603  // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
2604  if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
2605  CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2606  replaceInstrOperandWithImm(CompareUseMI, 1, 0);
2607  CompareUseMI.RemoveOperand(3);
2608  CompareUseMI.RemoveOperand(2);
2609  continue;
2610  }
2611  LLVM_DEBUG(
2612  dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n");
2613  LLVM_DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump());
2614  LLVM_DEBUG(dbgs() << "Is converted to:\n");
2615  // Convert to copy and remove unneeded operands.
2616  CompareUseMI.setDesc(get(PPC::COPY));
2617  CompareUseMI.RemoveOperand(3);
2618  CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
2619  CmpIselsConverted++;
2620  Changed = true;
2621  LLVM_DEBUG(CompareUseMI.dump());
2622  }
2623  if (Changed)
2624  return true;
2625  // This may end up incremented multiple times since this function is called
2626  // during a fixed-point transformation, but it is only meant to indicate the
2627  // presence of this opportunity.
2628  MissedConvertibleImmediateInstrs++;
2629  return false;
2630  }
2631 
2632  // Immediate forms - may simply be convertable to an LI.
2633  case PPC::ADDI:
2634  case PPC::ADDI8: {
2635  // Does the sum fit in a 16-bit signed field?
2636  int64_t Addend = MI.getOperand(2).getImm();
2637  if (isInt<16>(Addend + SExtImm)) {
2638  ReplaceWithLI = true;
2639  Is64BitLI = Opc == PPC::ADDI8;
2640  NewImm = Addend + SExtImm;
2641  break;
2642  }
2643  return false;
2644  }
2645  case PPC::RLDICL:
2646  case PPC::RLDICLo:
2647  case PPC::RLDICL_32:
2648  case PPC::RLDICL_32_64: {
2649  // Use APInt's rotate function.
2650  int64_t SH = MI.getOperand(2).getImm();
2651  int64_t MB = MI.getOperand(3).getImm();
2652  APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
2653  64 : 32, SExtImm, true);
2654  InVal = InVal.rotl(SH);
2655  uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2656  InVal &= Mask;
2657  // Can't replace negative values with an LI as that will sign-extend
2658  // and not clear the left bits. If we're setting the CR bit, we will use
2659  // ANDIo which won't sign extend, so that's safe.
2660  if (isUInt<15>(InVal.getSExtValue()) ||
2661  (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
2662  ReplaceWithLI = true;
2663  Is64BitLI = Opc != PPC::RLDICL_32;
2664  NewImm = InVal.getSExtValue();
2665  SetCR = Opc == PPC::RLDICLo;
2666  break;
2667  }
2668  return false;
2669  }
2670  case PPC::RLWINM:
2671  case PPC::RLWINM8:
2672  case PPC::RLWINMo:
2673  case PPC::RLWINM8o: {
2674  int64_t SH = MI.getOperand(2).getImm();
2675  int64_t MB = MI.getOperand(3).getImm();
2676  int64_t ME = MI.getOperand(4).getImm();
2677  APInt InVal(32, SExtImm, true);
2678  InVal = InVal.rotl(SH);
2679  // Set the bits ( MB + 32 ) to ( ME + 32 ).
2680  uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2681  InVal &= Mask;
2682  // Can't replace negative values with an LI as that will sign-extend
2683  // and not clear the left bits. If we're setting the CR bit, we will use
2684  // ANDIo which won't sign extend, so that's safe.
2685  bool ValueFits = isUInt<15>(InVal.getSExtValue());
2686  ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
2687  isUInt<16>(InVal.getSExtValue()));
2688  if (ValueFits) {
2689  ReplaceWithLI = true;
2690  Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2691  NewImm = InVal.getSExtValue();
2692  SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2693  break;
2694  }
2695  return false;
2696  }
2697  case PPC::ORI:
2698  case PPC::ORI8:
2699  case PPC::XORI:
2700  case PPC::XORI8: {
2701  int64_t LogicalImm = MI.getOperand(2).getImm();
2702  int64_t Result = 0;
2703  if (Opc == PPC::ORI || Opc == PPC::ORI8)
2704  Result = LogicalImm | SExtImm;
2705  else
2706  Result = LogicalImm ^ SExtImm;
2707  if (isInt<16>(Result)) {
2708  ReplaceWithLI = true;
2709  Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
2710  NewImm = Result;
2711  break;
2712  }
2713  return false;
2714  }
2715  }
2716 
2717  if (ReplaceWithLI) {
2718  // We need to be careful with CR-setting instructions we're replacing.
2719  if (SetCR) {
2720  // We don't know anything about uses when we're out of SSA, so only
2721  // replace if the new immediate will be reproduced.
2722  bool ImmChanged = (SExtImm & NewImm) != NewImm;
2723  if (PostRA && ImmChanged)
2724  return false;
2725 
2726  if (!PostRA) {
2727  // If the defining load-immediate has no other uses, we can just replace
2728  // the immediate with the new immediate.
2729  if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
2730  DefMI->getOperand(1).setImm(NewImm);
2731 
2732  // If we're not using the GPR result of the CR-setting instruction, we
2733  // just need to and with zero/non-zero depending on the new immediate.
2734  else if (MRI->use_empty(MI.getOperand(0).getReg())) {
2735  if (NewImm) {
2736  assert(Immediate && "Transformation converted zero to non-zero?");
2737  NewImm = Immediate;
2738  }
2739  }
2740  else if (ImmChanged)
2741  return false;
2742  }
2743  }
2744 
2745  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
2746  LLVM_DEBUG(MI.dump());
2747  LLVM_DEBUG(dbgs() << "Fed by:\n");
2748  LLVM_DEBUG(DefMI->dump());
2749  LoadImmediateInfo LII;
2750  LII.Imm = NewImm;
2751  LII.Is64Bit = Is64BitLI;
2752  LII.SetCR = SetCR;
2753  // If we're setting the CR, the original load-immediate must be kept (as an
2754  // operand to ANDIo/ANDI8o).
2755  if (KilledDef && SetCR)
2756  *KilledDef = nullptr;
2757  replaceInstrWithLI(MI, LII);
2758 
2759  // Fixup killed/dead flag after transformation.
2760  // Pattern:
2761  // ForwardingOperandReg = LI imm1
2762  // y = op2 imm2, ForwardingOperandReg(killed)
2763  if (IsForwardingOperandKilled)
2764  fixupIsDeadOrKill(*DefMI, MI, ForwardingOperandReg);
2765 
2766  LLVM_DEBUG(dbgs() << "With:\n");
2767  LLVM_DEBUG(MI.dump());
2768  return true;
2769  }
2770  return false;
2771 }
2772 
2773 static bool isVFReg(unsigned Reg) {
2774  return PPC::VFRCRegClass.contains(Reg);
2775 }
2776 
2778  ImmInstrInfo &III, bool PostRA) const {
2779  unsigned Opc = MI.getOpcode();
2780  // The vast majority of the instructions would need their operand 2 replaced
2781  // with an immediate when switching to the reg+imm form. A marked exception
2782  // are the update form loads/stores for which a constant operand 2 would need
2783  // to turn into a displacement and move operand 1 to the operand 2 position.
2784  III.ImmOpNo = 2;
2785  III.OpNoForForwarding = 2;
2786  III.ImmWidth = 16;
2787  III.ImmMustBeMultipleOf = 1;
2788  III.TruncateImmTo = 0;
2789  III.IsSummingOperands = false;
2790  switch (Opc) {
2791  default: return false;
2792  case PPC::ADD4:
2793  case PPC::ADD8:
2794  III.SignedImm = true;
2795  III.ZeroIsSpecialOrig = 0;
2796  III.ZeroIsSpecialNew = 1;
2797  III.IsCommutative = true;
2798  III.IsSummingOperands = true;
2799  III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
2800  break;
2801  case PPC::ADDC:
2802  case PPC::ADDC8:
2803  III.SignedImm = true;
2804  III.ZeroIsSpecialOrig = 0;
2805  III.ZeroIsSpecialNew = 0;
2806  III.IsCommutative = true;
2807  III.IsSummingOperands = true;
2808  III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
2809  break;
2810  case PPC::ADDCo:
2811  III.SignedImm = true;
2812  III.ZeroIsSpecialOrig = 0;
2813  III.ZeroIsSpecialNew = 0;
2814  III.IsCommutative = true;
2815  III.IsSummingOperands = true;
2816  III.ImmOpcode = PPC::ADDICo;
2817  break;
2818  case PPC::SUBFC:
2819  case PPC::SUBFC8:
2820  III.SignedImm = true;
2821  III.ZeroIsSpecialOrig = 0;
2822  III.ZeroIsSpecialNew = 0;
2823  III.IsCommutative = false;
2824  III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
2825  break;
2826  case PPC::CMPW:
2827  case PPC::CMPD:
2828  III.SignedImm = true;
2829  III.ZeroIsSpecialOrig = 0;
2830  III.ZeroIsSpecialNew = 0;
2831  III.IsCommutative = false;
2832  III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
2833  break;
2834  case PPC::CMPLW:
2835  case PPC::CMPLD:
2836  III.SignedImm = false;
2837  III.ZeroIsSpecialOrig = 0;
2838  III.ZeroIsSpecialNew = 0;
2839  III.IsCommutative = false;
2840  III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
2841  break;
2842  case PPC::ANDo:
2843  case PPC::AND8o:
2844  case PPC::OR:
2845  case PPC::OR8:
2846  case PPC::XOR:
2847  case PPC::XOR8:
2848  III.SignedImm = false;
2849  III.ZeroIsSpecialOrig = 0;
2850  III.ZeroIsSpecialNew = 0;
2851  III.IsCommutative = true;
2852  switch(Opc) {
2853  default: llvm_unreachable("Unknown opcode");
2854  case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
2855  case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
2856  case PPC::OR: III.ImmOpcode = PPC::ORI; break;
2857  case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
2858  case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
2859  case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
2860  }
2861  break;
2862  case PPC::RLWNM:
2863  case PPC::RLWNM8:
2864  case PPC::RLWNMo:
2865  case PPC::RLWNM8o:
2866  case PPC::SLW:
2867  case PPC::SLW8:
2868  case PPC::SLWo:
2869  case PPC::SLW8o:
2870  case PPC::SRW:
2871  case PPC::SRW8:
2872  case PPC::SRWo:
2873  case PPC::SRW8o:
2874  case PPC::SRAW:
2875  case PPC::SRAWo:
2876  III.SignedImm = false;
2877  III.ZeroIsSpecialOrig = 0;
2878  III.ZeroIsSpecialNew = 0;
2879  III.IsCommutative = false;
2880  // This isn't actually true, but the instructions ignore any of the
2881  // upper bits, so any immediate loaded with an LI is acceptable.
2882  // This does not apply to shift right algebraic because a value
2883  // out of range will produce a -1/0.
2884  III.ImmWidth = 16;
2885  if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
2886  Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
2887  III.TruncateImmTo = 5;
2888  else
2889  III.TruncateImmTo = 6;
2890  switch(Opc) {
2891  default: llvm_unreachable("Unknown opcode");
2892  case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
2893  case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
2894  case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
2895  case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
2896  case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
2897  case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
2898  case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
2899  case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2900  case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
2901  case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
2902  case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
2903  case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2904  case PPC::SRAW:
2905  III.ImmWidth = 5;
2906  III.TruncateImmTo = 0;
2907  III.ImmOpcode = PPC::SRAWI;
2908  break;
2909  case PPC::SRAWo:
2910  III.ImmWidth = 5;
2911  III.TruncateImmTo = 0;
2912  III.ImmOpcode = PPC::SRAWIo;
2913  break;
2914  }
2915  break;
2916  case PPC::RLDCL:
2917  case PPC::RLDCLo:
2918  case PPC::RLDCR:
2919  case PPC::RLDCRo:
2920  case PPC::SLD:
2921  case PPC::SLDo:
2922  case PPC::SRD:
2923  case PPC::SRDo:
2924  case PPC::SRAD:
2925  case PPC::SRADo:
2926  III.SignedImm = false;
2927  III.ZeroIsSpecialOrig = 0;
2928  III.ZeroIsSpecialNew = 0;
2929  III.IsCommutative = false;
2930  // This isn't actually true, but the instructions ignore any of the
2931  // upper bits, so any immediate loaded with an LI is acceptable.
2932  // This does not apply to shift right algebraic because a value
2933  // out of range will produce a -1/0.
2934  III.ImmWidth = 16;
2935  if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
2936  Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
2937  III.TruncateImmTo = 6;
2938  else
2939  III.TruncateImmTo = 7;
2940  switch(Opc) {
2941  default: llvm_unreachable("Unknown opcode");
2942  case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
2943  case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
2944  case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
2945  case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
2946  case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
2947  case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
2948  case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
2949  case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
2950  case PPC::SRAD:
2951  III.ImmWidth = 6;
2952  III.TruncateImmTo = 0;
2953  III.ImmOpcode = PPC::SRADI;
2954  break;
2955  case PPC::SRADo:
2956  III.ImmWidth = 6;
2957  III.TruncateImmTo = 0;
2958  III.ImmOpcode = PPC::SRADIo;
2959  break;
2960  }
2961  break;
2962  // Loads and stores:
2963  case PPC::LBZX:
2964  case PPC::LBZX8:
2965  case PPC::LHZX:
2966  case PPC::LHZX8:
2967  case PPC::LHAX:
2968  case PPC::LHAX8:
2969  case PPC::LWZX:
2970  case PPC::LWZX8:
2971  case PPC::LWAX:
2972  case PPC::LDX:
2973  case PPC::LFSX:
2974  case PPC::LFDX:
2975  case PPC::STBX:
2976  case PPC::STBX8:
2977  case PPC::STHX:
2978  case PPC::STHX8:
2979  case PPC::STWX:
2980  case PPC::STWX8:
2981  case PPC::STDX:
2982  case PPC::STFSX:
2983  case PPC::STFDX:
2984  III.SignedImm = true;
2985  III.ZeroIsSpecialOrig = 1;
2986  III.ZeroIsSpecialNew = 2;
2987  III.IsCommutative = true;
2988  III.IsSummingOperands = true;
2989  III.ImmOpNo = 1;
2990  III.OpNoForForwarding = 2;
2991  switch(Opc) {
2992  default: llvm_unreachable("Unknown opcode");
2993  case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
2994  case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
2995  case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
2996  case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
2997  case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
2998  case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
2999  case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
3000  case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
3001  case PPC::LWAX:
3002  III.ImmOpcode = PPC::LWA;
3003  III.ImmMustBeMultipleOf = 4;
3004  break;
3005  case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
3006  case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
3007  case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
3008  case PPC::STBX: III.ImmOpcode = PPC::STB; break;
3009  case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
3010  case PPC::STHX: III.ImmOpcode = PPC::STH; break;
3011  case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
3012  case PPC::STWX: III.ImmOpcode = PPC::STW; break;
3013  case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
3014  case PPC::STDX:
3015  III.ImmOpcode = PPC::STD;
3016  III.ImmMustBeMultipleOf = 4;
3017  break;
3018  case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
3019  case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
3020  }
3021  break;
3022  case PPC::LBZUX:
3023  case PPC::LBZUX8:
3024  case PPC::LHZUX:
3025  case PPC::LHZUX8:
3026  case PPC::LHAUX:
3027  case PPC::LHAUX8:
3028  case PPC::LWZUX:
3029  case PPC::LWZUX8:
3030  case PPC::LDUX:
3031  case PPC::LFSUX:
3032  case PPC::LFDUX:
3033  case PPC::STBUX:
3034  case PPC::STBUX8:
3035  case PPC::STHUX:
3036  case PPC::STHUX8:
3037  case PPC::STWUX:
3038  case PPC::STWUX8:
3039  case PPC::STDUX:
3040  case PPC::STFSUX:
3041  case PPC::STFDUX:
3042  III.SignedImm = true;
3043  III.ZeroIsSpecialOrig = 2;
3044  III.ZeroIsSpecialNew = 3;
3045  III.IsCommutative = false;
3046  III.IsSummingOperands = true;
3047  III.ImmOpNo = 2;
3048  III.OpNoForForwarding = 3;
3049  switch(Opc) {
3050  default: llvm_unreachable("Unknown opcode");
3051  case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
3052  case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
3053  case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
3054  case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
3055  case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
3056  case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
3057  case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
3058  case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
3059  case PPC::LDUX:
3060  III.ImmOpcode = PPC::LDU;
3061  III.ImmMustBeMultipleOf = 4;
3062  break;
3063  case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
3064  case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
3065  case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
3066  case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
3067  case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
3068  case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
3069  case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
3070  case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
3071  case PPC::STDUX:
3072  III.ImmOpcode = PPC::STDU;
3073  III.ImmMustBeMultipleOf = 4;
3074  break;
3075  case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
3076  case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
3077  }
3078  break;
3079  // Power9 and up only. For some of these, the X-Form version has access to all
3080  // 64 VSR's whereas the D-Form only has access to the VR's. We replace those
3081  // with pseudo-ops pre-ra and for post-ra, we check that the register loaded
3082  // into or stored from is one of the VR registers.
3083  case PPC::LXVX:
3084  case PPC::LXSSPX:
3085  case PPC::LXSDX:
3086  case PPC::STXVX:
3087  case PPC::STXSSPX:
3088  case PPC::STXSDX:
3089  case PPC::XFLOADf32:
3090  case PPC::XFLOADf64:
3091  case PPC::XFSTOREf32:
3092  case PPC::XFSTOREf64:
3093  if (!Subtarget.hasP9Vector())
3094  return false;
3095  III.SignedImm = true;
3096  III.ZeroIsSpecialOrig = 1;
3097  III.ZeroIsSpecialNew = 2;
3098  III.IsCommutative = true;
3099  III.IsSummingOperands = true;
3100  III.ImmOpNo = 1;
3101  III.OpNoForForwarding = 2;
3102  III.ImmMustBeMultipleOf = 4;
3103  switch(Opc) {
3104  default: llvm_unreachable("Unknown opcode");
3105  case PPC::LXVX:
3106  III.ImmOpcode = PPC::LXV;
3107  III.ImmMustBeMultipleOf = 16;
3108  break;
3109  case PPC::LXSSPX:
3110  if (PostRA) {
3111  if (isVFReg(MI.getOperand(0).getReg()))
3112  III.ImmOpcode = PPC::LXSSP;
3113  else {
3114  III.ImmOpcode = PPC::LFS;
3115  III.ImmMustBeMultipleOf = 1;
3116  }
3117  break;
3118  }
3120  case PPC::XFLOADf32:
3121  III.ImmOpcode = PPC::DFLOADf32;
3122  break;
3123  case PPC::LXSDX:
3124  if (PostRA) {
3125  if (isVFReg(MI.getOperand(0).getReg()))
3126  III.ImmOpcode = PPC::LXSD;
3127  else {
3128  III.ImmOpcode = PPC::LFD;
3129  III.ImmMustBeMultipleOf = 1;
3130  }
3131  break;
3132  }
3134  case PPC::XFLOADf64:
3135  III.ImmOpcode = PPC::DFLOADf64;
3136  break;
3137  case PPC::STXVX:
3138  III.ImmOpcode = PPC::STXV;
3139  III.ImmMustBeMultipleOf = 16;
3140  break;
3141  case PPC::STXSSPX:
3142  if (PostRA) {
3143  if (isVFReg(MI.getOperand(0).getReg()))
3144  III.ImmOpcode = PPC::STXSSP;
3145  else {
3146  III.ImmOpcode = PPC::STFS;
3147  III.ImmMustBeMultipleOf = 1;
3148  }
3149  break;
3150  }
3152  case PPC::XFSTOREf32:
3153  III.ImmOpcode = PPC::DFSTOREf32;
3154  break;
3155  case PPC::STXSDX:
3156  if (PostRA) {
3157  if (isVFReg(MI.getOperand(0).getReg()))
3158  III.ImmOpcode = PPC::STXSD;
3159  else {
3160  III.ImmOpcode = PPC::STFD;
3161  III.ImmMustBeMultipleOf = 1;
3162  }
3163  break;
3164  }
3166  case PPC::XFSTOREf64:
3167  III.ImmOpcode = PPC::DFSTOREf64;
3168  break;
3169  }
3170  break;
3171  }
3172  return true;
3173 }
3174 
3175 // Utility function for swaping two arbitrary operands of an instruction.
3176 static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
3177  assert(Op1 != Op2 && "Cannot swap operand with itself.");
3178 
3179  unsigned MaxOp = std::max(Op1, Op2);
3180  unsigned MinOp = std::min(Op1, Op2);
3181  MachineOperand MOp1 = MI.getOperand(MinOp);
3182  MachineOperand MOp2 = MI.getOperand(MaxOp);
3183  MI.RemoveOperand(std::max(Op1, Op2));
3184  MI.RemoveOperand(std::min(Op1, Op2));
3185 
3186  // If the operands we are swapping are the two at the end (the common case)
3187  // we can just remove both and add them in the opposite order.
3188  if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
3189  MI.addOperand(MOp2);
3190  MI.addOperand(MOp1);
3191  } else {
3192  // Store all operands in a temporary vector, remove them and re-add in the
3193  // right order.
3195  unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
3196  for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
3197  MOps.push_back(MI.getOperand(i));
3198  MI.RemoveOperand(i);
3199  }
3200  // MOp2 needs to be added next.
3201  MI.addOperand(MOp2);
3202  // Now add the rest.
3203  for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
3204  if (i == MaxOp)
3205  MI.addOperand(MOp1);
3206  else {
3207  MI.addOperand(MOps.back());
3208  MOps.pop_back();
3209  }
3210  }
3211  }
3212 }
3213 
3214 // Check if the 'MI' that has the index OpNoForForwarding
3215 // meets the requirement described in the ImmInstrInfo.
3216 bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
3217  const ImmInstrInfo &III,
3218  unsigned OpNoForForwarding
3219  ) const {
3220  // As the algorithm of checking for PPC::ZERO/PPC::ZERO8
3221  // would not work pre-RA, we can only do the check post RA.
3223  if (MRI.isSSA())
3224  return false;
3225 
3226  // Cannot do the transform if MI isn't summing the operands.
3227  if (!III.IsSummingOperands)
3228  return false;
3229 
3230  // The instruction we are trying to replace must have the ZeroIsSpecialOrig set.
3231  if (!III.ZeroIsSpecialOrig)
3232  return false;
3233 
3234  // We cannot do the transform if the operand we are trying to replace
3235  // isn't the same as the operand the instruction allows.
3236  if (OpNoForForwarding != III.OpNoForForwarding)
3237  return false;
3238 
3239  // Check if the instruction we are trying to transform really has
3240  // the special zero register as its operand.
3241  if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
3242  MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
3243  return false;
3244 
3245  // This machine instruction is convertible if it is,
3246  // 1. summing the operands.
3247  // 2. one of the operands is special zero register.
3248  // 3. the operand we are trying to replace is allowed by the MI.
3249  return true;
3250 }
3251 
3252 // Check if the DefMI is the add inst and set the ImmMO and RegMO
3253 // accordingly.
3254 bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
3255  const ImmInstrInfo &III,
3256  MachineOperand *&ImmMO,
3257  MachineOperand *&RegMO) const {
3258  unsigned Opc = DefMI.getOpcode();
3259  if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
3260  return false;
3261 
3262  assert(DefMI.getNumOperands() >= 3 &&
3263  "Add inst must have at least three operands");
3264  RegMO = &DefMI.getOperand(1);
3265  ImmMO = &DefMI.getOperand(2);
3266 
3267  // This DefMI is elgible for forwarding if it is:
3268  // 1. add inst
3269  // 2. one of the operands is Imm/CPI/Global.
3270  return isAnImmediateOperand(*ImmMO);
3271 }
3272 
3273 bool PPCInstrInfo::isRegElgibleForForwarding(
3274  const MachineOperand &RegMO, const MachineInstr &DefMI,
3275  const MachineInstr &MI, bool KillDefMI,
3276  bool &IsFwdFeederRegKilled) const {
3277  // x = addi y, imm
3278  // ...
3279  // z = lfdx 0, x -> z = lfd imm(y)
3280  // The Reg "y" can be forwarded to the MI(z) only when there is no DEF
3281  // of "y" between the DEF of "x" and "z".
3282  // The query is only valid post RA.
3284  if (MRI.isSSA())
3285  return false;
3286 
3287  unsigned Reg = RegMO.getReg();
3288 
3289  // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
3292  It++;
3293  for (; It != E; ++It) {
3294  if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3295  return false;
3296  else if (It->killsRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3297  IsFwdFeederRegKilled = true;
3298  // Made it to DefMI without encountering a clobber.
3299  if ((&*It) == &DefMI)
3300  break;
3301  }
3302  assert((&*It) == &DefMI && "DefMI is missing");
3303 
3304  // If DefMI also defines the register to be forwarded, we can only forward it
3305  // if DefMI is being erased.
3306  if (DefMI.modifiesRegister(Reg, &getRegisterInfo()))
3307  return KillDefMI;
3308 
3309  return true;
3310 }
3311 
3312 bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
3313  const MachineInstr &DefMI,
3314  const ImmInstrInfo &III,
3315  int64_t &Imm) const {
3316  assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate");
3317  if (DefMI.getOpcode() == PPC::ADDItocL) {
3318  // The operand for ADDItocL is CPI, which isn't imm at compiling time,
3319  // However, we know that, it is 16-bit width, and has the alignment of 4.
3320  // Check if the instruction met the requirement.
3321  if (III.ImmMustBeMultipleOf > 4 ||
3322  III.TruncateImmTo || III.ImmWidth != 16)
3323  return false;
3324 
3325  // Going from XForm to DForm loads means that the displacement needs to be
3326  // not just an immediate but also a multiple of 4, or 16 depending on the
3327  // load. A DForm load cannot be represented if it is a multiple of say 2.
3328  // XForm loads do not have this restriction.
3329  if (ImmMO.isGlobal() &&
3330  ImmMO.getGlobal()->getAlignment() < III.ImmMustBeMultipleOf)
3331  return false;
3332 
3333  return true;
3334  }
3335 
3336  if (ImmMO.isImm()) {
3337  // It is Imm, we need to check if the Imm fit the range.
3338  int64_t Immediate = ImmMO.getImm();
3339  // Sign-extend to 64-bits.
3340  Imm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
3341  (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
3342 
3343  if (Imm % III.ImmMustBeMultipleOf)
3344  return false;
3345  if (III.TruncateImmTo)
3346  Imm &= ((1 << III.TruncateImmTo) - 1);
3347  if (III.SignedImm) {
3348  APInt ActualValue(64, Imm, true);
3349  if (!ActualValue.isSignedIntN(III.ImmWidth))
3350  return false;
3351  } else {
3352  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3353  if ((uint64_t)Imm > UnsignedMax)
3354  return false;
3355  }
3356  }
3357  else
3358  return false;
3359 
3360  // This ImmMO is forwarded if it meets the requriement describle
3361  // in ImmInstrInfo
3362  return true;
3363 }
3364 
3365 // If an X-Form instruction is fed by an add-immediate and one of its operands
3366 // is the literal zero, attempt to forward the source of the add-immediate to
3367 // the corresponding D-Form instruction with the displacement coming from
3368 // the immediate being added.
3369 bool PPCInstrInfo::transformToImmFormFedByAdd(
3370  MachineInstr &MI, const ImmInstrInfo &III, unsigned OpNoForForwarding,
3371  MachineInstr &DefMI, bool KillDefMI) const {
3372  // RegMO ImmMO
3373  // | |
3374  // x = addi reg, imm <----- DefMI
3375  // y = op 0 , x <----- MI
3376  // |
3377  // OpNoForForwarding
3378  // Check if the MI meet the requirement described in the III.
3379  if (!isUseMIElgibleForForwarding(MI, III, OpNoForForwarding))
3380  return false;
3381 
3382  // Check if the DefMI meet the requirement
3383  // described in the III. If yes, set the ImmMO and RegMO accordingly.
3384  MachineOperand *ImmMO = nullptr;
3385  MachineOperand *RegMO = nullptr;
3386  if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
3387  return false;
3388  assert(ImmMO && RegMO && "Imm and Reg operand must have been set");
3389 
3390  // As we get the Imm operand now, we need to check if the ImmMO meet
3391  // the requirement described in the III. If yes set the Imm.
3392  int64_t Imm = 0;
3393  if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
3394  return false;
3395 
3396  bool IsFwdFeederRegKilled = false;
3397  // Check if the RegMO can be forwarded to MI.
3398  if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI,
3399  IsFwdFeederRegKilled))
3400  return false;
3401 
3402  // Get killed info in case fixup needed after transformation.
3403  unsigned ForwardKilledOperandReg = ~0U;
3405  bool PostRA = !MRI.isSSA();
3406  if (PostRA && MI.getOperand(OpNoForForwarding).isKill())
3407  ForwardKilledOperandReg = MI.getOperand(OpNoForForwarding).getReg();
3408 
3409  // We know that, the MI and DefMI both meet the pattern, and
3410  // the Imm also meet the requirement with the new Imm-form.
3411  // It is safe to do the transformation now.
3412  LLVM_DEBUG(dbgs() << "Replacing instruction:\n");
3413  LLVM_DEBUG(MI.dump());
3414  LLVM_DEBUG(dbgs() << "Fed by:\n");
3415  LLVM_DEBUG(DefMI.dump());
3416 
3417  // Update the base reg first.
3419  false, false,
3420  RegMO->isKill());
3421 
3422  // Then, update the imm.
3423  if (ImmMO->isImm()) {
3424  // If the ImmMO is Imm, change the operand that has ZERO to that Imm
3425  // directly.
3427  }
3428  else {
3429  // Otherwise, it is Constant Pool Index(CPI) or Global,
3430  // which is relocation in fact. We need to replace the special zero
3431  // register with ImmMO.
3432  // Before that, we need to fixup the target flags for imm.
3433  // For some reason, we miss to set the flag for the ImmMO if it is CPI.
3434  if (DefMI.getOpcode() == PPC::ADDItocL)
3436 
3437  // MI didn't have the interface such as MI.setOperand(i) though
3438  // it has MI.getOperand(i). To repalce the ZERO MachineOperand with
3439  // ImmMO, we need to remove ZERO operand and all the operands behind it,
3440  // and, add the ImmMO, then, move back all the operands behind ZERO.
3442  for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
3443  MOps.push_back(MI.getOperand(i));
3444  MI.RemoveOperand(i);
3445  }
3446 
3447  // Remove the last MO in the list, which is ZERO operand in fact.
3448  MOps.pop_back();
3449  // Add the imm operand.
3450  MI.addOperand(*ImmMO);
3451  // Now add the rest back.
3452  for (auto &MO : MOps)
3453  MI.addOperand(MO);
3454  }
3455 
3456  // Update the opcode.
3457  MI.setDesc(get(III.ImmOpcode));
3458 
3459  // Fix up killed/dead flag after transformation.
3460  // Pattern 1:
3461  // x = ADD KilledFwdFeederReg, imm
3462  // n = opn KilledFwdFeederReg(killed), regn
3463  // y = XOP 0, x
3464  // Pattern 2:
3465  // x = ADD reg(killed), imm
3466  // y = XOP 0, x
3467  if (IsFwdFeederRegKilled || RegMO->isKill())
3468  fixupIsDeadOrKill(DefMI, MI, RegMO->getReg());
3469  // Pattern 3:
3470  // ForwardKilledOperandReg = ADD reg, imm
3471  // y = XOP 0, ForwardKilledOperandReg(killed)
3472  if (ForwardKilledOperandReg != ~0U)
3473  fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
3474 
3475  LLVM_DEBUG(dbgs() << "With:\n");
3476  LLVM_DEBUG(MI.dump());
3477 
3478  return true;
3479 }
3480 
3481 bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
3482  const ImmInstrInfo &III,
3483  unsigned ConstantOpNo,
3484  MachineInstr &DefMI,
3485  int64_t Imm) const {
3487  bool PostRA = !MRI.isSSA();
3488  // Exit early if we can't convert this.
3489  if ((ConstantOpNo != III.OpNoForForwarding) && !III.IsCommutative)
3490  return false;
3491  if (Imm % III.ImmMustBeMultipleOf)
3492  return false;
3493  if (III.TruncateImmTo)
3494  Imm &= ((1 << III.TruncateImmTo) - 1);
3495  if (III.SignedImm) {
3496  APInt ActualValue(64, Imm, true);
3497  if (!ActualValue.isSignedIntN(III.ImmWidth))
3498  return false;
3499  } else {
3500  uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3501  if ((uint64_t)Imm > UnsignedMax)
3502  return false;
3503  }
3504 
3505  // If we're post-RA, the instructions don't agree on whether register zero is
3506  // special, we can transform this as long as the register operand that will
3507  // end up in the location where zero is special isn't R0.
3508  if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3509  unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
3510  III.ZeroIsSpecialNew + 1;
3511  unsigned OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3512  unsigned NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3513  // If R0 is in the operand where zero is special for the new instruction,
3514  // it is unsafe to transform if the constant operand isn't that operand.
3515  if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
3516  ConstantOpNo != III.ZeroIsSpecialNew)
3517  return false;
3518  if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
3519  ConstantOpNo != PosForOrigZero)
3520  return false;
3521  }
3522 
3523  // Get killed info in case fixup needed after transformation.
3524  unsigned ForwardKilledOperandReg = ~0U;
3525  if (PostRA && MI.getOperand(ConstantOpNo).isKill())
3526  ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
3527 
3528  unsigned Opc = MI.getOpcode();
3529  bool SpecialShift32 =
3530  Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
3531  bool SpecialShift64 =
3532  Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
3533  bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
3534  Opc == PPC::SLDo || Opc == PPC::SRDo;
3535  bool RightShift =
3536  Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
3537 
3538  MI.setDesc(get(III.ImmOpcode));
3539  if (ConstantOpNo == III.OpNoForForwarding) {
3540  // Converting shifts to immediate form is a bit tricky since they may do
3541  // one of three things:
3542  // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
3543  // 2. If the shift amount is zero, the result is unchanged (save for maybe
3544  // setting CR0)
3545  // 3. If the shift amount is in [1, OpSize), it's just a shift
3546  if (SpecialShift32 || SpecialShift64) {
3547  LoadImmediateInfo LII;
3548  LII.Imm = 0;
3549  LII.SetCR = SetCR;
3550  LII.Is64Bit = SpecialShift64;
3551  uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
3552  if (Imm & (SpecialShift32 ? 0x20 : 0x40))
3553  replaceInstrWithLI(MI, LII);
3554  // Shifts by zero don't change the value. If we don't need to set CR0,
3555  // just convert this to a COPY. Can't do this post-RA since we've already
3556  // cleaned up the copies.
3557  else if (!SetCR && ShAmt == 0 && !PostRA) {
3558  MI.RemoveOperand(2);
3559  MI.setDesc(get(PPC::COPY));
3560  } else {
3561  // The 32 bit and 64 bit instructions are quite different.
3562  if (SpecialShift32) {
3563  // Left shifts use (N, 0, 31-N), right shifts use (32-N, N, 31).
3564  uint64_t SH = RightShift ? 32 - ShAmt : ShAmt;
3565  uint64_t MB = RightShift ? ShAmt : 0;
3566  uint64_t ME = RightShift ? 31 : 31 - ShAmt;
3568  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3569  .addImm(ME);
3570  } else {
3571  // Left shifts use (N, 63-N), right shifts use (64-N, N).
3572  uint64_t SH = RightShift ? 64 - ShAmt : ShAmt;
3573  uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
3575  MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
3576  }
3577  }
3578  } else
3579  replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3580  }
3581  // Convert commutative instructions (switch the operands and convert the
3582  // desired one to an immediate.
3583  else if (III.IsCommutative) {
3584  replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3585  swapMIOperands(MI, ConstantOpNo, III.OpNoForForwarding);
3586  } else
3587  llvm_unreachable("Should have exited early!");
3588 
3589  // For instructions for which the constant register replaces a different
3590  // operand than where the immediate goes, we need to swap them.
3591  if (III.OpNoForForwarding != III.ImmOpNo)
3593 
3594  // If the special R0/X0 register index are different for original instruction
3595  // and new instruction, we need to fix up the register class in new
3596  // instruction.
3597  if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3598  if (III.ZeroIsSpecialNew) {
3599  // If operand at III.ZeroIsSpecialNew is physical reg(eg: ZERO/ZERO8), no
3600  // need to fix up register class.
3601  unsigned RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3602  if (TargetRegisterInfo::isVirtualRegister(RegToModify)) {
3603  const TargetRegisterClass *NewRC =
3604  MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
3605  &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
3606  MRI.setRegClass(RegToModify, NewRC);
3607  }
3608  }
3609  }
3610 
3611  // Fix up killed/dead flag after transformation.
3612  // Pattern:
3613  // ForwardKilledOperandReg = LI imm
3614  // y = XOP reg, ForwardKilledOperandReg(killed)
3615  if (ForwardKilledOperandReg != ~0U)
3616  fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
3617  return true;
3618 }
3619 
3620 const TargetRegisterClass *
3622  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
3623  return &PPC::VSRCRegClass;
3624  return RC;
3625 }
3626 
3628  return PPC::getRecordFormOpcode(Opcode);
3629 }
3630 
3631 // This function returns true if the machine instruction
3632 // always outputs a value by sign-extending a 32 bit value,
3633 // i.e. 0 to 31-th bits are same as 32-th bit.
3634 static bool isSignExtendingOp(const MachineInstr &MI) {
3635  int Opcode = MI.getOpcode();
3636  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3637  Opcode == PPC::LIS || Opcode == PPC::LIS8 ||
3638  Opcode == PPC::SRAW || Opcode == PPC::SRAWo ||
3639  Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo ||
3640  Opcode == PPC::LWA || Opcode == PPC::LWAX ||
3641  Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
3642  Opcode == PPC::LHA || Opcode == PPC::LHAX ||
3643  Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 ||
3644  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3645  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3646  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3647  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3648  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3649  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3650  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3651  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3652  Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo ||
3653  Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo ||
3654  Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 ||
3655  Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo ||
3656  Opcode == PPC::SETB || Opcode == PPC::SETB8 ||
3657  Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
3658  Opcode == PPC::EXTSB8_32_64)
3659  return true;
3660 
3661  if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3662  return true;
3663 
3664  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3665  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) &&
3666  MI.getOperand(3).getImm() > 0 &&
3667  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3668  return true;
3669 
3670  return false;
3671 }
3672 
3673 // This function returns true if the machine instruction
3674 // always outputs zeros in higher 32 bits.
3675 static bool isZeroExtendingOp(const MachineInstr &MI) {
3676  int Opcode = MI.getOpcode();
3677  // The 16-bit immediate is sign-extended in li/lis.
3678  // If the most significant bit is zero, all higher bits are zero.
3679  if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3680  Opcode == PPC::LIS || Opcode == PPC::LIS8) {
3681  int64_t Imm = MI.getOperand(1).getImm();
3682  if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
3683  return true;
3684  }
3685 
3686  // We have some variations of rotate-and-mask instructions
3687  // that clear higher 32-bits.
3688  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
3689  Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo ||
3690  Opcode == PPC::RLDICL_32_64) &&
3691  MI.getOperand(3).getImm() >= 32)
3692  return true;
3693 
3694  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
3695  MI.getOperand(3).getImm() >= 32 &&
3696  MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3697  return true;
3698 
3699  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3700  Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
3701  Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
3702  MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3703  return true;
3704 
3705  // There are other instructions that clear higher 32-bits.
3706  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
3707  Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
3708  Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
3709  Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
3710  Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo ||
3711  Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
3712  Opcode == PPC::SLW || Opcode == PPC::SLWo ||
3713  Opcode == PPC::SRW || Opcode == PPC::SRWo ||
3714  Opcode == PPC::SLW8 || Opcode == PPC::SRW8 ||
3715  Opcode == PPC::SLWI || Opcode == PPC::SLWIo ||
3716  Opcode == PPC::SRWI || Opcode == PPC::SRWIo ||
3717  Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
3718  Opcode == PPC::LWZU || Opcode == PPC::LWZUX ||
3719  Opcode == PPC::LWBRX || Opcode == PPC::LHBRX ||
3720  Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3721  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3722  Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3723  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3724  Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 ||
3725  Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 ||
3726  Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
3727  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3728  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3729  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3730  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3731  Opcode == PPC::ANDIo || Opcode == PPC::ANDISo ||
3732  Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo ||
3733  Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo ||
3734  Opcode == PPC::MFVSRWZ)
3735  return true;
3736 
3737  return false;
3738 }
3739 
3740 // This function returns true if the input MachineInstr is a TOC save
3741 // instruction.
3743  if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3744  return false;
3745  unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3746  unsigned StackOffset = MI.getOperand(1).getImm();
3747  unsigned StackReg = MI.getOperand(2).getReg();
3748  if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
3749  return true;
3750 
3751  return false;
3752 }
3753 
3754 // We limit the max depth to track incoming values of PHIs or binary ops
3755 // (e.g. AND) to avoid excessive cost.
3756 const unsigned MAX_DEPTH = 1;
3757 
3758 bool
3760  const unsigned Depth) const {
3761  const MachineFunction *MF = MI.getParent()->getParent();
3762  const MachineRegisterInfo *MRI = &MF->getRegInfo();
3763 
3764  // If we know this instruction returns sign- or zero-extended result,
3765  // return true.
3766  if (SignExt ? isSignExtendingOp(MI):
3767  isZeroExtendingOp(MI))
3768  return true;
3769 
3770  switch (MI.getOpcode()) {
3771  case PPC::COPY: {
3772  unsigned SrcReg = MI.getOperand(1).getReg();
3773 
3774  // In both ELFv1 and v2 ABI, method parameters and the return value
3775  // are sign- or zero-extended.
3776  if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
3777  const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
3778  // We check the ZExt/SExt flags for a method parameter.
3779  if (MI.getParent()->getBasicBlock() ==
3780  &MF->getFunction().getEntryBlock()) {
3781  unsigned VReg = MI.getOperand(0).getReg();
3782  if (MF->getRegInfo().isLiveIn(VReg))
3783  return SignExt ? FuncInfo->isLiveInSExt(VReg) :
3784  FuncInfo->isLiveInZExt(VReg);
3785  }
3786 
3787  // For a method return value, we check the ZExt/SExt flags in attribute.
3788  // We assume the following code sequence for method call.
3789  // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
3790  // BL8_NOP @func,...
3791  // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
3792  // %5 = COPY %x3; G8RC:%5
3793  if (SrcReg == PPC::X3) {
3794  const MachineBasicBlock *MBB = MI.getParent();
3797  if (II != MBB->instr_begin() &&
3798  (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
3799  const MachineInstr &CallMI = *(--II);
3800  if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
3801  const Function *CalleeFn =
3802  dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
3803  if (!CalleeFn)
3804  return false;
3805  const IntegerType *IntTy =
3806  dyn_cast<IntegerType>(CalleeFn->getReturnType());
3807  const AttributeSet &Attrs =
3808  CalleeFn->getAttributes().getRetAttributes();
3809  if (IntTy && IntTy->getBitWidth() <= 32)
3810  return Attrs.hasAttribute(SignExt ? Attribute::SExt :
3811  Attribute::ZExt);
3812  }
3813  }
3814  }
3815  }
3816 
3817  // If this is a copy from another register, we recursively check source.
3819  return false;
3820  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3821  if (SrcMI != NULL)
3822  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3823 
3824  return false;
3825  }
3826 
3827  case PPC::ANDIo:
3828  case PPC::ANDISo:
3829  case PPC::ORI:
3830  case PPC::ORIS:
3831  case PPC::XORI:
3832  case PPC::XORIS:
3833  case PPC::ANDIo8:
3834  case PPC::ANDISo8:
3835  case PPC::ORI8:
3836  case PPC::ORIS8:
3837  case PPC::XORI8:
3838  case PPC::XORIS8: {
3839  // logical operation with 16-bit immediate does not change the upper bits.
3840  // So, we track the operand register as we do for register copy.
3841  unsigned SrcReg = MI.getOperand(1).getReg();
3843  return false;
3844  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3845  if (SrcMI != NULL)
3846  return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3847 
3848  return false;
3849  }
3850 
3851  // If all incoming values are sign-/zero-extended,
3852  // the output of OR, ISEL or PHI is also sign-/zero-extended.
3853  case PPC::OR:
3854  case PPC::OR8:
3855  case PPC::ISEL:
3856  case PPC::PHI: {
3857  if (Depth >= MAX_DEPTH)
3858  return false;
3859 
3860  // The input registers for PHI are operand 1, 3, ...
3861  // The input registers for others are operand 1 and 2.
3862  unsigned E = 3, D = 1;
3863  if (MI.getOpcode() == PPC::PHI) {
3864  E = MI.getNumOperands();
3865  D = 2;
3866  }
3867 
3868  for (unsigned I = 1; I != E; I += D) {
3869  if (MI.getOperand(I).isReg()) {
3870  unsigned SrcReg = MI.getOperand(I).getReg();
3872  return false;
3873  const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3874  if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
3875  return false;
3876  }
3877  else
3878  return false;
3879  }
3880  return true;
3881  }
3882 
3883  // If at least one of the incoming values of an AND is zero extended
3884  // then the output is also zero-extended. If both of the incoming values
3885  // are sign-extended then the output is also sign extended.
3886  case PPC::AND:
3887  case PPC::AND8: {
3888  if (Depth >= MAX_DEPTH)
3889  return false;
3890 
3891  assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
3892 
3893  unsigned SrcReg1 = MI.getOperand(1).getReg();
3894  unsigned SrcReg2 = MI.getOperand(2).getReg();
3895 
3896  if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) ||
3898  return false;
3899 
3900  const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
3901  const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
3902  if (!MISrc1 || !MISrc2)
3903  return false;
3904 
3905  if(SignExt)
3906  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
3907  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3908  else
3909  return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
3910  isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3911  }
3912 
3913  default:
3914  break;
3915  }
3916  return false;
3917 }
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
instr_iterator instr_begin()
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:632
int getNonRecordFormOpcode(uint16_t)
MachineBasicBlock * getMBB() const
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:87
void setTargetFlags(unsigned F)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
iterator begin() const
begin/end - Return all of the registers in this class.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:382
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:523
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static int getRecordFormOpcode(unsigned Opcode)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
unsigned getSubReg() const
bool hasVSX() const
Definition: PPCSubtarget.h:249
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
uint64_t IsCommutative
Definition: PPCInstrInfo.h:89
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:99
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:305
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
void setIsDead(bool Val=true)
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:242
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
#define R2(n)
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:91
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:101
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:399
return AArch64::GPR64RegClass contains(Reg)
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
bool instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III, bool PostRA) const
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:188
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
A description of a memory reference used in the backend.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:411
bool hasDirectMove() const
Definition: PPCSubtarget.h:278
static Optional< unsigned > getOpcode(ArrayRef< VPValue *> Values)
Returns the opcode of Values or ~0 if they do not all agree.
Definition: VPlanSLP.cpp:196
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:648
AttributeSet getRetAttributes() const
The attributes for the ret value are returned.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:84
const char * getSymbolName() const
static bool isZeroExtendingOp(const MachineInstr &MI)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:695
static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2)
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool isTOCSaveMI(const MachineInstr &MI) const
defusechain_iterator - This class provides iterator support for machine operands in the function that...
PPCInstrInfo(PPCSubtarget &STI)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1574
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
bool hasP9Vector() const
Definition: PPCSubtarget.h:254
static bool isVFReg(unsigned Reg)
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a symbol with hidden visibility...
Definition: PPC.h:105
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:195
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
unsigned getAlignment() const
Definition: Globals.cpp:96
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:65
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
reverse_iterator rend()
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:656
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
unsigned getKillRegState(bool B)
bool hasAttribute(Attribute::AttrKind Kind) const
Return true if the attribute exists in this set.
Definition: Attributes.cpp:579
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
const BasicBlock & getEntryBlock() const
Definition: Function.h:645
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:576
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:545
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc, unsigned TrueReg, unsigned FalseReg, unsigned CRSubReg)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned const MachineRegisterInfo * MRI
bool isLiveInSExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and sign-extended.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
int getAltVSXFMAOpcode(uint16_t Opcode)
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:100
const GlobalValue * getGlobal() const
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:173
STFIWX - The STFIWX instruction.
use_instr_iterator use_instr_begin(unsigned RegNo) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
MI-level patchpoint operands.
Definition: StackMaps.h:76
Class to represent integer types.
Definition: DerivedTypes.h:39
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned getStoreOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1206
unsigned getPredicateHint(Predicate Opcode)
Return the hint bits of the predicate.
Definition: PPCPredicates.h:82
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:174
static unsigned getCRFromCRBit(unsigned SrcReg)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
unsigned first
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
The next are not flags but distinct values.
Definition: PPC.h:108
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:209
The memory access writes data.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:50
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:87
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:170
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
static uint64_t add(uint64_t LeftOp, uint64_t RightOp)
Definition: FileCheck.cpp:125
void getNoop(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
Definition: APInt.cpp:994
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
int64_t getImm() const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Class for arbitrary precision integers.
Definition: APInt.h:69
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
QVGPCI = This corresponds to the QPX qvgpci instruction.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:472
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:52
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool isLiveIn(unsigned Reg) const
Representation of each machine instruction.
Definition: MachineInstr.h:63
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:411
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
Definition: StackMaps.h:35
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
TargetOptions Options
static bool isSignExtendingOp(const MachineInstr &MI)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned getLoadOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const
void setSubReg(unsigned subReg)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
void fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI, unsigned RegNo) const
Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:104
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:345
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:455
const unsigned MAX_DEPTH
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:81
unsigned getPredicateCondition(Predicate Opcode)
Return the condition without hint bits.
Definition: PPCPredicates.h:77
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isLiveInZExt(unsigned VReg) const
This function returns true if the specified vreg is a live-in register and zero-extended.
LLVM Value Representation.
Definition: Value.h:72
static use_instr_iterator use_instr_end()
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:639
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isPredicable(const MachineInstr &MI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isSVR4ABI() const
Definition: PPCSubtarget.h:317
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:66
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:92
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:186
virtual unsigned lookThruCopyLike(unsigned SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:314
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
Instructions::const_iterator const_instr_iterator
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
SpillOpcodeKey
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function&#39;s picbase...
Definition: PPC.h:96
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
static bool isAnImmediateOperand(const MachineOperand &MO)
bool expandPostRAPseudo(MachineInstr &MI) const override
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:172
bool expandVSXMemPseudo(MachineInstr &MI) const
bool isImplicit() const
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:405
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...