LLVM 17.0.0git
RegisterPressure.cpp
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1//===- RegisterPressure.cpp - Dynamic Register Pressure -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RegisterPressure class which can be used to track
10// MachineInstr level register pressure.
11//
12//===----------------------------------------------------------------------===//
13
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/ADT/STLExtras.h"
30#include "llvm/Config/llvm-config.h"
31#include "llvm/MC/LaneBitmask.h"
34#include "llvm/Support/Debug.h"
37#include <algorithm>
38#include <cassert>
39#include <cstdint>
40#include <cstdlib>
41#include <cstring>
42#include <iterator>
43#include <limits>
44#include <utility>
45#include <vector>
46
47using namespace llvm;
48
49/// Increase pressure for each pressure set provided by TargetRegisterInfo.
50static void increaseSetPressure(std::vector<unsigned> &CurrSetPressure,
51 const MachineRegisterInfo &MRI, unsigned Reg,
52 LaneBitmask PrevMask, LaneBitmask NewMask) {
53 assert((PrevMask & ~NewMask).none() && "Must not remove bits");
54 if (PrevMask.any() || NewMask.none())
55 return;
56
57 PSetIterator PSetI = MRI.getPressureSets(Reg);
58 unsigned Weight = PSetI.getWeight();
59 for (; PSetI.isValid(); ++PSetI)
60 CurrSetPressure[*PSetI] += Weight;
61}
62
63/// Decrease pressure for each pressure set provided by TargetRegisterInfo.
64static void decreaseSetPressure(std::vector<unsigned> &CurrSetPressure,
66 LaneBitmask PrevMask, LaneBitmask NewMask) {
67 //assert((NewMask & !PrevMask) == 0 && "Must not add bits");
68 if (NewMask.any() || PrevMask.none())
69 return;
70
71 PSetIterator PSetI = MRI.getPressureSets(Reg);
72 unsigned Weight = PSetI.getWeight();
73 for (; PSetI.isValid(); ++PSetI) {
74 assert(CurrSetPressure[*PSetI] >= Weight && "register pressure underflow");
75 CurrSetPressure[*PSetI] -= Weight;
76 }
77}
78
79#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
82 const TargetRegisterInfo *TRI) {
83 bool Empty = true;
84 for (unsigned i = 0, e = SetPressure.size(); i < e; ++i) {
85 if (SetPressure[i] != 0) {
86 dbgs() << TRI->getRegPressureSetName(i) << "=" << SetPressure[i] << '\n';
87 Empty = false;
88 }
89 }
90 if (Empty)
91 dbgs() << "\n";
92}
93
96 dbgs() << "Max Pressure: ";
98 dbgs() << "Live In: ";
99 for (const RegisterMaskPair &P : LiveInRegs) {
100 dbgs() << printVRegOrUnit(P.RegUnit, TRI);
101 if (!P.LaneMask.all())
102 dbgs() << ':' << PrintLaneMask(P.LaneMask);
103 dbgs() << ' ';
104 }
105 dbgs() << '\n';
106 dbgs() << "Live Out: ";
107 for (const RegisterMaskPair &P : LiveOutRegs) {
108 dbgs() << printVRegOrUnit(P.RegUnit, TRI);
109 if (!P.LaneMask.all())
110 dbgs() << ':' << PrintLaneMask(P.LaneMask);
111 dbgs() << ' ';
112 }
113 dbgs() << '\n';
114}
115
118 if (!isTopClosed() || !isBottomClosed()) {
119 dbgs() << "Curr Pressure: ";
120 dumpRegSetPressure(CurrSetPressure, TRI);
121 }
122 P.dump(TRI);
123}
124
127 const char *sep = "";
128 for (const PressureChange &Change : *this) {
129 if (!Change.isValid())
130 break;
131 dbgs() << sep << TRI.getRegPressureSetName(Change.getPSet())
132 << " " << Change.getUnitInc();
133 sep = " ";
134 }
135 dbgs() << '\n';
136}
137
140 dbgs() << "[" << getPSetOrMax() << ", " << getUnitInc() << "]\n";
141}
142
144 dbgs() << "[Excess=";
145 Excess.dump();
146 dbgs() << ", CriticalMax=";
148 dbgs() << ", CurrentMax=";
150 dbgs() << "]\n";
151}
152
153#endif
154
156 LaneBitmask PreviousMask,
157 LaneBitmask NewMask) {
158 if (PreviousMask.any() || NewMask.none())
159 return;
160
161 PSetIterator PSetI = MRI->getPressureSets(RegUnit);
162 unsigned Weight = PSetI.getWeight();
163 for (; PSetI.isValid(); ++PSetI) {
164 CurrSetPressure[*PSetI] += Weight;
165 P.MaxSetPressure[*PSetI] =
166 std::max(P.MaxSetPressure[*PSetI], CurrSetPressure[*PSetI]);
167 }
168}
169
171 LaneBitmask PreviousMask,
172 LaneBitmask NewMask) {
173 decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask);
174}
175
176/// Clear the result so it can be used for another round of pressure tracking.
179 MaxSetPressure.clear();
180 LiveInRegs.clear();
181 LiveOutRegs.clear();
182}
183
184/// Clear the result so it can be used for another round of pressure tracking.
187 MaxSetPressure.clear();
188 LiveInRegs.clear();
189 LiveOutRegs.clear();
190}
191
192/// If the current top is not less than or equal to the next index, open it.
193/// We happen to need the SlotIndex for the next top for pressure update.
195 if (TopIdx <= NextTop)
196 return;
197 TopIdx = SlotIndex();
198 LiveInRegs.clear();
199}
200
201/// If the current top is the previous instruction (before receding), open it.
203 if (TopPos != PrevTop)
204 return;
206 LiveInRegs.clear();
207}
208
209/// If the current bottom is not greater than the previous index, open it.
211 if (BottomIdx > PrevBottom)
212 return;
214 LiveInRegs.clear();
215}
216
217/// If the current bottom is the previous instr (before advancing), open it.
219 if (BottomPos != PrevBottom)
220 return;
222 LiveInRegs.clear();
223}
224
226 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
227 unsigned NumRegUnits = TRI.getNumRegs();
228 unsigned NumVirtRegs = MRI.getNumVirtRegs();
229 Regs.setUniverse(NumRegUnits + NumVirtRegs);
230 this->NumRegUnits = NumRegUnits;
231}
232
234 Regs.clear();
235}
236
237static const LiveRange *getLiveRange(const LiveIntervals &LIS, unsigned Reg) {
239 return &LIS.getInterval(Reg);
240 return LIS.getCachedRegUnit(Reg);
241}
242
244 MBB = nullptr;
245 LIS = nullptr;
246
247 CurrSetPressure.clear();
248 LiveThruPressure.clear();
249 P.MaxSetPressure.clear();
250
251 if (RequireIntervals)
252 static_cast<IntervalPressure&>(P).reset();
253 else
254 static_cast<RegionPressure&>(P).reset();
255
256 LiveRegs.clear();
257 UntiedDefs.clear();
258}
259
260/// Setup the RegPressureTracker.
261///
262/// TODO: Add support for pressure without LiveIntervals.
264 const RegisterClassInfo *rci,
265 const LiveIntervals *lis,
266 const MachineBasicBlock *mbb,
268 bool TrackLaneMasks, bool TrackUntiedDefs) {
269 reset();
270
271 MF = mf;
272 TRI = MF->getSubtarget().getRegisterInfo();
273 RCI = rci;
274 MRI = &MF->getRegInfo();
275 MBB = mbb;
276 this->TrackUntiedDefs = TrackUntiedDefs;
277 this->TrackLaneMasks = TrackLaneMasks;
278
279 if (RequireIntervals) {
280 assert(lis && "IntervalPressure requires LiveIntervals");
281 LIS = lis;
282 }
283
284 CurrPos = pos;
285 CurrSetPressure.assign(TRI->getNumRegPressureSets(), 0);
286
287 P.MaxSetPressure = CurrSetPressure;
288
289 LiveRegs.init(*MRI);
290 if (TrackUntiedDefs)
291 UntiedDefs.setUniverse(MRI->getNumVirtRegs());
292}
293
294/// Does this pressure result have a valid top position and live ins.
296 if (RequireIntervals)
297 return static_cast<IntervalPressure&>(P).TopIdx.isValid();
298 return (static_cast<RegionPressure&>(P).TopPos ==
300}
301
302/// Does this pressure result have a valid bottom position and live outs.
304 if (RequireIntervals)
305 return static_cast<IntervalPressure&>(P).BottomIdx.isValid();
306 return (static_cast<RegionPressure&>(P).BottomPos ==
308}
309
312 skipDebugInstructionsForward(CurrPos, MBB->end());
313 if (IdxPos == MBB->end())
314 return LIS->getMBBEndIdx(MBB);
315 return LIS->getInstructionIndex(*IdxPos).getRegSlot();
316}
317
318/// Set the boundary for the top of the region and summarize live ins.
320 if (RequireIntervals)
321 static_cast<IntervalPressure&>(P).TopIdx = getCurrSlot();
322 else
323 static_cast<RegionPressure&>(P).TopPos = CurrPos;
324
325 assert(P.LiveInRegs.empty() && "inconsistent max pressure result");
326 P.LiveInRegs.reserve(LiveRegs.size());
327 LiveRegs.appendTo(P.LiveInRegs);
328}
329
330/// Set the boundary for the bottom of the region and summarize live outs.
332 if (RequireIntervals)
333 static_cast<IntervalPressure&>(P).BottomIdx = getCurrSlot();
334 else
335 static_cast<RegionPressure&>(P).BottomPos = CurrPos;
336
337 assert(P.LiveOutRegs.empty() && "inconsistent max pressure result");
338 P.LiveOutRegs.reserve(LiveRegs.size());
339 LiveRegs.appendTo(P.LiveOutRegs);
340}
341
342/// Finalize the region boundaries and record live ins and live outs.
344 if (!isTopClosed() && !isBottomClosed()) {
345 assert(LiveRegs.size() == 0 && "no region boundary");
346 return;
347 }
348 if (!isBottomClosed())
349 closeBottom();
350 else if (!isTopClosed())
351 closeTop();
352 // If both top and bottom are closed, do nothing.
353}
354
355/// The register tracker is unaware of global liveness so ignores normal
356/// live-thru ranges. However, two-address or coalesced chains can also lead
357/// to live ranges with no holes. Count these to inform heuristics that we
358/// can never drop below this pressure.
360 LiveThruPressure.assign(TRI->getNumRegPressureSets(), 0);
361 assert(isBottomClosed() && "need bottom-up tracking to intialize.");
362 for (const RegisterMaskPair &Pair : P.LiveOutRegs) {
363 Register RegUnit = Pair.RegUnit;
364 if (RegUnit.isVirtual() && !RPTracker.hasUntiedDef(RegUnit))
365 increaseSetPressure(LiveThruPressure, *MRI, RegUnit,
367 }
368}
369
371 Register RegUnit) {
372 auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
373 return Other.RegUnit == RegUnit;
374 });
375 if (I == RegUnits.end())
376 return LaneBitmask::getNone();
377 return I->LaneMask;
378}
379
381 RegisterMaskPair Pair) {
382 Register RegUnit = Pair.RegUnit;
383 assert(Pair.LaneMask.any());
384 auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
385 return Other.RegUnit == RegUnit;
386 });
387 if (I == RegUnits.end()) {
388 RegUnits.push_back(Pair);
389 } else {
390 I->LaneMask |= Pair.LaneMask;
391 }
392}
393
395 Register RegUnit) {
396 auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
397 return Other.RegUnit == RegUnit;
398 });
399 if (I == RegUnits.end()) {
400 RegUnits.push_back(RegisterMaskPair(RegUnit, LaneBitmask::getNone()));
401 } else {
402 I->LaneMask = LaneBitmask::getNone();
403 }
404}
405
407 RegisterMaskPair Pair) {
408 Register RegUnit = Pair.RegUnit;
409 assert(Pair.LaneMask.any());
410 auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
411 return Other.RegUnit == RegUnit;
412 });
413 if (I != RegUnits.end()) {
414 I->LaneMask &= ~Pair.LaneMask;
415 if (I->LaneMask.none())
416 RegUnits.erase(I);
417 }
418}
419
420static LaneBitmask
422 bool TrackLaneMasks, Register RegUnit, SlotIndex Pos,
423 LaneBitmask SafeDefault,
424 bool (*Property)(const LiveRange &LR, SlotIndex Pos)) {
425 if (RegUnit.isVirtual()) {
426 const LiveInterval &LI = LIS.getInterval(RegUnit);
427 LaneBitmask Result;
428 if (TrackLaneMasks && LI.hasSubRanges()) {
429 for (const LiveInterval::SubRange &SR : LI.subranges()) {
430 if (Property(SR, Pos))
431 Result |= SR.LaneMask;
432 }
433 } else if (Property(LI, Pos)) {
434 Result = TrackLaneMasks ? MRI.getMaxLaneMaskForVReg(RegUnit)
436 }
437
438 return Result;
439 } else {
440 const LiveRange *LR = LIS.getCachedRegUnit(RegUnit);
441 // Be prepared for missing liveranges: We usually do not compute liveranges
442 // for physical registers on targets with many registers (GPUs).
443 if (LR == nullptr)
444 return SafeDefault;
445 return Property(*LR, Pos) ? LaneBitmask::getAll() : LaneBitmask::getNone();
446 }
447}
448
451 bool TrackLaneMasks, Register RegUnit,
452 SlotIndex Pos) {
453 return getLanesWithProperty(LIS, MRI, TrackLaneMasks, RegUnit, Pos,
455 [](const LiveRange &LR, SlotIndex Pos) {
456 return LR.liveAt(Pos);
457 });
458}
459
460namespace {
461
462/// Collect this instruction's unique uses and defs into SmallVectors for
463/// processing defs and uses in order.
464///
465/// FIXME: always ignore tied opers
466class RegisterOperandsCollector {
467 friend class llvm::RegisterOperands;
468
469 RegisterOperands &RegOpers;
470 const TargetRegisterInfo &TRI;
472 bool IgnoreDead;
473
474 RegisterOperandsCollector(RegisterOperands &RegOpers,
475 const TargetRegisterInfo &TRI,
476 const MachineRegisterInfo &MRI, bool IgnoreDead)
477 : RegOpers(RegOpers), TRI(TRI), MRI(MRI), IgnoreDead(IgnoreDead) {}
478
479 void collectInstr(const MachineInstr &MI) const {
480 for (ConstMIBundleOperands OperI(MI); OperI.isValid(); ++OperI)
481 collectOperand(*OperI);
482
483 // Remove redundant physreg dead defs.
484 for (const RegisterMaskPair &P : RegOpers.Defs)
485 removeRegLanes(RegOpers.DeadDefs, P);
486 }
487
488 void collectInstrLanes(const MachineInstr &MI) const {
489 for (ConstMIBundleOperands OperI(MI); OperI.isValid(); ++OperI)
490 collectOperandLanes(*OperI);
491
492 // Remove redundant physreg dead defs.
493 for (const RegisterMaskPair &P : RegOpers.Defs)
494 removeRegLanes(RegOpers.DeadDefs, P);
495 }
496
497 /// Push this operand's register onto the correct vectors.
498 void collectOperand(const MachineOperand &MO) const {
499 if (!MO.isReg() || !MO.getReg())
500 return;
501 Register Reg = MO.getReg();
502 if (MO.isUse()) {
503 if (!MO.isUndef() && !MO.isInternalRead())
504 pushReg(Reg, RegOpers.Uses);
505 } else {
506 assert(MO.isDef());
507 // Subregister definitions may imply a register read.
508 if (MO.readsReg())
509 pushReg(Reg, RegOpers.Uses);
510
511 if (MO.isDead()) {
512 if (!IgnoreDead)
513 pushReg(Reg, RegOpers.DeadDefs);
514 } else
515 pushReg(Reg, RegOpers.Defs);
516 }
517 }
518
519 void pushReg(Register Reg,
520 SmallVectorImpl<RegisterMaskPair> &RegUnits) const {
521 if (Reg.isVirtual()) {
523 } else if (MRI.isAllocatable(Reg)) {
524 for (MCRegUnitIterator Units(Reg.asMCReg(), &TRI); Units.isValid();
525 ++Units)
527 }
528 }
529
530 void collectOperandLanes(const MachineOperand &MO) const {
531 if (!MO.isReg() || !MO.getReg())
532 return;
533 Register Reg = MO.getReg();
534 unsigned SubRegIdx = MO.getSubReg();
535 if (MO.isUse()) {
536 if (!MO.isUndef() && !MO.isInternalRead())
537 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses);
538 } else {
539 assert(MO.isDef());
540 // Treat read-undef subreg defs as definitions of the whole register.
541 if (MO.isUndef())
542 SubRegIdx = 0;
543
544 if (MO.isDead()) {
545 if (!IgnoreDead)
546 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs);
547 } else
548 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs);
549 }
550 }
551
552 void pushRegLanes(Register Reg, unsigned SubRegIdx,
553 SmallVectorImpl<RegisterMaskPair> &RegUnits) const {
554 if (Reg.isVirtual()) {
555 LaneBitmask LaneMask = SubRegIdx != 0
556 ? TRI.getSubRegIndexLaneMask(SubRegIdx)
557 : MRI.getMaxLaneMaskForVReg(Reg);
558 addRegLanes(RegUnits, RegisterMaskPair(Reg, LaneMask));
559 } else if (MRI.isAllocatable(Reg)) {
560 for (MCRegUnitIterator Units(Reg.asMCReg(), &TRI); Units.isValid();
561 ++Units)
563 }
564 }
565};
566
567} // end anonymous namespace
568
570 const TargetRegisterInfo &TRI,
572 bool TrackLaneMasks, bool IgnoreDead) {
573 RegisterOperandsCollector Collector(*this, TRI, MRI, IgnoreDead);
574 if (TrackLaneMasks)
575 Collector.collectInstrLanes(MI);
576 else
577 Collector.collectInstr(MI);
578}
579
581 const LiveIntervals &LIS) {
582 SlotIndex SlotIdx = LIS.getInstructionIndex(MI);
583 for (auto *RI = Defs.begin(); RI != Defs.end(); /*empty*/) {
584 Register Reg = RI->RegUnit;
585 const LiveRange *LR = getLiveRange(LIS, Reg);
586 if (LR != nullptr) {
587 LiveQueryResult LRQ = LR->Query(SlotIdx);
588 if (LRQ.isDeadDef()) {
589 // LiveIntervals knows this is a dead even though it's MachineOperand is
590 // not flagged as such.
591 DeadDefs.push_back(*RI);
592 RI = Defs.erase(RI);
593 continue;
594 }
595 }
596 ++RI;
597 }
598}
599
602 SlotIndex Pos,
603 MachineInstr *AddFlagsMI) {
604 for (auto *I = Defs.begin(); I != Defs.end();) {
605 LaneBitmask LiveAfter = getLiveLanesAt(LIS, MRI, true, I->RegUnit,
606 Pos.getDeadSlot());
607 // If the def is all that is live after the instruction, then in case
608 // of a subregister def we need a read-undef flag.
609 Register RegUnit = I->RegUnit;
610 if (RegUnit.isVirtual() && AddFlagsMI != nullptr &&
611 (LiveAfter & ~I->LaneMask).none())
612 AddFlagsMI->setRegisterDefReadUndef(RegUnit);
613
614 LaneBitmask ActualDef = I->LaneMask & LiveAfter;
615 if (ActualDef.none()) {
616 I = Defs.erase(I);
617 } else {
618 I->LaneMask = ActualDef;
619 ++I;
620 }
621 }
622 for (auto *I = Uses.begin(); I != Uses.end();) {
623 LaneBitmask LiveBefore = getLiveLanesAt(LIS, MRI, true, I->RegUnit,
624 Pos.getBaseIndex());
625 LaneBitmask LaneMask = I->LaneMask & LiveBefore;
626 if (LaneMask.none()) {
627 I = Uses.erase(I);
628 } else {
629 I->LaneMask = LaneMask;
630 ++I;
631 }
632 }
633 if (AddFlagsMI != nullptr) {
634 for (const RegisterMaskPair &P : DeadDefs) {
635 Register RegUnit = P.RegUnit;
636 if (!RegUnit.isVirtual())
637 continue;
638 LaneBitmask LiveAfter = getLiveLanesAt(LIS, MRI, true, RegUnit,
639 Pos.getDeadSlot());
640 if (LiveAfter.none())
641 AddFlagsMI->setRegisterDefReadUndef(RegUnit);
642 }
643 }
644}
645
646/// Initialize an array of N PressureDiffs.
647void PressureDiffs::init(unsigned N) {
648 Size = N;
649 if (N <= Max) {
650 memset(PDiffArray, 0, N * sizeof(PressureDiff));
651 return;
652 }
653 Max = Size;
654 free(PDiffArray);
655 PDiffArray = static_cast<PressureDiff*>(safe_calloc(N, sizeof(PressureDiff)));
656}
657
659 const RegisterOperands &RegOpers,
660 const MachineRegisterInfo &MRI) {
661 PressureDiff &PDiff = (*this)[Idx];
662 assert(!PDiff.begin()->isValid() && "stale PDiff");
663 for (const RegisterMaskPair &P : RegOpers.Defs)
664 PDiff.addPressureChange(P.RegUnit, true, &MRI);
665
666 for (const RegisterMaskPair &P : RegOpers.Uses)
667 PDiff.addPressureChange(P.RegUnit, false, &MRI);
668}
669
670/// Add a change in pressure to the pressure diff of a given instruction.
672 const MachineRegisterInfo *MRI) {
673 PSetIterator PSetI = MRI->getPressureSets(RegUnit);
674 int Weight = IsDec ? -PSetI.getWeight() : PSetI.getWeight();
675 for (; PSetI.isValid(); ++PSetI) {
676 // Find an existing entry in the pressure diff for this PSet.
677 PressureDiff::iterator I = nonconst_begin(), E = nonconst_end();
678 for (; I != E && I->isValid(); ++I) {
679 if (I->getPSet() >= *PSetI)
680 break;
681 }
682 // If all pressure sets are more constrained, skip the remaining PSets.
683 if (I == E)
684 break;
685 // Insert this PressureChange.
686 if (!I->isValid() || I->getPSet() != *PSetI) {
687 PressureChange PTmp = PressureChange(*PSetI);
688 for (PressureDiff::iterator J = I; J != E && PTmp.isValid(); ++J)
689 std::swap(*J, PTmp);
690 }
691 // Update the units for this pressure set.
692 unsigned NewUnitInc = I->getUnitInc() + Weight;
693 if (NewUnitInc != 0) {
694 I->setUnitInc(NewUnitInc);
695 } else {
696 // Remove entry
698 for (J = std::next(I); J != E && J->isValid(); ++J, ++I)
699 *I = *J;
700 *I = PressureChange();
701 }
702 }
703}
704
705/// Force liveness of registers.
707 for (const RegisterMaskPair &P : Regs) {
708 LaneBitmask PrevMask = LiveRegs.insert(P);
709 LaneBitmask NewMask = PrevMask | P.LaneMask;
710 increaseRegPressure(P.RegUnit, PrevMask, NewMask);
711 }
712}
713
716 assert(Pair.LaneMask.any());
717
718 Register RegUnit = Pair.RegUnit;
719 auto I = llvm::find_if(LiveInOrOut, [RegUnit](const RegisterMaskPair &Other) {
720 return Other.RegUnit == RegUnit;
721 });
722 LaneBitmask PrevMask;
723 LaneBitmask NewMask;
724 if (I == LiveInOrOut.end()) {
725 PrevMask = LaneBitmask::getNone();
726 NewMask = Pair.LaneMask;
727 LiveInOrOut.push_back(Pair);
728 } else {
729 PrevMask = I->LaneMask;
730 NewMask = PrevMask | Pair.LaneMask;
731 I->LaneMask = NewMask;
732 }
733 increaseSetPressure(P.MaxSetPressure, *MRI, RegUnit, PrevMask, NewMask);
734}
735
737 discoverLiveInOrOut(Pair, P.LiveInRegs);
738}
739
741 discoverLiveInOrOut(Pair, P.LiveOutRegs);
742}
743
745 for (const RegisterMaskPair &P : DeadDefs) {
746 Register Reg = P.RegUnit;
747 LaneBitmask LiveMask = LiveRegs.contains(Reg);
748 LaneBitmask BumpedMask = LiveMask | P.LaneMask;
749 increaseRegPressure(Reg, LiveMask, BumpedMask);
750 }
751 for (const RegisterMaskPair &P : DeadDefs) {
752 Register Reg = P.RegUnit;
753 LaneBitmask LiveMask = LiveRegs.contains(Reg);
754 LaneBitmask BumpedMask = LiveMask | P.LaneMask;
755 decreaseRegPressure(Reg, BumpedMask, LiveMask);
756 }
757}
758
759/// Recede across the previous instruction. If LiveUses is provided, record any
760/// RegUnits that are made live by the current instruction's uses. This includes
761/// registers that are both defined and used by the instruction. If a pressure
762/// difference pointer is provided record the changes is pressure caused by this
763/// instruction independent of liveness.
766 assert(!CurrPos->isDebugOrPseudoInstr());
767
768 // Boost pressure for all dead defs together.
769 bumpDeadDefs(RegOpers.DeadDefs);
770
771 // Kill liveness at live defs.
772 // TODO: consider earlyclobbers?
773 for (const RegisterMaskPair &Def : RegOpers.Defs) {
774 Register Reg = Def.RegUnit;
775
776 LaneBitmask PreviousMask = LiveRegs.erase(Def);
777 LaneBitmask NewMask = PreviousMask & ~Def.LaneMask;
778
779 LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;
780 if (LiveOut.any()) {
782 // Retroactively model effects on pressure of the live out lanes.
783 increaseSetPressure(CurrSetPressure, *MRI, Reg, LaneBitmask::getNone(),
784 LiveOut);
785 PreviousMask = LiveOut;
786 }
787
788 if (NewMask.none()) {
789 // Add a 0 entry to LiveUses as a marker that the complete vreg has become
790 // dead.
791 if (TrackLaneMasks && LiveUses != nullptr)
792 setRegZero(*LiveUses, Reg);
793 }
794
795 decreaseRegPressure(Reg, PreviousMask, NewMask);
796 }
797
798 SlotIndex SlotIdx;
799 if (RequireIntervals)
800 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
801
802 // Generate liveness for uses.
803 for (const RegisterMaskPair &Use : RegOpers.Uses) {
804 Register Reg = Use.RegUnit;
805 assert(Use.LaneMask.any());
806 LaneBitmask PreviousMask = LiveRegs.insert(Use);
807 LaneBitmask NewMask = PreviousMask | Use.LaneMask;
808 if (NewMask == PreviousMask)
809 continue;
810
811 // Did the register just become live?
812 if (PreviousMask.none()) {
813 if (LiveUses != nullptr) {
814 if (!TrackLaneMasks) {
815 addRegLanes(*LiveUses, RegisterMaskPair(Reg, NewMask));
816 } else {
817 auto I =
818 llvm::find_if(*LiveUses, [Reg](const RegisterMaskPair Other) {
819 return Other.RegUnit == Reg;
820 });
821 bool IsRedef = I != LiveUses->end();
822 if (IsRedef) {
823 // ignore re-defs here...
824 assert(I->LaneMask.none());
825 removeRegLanes(*LiveUses, RegisterMaskPair(Reg, NewMask));
826 } else {
827 addRegLanes(*LiveUses, RegisterMaskPair(Reg, NewMask));
828 }
829 }
830 }
831
832 // Discover live outs if this may be the first occurance of this register.
833 if (RequireIntervals) {
834 LaneBitmask LiveOut = getLiveThroughAt(Reg, SlotIdx);
835 if (LiveOut.any())
837 }
838 }
839
840 increaseRegPressure(Reg, PreviousMask, NewMask);
841 }
842 if (TrackUntiedDefs) {
843 for (const RegisterMaskPair &Def : RegOpers.Defs) {
844 Register RegUnit = Def.RegUnit;
845 if (RegUnit.isVirtual() &&
846 (LiveRegs.contains(RegUnit) & Def.LaneMask).none())
847 UntiedDefs.insert(RegUnit);
848 }
849 }
850}
851
853 assert(CurrPos != MBB->begin());
854 if (!isBottomClosed())
855 closeBottom();
856
857 // Open the top of the region using block iterators.
858 if (!RequireIntervals && isTopClosed())
859 static_cast<RegionPressure&>(P).openTop(CurrPos);
860
861 // Find the previous instruction.
862 CurrPos = prev_nodbg(CurrPos, MBB->begin());
863
864 SlotIndex SlotIdx;
865 if (RequireIntervals && !CurrPos->isDebugOrPseudoInstr())
866 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
867
868 // Open the top of the region using slot indexes.
869 if (RequireIntervals && isTopClosed())
870 static_cast<IntervalPressure&>(P).openTop(SlotIdx);
871}
872
875 if (CurrPos->isDebugInstr() || CurrPos->isPseudoProbe()) {
876 // It's possible to only have debug_value and pseudo probe instructions and
877 // hit the start of the block.
878 assert(CurrPos == MBB->begin());
879 return;
880 }
881
882 const MachineInstr &MI = *CurrPos;
883 RegisterOperands RegOpers;
884 RegOpers.collect(MI, *TRI, *MRI, TrackLaneMasks, false);
885 if (TrackLaneMasks) {
886 SlotIndex SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
887 RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
888 } else if (RequireIntervals) {
889 RegOpers.detectDeadDefs(MI, *LIS);
890 }
891
892 recede(RegOpers, LiveUses);
893}
894
895/// Advance across the current instruction.
897 assert(!TrackUntiedDefs && "unsupported mode");
898 assert(CurrPos != MBB->end());
899 if (!isTopClosed())
900 closeTop();
901
902 SlotIndex SlotIdx;
903 if (RequireIntervals)
904 SlotIdx = getCurrSlot();
905
906 // Open the bottom of the region using slot indexes.
907 if (isBottomClosed()) {
908 if (RequireIntervals)
909 static_cast<IntervalPressure&>(P).openBottom(SlotIdx);
910 else
911 static_cast<RegionPressure&>(P).openBottom(CurrPos);
912 }
913
914 for (const RegisterMaskPair &Use : RegOpers.Uses) {
915 Register Reg = Use.RegUnit;
916 LaneBitmask LiveMask = LiveRegs.contains(Reg);
917 LaneBitmask LiveIn = Use.LaneMask & ~LiveMask;
918 if (LiveIn.any()) {
920 increaseRegPressure(Reg, LiveMask, LiveMask | LiveIn);
921 LiveRegs.insert(RegisterMaskPair(Reg, LiveIn));
922 }
923 // Kill liveness at last uses.
924 if (RequireIntervals) {
925 LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx);
926 if (LastUseMask.any()) {
927 LiveRegs.erase(RegisterMaskPair(Reg, LastUseMask));
928 decreaseRegPressure(Reg, LiveMask, LiveMask & ~LastUseMask);
929 }
930 }
931 }
932
933 // Generate liveness for defs.
934 for (const RegisterMaskPair &Def : RegOpers.Defs) {
935 LaneBitmask PreviousMask = LiveRegs.insert(Def);
936 LaneBitmask NewMask = PreviousMask | Def.LaneMask;
937 increaseRegPressure(Def.RegUnit, PreviousMask, NewMask);
938 }
939
940 // Boost pressure for all dead defs together.
941 bumpDeadDefs(RegOpers.DeadDefs);
942
943 // Find the next instruction.
944 CurrPos = next_nodbg(CurrPos, MBB->end());
945}
946
948 const MachineInstr &MI = *CurrPos;
949 RegisterOperands RegOpers;
950 RegOpers.collect(MI, *TRI, *MRI, TrackLaneMasks, false);
951 if (TrackLaneMasks) {
952 SlotIndex SlotIdx = getCurrSlot();
953 RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
954 }
955 advance(RegOpers);
956}
957
958/// Find the max change in excess pressure across all sets.
960 ArrayRef<unsigned> NewPressureVec,
961 RegPressureDelta &Delta,
962 const RegisterClassInfo *RCI,
963 ArrayRef<unsigned> LiveThruPressureVec) {
964 Delta.Excess = PressureChange();
965 for (unsigned i = 0, e = OldPressureVec.size(); i < e; ++i) {
966 unsigned POld = OldPressureVec[i];
967 unsigned PNew = NewPressureVec[i];
968 int PDiff = (int)PNew - (int)POld;
969 if (!PDiff) // No change in this set in the common case.
970 continue;
971 // Only consider change beyond the limit.
972 unsigned Limit = RCI->getRegPressureSetLimit(i);
973 if (!LiveThruPressureVec.empty())
974 Limit += LiveThruPressureVec[i];
975
976 if (Limit > POld) {
977 if (Limit > PNew)
978 PDiff = 0; // Under the limit
979 else
980 PDiff = PNew - Limit; // Just exceeded limit.
981 } else if (Limit > PNew)
982 PDiff = Limit - POld; // Just obeyed limit.
983
984 if (PDiff) {
985 Delta.Excess = PressureChange(i);
986 Delta.Excess.setUnitInc(PDiff);
987 break;
988 }
989 }
990}
991
992/// Find the max change in max pressure that either surpasses a critical PSet
993/// limit or exceeds the current MaxPressureLimit.
994///
995/// FIXME: comparing each element of the old and new MaxPressure vectors here is
996/// silly. It's done now to demonstrate the concept but will go away with a
997/// RegPressureTracker API change to work with pressure differences.
998static void computeMaxPressureDelta(ArrayRef<unsigned> OldMaxPressureVec,
999 ArrayRef<unsigned> NewMaxPressureVec,
1000 ArrayRef<PressureChange> CriticalPSets,
1001 ArrayRef<unsigned> MaxPressureLimit,
1002 RegPressureDelta &Delta) {
1003 Delta.CriticalMax = PressureChange();
1004 Delta.CurrentMax = PressureChange();
1005
1006 unsigned CritIdx = 0, CritEnd = CriticalPSets.size();
1007 for (unsigned i = 0, e = OldMaxPressureVec.size(); i < e; ++i) {
1008 unsigned POld = OldMaxPressureVec[i];
1009 unsigned PNew = NewMaxPressureVec[i];
1010 if (PNew == POld) // No change in this set in the common case.
1011 continue;
1012
1013 if (!Delta.CriticalMax.isValid()) {
1014 while (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() < i)
1015 ++CritIdx;
1016
1017 if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == i) {
1018 int PDiff = (int)PNew - (int)CriticalPSets[CritIdx].getUnitInc();
1019 if (PDiff > 0) {
1020 Delta.CriticalMax = PressureChange(i);
1021 Delta.CriticalMax.setUnitInc(PDiff);
1022 }
1023 }
1024 }
1025 // Find the first increase above MaxPressureLimit.
1026 // (Ignores negative MDiff).
1027 if (!Delta.CurrentMax.isValid() && PNew > MaxPressureLimit[i]) {
1028 Delta.CurrentMax = PressureChange(i);
1029 Delta.CurrentMax.setUnitInc(PNew - POld);
1030 if (CritIdx == CritEnd || Delta.CriticalMax.isValid())
1031 break;
1032 }
1033 }
1034}
1035
1036/// Record the upward impact of a single instruction on current register
1037/// pressure. Unlike the advance/recede pressure tracking interface, this does
1038/// not discover live in/outs.
1039///
1040/// This is intended for speculative queries. It leaves pressure inconsistent
1041/// with the current position, so must be restored by the caller.
1043 assert(!MI->isDebugOrPseudoInstr() && "Expect a nondebug instruction.");
1044
1045 SlotIndex SlotIdx;
1046 if (RequireIntervals)
1047 SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
1048
1049 // Account for register pressure similar to RegPressureTracker::recede().
1050 RegisterOperands RegOpers;
1051 RegOpers.collect(*MI, *TRI, *MRI, TrackLaneMasks, /*IgnoreDead=*/true);
1052 assert(RegOpers.DeadDefs.size() == 0);
1053 if (TrackLaneMasks)
1054 RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
1055 else if (RequireIntervals)
1056 RegOpers.detectDeadDefs(*MI, *LIS);
1057
1058 // Boost max pressure for all dead defs together.
1059 // Since CurrSetPressure and MaxSetPressure
1060 bumpDeadDefs(RegOpers.DeadDefs);
1061
1062 // Kill liveness at live defs.
1063 for (const RegisterMaskPair &P : RegOpers.Defs) {
1064 Register Reg = P.RegUnit;
1065 LaneBitmask LiveLanes = LiveRegs.contains(Reg);
1066 LaneBitmask UseLanes = getRegLanes(RegOpers.Uses, Reg);
1067 LaneBitmask DefLanes = P.LaneMask;
1068 LaneBitmask LiveAfter = (LiveLanes & ~DefLanes) | UseLanes;
1069 decreaseRegPressure(Reg, LiveLanes, LiveAfter);
1070 }
1071 // Generate liveness for uses.
1072 for (const RegisterMaskPair &P : RegOpers.Uses) {
1073 Register Reg = P.RegUnit;
1074 LaneBitmask LiveLanes = LiveRegs.contains(Reg);
1075 LaneBitmask LiveAfter = LiveLanes | P.LaneMask;
1076 increaseRegPressure(Reg, LiveLanes, LiveAfter);
1077 }
1078}
1079
1080/// Consider the pressure increase caused by traversing this instruction
1081/// bottom-up. Find the pressure set with the most change beyond its pressure
1082/// limit based on the tracker's current pressure, and return the change in
1083/// number of register units of that pressure set introduced by this
1084/// instruction.
1085///
1086/// This assumes that the current LiveOut set is sufficient.
1087///
1088/// This is expensive for an on-the-fly query because it calls
1089/// bumpUpwardPressure to recompute the pressure sets based on current
1090/// liveness. This mainly exists to verify correctness, e.g. with
1091/// -verify-misched. getUpwardPressureDelta is the fast version of this query
1092/// that uses the per-SUnit cache of the PressureDiff.
1095 RegPressureDelta &Delta,
1096 ArrayRef<PressureChange> CriticalPSets,
1097 ArrayRef<unsigned> MaxPressureLimit) {
1098 // Snapshot Pressure.
1099 // FIXME: The snapshot heap space should persist. But I'm planning to
1100 // summarize the pressure effect so we don't need to snapshot at all.
1101 std::vector<unsigned> SavedPressure = CurrSetPressure;
1102 std::vector<unsigned> SavedMaxPressure = P.MaxSetPressure;
1103
1105
1106 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI,
1107 LiveThruPressure);
1108 computeMaxPressureDelta(SavedMaxPressure, P.MaxSetPressure, CriticalPSets,
1109 MaxPressureLimit, Delta);
1110 assert(Delta.CriticalMax.getUnitInc() >= 0 &&
1111 Delta.CurrentMax.getUnitInc() >= 0 && "cannot decrease max pressure");
1112
1113 // Restore the tracker's state.
1114 P.MaxSetPressure.swap(SavedMaxPressure);
1115 CurrSetPressure.swap(SavedPressure);
1116
1117#ifndef NDEBUG
1118 if (!PDiff)
1119 return;
1120
1121 // Check if the alternate algorithm yields the same result.
1122 RegPressureDelta Delta2;
1123 getUpwardPressureDelta(MI, *PDiff, Delta2, CriticalPSets, MaxPressureLimit);
1124 if (Delta != Delta2) {
1125 dbgs() << "PDiff: ";
1126 PDiff->dump(*TRI);
1127 dbgs() << "DELTA: " << *MI;
1128 if (Delta.Excess.isValid())
1129 dbgs() << "Excess1 " << TRI->getRegPressureSetName(Delta.Excess.getPSet())
1130 << " " << Delta.Excess.getUnitInc() << "\n";
1131 if (Delta.CriticalMax.isValid())
1132 dbgs() << "Critic1 " << TRI->getRegPressureSetName(Delta.CriticalMax.getPSet())
1133 << " " << Delta.CriticalMax.getUnitInc() << "\n";
1134 if (Delta.CurrentMax.isValid())
1135 dbgs() << "CurrMx1 " << TRI->getRegPressureSetName(Delta.CurrentMax.getPSet())
1136 << " " << Delta.CurrentMax.getUnitInc() << "\n";
1137 if (Delta2.Excess.isValid())
1138 dbgs() << "Excess2 " << TRI->getRegPressureSetName(Delta2.Excess.getPSet())
1139 << " " << Delta2.Excess.getUnitInc() << "\n";
1140 if (Delta2.CriticalMax.isValid())
1141 dbgs() << "Critic2 " << TRI->getRegPressureSetName(Delta2.CriticalMax.getPSet())
1142 << " " << Delta2.CriticalMax.getUnitInc() << "\n";
1143 if (Delta2.CurrentMax.isValid())
1144 dbgs() << "CurrMx2 " << TRI->getRegPressureSetName(Delta2.CurrentMax.getPSet())
1145 << " " << Delta2.CurrentMax.getUnitInc() << "\n";
1146 llvm_unreachable("RegP Delta Mismatch");
1147 }
1148#endif
1149}
1150
1151/// This is the fast version of querying register pressure that does not
1152/// directly depend on current liveness.
1153///
1154/// @param Delta captures information needed for heuristics.
1155///
1156/// @param CriticalPSets Are the pressure sets that are known to exceed some
1157/// limit within the region, not necessarily at the current position.
1158///
1159/// @param MaxPressureLimit Is the max pressure within the region, not
1160/// necessarily at the current position.
1162getUpwardPressureDelta(const MachineInstr *MI, /*const*/ PressureDiff &PDiff,
1163 RegPressureDelta &Delta,
1164 ArrayRef<PressureChange> CriticalPSets,
1165 ArrayRef<unsigned> MaxPressureLimit) const {
1166 unsigned CritIdx = 0, CritEnd = CriticalPSets.size();
1168 PDiffI = PDiff.begin(), PDiffE = PDiff.end();
1169 PDiffI != PDiffE && PDiffI->isValid(); ++PDiffI) {
1170
1171 unsigned PSetID = PDiffI->getPSet();
1172 unsigned Limit = RCI->getRegPressureSetLimit(PSetID);
1173 if (!LiveThruPressure.empty())
1174 Limit += LiveThruPressure[PSetID];
1175
1176 unsigned POld = CurrSetPressure[PSetID];
1177 unsigned MOld = P.MaxSetPressure[PSetID];
1178 unsigned MNew = MOld;
1179 // Ignore DeadDefs here because they aren't captured by PressureChange.
1180 unsigned PNew = POld + PDiffI->getUnitInc();
1181 assert((PDiffI->getUnitInc() >= 0) == (PNew >= POld)
1182 && "PSet overflow/underflow");
1183 if (PNew > MOld)
1184 MNew = PNew;
1185 // Check if current pressure has exceeded the limit.
1186 if (!Delta.Excess.isValid()) {
1187 unsigned ExcessInc = 0;
1188 if (PNew > Limit)
1189 ExcessInc = POld > Limit ? PNew - POld : PNew - Limit;
1190 else if (POld > Limit)
1191 ExcessInc = Limit - POld;
1192 if (ExcessInc) {
1193 Delta.Excess = PressureChange(PSetID);
1194 Delta.Excess.setUnitInc(ExcessInc);
1195 }
1196 }
1197 // Check if max pressure has exceeded a critical pressure set max.
1198 if (MNew == MOld)
1199 continue;
1200 if (!Delta.CriticalMax.isValid()) {
1201 while (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() < PSetID)
1202 ++CritIdx;
1203
1204 if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == PSetID) {
1205 int CritInc = (int)MNew - (int)CriticalPSets[CritIdx].getUnitInc();
1206 if (CritInc > 0 && CritInc <= std::numeric_limits<int16_t>::max()) {
1207 Delta.CriticalMax = PressureChange(PSetID);
1208 Delta.CriticalMax.setUnitInc(CritInc);
1209 }
1210 }
1211 }
1212 // Check if max pressure has exceeded the current max.
1213 if (!Delta.CurrentMax.isValid() && MNew > MaxPressureLimit[PSetID]) {
1214 Delta.CurrentMax = PressureChange(PSetID);
1215 Delta.CurrentMax.setUnitInc(MNew - MOld);
1216 }
1217 }
1218}
1219
1220/// Helper to find a vreg use between two indices [PriorUseIdx, NextUseIdx).
1221/// The query starts with a lane bitmask which gets lanes/bits removed for every
1222/// use we find.
1223static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask,
1224 SlotIndex PriorUseIdx, SlotIndex NextUseIdx,
1225 const MachineRegisterInfo &MRI,
1226 const LiveIntervals *LIS) {
1227 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
1228 for (const MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1229 if (MO.isUndef())
1230 continue;
1231 const MachineInstr *MI = MO.getParent();
1232 SlotIndex InstSlot = LIS->getInstructionIndex(*MI).getRegSlot();
1233 if (InstSlot >= PriorUseIdx && InstSlot < NextUseIdx) {
1234 unsigned SubRegIdx = MO.getSubReg();
1235 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
1236 LastUseMask &= ~UseMask;
1237 if (LastUseMask.none())
1238 return LaneBitmask::getNone();
1239 }
1240 }
1241 return LastUseMask;
1242}
1243
1245 SlotIndex Pos) const {
1246 assert(RequireIntervals);
1247 return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos,
1249 [](const LiveRange &LR, SlotIndex Pos) {
1250 return LR.liveAt(Pos);
1251 });
1252}
1253
1255 SlotIndex Pos) const {
1256 assert(RequireIntervals);
1257 return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit,
1259 [](const LiveRange &LR, SlotIndex Pos) {
1260 const LiveRange::Segment *S = LR.getSegmentContaining(Pos);
1261 return S != nullptr && S->end == Pos.getRegSlot();
1262 });
1263}
1264
1266 SlotIndex Pos) const {
1267 assert(RequireIntervals);
1268 return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos,
1270 [](const LiveRange &LR, SlotIndex Pos) {
1271 const LiveRange::Segment *S = LR.getSegmentContaining(Pos);
1272 return S != nullptr && S->start < Pos.getRegSlot(true) &&
1273 S->end != Pos.getDeadSlot();
1274 });
1275}
1276
1277/// Record the downward impact of a single instruction on current register
1278/// pressure. Unlike the advance/recede pressure tracking interface, this does
1279/// not discover live in/outs.
1280///
1281/// This is intended for speculative queries. It leaves pressure inconsistent
1282/// with the current position, so must be restored by the caller.
1284 assert(!MI->isDebugOrPseudoInstr() && "Expect a nondebug instruction.");
1285
1286 SlotIndex SlotIdx;
1287 if (RequireIntervals)
1288 SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
1289
1290 // Account for register pressure similar to RegPressureTracker::recede().
1291 RegisterOperands RegOpers;
1292 RegOpers.collect(*MI, *TRI, *MRI, TrackLaneMasks, false);
1293 if (TrackLaneMasks)
1294 RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
1295
1296 if (RequireIntervals) {
1297 for (const RegisterMaskPair &Use : RegOpers.Uses) {
1298 Register Reg = Use.RegUnit;
1299 LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx);
1300 if (LastUseMask.none())
1301 continue;
1302 // The LastUseMask is queried from the liveness information of instruction
1303 // which may be further down the schedule. Some lanes may actually not be
1304 // last uses for the current position.
1305 // FIXME: allow the caller to pass in the list of vreg uses that remain
1306 // to be bottom-scheduled to avoid searching uses at each query.
1307 SlotIndex CurrIdx = getCurrSlot();
1308 LastUseMask
1309 = findUseBetween(Reg, LastUseMask, CurrIdx, SlotIdx, *MRI, LIS);
1310 if (LastUseMask.none())
1311 continue;
1312
1313 LaneBitmask LiveMask = LiveRegs.contains(Reg);
1314 LaneBitmask NewMask = LiveMask & ~LastUseMask;
1315 decreaseRegPressure(Reg, LiveMask, NewMask);
1316 }
1317 }
1318
1319 // Generate liveness for defs.
1320 for (const RegisterMaskPair &Def : RegOpers.Defs) {
1321 Register Reg = Def.RegUnit;
1322 LaneBitmask LiveMask = LiveRegs.contains(Reg);
1323 LaneBitmask NewMask = LiveMask | Def.LaneMask;
1324 increaseRegPressure(Reg, LiveMask, NewMask);
1325 }
1326
1327 // Boost pressure for all dead defs together.
1328 bumpDeadDefs(RegOpers.DeadDefs);
1329}
1330
1331/// Consider the pressure increase caused by traversing this instruction
1332/// top-down. Find the register class with the most change in its pressure limit
1333/// based on the tracker's current pressure, and return the number of excess
1334/// register units of that pressure set introduced by this instruction.
1335///
1336/// This assumes that the current LiveIn set is sufficient.
1337///
1338/// This is expensive for an on-the-fly query because it calls
1339/// bumpDownwardPressure to recompute the pressure sets based on current
1340/// liveness. We don't yet have a fast version of downward pressure tracking
1341/// analogous to getUpwardPressureDelta.
1344 ArrayRef<PressureChange> CriticalPSets,
1345 ArrayRef<unsigned> MaxPressureLimit) {
1346 // Snapshot Pressure.
1347 std::vector<unsigned> SavedPressure = CurrSetPressure;
1348 std::vector<unsigned> SavedMaxPressure = P.MaxSetPressure;
1349
1351
1352 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI,
1353 LiveThruPressure);
1354 computeMaxPressureDelta(SavedMaxPressure, P.MaxSetPressure, CriticalPSets,
1355 MaxPressureLimit, Delta);
1356 assert(Delta.CriticalMax.getUnitInc() >= 0 &&
1357 Delta.CurrentMax.getUnitInc() >= 0 && "cannot decrease max pressure");
1358
1359 // Restore the tracker's state.
1360 P.MaxSetPressure.swap(SavedMaxPressure);
1361 CurrSetPressure.swap(SavedPressure);
1362}
1363
1364/// Get the pressure of each PSet after traversing this instruction bottom-up.
1367 std::vector<unsigned> &PressureResult,
1368 std::vector<unsigned> &MaxPressureResult) {
1369 // Snapshot pressure.
1370 PressureResult = CurrSetPressure;
1371 MaxPressureResult = P.MaxSetPressure;
1372
1374
1375 // Current pressure becomes the result. Restore current pressure.
1376 P.MaxSetPressure.swap(MaxPressureResult);
1377 CurrSetPressure.swap(PressureResult);
1378}
1379
1380/// Get the pressure of each PSet after traversing this instruction top-down.
1383 std::vector<unsigned> &PressureResult,
1384 std::vector<unsigned> &MaxPressureResult) {
1385 // Snapshot pressure.
1386 PressureResult = CurrSetPressure;
1387 MaxPressureResult = P.MaxSetPressure;
1388
1390
1391 // Current pressure becomes the result. Restore current pressure.
1392 P.MaxSetPressure.swap(MaxPressureResult);
1393 CurrSetPressure.swap(PressureResult);
1394}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:492
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
IRTranslator LLVM IR MI
A common definition of LaneBitmask for use in TableGen and CodeGen.
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
#define P(N)
Register Usage Information Collector
static void computeExcessPressureDelta(ArrayRef< unsigned > OldPressureVec, ArrayRef< unsigned > NewPressureVec, RegPressureDelta &Delta, const RegisterClassInfo *RCI, ArrayRef< unsigned > LiveThruPressureVec)
Find the max change in excess pressure across all sets.
static void removeRegLanes(SmallVectorImpl< RegisterMaskPair > &RegUnits, RegisterMaskPair Pair)
static void increaseSetPressure(std::vector< unsigned > &CurrSetPressure, const MachineRegisterInfo &MRI, unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask)
Increase pressure for each pressure set provided by TargetRegisterInfo.
static void decreaseSetPressure(std::vector< unsigned > &CurrSetPressure, const MachineRegisterInfo &MRI, Register Reg, LaneBitmask PrevMask, LaneBitmask NewMask)
Decrease pressure for each pressure set provided by TargetRegisterInfo.
static void computeMaxPressureDelta(ArrayRef< unsigned > OldMaxPressureVec, ArrayRef< unsigned > NewMaxPressureVec, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit, RegPressureDelta &Delta)
Find the max change in max pressure that either surpasses a critical PSet limit or exceeds the curren...
static const LiveRange * getLiveRange(const LiveIntervals &LIS, unsigned Reg)
static LaneBitmask getLiveLanesAt(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, bool TrackLaneMasks, Register RegUnit, SlotIndex Pos)
static void addRegLanes(SmallVectorImpl< RegisterMaskPair > &RegUnits, RegisterMaskPair Pair)
static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo &MRI, const LiveIntervals *LIS)
Helper to find a vreg use between two indices [PriorUseIdx, NextUseIdx).
static void setRegZero(SmallVectorImpl< RegisterMaskPair > &RegUnits, Register RegUnit)
static LaneBitmask getLanesWithProperty(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, bool TrackLaneMasks, Register RegUnit, SlotIndex Pos, LaneBitmask SafeDefault, bool(*Property)(const LiveRange &LR, SlotIndex Pos))
static LaneBitmask getRegLanes(ArrayRef< RegisterMaskPair > RegUnits, Register RegUnit)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
iterator end() const
Definition: ArrayRef.h:152
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
A live range for subregisters.
Definition: LiveInterval.h:693
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:803
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:775
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
Result of a LiveRange query.
Definition: LiveInterval.h:90
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:117
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
Definition: LiveInterval.h:408
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:401
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:541
LaneBitmask contains(Register Reg) const
void init(const MachineRegisterInfo &MRI)
size_t size() const
LaneBitmask insert(RegisterMaskPair Pair)
Mark the Pair.LaneMask lanes of Pair.Reg as live.
LaneBitmask erase(RegisterMaskPair Pair)
Clears the Pair.LaneMask lanes of Pair.Reg (mark them as dead).
void appendTo(ContainerT &To) const
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool isValid() const
isValid - Returns true until all the operands have been visited.
MachineInstrBundleIterator< const MachineInstr > const_iterator
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
Definition: MachineInstr.h:68
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PSetIterator getPressureSets(Register RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Iterate over the pressure sets affected by the given physical or virtual register.
unsigned getWeight() const
Capture a change in pressure for a single pressure set.
unsigned getPSetOrMax() const
void setUnitInc(int Inc)
unsigned getPSet() const
List of PressureChanges in order of increasing, unique PSetID.
void dump(const TargetRegisterInfo &TRI) const
void addPressureChange(Register RegUnit, bool IsDec, const MachineRegisterInfo *MRI)
Add a change in pressure to the pressure diff of a given instruction.
const_iterator end() const
const_iterator begin() const
void addInstruction(unsigned Idx, const RegisterOperands &RegOpers, const MachineRegisterInfo &MRI)
Record pressure difference induced by the given operand list to node with index Idx.
void init(unsigned N)
Initialize an array of N PressureDiffs.
Track the current register pressure at some position in the instruction stream, and remember the high...
void closeRegion()
Finalize the region boundaries and recored live ins and live outs.
void recede(SmallVectorImpl< RegisterMaskPair > *LiveUses=nullptr)
Recede across the previous instruction.
void closeBottom()
Set the boundary for the bottom of the region and summarize live outs.
void bumpDownwardPressure(const MachineInstr *MI)
Record the downward impact of a single instruction on current register pressure.
void recedeSkipDebugValues()
Recede until we find an instruction which is not a DebugValue.
void getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit)
Consider the pressure increase caused by traversing this instruction bottom-up.
void initLiveThru(const RegPressureTracker &RPTracker)
Initialize the LiveThru pressure set based on the untied defs found in RPTracker.
void discoverLiveInOrOut(RegisterMaskPair Pair, SmallVectorImpl< RegisterMaskPair > &LiveInOrOut)
void init(const MachineFunction *mf, const RegisterClassInfo *rci, const LiveIntervals *lis, const MachineBasicBlock *mbb, MachineBasicBlock::const_iterator pos, bool TrackLaneMasks, bool TrackUntiedDefs)
Setup the RegPressureTracker.
void discoverLiveOut(RegisterMaskPair Pair)
Add Reg to the live out set and increase max pressure.
bool isBottomClosed() const
Does this pressure result have a valid bottom position and live outs.
bool hasUntiedDef(Register VirtReg) const
void discoverLiveIn(RegisterMaskPair Pair)
Add Reg to the live in set and increase max pressure.
void closeTop()
Set the boundary for the top of the region and summarize live ins.
LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const
void getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit)
Consider the pressure increase caused by traversing this instruction top-down.
void advance()
Advance across the current instruction.
bool isTopClosed() const
Does this pressure result have a valid top position and live ins.
void bumpUpwardPressure(const MachineInstr *MI)
Record the upward impact of a single instruction on current register pressure.
void bumpDeadDefs(ArrayRef< RegisterMaskPair > DeadDefs)
void getDownwardPressure(const MachineInstr *MI, std::vector< unsigned > &PressureResult, std::vector< unsigned > &MaxPressureResult)
Get the pressure of each PSet after traversing this instruction top-down.
SlotIndex getCurrSlot() const
Get the SlotIndex for the first nondebug instruction including or after the current position.
LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const
void getUpwardPressure(const MachineInstr *MI, std::vector< unsigned > &PressureResult, std::vector< unsigned > &MaxPressureResult)
Get the pressure of each PSet after traversing this instruction bottom-up.
LaneBitmask getLiveThroughAt(Register RegUnit, SlotIndex Pos) const
void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask)
void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask)
void addLiveRegs(ArrayRef< RegisterMaskPair > Regs)
Force liveness of virtual registers or physical register units.
void getUpwardPressureDelta(const MachineInstr *MI, PressureDiff &PDiff, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit) const
This is the fast version of querying register pressure that does not directly depend on current liven...
unsigned getRegPressureSetLimit(unsigned Idx) const
Get the register unit limit for the given pressure set index.
List of registers defined and used by a machine instruction.
void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, bool TrackLaneMasks, bool IgnoreDead)
Analyze the given instruction MI and fill in the Uses, Defs and DeadDefs list based on the MachineOpe...
void adjustLaneLiveness(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, SlotIndex Pos, MachineInstr *AddFlagsMI=nullptr)
Use liveness information to find out which uses/defs are partially undefined/dead and adjust the Regi...
SmallVector< RegisterMaskPair, 8 > DeadDefs
List of virtual registers and register units defined by the instruction but dead.
void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS)
Use liveness information to find dead defs not marked with a dead flag and move them to the DeadDefs ...
SmallVector< RegisterMaskPair, 8 > Uses
List of virtual registers and register units read by the instruction.
SmallVector< RegisterMaskPair, 8 > Defs
List of virtual registers and register units defined by the instruction which are not dead.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:82
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:264
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
Definition: SlotIndexes.h:246
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:259
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
iterator erase(const_iterator CI)
Definition: SmallVector.h:741
void push_back(const T &Elt)
Definition: SmallVector.h:416
void clear()
clear - Clears the set.
Definition: SparseSet.h:194
void setUniverse(unsigned U)
setUniverse - Set the universe size which determines the largest key the set can hold.
Definition: SparseSet.h:155
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
IterT next_nodbg(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It, then continue incrementing it while it points to a debug instruction.
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:92
LLVM_ATTRIBUTE_RETURNS_NONNULL void * safe_calloc(size_t Count, size_t Sz)
Definition: MemAlloc.h:38
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1809
void dumpRegSetPressure(ArrayRef< unsigned > SetPressure, const TargetRegisterInfo *TRI)
IterT prev_nodbg(IterT It, IterT Begin, bool SkipPseudoOp=true)
Decrement It, then continue decrementing it while it points to a debug instruction.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
#define N
RegisterPressure computed within a region of instructions delimited by TopIdx and BottomIdx.
void reset()
Clear the result so it can be used for another round of pressure tracking.
void openBottom(SlotIndex PrevBottom)
If the current bottom is not greater than the previous index, open it.
SlotIndex TopIdx
Record the boundary of the region being tracked.
void openTop(SlotIndex NextTop)
If the current top is not less than or equal to the next index, open it.
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:82
constexpr bool none() const
Definition: LaneBitmask.h:52
constexpr bool any() const
Definition: LaneBitmask.h:53
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:81
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
Store the effects of a change in pressure on things that MI scheduler cares about.
PressureChange CriticalMax
RegisterPressure computed within a region of instructions delimited by TopPos and BottomPos.
MachineBasicBlock::const_iterator TopPos
Record the boundary of the region being tracked.
MachineBasicBlock::const_iterator BottomPos
void openTop(MachineBasicBlock::const_iterator PrevTop)
If the current top is the previous instruction (before receding), open it.
void reset()
Clear the result so it can be used for another round of pressure tracking.
void openBottom(MachineBasicBlock::const_iterator PrevBottom)
If the current bottom is the previous instr (before advancing), open it.
Register RegUnit
Virtual register or register unit.
SmallVector< RegisterMaskPair, 8 > LiveInRegs
List of live in virtual registers or physical register units.
void dump(const TargetRegisterInfo *TRI) const
std::vector< unsigned > MaxSetPressure
Map of max reg pressure indexed by pressure set ID, not class ID.
SmallVector< RegisterMaskPair, 8 > LiveOutRegs