30#include "llvm/Config/llvm-config.h"
52 assert((PrevMask & ~NewMask).
none() &&
"Must not remove bits");
53 if (PrevMask.
any() || NewMask.
none())
58 for (; PSetI.
isValid(); ++PSetI)
59 CurrSetPressure[*PSetI] += Weight;
66 assert((NewMask & ~PrevMask).
none() &&
"Must not add bits");
67 if (NewMask.
any() || PrevMask.
none())
72 for (; PSetI.
isValid(); ++PSetI) {
73 assert(CurrSetPressure[*PSetI] >= Weight &&
"register pressure underflow");
74 CurrSetPressure[*PSetI] -= Weight;
78#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
83 for (
unsigned i = 0, e = SetPressure.
size(); i < e; ++i) {
84 if (SetPressure[i] != 0) {
85 dbgs() <<
TRI->getRegPressureSetName(i) <<
"=" << SetPressure[i] <<
'\n';
95 dbgs() <<
"Max Pressure: ";
97 dbgs() <<
"Live In: ";
100 if (!
P.LaneMask.all())
105 dbgs() <<
"Live Out: ";
108 if (!
P.LaneMask.all())
118 dbgs() <<
"Curr Pressure: ";
126 const char *sep =
"";
143 dbgs() <<
"[Excess=";
145 dbgs() <<
", CriticalMax=";
147 dbgs() <<
", CurrentMax=";
157 if (PreviousMask.
any() || NewMask.
none())
162 for (; PSetI.
isValid(); ++PSetI) {
163 CurrSetPressure[*PSetI] += Weight;
226 unsigned NumRegUnits =
TRI.getNumRegs();
227 unsigned NumVirtRegs =
MRI.getNumVirtRegs();
229 this->NumRegUnits = NumRegUnits;
246 CurrSetPressure.clear();
247 LiveThruPressure.clear();
250 if (RequireIntervals)
267 bool TrackLaneMasks,
bool TrackUntiedDefs) {
275 this->TrackUntiedDefs = TrackUntiedDefs;
276 this->TrackLaneMasks = TrackLaneMasks;
278 if (RequireIntervals) {
279 assert(lis &&
"IntervalPressure requires LiveIntervals");
295 if (RequireIntervals)
303 if (RequireIntervals)
312 if (IdxPos == MBB->
end())
319 if (RequireIntervals)
331 if (RequireIntervals)
344 assert(LiveRegs.
size() == 0 &&
"no region boundary");
372 return Other.RegUnit == RegUnit;
374 if (
I == RegUnits.
end())
384 return Other.RegUnit == RegUnit;
386 if (
I == RegUnits.
end()) {
396 return Other.RegUnit == RegUnit;
398 if (
I == RegUnits.
end()) {
410 return Other.RegUnit == RegUnit;
412 if (
I != RegUnits.
end()) {
413 I->LaneMask &= ~Pair.LaneMask;
414 if (
I->LaneMask.none())
429 if (Property(SR, Pos))
430 Result |= SR.LaneMask;
432 }
else if (Property(LI, Pos)) {
433 Result = TrackLaneMasks ?
MRI.getMaxLaneMaskForVReg(RegUnit)
450 bool TrackLaneMasks,
Register RegUnit,
465class RegisterOperandsCollector {
476 : RegOpers(RegOpers),
TRI(
TRI),
MRI(
MRI), IgnoreDead(IgnoreDead) {}
480 collectOperand(*OperI);
489 collectOperandLanes(*OperI);
520 if (
Reg.isVirtual()) {
522 }
else if (
MRI.isAllocatable(
Reg)) {
535 pushRegLanes(
Reg, SubRegIdx, RegOpers.
Uses);
546 pushRegLanes(
Reg, SubRegIdx, RegOpers.
Defs);
550 void pushRegLanes(
Register Reg,
unsigned SubRegIdx,
552 if (
Reg.isVirtual()) {
554 ?
TRI.getSubRegIndexLaneMask(SubRegIdx)
555 :
MRI.getMaxLaneMaskForVReg(
Reg);
557 }
else if (
MRI.isAllocatable(
Reg)) {
569 bool TrackLaneMasks,
bool IgnoreDead) {
580 for (
auto *RI =
Defs.begin(); RI !=
Defs.end(); ) {
601 for (
auto *
I =
Defs.begin();
I !=
Defs.end();) {
607 if (RegUnit.
isVirtual() && AddFlagsMI !=
nullptr &&
608 (LiveAfter & ~
I->LaneMask).none())
612 if (ActualDef.
none()) {
615 I->LaneMask = ActualDef;
621 for (
auto &[RegUnit, LaneMask] :
Uses)
624 if (AddFlagsMI !=
nullptr) {
631 if (LiveAfter.
none())
666 for (; PSetI.
isValid(); ++PSetI) {
669 for (;
I !=
E &&
I->isValid(); ++
I) {
670 if (
I->getPSet() >= *PSetI)
677 if (!
I->isValid() ||
I->getPSet() != *PSetI) {
683 unsigned NewUnitInc =
I->getUnitInc() + Weight;
684 if (NewUnitInc != 0) {
685 I->setUnitInc(NewUnitInc);
689 for (J = std::next(
I); J !=
E && J->
isValid(); ++J, ++
I)
711 return Other.RegUnit == RegUnit;
715 if (
I == LiveInOrOut.
end()) {
720 PrevMask =
I->LaneMask;
722 I->LaneMask = NewMask;
757 assert(!CurrPos->isDebugOrPseudoInstr());
768 LaneBitmask NewMask = PreviousMask & ~Def.LaneMask;
770 LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;
776 PreviousMask = LiveOut;
779 if (NewMask.
none()) {
782 if (TrackLaneMasks && LiveUses !=
nullptr)
790 if (RequireIntervals)
799 if (NewMask == PreviousMask)
803 if (PreviousMask.
none()) {
804 if (LiveUses !=
nullptr) {
805 if (!TrackLaneMasks) {
812 bool IsRedef =
I != LiveUses->
end();
824 if (RequireIntervals) {
833 if (TrackUntiedDefs) {
837 (LiveRegs.
contains(RegUnit) & Def.LaneMask).none())
838 UntiedDefs.insert(RegUnit);
856 if (RequireIntervals && !CurrPos->isDebugOrPseudoInstr())
866 if (CurrPos->isDebugInstr() || CurrPos->isPseudoProbe()) {
876 if (TrackLaneMasks) {
879 }
else if (RequireIntervals) {
883 recede(RegOpers, LiveUses);
888 assert(!TrackUntiedDefs &&
"unsupported mode");
894 if (RequireIntervals)
899 if (RequireIntervals)
915 if (RequireIntervals) {
917 if (LastUseMask.
any()) {
942 if (TrackLaneMasks) {
956 for (
unsigned i = 0, e = OldPressureVec.
size(); i < e; ++i) {
957 unsigned POld = OldPressureVec[i];
958 unsigned PNew = NewPressureVec[i];
959 int PDiff = (int)PNew - (
int)POld;
964 if (!LiveThruPressureVec.
empty())
965 Limit += LiveThruPressureVec[i];
971 PDiff = PNew - Limit;
972 }
else if (Limit > PNew)
973 PDiff = Limit - POld;
997 unsigned CritIdx = 0, CritEnd = CriticalPSets.
size();
998 for (
unsigned i = 0, e = OldMaxPressureVec.
size(); i < e; ++i) {
999 unsigned POld = OldMaxPressureVec[i];
1000 unsigned PNew = NewMaxPressureVec[i];
1005 while (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() < i)
1008 if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == i) {
1009 int PDiff = (int)PNew - (
int)CriticalPSets[CritIdx].getUnitInc();
1034 assert(!
MI->isDebugOrPseudoInstr() &&
"Expect a nondebug instruction.");
1037 if (RequireIntervals)
1046 else if (RequireIntervals)
1059 LaneBitmask LiveBefore = (LiveAfter & ~DefLanes) | UseLanes;
1095 std::vector<unsigned> SavedPressure = CurrSetPressure;
1096 std::vector<unsigned> SavedMaxPressure =
P.MaxSetPressure;
1103 MaxPressureLimit, Delta);
1108 P.MaxSetPressure.swap(SavedMaxPressure);
1109 CurrSetPressure.swap(SavedPressure);
1118 if (Delta != Delta2) {
1119 dbgs() <<
"PDiff: ";
1121 dbgs() <<
"DELTA: " << *
MI;
1160 unsigned CritIdx = 0, CritEnd = CriticalPSets.
size();
1162 PDiffI = PDiff.
begin(), PDiffE = PDiff.
end();
1163 PDiffI != PDiffE && PDiffI->
isValid(); ++PDiffI) {
1165 unsigned PSetID = PDiffI->getPSet();
1167 if (!LiveThruPressure.empty())
1168 Limit += LiveThruPressure[PSetID];
1170 unsigned POld = CurrSetPressure[PSetID];
1171 unsigned MOld =
P.MaxSetPressure[PSetID];
1172 unsigned MNew = MOld;
1174 unsigned PNew = POld + PDiffI->getUnitInc();
1175 assert((PDiffI->getUnitInc() >= 0) == (PNew >= POld)
1176 &&
"PSet overflow/underflow");
1181 unsigned ExcessInc = 0;
1183 ExcessInc = POld > Limit ? PNew - POld : PNew - Limit;
1184 else if (POld > Limit)
1185 ExcessInc = Limit - POld;
1195 while (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() < PSetID)
1198 if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == PSetID) {
1199 int CritInc = (int)MNew - (
int)CriticalPSets[CritIdx].getUnitInc();
1200 if (CritInc > 0 && CritInc <= std::numeric_limits<int16_t>::max()) {
1227 if (InstSlot >= PriorUseIdx && InstSlot < NextUseIdx) {
1230 LastUseMask &= ~UseMask;
1231 if (LastUseMask.
none())
1240 assert(RequireIntervals);
1250 assert(RequireIntervals);
1254 const LiveRange::Segment *S = LR.getSegmentContaining(Pos);
1255 return S != nullptr && S->end == Pos.getRegSlot();
1261 assert(RequireIntervals);
1278 assert(!
MI->isDebugOrPseudoInstr() &&
"Expect a nondebug instruction.");
1281 if (RequireIntervals)
1290 if (RequireIntervals) {
1294 if (LastUseMask.
none())
1304 if (LastUseMask.
none())
1341 std::vector<unsigned> SavedPressure = CurrSetPressure;
1342 std::vector<unsigned> SavedMaxPressure =
P.MaxSetPressure;
1349 MaxPressureLimit, Delta);
1354 P.MaxSetPressure.swap(SavedMaxPressure);
1355 CurrSetPressure.swap(SavedPressure);
1361 std::vector<unsigned> &PressureResult,
1362 std::vector<unsigned> &MaxPressureResult) {
1364 PressureResult = CurrSetPressure;
1365 MaxPressureResult =
P.MaxSetPressure;
1370 P.MaxSetPressure.swap(MaxPressureResult);
1371 CurrSetPressure.swap(PressureResult);
1377 std::vector<unsigned> &PressureResult,
1378 std::vector<unsigned> &MaxPressureResult) {
1380 PressureResult = CurrSetPressure;
1381 MaxPressureResult =
P.MaxSetPressure;
1386 P.MaxSetPressure.swap(MaxPressureResult);
1387 CurrSetPressure.swap(PressureResult);
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
A common definition of LaneBitmask for use in TableGen and CodeGen.
unsigned const TargetRegisterInfo * TRI
Register Usage Information Collector
static void computeExcessPressureDelta(ArrayRef< unsigned > OldPressureVec, ArrayRef< unsigned > NewPressureVec, RegPressureDelta &Delta, const RegisterClassInfo *RCI, ArrayRef< unsigned > LiveThruPressureVec)
Find the max change in excess pressure across all sets.
static void removeRegLanes(SmallVectorImpl< RegisterMaskPair > &RegUnits, RegisterMaskPair Pair)
static void increaseSetPressure(std::vector< unsigned > &CurrSetPressure, const MachineRegisterInfo &MRI, unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask)
Increase pressure for each pressure set provided by TargetRegisterInfo.
static void decreaseSetPressure(std::vector< unsigned > &CurrSetPressure, const MachineRegisterInfo &MRI, Register Reg, LaneBitmask PrevMask, LaneBitmask NewMask)
Decrease pressure for each pressure set provided by TargetRegisterInfo.
static void computeMaxPressureDelta(ArrayRef< unsigned > OldMaxPressureVec, ArrayRef< unsigned > NewMaxPressureVec, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit, RegPressureDelta &Delta)
Find the max change in max pressure that either surpasses a critical PSet limit or exceeds the curren...
static const LiveRange * getLiveRange(const LiveIntervals &LIS, unsigned Reg)
static LaneBitmask getLiveLanesAt(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, bool TrackLaneMasks, Register RegUnit, SlotIndex Pos)
static void addRegLanes(SmallVectorImpl< RegisterMaskPair > &RegUnits, RegisterMaskPair Pair)
static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo &MRI, const LiveIntervals *LIS)
Helper to find a vreg use between two indices [PriorUseIdx, NextUseIdx).
static void setRegZero(SmallVectorImpl< RegisterMaskPair > &RegUnits, Register RegUnit)
static LaneBitmask getLanesWithProperty(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, bool TrackLaneMasks, Register RegUnit, SlotIndex Pos, LaneBitmask SafeDefault, bool(*Property)(const LiveRange &LR, SlotIndex Pos))
static LaneBitmask getRegLanes(ArrayRef< RegisterMaskPair > RegUnits, Register RegUnit)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
Result of a LiveRange query.
bool isDeadDef() const
Return true if this instruction has a dead def.
This class represents the liveness of a register, stack slot, etc.
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
bool liveAt(SlotIndex index) const
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
LaneBitmask contains(Register Reg) const
void init(const MachineRegisterInfo &MRI)
LaneBitmask insert(RegisterMaskPair Pair)
Mark the Pair.LaneMask lanes of Pair.Reg as live.
LaneBitmask erase(RegisterMaskPair Pair)
Clears the Pair.LaneMask lanes of Pair.Reg (mark them as dead).
void appendTo(ContainerT &To) const
bool isValid() const
isValid - Returns true until all the operands have been visited.
MachineInstrBundleIterator< const MachineInstr > const_iterator
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PSetIterator getPressureSets(Register RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Iterate over the pressure sets affected by the given physical or virtual register.
unsigned getWeight() const
Capture a change in pressure for a single pressure set.
unsigned getPSetOrMax() const
List of PressureChanges in order of increasing, unique PSetID.
void dump(const TargetRegisterInfo &TRI) const
void addPressureChange(Register RegUnit, bool IsDec, const MachineRegisterInfo *MRI)
Add a change in pressure to the pressure diff of a given instruction.
const_iterator end() const
const_iterator begin() const
void addInstruction(unsigned Idx, const RegisterOperands &RegOpers, const MachineRegisterInfo &MRI)
Record pressure difference induced by the given operand list to node with index Idx.
void init(unsigned N)
Initialize an array of N PressureDiffs.
Track the current register pressure at some position in the instruction stream, and remember the high...
void closeRegion()
Finalize the region boundaries and recored live ins and live outs.
void recede(SmallVectorImpl< RegisterMaskPair > *LiveUses=nullptr)
Recede across the previous instruction.
void closeBottom()
Set the boundary for the bottom of the region and summarize live outs.
void bumpDownwardPressure(const MachineInstr *MI)
Record the downward impact of a single instruction on current register pressure.
void recedeSkipDebugValues()
Recede until we find an instruction which is not a DebugValue.
void getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit)
Consider the pressure increase caused by traversing this instruction bottom-up.
void initLiveThru(const RegPressureTracker &RPTracker)
Initialize the LiveThru pressure set based on the untied defs found in RPTracker.
void discoverLiveInOrOut(RegisterMaskPair Pair, SmallVectorImpl< RegisterMaskPair > &LiveInOrOut)
void init(const MachineFunction *mf, const RegisterClassInfo *rci, const LiveIntervals *lis, const MachineBasicBlock *mbb, MachineBasicBlock::const_iterator pos, bool TrackLaneMasks, bool TrackUntiedDefs)
Setup the RegPressureTracker.
void discoverLiveOut(RegisterMaskPair Pair)
Add Reg to the live out set and increase max pressure.
bool isBottomClosed() const
Does this pressure result have a valid bottom position and live outs.
bool hasUntiedDef(Register VirtReg) const
void discoverLiveIn(RegisterMaskPair Pair)
Add Reg to the live in set and increase max pressure.
void closeTop()
Set the boundary for the top of the region and summarize live ins.
LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const
void getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit)
Consider the pressure increase caused by traversing this instruction top-down.
void advance()
Advance across the current instruction.
bool isTopClosed() const
Does this pressure result have a valid top position and live ins.
void bumpUpwardPressure(const MachineInstr *MI)
Record the upward impact of a single instruction on current register pressure.
void bumpDeadDefs(ArrayRef< RegisterMaskPair > DeadDefs)
void getDownwardPressure(const MachineInstr *MI, std::vector< unsigned > &PressureResult, std::vector< unsigned > &MaxPressureResult)
Get the pressure of each PSet after traversing this instruction top-down.
SlotIndex getCurrSlot() const
Get the SlotIndex for the first nondebug instruction including or after the current position.
LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const
void getUpwardPressure(const MachineInstr *MI, std::vector< unsigned > &PressureResult, std::vector< unsigned > &MaxPressureResult)
Get the pressure of each PSet after traversing this instruction bottom-up.
LaneBitmask getLiveThroughAt(Register RegUnit, SlotIndex Pos) const
void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask)
void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask)
void addLiveRegs(ArrayRef< RegisterMaskPair > Regs)
Force liveness of virtual registers or physical register units.
void getUpwardPressureDelta(const MachineInstr *MI, PressureDiff &PDiff, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit) const
This is the fast version of querying register pressure that does not directly depend on current liven...
unsigned getRegPressureSetLimit(unsigned Idx) const
Get the register unit limit for the given pressure set index.
List of registers defined and used by a machine instruction.
void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, bool TrackLaneMasks, bool IgnoreDead)
Analyze the given instruction MI and fill in the Uses, Defs and DeadDefs list based on the MachineOpe...
void adjustLaneLiveness(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, SlotIndex Pos, MachineInstr *AddFlagsMI=nullptr)
Use liveness information to find out which uses/defs are partially undefined/dead and adjust the Regi...
SmallVector< RegisterMaskPair, 8 > DeadDefs
List of virtual registers and register units defined by the instruction but dead.
void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS)
Use liveness information to find dead defs not marked with a dead flag and move them to the DeadDefs ...
SmallVector< RegisterMaskPair, 8 > Uses
List of virtual registers and register units read by the instruction.
SmallVector< RegisterMaskPair, 8 > Defs
List of virtual registers and register units defined by the instruction which are not dead.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
SlotIndex - An opaque wrapper around machine indexes.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
iterator erase(const_iterator CI)
void push_back(const T &Elt)
void clear()
clear - Clears the set.
void setUniverse(unsigned U)
setUniverse - Set the universe size which determines the largest key the set can hold.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
A Use represents the edge between a Value definition and its users.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
IterT next_nodbg(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It, then continue incrementing it while it points to a debug instruction.
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
LLVM_ATTRIBUTE_RETURNS_NONNULL void * safe_calloc(size_t Count, size_t Sz)
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
void dumpRegSetPressure(ArrayRef< unsigned > SetPressure, const TargetRegisterInfo *TRI)
IterT prev_nodbg(IterT It, IterT Begin, bool SkipPseudoOp=true)
Decrement It, then continue decrementing it while it points to a debug instruction.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
RegisterPressure computed within a region of instructions delimited by TopIdx and BottomIdx.
void reset()
Clear the result so it can be used for another round of pressure tracking.
void openBottom(SlotIndex PrevBottom)
If the current bottom is not greater than the previous index, open it.
SlotIndex TopIdx
Record the boundary of the region being tracked.
void openTop(SlotIndex NextTop)
If the current top is not less than or equal to the next index, open it.
static constexpr LaneBitmask getAll()
constexpr bool none() const
constexpr bool any() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
Store the effects of a change in pressure on things that MI scheduler cares about.
PressureChange CriticalMax
PressureChange CurrentMax
RegisterPressure computed within a region of instructions delimited by TopPos and BottomPos.
MachineBasicBlock::const_iterator TopPos
Record the boundary of the region being tracked.
MachineBasicBlock::const_iterator BottomPos
void openTop(MachineBasicBlock::const_iterator PrevTop)
If the current top is the previous instruction (before receding), open it.
void reset()
Clear the result so it can be used for another round of pressure tracking.
void openBottom(MachineBasicBlock::const_iterator PrevBottom)
If the current bottom is the previous instr (before advancing), open it.
Register RegUnit
Virtual register or register unit.
SmallVector< RegisterMaskPair, 8 > LiveInRegs
List of live in virtual registers or physical register units.
void dump(const TargetRegisterInfo *TRI) const
std::vector< unsigned > MaxSetPressure
Map of max reg pressure indexed by pressure set ID, not class ID.
SmallVector< RegisterMaskPair, 8 > LiveOutRegs