LLVM 20.0.0git
RegisterPressure.cpp
Go to the documentation of this file.
1//===- RegisterPressure.cpp - Dynamic Register Pressure -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RegisterPressure class which can be used to track
10// MachineInstr level register pressure.
11//
12//===----------------------------------------------------------------------===//
13
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/ADT/STLExtras.h"
30#include "llvm/Config/llvm-config.h"
31#include "llvm/MC/LaneBitmask.h"
33#include "llvm/Support/Debug.h"
36#include <algorithm>
37#include <cassert>
38#include <cstdint>
39#include <cstdlib>
40#include <cstring>
41#include <iterator>
42#include <limits>
43#include <utility>
44#include <vector>
45
46using namespace llvm;
47
48/// Increase pressure for each pressure set provided by TargetRegisterInfo.
49static void increaseSetPressure(std::vector<unsigned> &CurrSetPressure,
50 const MachineRegisterInfo &MRI, unsigned Reg,
51 LaneBitmask PrevMask, LaneBitmask NewMask) {
52 assert((PrevMask & ~NewMask).none() && "Must not remove bits");
53 if (PrevMask.any() || NewMask.none())
54 return;
55
56 PSetIterator PSetI = MRI.getPressureSets(Reg);
57 unsigned Weight = PSetI.getWeight();
58 for (; PSetI.isValid(); ++PSetI)
59 CurrSetPressure[*PSetI] += Weight;
60}
61
62/// Decrease pressure for each pressure set provided by TargetRegisterInfo.
63static void decreaseSetPressure(std::vector<unsigned> &CurrSetPressure,
65 LaneBitmask PrevMask, LaneBitmask NewMask) {
66 assert((NewMask & ~PrevMask).none() && "Must not add bits");
67 if (NewMask.any() || PrevMask.none())
68 return;
69
70 PSetIterator PSetI = MRI.getPressureSets(Reg);
71 unsigned Weight = PSetI.getWeight();
72 for (; PSetI.isValid(); ++PSetI) {
73 assert(CurrSetPressure[*PSetI] >= Weight && "register pressure underflow");
74 CurrSetPressure[*PSetI] -= Weight;
75 }
76}
77
78#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
81 const TargetRegisterInfo *TRI) {
82 bool Empty = true;
83 for (unsigned i = 0, e = SetPressure.size(); i < e; ++i) {
84 if (SetPressure[i] != 0) {
85 dbgs() << TRI->getRegPressureSetName(i) << "=" << SetPressure[i] << '\n';
86 Empty = false;
87 }
88 }
89 if (Empty)
90 dbgs() << "\n";
91}
92
95 dbgs() << "Max Pressure: ";
97 dbgs() << "Live In: ";
98 for (const RegisterMaskPair &P : LiveInRegs) {
99 dbgs() << printVRegOrUnit(P.RegUnit, TRI);
100 if (!P.LaneMask.all())
101 dbgs() << ':' << PrintLaneMask(P.LaneMask);
102 dbgs() << ' ';
103 }
104 dbgs() << '\n';
105 dbgs() << "Live Out: ";
106 for (const RegisterMaskPair &P : LiveOutRegs) {
107 dbgs() << printVRegOrUnit(P.RegUnit, TRI);
108 if (!P.LaneMask.all())
109 dbgs() << ':' << PrintLaneMask(P.LaneMask);
110 dbgs() << ' ';
111 }
112 dbgs() << '\n';
113}
114
117 if (!isTopClosed() || !isBottomClosed()) {
118 dbgs() << "Curr Pressure: ";
119 dumpRegSetPressure(CurrSetPressure, TRI);
120 }
121 P.dump(TRI);
122}
123
126 const char *sep = "";
127 for (const PressureChange &Change : *this) {
128 if (!Change.isValid())
129 break;
130 dbgs() << sep << TRI.getRegPressureSetName(Change.getPSet())
131 << " " << Change.getUnitInc();
132 sep = " ";
133 }
134 dbgs() << '\n';
135}
136
139 dbgs() << "[" << getPSetOrMax() << ", " << getUnitInc() << "]\n";
140}
141
143 dbgs() << "[Excess=";
144 Excess.dump();
145 dbgs() << ", CriticalMax=";
147 dbgs() << ", CurrentMax=";
149 dbgs() << "]\n";
150}
151
152#endif
153
155 LaneBitmask PreviousMask,
156 LaneBitmask NewMask) {
157 if (PreviousMask.any() || NewMask.none())
158 return;
159
160 PSetIterator PSetI = MRI->getPressureSets(RegUnit);
161 unsigned Weight = PSetI.getWeight();
162 for (; PSetI.isValid(); ++PSetI) {
163 CurrSetPressure[*PSetI] += Weight;
164 P.MaxSetPressure[*PSetI] =
165 std::max(P.MaxSetPressure[*PSetI], CurrSetPressure[*PSetI]);
166 }
167}
168
170 LaneBitmask PreviousMask,
171 LaneBitmask NewMask) {
172 decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask);
173}
174
175/// Clear the result so it can be used for another round of pressure tracking.
178 MaxSetPressure.clear();
179 LiveInRegs.clear();
180 LiveOutRegs.clear();
181}
182
183/// Clear the result so it can be used for another round of pressure tracking.
186 MaxSetPressure.clear();
187 LiveInRegs.clear();
188 LiveOutRegs.clear();
189}
190
191/// If the current top is not less than or equal to the next index, open it.
192/// We happen to need the SlotIndex for the next top for pressure update.
194 if (TopIdx <= NextTop)
195 return;
196 TopIdx = SlotIndex();
197 LiveInRegs.clear();
198}
199
200/// If the current top is the previous instruction (before receding), open it.
202 if (TopPos != PrevTop)
203 return;
205 LiveInRegs.clear();
206}
207
208/// If the current bottom is not greater than the previous index, open it.
210 if (BottomIdx > PrevBottom)
211 return;
213 LiveInRegs.clear();
214}
215
216/// If the current bottom is the previous instr (before advancing), open it.
218 if (BottomPos != PrevBottom)
219 return;
221 LiveInRegs.clear();
222}
223
225 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
226 unsigned NumRegUnits = TRI.getNumRegs();
227 unsigned NumVirtRegs = MRI.getNumVirtRegs();
228 Regs.setUniverse(NumRegUnits + NumVirtRegs);
229 this->NumRegUnits = NumRegUnits;
230}
231
233 Regs.clear();
234}
235
236static const LiveRange *getLiveRange(const LiveIntervals &LIS, unsigned Reg) {
238 return &LIS.getInterval(Reg);
239 return LIS.getCachedRegUnit(Reg);
240}
241
243 MBB = nullptr;
244 LIS = nullptr;
245
246 CurrSetPressure.clear();
247 LiveThruPressure.clear();
248 P.MaxSetPressure.clear();
249
250 if (RequireIntervals)
251 static_cast<IntervalPressure&>(P).reset();
252 else
253 static_cast<RegionPressure&>(P).reset();
254
255 LiveRegs.clear();
256 UntiedDefs.clear();
257}
258
259/// Setup the RegPressureTracker.
260///
261/// TODO: Add support for pressure without LiveIntervals.
263 const RegisterClassInfo *rci,
264 const LiveIntervals *lis,
265 const MachineBasicBlock *mbb,
267 bool TrackLaneMasks, bool TrackUntiedDefs) {
268 reset();
269
270 MF = mf;
271 TRI = MF->getSubtarget().getRegisterInfo();
272 RCI = rci;
273 MRI = &MF->getRegInfo();
274 MBB = mbb;
275 this->TrackUntiedDefs = TrackUntiedDefs;
276 this->TrackLaneMasks = TrackLaneMasks;
277
278 if (RequireIntervals) {
279 assert(lis && "IntervalPressure requires LiveIntervals");
280 LIS = lis;
281 }
282
283 CurrPos = pos;
284 CurrSetPressure.assign(TRI->getNumRegPressureSets(), 0);
285
286 P.MaxSetPressure = CurrSetPressure;
287
288 LiveRegs.init(*MRI);
289 if (TrackUntiedDefs)
290 UntiedDefs.setUniverse(MRI->getNumVirtRegs());
291}
292
293/// Does this pressure result have a valid top position and live ins.
295 if (RequireIntervals)
296 return static_cast<IntervalPressure&>(P).TopIdx.isValid();
297 return (static_cast<RegionPressure&>(P).TopPos ==
299}
300
301/// Does this pressure result have a valid bottom position and live outs.
303 if (RequireIntervals)
304 return static_cast<IntervalPressure&>(P).BottomIdx.isValid();
305 return (static_cast<RegionPressure&>(P).BottomPos ==
307}
308
311 skipDebugInstructionsForward(CurrPos, MBB->end());
312 if (IdxPos == MBB->end())
313 return LIS->getMBBEndIdx(MBB);
314 return LIS->getInstructionIndex(*IdxPos).getRegSlot();
315}
316
317/// Set the boundary for the top of the region and summarize live ins.
319 if (RequireIntervals)
320 static_cast<IntervalPressure&>(P).TopIdx = getCurrSlot();
321 else
322 static_cast<RegionPressure&>(P).TopPos = CurrPos;
323
324 assert(P.LiveInRegs.empty() && "inconsistent max pressure result");
325 P.LiveInRegs.reserve(LiveRegs.size());
326 LiveRegs.appendTo(P.LiveInRegs);
327}
328
329/// Set the boundary for the bottom of the region and summarize live outs.
331 if (RequireIntervals)
332 static_cast<IntervalPressure&>(P).BottomIdx = getCurrSlot();
333 else
334 static_cast<RegionPressure&>(P).BottomPos = CurrPos;
335
336 assert(P.LiveOutRegs.empty() && "inconsistent max pressure result");
337 P.LiveOutRegs.reserve(LiveRegs.size());
338 LiveRegs.appendTo(P.LiveOutRegs);
339}
340
341/// Finalize the region boundaries and record live ins and live outs.
343 if (!isTopClosed() && !isBottomClosed()) {
344 assert(LiveRegs.size() == 0 && "no region boundary");
345 return;
346 }
347 if (!isBottomClosed())
348 closeBottom();
349 else if (!isTopClosed())
350 closeTop();
351 // If both top and bottom are closed, do nothing.
352}
353
354/// The register tracker is unaware of global liveness so ignores normal
355/// live-thru ranges. However, two-address or coalesced chains can also lead
356/// to live ranges with no holes. Count these to inform heuristics that we
357/// can never drop below this pressure.
359 LiveThruPressure.assign(TRI->getNumRegPressureSets(), 0);
360 assert(isBottomClosed() && "need bottom-up tracking to intialize.");
361 for (const RegisterMaskPair &Pair : P.LiveOutRegs) {
362 Register RegUnit = Pair.RegUnit;
363 if (RegUnit.isVirtual() && !RPTracker.hasUntiedDef(RegUnit))
364 increaseSetPressure(LiveThruPressure, *MRI, RegUnit,
366 }
367}
368
370 Register RegUnit) {
371 auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
372 return Other.RegUnit == RegUnit;
373 });
374 if (I == RegUnits.end())
375 return LaneBitmask::getNone();
376 return I->LaneMask;
377}
378
380 RegisterMaskPair Pair) {
381 Register RegUnit = Pair.RegUnit;
382 assert(Pair.LaneMask.any());
383 auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
384 return Other.RegUnit == RegUnit;
385 });
386 if (I == RegUnits.end()) {
387 RegUnits.push_back(Pair);
388 } else {
389 I->LaneMask |= Pair.LaneMask;
390 }
391}
392
394 Register RegUnit) {
395 auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
396 return Other.RegUnit == RegUnit;
397 });
398 if (I == RegUnits.end()) {
399 RegUnits.push_back(RegisterMaskPair(RegUnit, LaneBitmask::getNone()));
400 } else {
401 I->LaneMask = LaneBitmask::getNone();
402 }
403}
404
406 RegisterMaskPair Pair) {
407 Register RegUnit = Pair.RegUnit;
408 assert(Pair.LaneMask.any());
409 auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
410 return Other.RegUnit == RegUnit;
411 });
412 if (I != RegUnits.end()) {
413 I->LaneMask &= ~Pair.LaneMask;
414 if (I->LaneMask.none())
415 RegUnits.erase(I);
416 }
417}
418
419static LaneBitmask
421 bool TrackLaneMasks, Register RegUnit, SlotIndex Pos,
422 LaneBitmask SafeDefault,
423 bool (*Property)(const LiveRange &LR, SlotIndex Pos)) {
424 if (RegUnit.isVirtual()) {
425 const LiveInterval &LI = LIS.getInterval(RegUnit);
426 LaneBitmask Result;
427 if (TrackLaneMasks && LI.hasSubRanges()) {
428 for (const LiveInterval::SubRange &SR : LI.subranges()) {
429 if (Property(SR, Pos))
430 Result |= SR.LaneMask;
431 }
432 } else if (Property(LI, Pos)) {
433 Result = TrackLaneMasks ? MRI.getMaxLaneMaskForVReg(RegUnit)
435 }
436
437 return Result;
438 } else {
439 const LiveRange *LR = LIS.getCachedRegUnit(RegUnit);
440 // Be prepared for missing liveranges: We usually do not compute liveranges
441 // for physical registers on targets with many registers (GPUs).
442 if (LR == nullptr)
443 return SafeDefault;
444 return Property(*LR, Pos) ? LaneBitmask::getAll() : LaneBitmask::getNone();
445 }
446}
447
450 bool TrackLaneMasks, Register RegUnit,
451 SlotIndex Pos) {
452 return getLanesWithProperty(LIS, MRI, TrackLaneMasks, RegUnit, Pos,
454 [](const LiveRange &LR, SlotIndex Pos) {
455 return LR.liveAt(Pos);
456 });
457}
458
459namespace {
460
461/// Collect this instruction's unique uses and defs into SmallVectors for
462/// processing defs and uses in order.
463///
464/// FIXME: always ignore tied opers
465class RegisterOperandsCollector {
466 friend class llvm::RegisterOperands;
467
468 RegisterOperands &RegOpers;
469 const TargetRegisterInfo &TRI;
471 bool IgnoreDead;
472
473 RegisterOperandsCollector(RegisterOperands &RegOpers,
474 const TargetRegisterInfo &TRI,
475 const MachineRegisterInfo &MRI, bool IgnoreDead)
476 : RegOpers(RegOpers), TRI(TRI), MRI(MRI), IgnoreDead(IgnoreDead) {}
477
478 void collectInstr(const MachineInstr &MI) const {
479 for (ConstMIBundleOperands OperI(MI); OperI.isValid(); ++OperI)
480 collectOperand(*OperI);
481
482 // Remove redundant physreg dead defs.
483 for (const RegisterMaskPair &P : RegOpers.Defs)
484 removeRegLanes(RegOpers.DeadDefs, P);
485 }
486
487 void collectInstrLanes(const MachineInstr &MI) const {
488 for (ConstMIBundleOperands OperI(MI); OperI.isValid(); ++OperI)
489 collectOperandLanes(*OperI);
490
491 // Remove redundant physreg dead defs.
492 for (const RegisterMaskPair &P : RegOpers.Defs)
493 removeRegLanes(RegOpers.DeadDefs, P);
494 }
495
496 /// Push this operand's register onto the correct vectors.
497 void collectOperand(const MachineOperand &MO) const {
498 if (!MO.isReg() || !MO.getReg())
499 return;
500 Register Reg = MO.getReg();
501 if (MO.isUse()) {
502 if (!MO.isUndef() && !MO.isInternalRead())
503 pushReg(Reg, RegOpers.Uses);
504 } else {
505 assert(MO.isDef());
506 // Subregister definitions may imply a register read.
507 if (MO.readsReg())
508 pushReg(Reg, RegOpers.Uses);
509
510 if (MO.isDead()) {
511 if (!IgnoreDead)
512 pushReg(Reg, RegOpers.DeadDefs);
513 } else
514 pushReg(Reg, RegOpers.Defs);
515 }
516 }
517
518 void pushReg(Register Reg,
519 SmallVectorImpl<RegisterMaskPair> &RegUnits) const {
520 if (Reg.isVirtual()) {
522 } else if (MRI.isAllocatable(Reg)) {
523 for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))
525 }
526 }
527
528 void collectOperandLanes(const MachineOperand &MO) const {
529 if (!MO.isReg() || !MO.getReg())
530 return;
531 Register Reg = MO.getReg();
532 unsigned SubRegIdx = MO.getSubReg();
533 if (MO.isUse()) {
534 if (!MO.isUndef() && !MO.isInternalRead())
535 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses);
536 } else {
537 assert(MO.isDef());
538 // Treat read-undef subreg defs as definitions of the whole register.
539 if (MO.isUndef())
540 SubRegIdx = 0;
541
542 if (MO.isDead()) {
543 if (!IgnoreDead)
544 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs);
545 } else
546 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs);
547 }
548 }
549
550 void pushRegLanes(Register Reg, unsigned SubRegIdx,
551 SmallVectorImpl<RegisterMaskPair> &RegUnits) const {
552 if (Reg.isVirtual()) {
553 LaneBitmask LaneMask = SubRegIdx != 0
554 ? TRI.getSubRegIndexLaneMask(SubRegIdx)
555 : MRI.getMaxLaneMaskForVReg(Reg);
556 addRegLanes(RegUnits, RegisterMaskPair(Reg, LaneMask));
557 } else if (MRI.isAllocatable(Reg)) {
558 for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))
560 }
561 }
562};
563
564} // end anonymous namespace
565
567 const TargetRegisterInfo &TRI,
569 bool TrackLaneMasks, bool IgnoreDead) {
570 RegisterOperandsCollector Collector(*this, TRI, MRI, IgnoreDead);
571 if (TrackLaneMasks)
572 Collector.collectInstrLanes(MI);
573 else
574 Collector.collectInstr(MI);
575}
576
578 const LiveIntervals &LIS) {
579 SlotIndex SlotIdx = LIS.getInstructionIndex(MI);
580 for (auto *RI = Defs.begin(); RI != Defs.end(); /*empty*/) {
581 Register Reg = RI->RegUnit;
582 const LiveRange *LR = getLiveRange(LIS, Reg);
583 if (LR != nullptr) {
584 LiveQueryResult LRQ = LR->Query(SlotIdx);
585 if (LRQ.isDeadDef()) {
586 // LiveIntervals knows this is a dead even though it's MachineOperand is
587 // not flagged as such.
588 DeadDefs.push_back(*RI);
589 RI = Defs.erase(RI);
590 continue;
591 }
592 }
593 ++RI;
594 }
595}
596
599 SlotIndex Pos,
600 MachineInstr *AddFlagsMI) {
601 for (auto *I = Defs.begin(); I != Defs.end();) {
602 LaneBitmask LiveAfter = getLiveLanesAt(LIS, MRI, true, I->RegUnit,
603 Pos.getDeadSlot());
604 // If the def is all that is live after the instruction, then in case
605 // of a subregister def we need a read-undef flag.
606 Register RegUnit = I->RegUnit;
607 if (RegUnit.isVirtual() && AddFlagsMI != nullptr &&
608 (LiveAfter & ~I->LaneMask).none())
609 AddFlagsMI->setRegisterDefReadUndef(RegUnit);
610
611 LaneBitmask ActualDef = I->LaneMask & LiveAfter;
612 if (ActualDef.none()) {
613 I = Defs.erase(I);
614 } else {
615 I->LaneMask = ActualDef;
616 ++I;
617 }
618 }
619
620 // For uses just copy the information from LIS.
621 for (auto &[RegUnit, LaneMask] : Uses)
622 LaneMask = getLiveLanesAt(LIS, MRI, true, RegUnit, Pos.getBaseIndex());
623
624 if (AddFlagsMI != nullptr) {
625 for (const RegisterMaskPair &P : DeadDefs) {
626 Register RegUnit = P.RegUnit;
627 if (!RegUnit.isVirtual())
628 continue;
629 LaneBitmask LiveAfter = getLiveLanesAt(LIS, MRI, true, RegUnit,
630 Pos.getDeadSlot());
631 if (LiveAfter.none())
632 AddFlagsMI->setRegisterDefReadUndef(RegUnit);
633 }
634 }
635}
636
637/// Initialize an array of N PressureDiffs.
638void PressureDiffs::init(unsigned N) {
639 Size = N;
640 if (N <= Max) {
641 memset(PDiffArray, 0, N * sizeof(PressureDiff));
642 return;
643 }
644 Max = Size;
645 free(PDiffArray);
646 PDiffArray = static_cast<PressureDiff*>(safe_calloc(N, sizeof(PressureDiff)));
647}
648
650 const RegisterOperands &RegOpers,
651 const MachineRegisterInfo &MRI) {
652 PressureDiff &PDiff = (*this)[Idx];
653 assert(!PDiff.begin()->isValid() && "stale PDiff");
654 for (const RegisterMaskPair &P : RegOpers.Defs)
655 PDiff.addPressureChange(P.RegUnit, true, &MRI);
656
657 for (const RegisterMaskPair &P : RegOpers.Uses)
658 PDiff.addPressureChange(P.RegUnit, false, &MRI);
659}
660
661/// Add a change in pressure to the pressure diff of a given instruction.
663 const MachineRegisterInfo *MRI) {
664 PSetIterator PSetI = MRI->getPressureSets(RegUnit);
665 int Weight = IsDec ? -PSetI.getWeight() : PSetI.getWeight();
666 for (; PSetI.isValid(); ++PSetI) {
667 // Find an existing entry in the pressure diff for this PSet.
668 PressureDiff::iterator I = nonconst_begin(), E = nonconst_end();
669 for (; I != E && I->isValid(); ++I) {
670 if (I->getPSet() >= *PSetI)
671 break;
672 }
673 // If all pressure sets are more constrained, skip the remaining PSets.
674 if (I == E)
675 break;
676 // Insert this PressureChange.
677 if (!I->isValid() || I->getPSet() != *PSetI) {
678 PressureChange PTmp = PressureChange(*PSetI);
679 for (PressureDiff::iterator J = I; J != E && PTmp.isValid(); ++J)
680 std::swap(*J, PTmp);
681 }
682 // Update the units for this pressure set.
683 unsigned NewUnitInc = I->getUnitInc() + Weight;
684 if (NewUnitInc != 0) {
685 I->setUnitInc(NewUnitInc);
686 } else {
687 // Remove entry
689 for (J = std::next(I); J != E && J->isValid(); ++J, ++I)
690 *I = *J;
691 *I = PressureChange();
692 }
693 }
694}
695
696/// Force liveness of registers.
698 for (const RegisterMaskPair &P : Regs) {
699 LaneBitmask PrevMask = LiveRegs.insert(P);
700 LaneBitmask NewMask = PrevMask | P.LaneMask;
701 increaseRegPressure(P.RegUnit, PrevMask, NewMask);
702 }
703}
704
707 assert(Pair.LaneMask.any());
708
709 Register RegUnit = Pair.RegUnit;
710 auto I = llvm::find_if(LiveInOrOut, [RegUnit](const RegisterMaskPair &Other) {
711 return Other.RegUnit == RegUnit;
712 });
713 LaneBitmask PrevMask;
714 LaneBitmask NewMask;
715 if (I == LiveInOrOut.end()) {
716 PrevMask = LaneBitmask::getNone();
717 NewMask = Pair.LaneMask;
718 LiveInOrOut.push_back(Pair);
719 } else {
720 PrevMask = I->LaneMask;
721 NewMask = PrevMask | Pair.LaneMask;
722 I->LaneMask = NewMask;
723 }
724 increaseSetPressure(P.MaxSetPressure, *MRI, RegUnit, PrevMask, NewMask);
725}
726
728 discoverLiveInOrOut(Pair, P.LiveInRegs);
729}
730
732 discoverLiveInOrOut(Pair, P.LiveOutRegs);
733}
734
736 for (const RegisterMaskPair &P : DeadDefs) {
737 Register Reg = P.RegUnit;
738 LaneBitmask LiveMask = LiveRegs.contains(Reg);
739 LaneBitmask BumpedMask = LiveMask | P.LaneMask;
740 increaseRegPressure(Reg, LiveMask, BumpedMask);
741 }
742 for (const RegisterMaskPair &P : DeadDefs) {
743 Register Reg = P.RegUnit;
744 LaneBitmask LiveMask = LiveRegs.contains(Reg);
745 LaneBitmask BumpedMask = LiveMask | P.LaneMask;
746 decreaseRegPressure(Reg, BumpedMask, LiveMask);
747 }
748}
749
750/// Recede across the previous instruction. If LiveUses is provided, record any
751/// RegUnits that are made live by the current instruction's uses. This includes
752/// registers that are both defined and used by the instruction. If a pressure
753/// difference pointer is provided record the changes is pressure caused by this
754/// instruction independent of liveness.
757 assert(!CurrPos->isDebugOrPseudoInstr());
758
759 // Boost pressure for all dead defs together.
760 bumpDeadDefs(RegOpers.DeadDefs);
761
762 // Kill liveness at live defs.
763 // TODO: consider earlyclobbers?
764 for (const RegisterMaskPair &Def : RegOpers.Defs) {
765 Register Reg = Def.RegUnit;
766
767 LaneBitmask PreviousMask = LiveRegs.erase(Def);
768 LaneBitmask NewMask = PreviousMask & ~Def.LaneMask;
769
770 LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;
771 if (LiveOut.any()) {
773 // Retroactively model effects on pressure of the live out lanes.
774 increaseSetPressure(CurrSetPressure, *MRI, Reg, LaneBitmask::getNone(),
775 LiveOut);
776 PreviousMask = LiveOut;
777 }
778
779 if (NewMask.none()) {
780 // Add a 0 entry to LiveUses as a marker that the complete vreg has become
781 // dead.
782 if (TrackLaneMasks && LiveUses != nullptr)
783 setRegZero(*LiveUses, Reg);
784 }
785
786 decreaseRegPressure(Reg, PreviousMask, NewMask);
787 }
788
789 SlotIndex SlotIdx;
790 if (RequireIntervals)
791 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
792
793 // Generate liveness for uses.
794 for (const RegisterMaskPair &Use : RegOpers.Uses) {
795 Register Reg = Use.RegUnit;
796 assert(Use.LaneMask.any());
797 LaneBitmask PreviousMask = LiveRegs.insert(Use);
798 LaneBitmask NewMask = PreviousMask | Use.LaneMask;
799 if (NewMask == PreviousMask)
800 continue;
801
802 // Did the register just become live?
803 if (PreviousMask.none()) {
804 if (LiveUses != nullptr) {
805 if (!TrackLaneMasks) {
806 addRegLanes(*LiveUses, RegisterMaskPair(Reg, NewMask));
807 } else {
808 auto I =
809 llvm::find_if(*LiveUses, [Reg](const RegisterMaskPair Other) {
810 return Other.RegUnit == Reg;
811 });
812 bool IsRedef = I != LiveUses->end();
813 if (IsRedef) {
814 // ignore re-defs here...
815 assert(I->LaneMask.none());
816 removeRegLanes(*LiveUses, RegisterMaskPair(Reg, NewMask));
817 } else {
818 addRegLanes(*LiveUses, RegisterMaskPair(Reg, NewMask));
819 }
820 }
821 }
822
823 // Discover live outs if this may be the first occurance of this register.
824 if (RequireIntervals) {
825 LaneBitmask LiveOut = getLiveThroughAt(Reg, SlotIdx);
826 if (LiveOut.any())
828 }
829 }
830
831 increaseRegPressure(Reg, PreviousMask, NewMask);
832 }
833 if (TrackUntiedDefs) {
834 for (const RegisterMaskPair &Def : RegOpers.Defs) {
835 Register RegUnit = Def.RegUnit;
836 if (RegUnit.isVirtual() &&
837 (LiveRegs.contains(RegUnit) & Def.LaneMask).none())
838 UntiedDefs.insert(RegUnit);
839 }
840 }
841}
842
844 assert(CurrPos != MBB->begin());
845 if (!isBottomClosed())
846 closeBottom();
847
848 // Open the top of the region using block iterators.
849 if (!RequireIntervals && isTopClosed())
850 static_cast<RegionPressure&>(P).openTop(CurrPos);
851
852 // Find the previous instruction.
853 CurrPos = prev_nodbg(CurrPos, MBB->begin());
854
855 SlotIndex SlotIdx;
856 if (RequireIntervals && !CurrPos->isDebugOrPseudoInstr())
857 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
858
859 // Open the top of the region using slot indexes.
860 if (RequireIntervals && isTopClosed())
861 static_cast<IntervalPressure&>(P).openTop(SlotIdx);
862}
863
866 if (CurrPos->isDebugInstr() || CurrPos->isPseudoProbe()) {
867 // It's possible to only have debug_value and pseudo probe instructions and
868 // hit the start of the block.
869 assert(CurrPos == MBB->begin());
870 return;
871 }
872
873 const MachineInstr &MI = *CurrPos;
874 RegisterOperands RegOpers;
875 RegOpers.collect(MI, *TRI, *MRI, TrackLaneMasks, /*IgnoreDead=*/false);
876 if (TrackLaneMasks) {
877 SlotIndex SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
878 RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
879 } else if (RequireIntervals) {
880 RegOpers.detectDeadDefs(MI, *LIS);
881 }
882
883 recede(RegOpers, LiveUses);
884}
885
886/// Advance across the current instruction.
888 assert(!TrackUntiedDefs && "unsupported mode");
889 assert(CurrPos != MBB->end());
890 if (!isTopClosed())
891 closeTop();
892
893 SlotIndex SlotIdx;
894 if (RequireIntervals)
895 SlotIdx = getCurrSlot();
896
897 // Open the bottom of the region using slot indexes.
898 if (isBottomClosed()) {
899 if (RequireIntervals)
900 static_cast<IntervalPressure&>(P).openBottom(SlotIdx);
901 else
902 static_cast<RegionPressure&>(P).openBottom(CurrPos);
903 }
904
905 for (const RegisterMaskPair &Use : RegOpers.Uses) {
906 Register Reg = Use.RegUnit;
907 LaneBitmask LiveMask = LiveRegs.contains(Reg);
908 LaneBitmask LiveIn = Use.LaneMask & ~LiveMask;
909 if (LiveIn.any()) {
911 increaseRegPressure(Reg, LiveMask, LiveMask | LiveIn);
912 LiveRegs.insert(RegisterMaskPair(Reg, LiveIn));
913 }
914 // Kill liveness at last uses.
915 if (RequireIntervals) {
916 LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx);
917 if (LastUseMask.any()) {
918 LiveRegs.erase(RegisterMaskPair(Reg, LastUseMask));
919 decreaseRegPressure(Reg, LiveMask, LiveMask & ~LastUseMask);
920 }
921 }
922 }
923
924 // Generate liveness for defs.
925 for (const RegisterMaskPair &Def : RegOpers.Defs) {
926 LaneBitmask PreviousMask = LiveRegs.insert(Def);
927 LaneBitmask NewMask = PreviousMask | Def.LaneMask;
928 increaseRegPressure(Def.RegUnit, PreviousMask, NewMask);
929 }
930
931 // Boost pressure for all dead defs together.
932 bumpDeadDefs(RegOpers.DeadDefs);
933
934 // Find the next instruction.
935 CurrPos = next_nodbg(CurrPos, MBB->end());
936}
937
939 const MachineInstr &MI = *CurrPos;
940 RegisterOperands RegOpers;
941 RegOpers.collect(MI, *TRI, *MRI, TrackLaneMasks, false);
942 if (TrackLaneMasks) {
943 SlotIndex SlotIdx = getCurrSlot();
944 RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
945 }
946 advance(RegOpers);
947}
948
949/// Find the max change in excess pressure across all sets.
951 ArrayRef<unsigned> NewPressureVec,
952 RegPressureDelta &Delta,
953 const RegisterClassInfo *RCI,
954 ArrayRef<unsigned> LiveThruPressureVec) {
955 Delta.Excess = PressureChange();
956 for (unsigned i = 0, e = OldPressureVec.size(); i < e; ++i) {
957 unsigned POld = OldPressureVec[i];
958 unsigned PNew = NewPressureVec[i];
959 int PDiff = (int)PNew - (int)POld;
960 if (!PDiff) // No change in this set in the common case.
961 continue;
962 // Only consider change beyond the limit.
963 unsigned Limit = RCI->getRegPressureSetLimit(i);
964 if (!LiveThruPressureVec.empty())
965 Limit += LiveThruPressureVec[i];
966
967 if (Limit > POld) {
968 if (Limit > PNew)
969 PDiff = 0; // Under the limit
970 else
971 PDiff = PNew - Limit; // Just exceeded limit.
972 } else if (Limit > PNew)
973 PDiff = Limit - POld; // Just obeyed limit.
974
975 if (PDiff) {
976 Delta.Excess = PressureChange(i);
977 Delta.Excess.setUnitInc(PDiff);
978 break;
979 }
980 }
981}
982
983/// Find the max change in max pressure that either surpasses a critical PSet
984/// limit or exceeds the current MaxPressureLimit.
985///
986/// FIXME: comparing each element of the old and new MaxPressure vectors here is
987/// silly. It's done now to demonstrate the concept but will go away with a
988/// RegPressureTracker API change to work with pressure differences.
989static void computeMaxPressureDelta(ArrayRef<unsigned> OldMaxPressureVec,
990 ArrayRef<unsigned> NewMaxPressureVec,
991 ArrayRef<PressureChange> CriticalPSets,
992 ArrayRef<unsigned> MaxPressureLimit,
993 RegPressureDelta &Delta) {
994 Delta.CriticalMax = PressureChange();
995 Delta.CurrentMax = PressureChange();
996
997 unsigned CritIdx = 0, CritEnd = CriticalPSets.size();
998 for (unsigned i = 0, e = OldMaxPressureVec.size(); i < e; ++i) {
999 unsigned POld = OldMaxPressureVec[i];
1000 unsigned PNew = NewMaxPressureVec[i];
1001 if (PNew == POld) // No change in this set in the common case.
1002 continue;
1003
1004 if (!Delta.CriticalMax.isValid()) {
1005 while (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() < i)
1006 ++CritIdx;
1007
1008 if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == i) {
1009 int PDiff = (int)PNew - (int)CriticalPSets[CritIdx].getUnitInc();
1010 if (PDiff > 0) {
1011 Delta.CriticalMax = PressureChange(i);
1012 Delta.CriticalMax.setUnitInc(PDiff);
1013 }
1014 }
1015 }
1016 // Find the first increase above MaxPressureLimit.
1017 // (Ignores negative MDiff).
1018 if (!Delta.CurrentMax.isValid() && PNew > MaxPressureLimit[i]) {
1019 Delta.CurrentMax = PressureChange(i);
1020 Delta.CurrentMax.setUnitInc(PNew - POld);
1021 if (CritIdx == CritEnd || Delta.CriticalMax.isValid())
1022 break;
1023 }
1024 }
1025}
1026
1027/// Record the upward impact of a single instruction on current register
1028/// pressure. Unlike the advance/recede pressure tracking interface, this does
1029/// not discover live in/outs.
1030///
1031/// This is intended for speculative queries. It leaves pressure inconsistent
1032/// with the current position, so must be restored by the caller.
1034 assert(!MI->isDebugOrPseudoInstr() && "Expect a nondebug instruction.");
1035
1036 SlotIndex SlotIdx;
1037 if (RequireIntervals)
1038 SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
1039
1040 // Account for register pressure similar to RegPressureTracker::recede().
1041 RegisterOperands RegOpers;
1042 RegOpers.collect(*MI, *TRI, *MRI, TrackLaneMasks, /*IgnoreDead=*/true);
1043 assert(RegOpers.DeadDefs.empty());
1044 if (TrackLaneMasks)
1045 RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
1046 else if (RequireIntervals)
1047 RegOpers.detectDeadDefs(*MI, *LIS);
1048
1049 // Boost max pressure for all dead defs together.
1050 // Since CurrSetPressure and MaxSetPressure
1051 bumpDeadDefs(RegOpers.DeadDefs);
1052
1053 // Kill liveness at live defs.
1054 for (const RegisterMaskPair &P : RegOpers.Defs) {
1055 Register Reg = P.RegUnit;
1056 LaneBitmask LiveAfter = LiveRegs.contains(Reg);
1057 LaneBitmask UseLanes = getRegLanes(RegOpers.Uses, Reg);
1058 LaneBitmask DefLanes = P.LaneMask;
1059 LaneBitmask LiveBefore = (LiveAfter & ~DefLanes) | UseLanes;
1060
1061 // There may be parts of the register that were dead before the
1062 // instruction, but became live afterwards.
1063 decreaseRegPressure(Reg, LiveAfter, LiveAfter & LiveBefore);
1064 }
1065 // Generate liveness for uses. Also handle any uses which overlap with defs.
1066 for (const RegisterMaskPair &P : RegOpers.Uses) {
1067 Register Reg = P.RegUnit;
1068 LaneBitmask LiveAfter = LiveRegs.contains(Reg);
1069 LaneBitmask LiveBefore = LiveAfter | P.LaneMask;
1070 increaseRegPressure(Reg, LiveAfter, LiveBefore);
1071 }
1072}
1073
1074/// Consider the pressure increase caused by traversing this instruction
1075/// bottom-up. Find the pressure set with the most change beyond its pressure
1076/// limit based on the tracker's current pressure, and return the change in
1077/// number of register units of that pressure set introduced by this
1078/// instruction.
1079///
1080/// This assumes that the current LiveOut set is sufficient.
1081///
1082/// This is expensive for an on-the-fly query because it calls
1083/// bumpUpwardPressure to recompute the pressure sets based on current
1084/// liveness. This mainly exists to verify correctness, e.g. with
1085/// -verify-misched. getUpwardPressureDelta is the fast version of this query
1086/// that uses the per-SUnit cache of the PressureDiff.
1089 RegPressureDelta &Delta,
1090 ArrayRef<PressureChange> CriticalPSets,
1091 ArrayRef<unsigned> MaxPressureLimit) {
1092 // Snapshot Pressure.
1093 // FIXME: The snapshot heap space should persist. But I'm planning to
1094 // summarize the pressure effect so we don't need to snapshot at all.
1095 std::vector<unsigned> SavedPressure = CurrSetPressure;
1096 std::vector<unsigned> SavedMaxPressure = P.MaxSetPressure;
1097
1099
1100 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI,
1101 LiveThruPressure);
1102 computeMaxPressureDelta(SavedMaxPressure, P.MaxSetPressure, CriticalPSets,
1103 MaxPressureLimit, Delta);
1104 assert(Delta.CriticalMax.getUnitInc() >= 0 &&
1105 Delta.CurrentMax.getUnitInc() >= 0 && "cannot decrease max pressure");
1106
1107 // Restore the tracker's state.
1108 P.MaxSetPressure.swap(SavedMaxPressure);
1109 CurrSetPressure.swap(SavedPressure);
1110
1111#ifndef NDEBUG
1112 if (!PDiff)
1113 return;
1114
1115 // Check if the alternate algorithm yields the same result.
1116 RegPressureDelta Delta2;
1117 getUpwardPressureDelta(MI, *PDiff, Delta2, CriticalPSets, MaxPressureLimit);
1118 if (Delta != Delta2) {
1119 dbgs() << "PDiff: ";
1120 PDiff->dump(*TRI);
1121 dbgs() << "DELTA: " << *MI;
1122 if (Delta.Excess.isValid())
1123 dbgs() << "Excess1 " << TRI->getRegPressureSetName(Delta.Excess.getPSet())
1124 << " " << Delta.Excess.getUnitInc() << "\n";
1125 if (Delta.CriticalMax.isValid())
1126 dbgs() << "Critic1 " << TRI->getRegPressureSetName(Delta.CriticalMax.getPSet())
1127 << " " << Delta.CriticalMax.getUnitInc() << "\n";
1128 if (Delta.CurrentMax.isValid())
1129 dbgs() << "CurrMx1 " << TRI->getRegPressureSetName(Delta.CurrentMax.getPSet())
1130 << " " << Delta.CurrentMax.getUnitInc() << "\n";
1131 if (Delta2.Excess.isValid())
1132 dbgs() << "Excess2 " << TRI->getRegPressureSetName(Delta2.Excess.getPSet())
1133 << " " << Delta2.Excess.getUnitInc() << "\n";
1134 if (Delta2.CriticalMax.isValid())
1135 dbgs() << "Critic2 " << TRI->getRegPressureSetName(Delta2.CriticalMax.getPSet())
1136 << " " << Delta2.CriticalMax.getUnitInc() << "\n";
1137 if (Delta2.CurrentMax.isValid())
1138 dbgs() << "CurrMx2 " << TRI->getRegPressureSetName(Delta2.CurrentMax.getPSet())
1139 << " " << Delta2.CurrentMax.getUnitInc() << "\n";
1140 llvm_unreachable("RegP Delta Mismatch");
1141 }
1142#endif
1143}
1144
1145/// This is the fast version of querying register pressure that does not
1146/// directly depend on current liveness.
1147///
1148/// @param Delta captures information needed for heuristics.
1149///
1150/// @param CriticalPSets Are the pressure sets that are known to exceed some
1151/// limit within the region, not necessarily at the current position.
1152///
1153/// @param MaxPressureLimit Is the max pressure within the region, not
1154/// necessarily at the current position.
1156getUpwardPressureDelta(const MachineInstr *MI, /*const*/ PressureDiff &PDiff,
1157 RegPressureDelta &Delta,
1158 ArrayRef<PressureChange> CriticalPSets,
1159 ArrayRef<unsigned> MaxPressureLimit) const {
1160 unsigned CritIdx = 0, CritEnd = CriticalPSets.size();
1162 PDiffI = PDiff.begin(), PDiffE = PDiff.end();
1163 PDiffI != PDiffE && PDiffI->isValid(); ++PDiffI) {
1164
1165 unsigned PSetID = PDiffI->getPSet();
1166 unsigned Limit = RCI->getRegPressureSetLimit(PSetID);
1167 if (!LiveThruPressure.empty())
1168 Limit += LiveThruPressure[PSetID];
1169
1170 unsigned POld = CurrSetPressure[PSetID];
1171 unsigned MOld = P.MaxSetPressure[PSetID];
1172 unsigned MNew = MOld;
1173 // Ignore DeadDefs here because they aren't captured by PressureChange.
1174 unsigned PNew = POld + PDiffI->getUnitInc();
1175 assert((PDiffI->getUnitInc() >= 0) == (PNew >= POld)
1176 && "PSet overflow/underflow");
1177 if (PNew > MOld)
1178 MNew = PNew;
1179 // Check if current pressure has exceeded the limit.
1180 if (!Delta.Excess.isValid()) {
1181 unsigned ExcessInc = 0;
1182 if (PNew > Limit)
1183 ExcessInc = POld > Limit ? PNew - POld : PNew - Limit;
1184 else if (POld > Limit)
1185 ExcessInc = Limit - POld;
1186 if (ExcessInc) {
1187 Delta.Excess = PressureChange(PSetID);
1188 Delta.Excess.setUnitInc(ExcessInc);
1189 }
1190 }
1191 // Check if max pressure has exceeded a critical pressure set max.
1192 if (MNew == MOld)
1193 continue;
1194 if (!Delta.CriticalMax.isValid()) {
1195 while (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() < PSetID)
1196 ++CritIdx;
1197
1198 if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == PSetID) {
1199 int CritInc = (int)MNew - (int)CriticalPSets[CritIdx].getUnitInc();
1200 if (CritInc > 0 && CritInc <= std::numeric_limits<int16_t>::max()) {
1201 Delta.CriticalMax = PressureChange(PSetID);
1202 Delta.CriticalMax.setUnitInc(CritInc);
1203 }
1204 }
1205 }
1206 // Check if max pressure has exceeded the current max.
1207 if (!Delta.CurrentMax.isValid() && MNew > MaxPressureLimit[PSetID]) {
1208 Delta.CurrentMax = PressureChange(PSetID);
1209 Delta.CurrentMax.setUnitInc(MNew - MOld);
1210 }
1211 }
1212}
1213
1214/// Helper to find a vreg use between two indices [PriorUseIdx, NextUseIdx).
1215/// The query starts with a lane bitmask which gets lanes/bits removed for every
1216/// use we find.
1217static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask,
1218 SlotIndex PriorUseIdx, SlotIndex NextUseIdx,
1219 const MachineRegisterInfo &MRI,
1220 const LiveIntervals *LIS) {
1221 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
1222 for (const MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1223 if (MO.isUndef())
1224 continue;
1225 const MachineInstr *MI = MO.getParent();
1226 SlotIndex InstSlot = LIS->getInstructionIndex(*MI).getRegSlot();
1227 if (InstSlot >= PriorUseIdx && InstSlot < NextUseIdx) {
1228 unsigned SubRegIdx = MO.getSubReg();
1229 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
1230 LastUseMask &= ~UseMask;
1231 if (LastUseMask.none())
1232 return LaneBitmask::getNone();
1233 }
1234 }
1235 return LastUseMask;
1236}
1237
1239 SlotIndex Pos) const {
1240 assert(RequireIntervals);
1241 return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos,
1243 [](const LiveRange &LR, SlotIndex Pos) {
1244 return LR.liveAt(Pos);
1245 });
1246}
1247
1249 SlotIndex Pos) const {
1250 assert(RequireIntervals);
1251 return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit,
1253 [](const LiveRange &LR, SlotIndex Pos) {
1254 const LiveRange::Segment *S = LR.getSegmentContaining(Pos);
1255 return S != nullptr && S->end == Pos.getRegSlot();
1256 });
1257}
1258
1260 SlotIndex Pos) const {
1261 assert(RequireIntervals);
1262 return getLanesWithProperty(*LIS, *MRI, TrackLaneMasks, RegUnit, Pos,
1264 [](const LiveRange &LR, SlotIndex Pos) {
1265 const LiveRange::Segment *S = LR.getSegmentContaining(Pos);
1266 return S != nullptr && S->start < Pos.getRegSlot(true) &&
1267 S->end != Pos.getDeadSlot();
1268 });
1269}
1270
1271/// Record the downward impact of a single instruction on current register
1272/// pressure. Unlike the advance/recede pressure tracking interface, this does
1273/// not discover live in/outs.
1274///
1275/// This is intended for speculative queries. It leaves pressure inconsistent
1276/// with the current position, so must be restored by the caller.
1278 assert(!MI->isDebugOrPseudoInstr() && "Expect a nondebug instruction.");
1279
1280 SlotIndex SlotIdx;
1281 if (RequireIntervals)
1282 SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
1283
1284 // Account for register pressure similar to RegPressureTracker::advance().
1285 RegisterOperands RegOpers;
1286 RegOpers.collect(*MI, *TRI, *MRI, TrackLaneMasks, /*IgnoreDead=*/false);
1287 if (TrackLaneMasks)
1288 RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
1289
1290 if (RequireIntervals) {
1291 for (const RegisterMaskPair &Use : RegOpers.Uses) {
1292 Register Reg = Use.RegUnit;
1293 LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx);
1294 if (LastUseMask.none())
1295 continue;
1296 // The LastUseMask is queried from the liveness information of instruction
1297 // which may be further down the schedule. Some lanes may actually not be
1298 // last uses for the current position.
1299 // FIXME: allow the caller to pass in the list of vreg uses that remain
1300 // to be bottom-scheduled to avoid searching uses at each query.
1301 SlotIndex CurrIdx = getCurrSlot();
1302 LastUseMask
1303 = findUseBetween(Reg, LastUseMask, CurrIdx, SlotIdx, *MRI, LIS);
1304 if (LastUseMask.none())
1305 continue;
1306
1307 LaneBitmask LiveMask = LiveRegs.contains(Reg);
1308 LaneBitmask NewMask = LiveMask & ~LastUseMask;
1309 decreaseRegPressure(Reg, LiveMask, NewMask);
1310 }
1311 }
1312
1313 // Generate liveness for defs.
1314 for (const RegisterMaskPair &Def : RegOpers.Defs) {
1315 Register Reg = Def.RegUnit;
1316 LaneBitmask LiveMask = LiveRegs.contains(Reg);
1317 LaneBitmask NewMask = LiveMask | Def.LaneMask;
1318 increaseRegPressure(Reg, LiveMask, NewMask);
1319 }
1320
1321 // Boost pressure for all dead defs together.
1322 bumpDeadDefs(RegOpers.DeadDefs);
1323}
1324
1325/// Consider the pressure increase caused by traversing this instruction
1326/// top-down. Find the register class with the most change in its pressure limit
1327/// based on the tracker's current pressure, and return the number of excess
1328/// register units of that pressure set introduced by this instruction.
1329///
1330/// This assumes that the current LiveIn set is sufficient.
1331///
1332/// This is expensive for an on-the-fly query because it calls
1333/// bumpDownwardPressure to recompute the pressure sets based on current
1334/// liveness. We don't yet have a fast version of downward pressure tracking
1335/// analogous to getUpwardPressureDelta.
1338 ArrayRef<PressureChange> CriticalPSets,
1339 ArrayRef<unsigned> MaxPressureLimit) {
1340 // Snapshot Pressure.
1341 std::vector<unsigned> SavedPressure = CurrSetPressure;
1342 std::vector<unsigned> SavedMaxPressure = P.MaxSetPressure;
1343
1345
1346 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI,
1347 LiveThruPressure);
1348 computeMaxPressureDelta(SavedMaxPressure, P.MaxSetPressure, CriticalPSets,
1349 MaxPressureLimit, Delta);
1350 assert(Delta.CriticalMax.getUnitInc() >= 0 &&
1351 Delta.CurrentMax.getUnitInc() >= 0 && "cannot decrease max pressure");
1352
1353 // Restore the tracker's state.
1354 P.MaxSetPressure.swap(SavedMaxPressure);
1355 CurrSetPressure.swap(SavedPressure);
1356}
1357
1358/// Get the pressure of each PSet after traversing this instruction bottom-up.
1361 std::vector<unsigned> &PressureResult,
1362 std::vector<unsigned> &MaxPressureResult) {
1363 // Snapshot pressure.
1364 PressureResult = CurrSetPressure;
1365 MaxPressureResult = P.MaxSetPressure;
1366
1368
1369 // Current pressure becomes the result. Restore current pressure.
1370 P.MaxSetPressure.swap(MaxPressureResult);
1371 CurrSetPressure.swap(PressureResult);
1372}
1373
1374/// Get the pressure of each PSet after traversing this instruction top-down.
1377 std::vector<unsigned> &PressureResult,
1378 std::vector<unsigned> &MaxPressureResult) {
1379 // Snapshot pressure.
1380 PressureResult = CurrSetPressure;
1381 MaxPressureResult = P.MaxSetPressure;
1382
1384
1385 // Current pressure becomes the result. Restore current pressure.
1386 P.MaxSetPressure.swap(MaxPressureResult);
1387 CurrSetPressure.swap(PressureResult);
1388}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:622
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
IRTranslator LLVM IR MI
A common definition of LaneBitmask for use in TableGen and CodeGen.
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
#define P(N)
Register Usage Information Collector
static void computeExcessPressureDelta(ArrayRef< unsigned > OldPressureVec, ArrayRef< unsigned > NewPressureVec, RegPressureDelta &Delta, const RegisterClassInfo *RCI, ArrayRef< unsigned > LiveThruPressureVec)
Find the max change in excess pressure across all sets.
static void removeRegLanes(SmallVectorImpl< RegisterMaskPair > &RegUnits, RegisterMaskPair Pair)
static void increaseSetPressure(std::vector< unsigned > &CurrSetPressure, const MachineRegisterInfo &MRI, unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask)
Increase pressure for each pressure set provided by TargetRegisterInfo.
static void decreaseSetPressure(std::vector< unsigned > &CurrSetPressure, const MachineRegisterInfo &MRI, Register Reg, LaneBitmask PrevMask, LaneBitmask NewMask)
Decrease pressure for each pressure set provided by TargetRegisterInfo.
static void computeMaxPressureDelta(ArrayRef< unsigned > OldMaxPressureVec, ArrayRef< unsigned > NewMaxPressureVec, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit, RegPressureDelta &Delta)
Find the max change in max pressure that either surpasses a critical PSet limit or exceeds the curren...
static const LiveRange * getLiveRange(const LiveIntervals &LIS, unsigned Reg)
static LaneBitmask getLiveLanesAt(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, bool TrackLaneMasks, Register RegUnit, SlotIndex Pos)
static void addRegLanes(SmallVectorImpl< RegisterMaskPair > &RegUnits, RegisterMaskPair Pair)
static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo &MRI, const LiveIntervals *LIS)
Helper to find a vreg use between two indices [PriorUseIdx, NextUseIdx).
static void setRegZero(SmallVectorImpl< RegisterMaskPair > &RegUnits, Register RegUnit)
static LaneBitmask getLanesWithProperty(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, bool TrackLaneMasks, Register RegUnit, SlotIndex Pos, LaneBitmask SafeDefault, bool(*Property)(const LiveRange &LR, SlotIndex Pos))
static LaneBitmask getRegLanes(ArrayRef< RegisterMaskPair > RegUnits, Register RegUnit)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
iterator end() const
Definition: ArrayRef.h:157
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:168
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:163
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
A live range for subregisters.
Definition: LiveInterval.h:694
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:687
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:810
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:782
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
Result of a LiveRange query.
Definition: LiveInterval.h:90
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:117
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
Definition: LiveInterval.h:408
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:401
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:542
LaneBitmask contains(Register Reg) const
void init(const MachineRegisterInfo &MRI)
size_t size() const
LaneBitmask insert(RegisterMaskPair Pair)
Mark the Pair.LaneMask lanes of Pair.Reg as live.
LaneBitmask erase(RegisterMaskPair Pair)
Clears the Pair.LaneMask lanes of Pair.Reg (mark them as dead).
void appendTo(ContainerT &To) const
bool isValid() const
isValid - Returns true until all the operands have been visited.
MachineInstrBundleIterator< const MachineInstr > const_iterator
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
Definition: MachineInstr.h:69
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PSetIterator getPressureSets(Register RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Iterate over the pressure sets affected by the given physical or virtual register.
unsigned getWeight() const
Capture a change in pressure for a single pressure set.
unsigned getPSetOrMax() const
void setUnitInc(int Inc)
unsigned getPSet() const
List of PressureChanges in order of increasing, unique PSetID.
void dump(const TargetRegisterInfo &TRI) const
void addPressureChange(Register RegUnit, bool IsDec, const MachineRegisterInfo *MRI)
Add a change in pressure to the pressure diff of a given instruction.
const_iterator end() const
const_iterator begin() const
void addInstruction(unsigned Idx, const RegisterOperands &RegOpers, const MachineRegisterInfo &MRI)
Record pressure difference induced by the given operand list to node with index Idx.
void init(unsigned N)
Initialize an array of N PressureDiffs.
Track the current register pressure at some position in the instruction stream, and remember the high...
void closeRegion()
Finalize the region boundaries and recored live ins and live outs.
void recede(SmallVectorImpl< RegisterMaskPair > *LiveUses=nullptr)
Recede across the previous instruction.
void closeBottom()
Set the boundary for the bottom of the region and summarize live outs.
void bumpDownwardPressure(const MachineInstr *MI)
Record the downward impact of a single instruction on current register pressure.
void recedeSkipDebugValues()
Recede until we find an instruction which is not a DebugValue.
void getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit)
Consider the pressure increase caused by traversing this instruction bottom-up.
void initLiveThru(const RegPressureTracker &RPTracker)
Initialize the LiveThru pressure set based on the untied defs found in RPTracker.
void discoverLiveInOrOut(RegisterMaskPair Pair, SmallVectorImpl< RegisterMaskPair > &LiveInOrOut)
void init(const MachineFunction *mf, const RegisterClassInfo *rci, const LiveIntervals *lis, const MachineBasicBlock *mbb, MachineBasicBlock::const_iterator pos, bool TrackLaneMasks, bool TrackUntiedDefs)
Setup the RegPressureTracker.
void discoverLiveOut(RegisterMaskPair Pair)
Add Reg to the live out set and increase max pressure.
bool isBottomClosed() const
Does this pressure result have a valid bottom position and live outs.
bool hasUntiedDef(Register VirtReg) const
void discoverLiveIn(RegisterMaskPair Pair)
Add Reg to the live in set and increase max pressure.
void closeTop()
Set the boundary for the top of the region and summarize live ins.
LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const
void getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit)
Consider the pressure increase caused by traversing this instruction top-down.
void advance()
Advance across the current instruction.
bool isTopClosed() const
Does this pressure result have a valid top position and live ins.
void bumpUpwardPressure(const MachineInstr *MI)
Record the upward impact of a single instruction on current register pressure.
void bumpDeadDefs(ArrayRef< RegisterMaskPair > DeadDefs)
void getDownwardPressure(const MachineInstr *MI, std::vector< unsigned > &PressureResult, std::vector< unsigned > &MaxPressureResult)
Get the pressure of each PSet after traversing this instruction top-down.
SlotIndex getCurrSlot() const
Get the SlotIndex for the first nondebug instruction including or after the current position.
LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const
void getUpwardPressure(const MachineInstr *MI, std::vector< unsigned > &PressureResult, std::vector< unsigned > &MaxPressureResult)
Get the pressure of each PSet after traversing this instruction bottom-up.
LaneBitmask getLiveThroughAt(Register RegUnit, SlotIndex Pos) const
void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask)
void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask)
void addLiveRegs(ArrayRef< RegisterMaskPair > Regs)
Force liveness of virtual registers or physical register units.
void getUpwardPressureDelta(const MachineInstr *MI, PressureDiff &PDiff, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit) const
This is the fast version of querying register pressure that does not directly depend on current liven...
unsigned getRegPressureSetLimit(unsigned Idx) const
Get the register unit limit for the given pressure set index.
List of registers defined and used by a machine instruction.
void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, bool TrackLaneMasks, bool IgnoreDead)
Analyze the given instruction MI and fill in the Uses, Defs and DeadDefs list based on the MachineOpe...
void adjustLaneLiveness(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, SlotIndex Pos, MachineInstr *AddFlagsMI=nullptr)
Use liveness information to find out which uses/defs are partially undefined/dead and adjust the Regi...
SmallVector< RegisterMaskPair, 8 > DeadDefs
List of virtual registers and register units defined by the instruction but dead.
void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS)
Use liveness information to find dead defs not marked with a dead flag and move them to the DeadDefs ...
SmallVector< RegisterMaskPair, 8 > Uses
List of virtual registers and register units read by the instruction.
SmallVector< RegisterMaskPair, 8 > Defs
List of virtual registers and register units defined by the instruction which are not dead.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:65
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:242
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
Definition: SlotIndexes.h:224
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:237
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
iterator erase(const_iterator CI)
Definition: SmallVector.h:737
void push_back(const T &Elt)
Definition: SmallVector.h:413
void clear()
clear - Clears the set.
Definition: SparseSet.h:198
void setUniverse(unsigned U)
setUniverse - Set the universe size which determines the largest key the set can hold.
Definition: SparseSet.h:160
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
IterT next_nodbg(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It, then continue incrementing it while it points to a debug instruction.
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:92
LLVM_ATTRIBUTE_RETURNS_NONNULL void * safe_calloc(size_t Count, size_t Sz)
Definition: MemAlloc.h:38
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
@ Other
Any other memory.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1766
void dumpRegSetPressure(ArrayRef< unsigned > SetPressure, const TargetRegisterInfo *TRI)
IterT prev_nodbg(IterT It, IterT Begin, bool SkipPseudoOp=true)
Decrement It, then continue decrementing it while it points to a debug instruction.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:860
#define N
RegisterPressure computed within a region of instructions delimited by TopIdx and BottomIdx.
void reset()
Clear the result so it can be used for another round of pressure tracking.
void openBottom(SlotIndex PrevBottom)
If the current bottom is not greater than the previous index, open it.
SlotIndex TopIdx
Record the boundary of the region being tracked.
void openTop(SlotIndex NextTop)
If the current top is not less than or equal to the next index, open it.
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:82
constexpr bool none() const
Definition: LaneBitmask.h:52
constexpr bool any() const
Definition: LaneBitmask.h:53
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:81
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
Store the effects of a change in pressure on things that MI scheduler cares about.
PressureChange CriticalMax
RegisterPressure computed within a region of instructions delimited by TopPos and BottomPos.
MachineBasicBlock::const_iterator TopPos
Record the boundary of the region being tracked.
MachineBasicBlock::const_iterator BottomPos
void openTop(MachineBasicBlock::const_iterator PrevTop)
If the current top is the previous instruction (before receding), open it.
void reset()
Clear the result so it can be used for another round of pressure tracking.
void openBottom(MachineBasicBlock::const_iterator PrevBottom)
If the current bottom is the previous instr (before advancing), open it.
Register RegUnit
Virtual register or register unit.
SmallVector< RegisterMaskPair, 8 > LiveInRegs
List of live in virtual registers or physical register units.
void dump(const TargetRegisterInfo *TRI) const
std::vector< unsigned > MaxSetPressure
Map of max reg pressure indexed by pressure set ID, not class ID.
SmallVector< RegisterMaskPair, 8 > LiveOutRegs