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31 #define GET_REGINFO_TARGET_DESC
32 #include "M68kGenRegisterInfo.inc"
34 #define DEBUG_TYPE "m68k-reg-info"
40 cl::desc(
"Enable use of a base pointer for complex stack frames"));
43 void M68kRegisterInfo::anchor() {}
51 GlobalBasePtr = M68k::A5;
61 return CSR_STD_SaveList;
67 return CSR_STD_RegMask;
72 return &M68k::XR32_TCRegClass;
87 "reg must be a physical register");
92 for (regclass_iterator
I = regclass_begin(),
E = regclass_end();
I !=
E;
95 if ((VT ==
MVT::Other || isTypeLegalForClass(*RC, VT)) &&
102 assert(BestRC &&
"Couldn't find the register class");
118 assert(Result >= 0 &&
"Can not determine spill order");
128 auto setBitVector = [&Reserved,
this](
unsigned Reg) {
138 for (
size_t Reg = 0, Total = getNumRegs();
Reg != Total; ++
Reg) {
143 setBitVector(M68k::PC);
144 setBitVector(M68k::SP);
146 if (TFI->
hasFP(MF)) {
147 setBitVector(FramePtr);
157 "this calling convention.");
166 int SPAdj,
unsigned FIOperandNum,
178 int FIndex = (
int)(
Base.getIndex());
181 bool AfterFPPop =
false;
186 else if (hasStackRealignment(MF))
187 BasePtr = (FIndex < 0 ? FramePtr : StackPtr);
191 BasePtr = (TFI->
hasFP(MF) ? FramePtr : StackPtr);
193 Base.ChangeToRegister(BasePtr,
false);
207 if (BasePtr == StackPtr)
238 bool CantUseFP = hasStackRealignment(MF);
263 return TFI->
hasFP(MF) ? FramePtr : StackPtr;
267 return &M68k::DR32RegClass;
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
This is an optimization pass for GlobalISel generic memory operations.
const TargetRegisterClass * intRegClass(unsigned Size) const
Information about stack frame layout on the target.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
M68kRegisterInfo(const M68kSubtarget &Subtarget)
int getSpillRegisterOrder(unsigned Reg) const
Return spill order index of a register, if there is none then trap.
Reg
All possible values of the reg field in the ModR/M byte.
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
static bool CantUseSP(const MachineFrameInfo &MFI)
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
bool isRegisterReservedByUser(Register R) const
Register getFrameRegister(const MachineFunction &MF) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
unsigned getMatchingMegaReg(unsigned Reg, const TargetRegisterClass *RC) const
Return a mega-register of the specified register Reg so its sub-register of index SubIdx is Reg,...
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
const TargetRegisterClass * getMaximalPhysRegClass(unsigned reg, MVT VT) const
Returns the Register Class of a physical register of the given type, picking the biggest register cla...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
MachineOperand class - Representation of each machine instruction operand.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
bool canRealignStack(const MachineFunction &MF) const override
True if the stack can be realigned for the target.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
FrameIndex represent objects inside a abstract stack.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool hasFP(const MachineFunction &MF) const override
Return true if the specified function should have a dedicated frame pointer register.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Representation of each machine instruction.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
initializer< Ty > init(const Ty &Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCSuperRegIterator enumerates all super-registers of Reg.
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
This method should return the base register and offset used to reference a frame index location.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
static StackOffset getFixed(ScalarTy Fixed)
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
static const TargetRegisterClass * getRegClass(const MachineInstr &MI, Register Reg)
static cl::opt< bool > EnableBasePointer("m68k-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
const TargetRegisterClass * getRegsForTailCall(const MachineFunction &MF) const
Returns a register class with registers that can be used in forming tail calls.
BitVector getReservedRegs(const MachineFunction &MF) const override
unsigned getNumRegs() const
Return the number of registers in this class.
Function & getFunction()
Return the LLVM function that this machine code represents.
virtual const TargetFrameLowering * getFrameLowering() const
bool hasBasePointer(const MachineFunction &MF) const
int getRegisterOrder(unsigned Reg, const TargetRegisterClass &TRC) const
Return index of a register within a register class, otherwise return -1.
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
MCSubRegIterator enumerates all sub-registers of Reg.
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
unsigned getBaseRegister() const
MCRegAliasIterator enumerates all registers aliasing Reg.