LLVM  14.0.0git
M68kRegisterInfo.cpp
Go to the documentation of this file.
1 //===-- M68kRegisterInfo.cpp - CPU0 Register Information -----*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file contains the CPU0 implementation of the TargetRegisterInfo class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "M68kRegisterInfo.h"
15 
16 #include "M68k.h"
17 #include "M68kMachineFunction.h"
18 #include "M68kSubtarget.h"
19 
21 
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/Type.h"
26 #include "llvm/Support/Debug.h"
29 
30 #define GET_REGINFO_TARGET_DESC
31 #include "M68kGenRegisterInfo.inc"
32 
33 #define DEBUG_TYPE "m68k-reg-info"
34 
35 using namespace llvm;
36 
38  "m68k-use-base-pointer", cl::Hidden, cl::init(true),
39  cl::desc("Enable use of a base pointer for complex stack frames"));
40 
41 // Pin the vtable to this file.
42 void M68kRegisterInfo::anchor() {}
43 
45  // FIXME x26 not sure it this the correct value, it expects RA, but M68k
46  // passes IP anyway, how this works?
47  : M68kGenRegisterInfo(M68k::A0, 0, 0, M68k::PC), Subtarget(ST) {
48  StackPtr = M68k::SP;
49  FramePtr = M68k::A6;
50  GlobalBasePtr = M68k::A5;
51  BasePtr = M68k::A4;
52 }
53 
54 //===----------------------------------------------------------------------===//
55 // Callee Saved Registers methods
56 //===----------------------------------------------------------------------===//
57 
58 const MCPhysReg *
60  return CSR_STD_SaveList;
61 }
62 
63 const uint32_t *
65  CallingConv::ID) const {
66  return CSR_STD_RegMask;
67 }
68 
69 const TargetRegisterClass *
71  return &M68k::XR32_TCRegClass;
72 }
73 
74 unsigned
76  const TargetRegisterClass *RC) const {
77  for (MCSuperRegIterator Super(Reg, this); Super.isValid(); ++Super)
78  if (RC->contains(*Super))
79  return *Super;
80  return 0;
81 }
82 
83 const TargetRegisterClass *
86  "reg must be a physical register");
87 
88  // Pick the most sub register class of the right type that contains
89  // this physreg.
90  const TargetRegisterClass *BestRC = nullptr;
91  for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E;
92  ++I) {
93  const TargetRegisterClass *RC = *I;
94  if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
95  RC->contains(reg) &&
96  (!BestRC ||
97  (BestRC->hasSubClass(RC) && RC->getNumRegs() > BestRC->getNumRegs())))
98  BestRC = RC;
99  }
100 
101  assert(BestRC && "Couldn't find the register class");
102  return BestRC;
103 }
104 
106  const TargetRegisterClass &TRC) const {
107  for (unsigned i = 0; i < TRC.getNumRegs(); ++i) {
108  if (regsOverlap(Reg, TRC.getRegister(i))) {
109  return i;
110  }
111  }
112  return -1;
113 }
114 
116  int Result = getRegisterOrder(Reg, *getRegClass(M68k::SPILLRegClassID));
117  assert(Result >= 0 && "Can not determine spill order");
118  return Result;
119 }
120 
122  const M68kFrameLowering *TFI = getFrameLowering(MF);
123 
124  BitVector Reserved(getNumRegs());
125 
126  // Set a register's and its sub-registers and aliases as reserved.
127  auto setBitVector = [&Reserved, this](unsigned Reg) {
128  for (MCRegAliasIterator I(Reg, this, /* self */ true); I.isValid(); ++I) {
129  Reserved.set(*I);
130  }
131  for (MCSubRegIterator I(Reg, this, /* self */ true); I.isValid(); ++I) {
132  Reserved.set(*I);
133  }
134  };
135 
136  // Registers reserved by users
137  for (size_t Reg = 0, Total = getNumRegs(); Reg != Total; ++Reg) {
139  setBitVector(Reg);
140  }
141 
142  setBitVector(M68k::PC);
143  setBitVector(M68k::SP);
144 
145  if (TFI->hasFP(MF)) {
146  setBitVector(FramePtr);
147  }
148 
149  // Set the base-pointer register and its aliases as reserved if needed.
150  if (hasBasePointer(MF)) {
152  const uint32_t *RegMask = getCallPreservedMask(MF, CC);
154  report_fatal_error("Stack realignment in presence of dynamic allocas is "
155  "not supported with"
156  "this calling convention.");
157 
158  setBitVector(getBaseRegister());
159  }
160 
161  return Reserved;
162 }
163 
165  int SPAdj, unsigned FIOperandNum,
166  RegScavenger *RS) const {
167  MachineInstr &MI = *II;
168  MachineFunction &MF = *MI.getParent()->getParent();
169  const M68kFrameLowering *TFI = getFrameLowering(MF);
170 
171  // We have either (i,An,Rn) or (i,An) EA form
172  // NOTE Base contains the FI and we need to backtrace a bit to get Disp
173  MachineOperand &Disp = MI.getOperand(FIOperandNum - 1);
174  MachineOperand &Base = MI.getOperand(FIOperandNum);
175 
176  int Imm = (int)(Disp.getImm());
177  int FIndex = (int)(Base.getIndex());
178 
179  // FIXME tail call: implement jmp from mem
180  bool AfterFPPop = false;
181 
182  unsigned BasePtr;
183  if (hasBasePointer(MF))
184  BasePtr = (FIndex < 0 ? FramePtr : getBaseRegister());
185  else if (hasStackRealignment(MF))
186  BasePtr = (FIndex < 0 ? FramePtr : StackPtr);
187  else if (AfterFPPop)
188  BasePtr = StackPtr;
189  else
190  BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
191 
192  Base.ChangeToRegister(BasePtr, false);
193 
194  // Now add the frame object offset to the offset from FP.
195  int64_t FIOffset;
196  Register IgnoredFrameReg;
197  if (AfterFPPop) {
198  // Tail call jmp happens after FP is popped.
199  const MachineFrameInfo &MFI = MF.getFrameInfo();
200  FIOffset = MFI.getObjectOffset(FIndex) - TFI->getOffsetOfLocalArea();
201  } else {
202  FIOffset =
203  TFI->getFrameIndexReference(MF, FIndex, IgnoredFrameReg).getFixed();
204  }
205 
206  if (BasePtr == StackPtr)
207  FIOffset += SPAdj;
208 
209  Disp.ChangeToImmediate(FIOffset + Imm);
210 }
211 
213  const MachineFunction &MF) const {
214  return true;
215 }
216 
218  const MachineFunction &MF) const {
219  return true;
220 }
221 
222 static bool CantUseSP(const MachineFrameInfo &MFI) {
223  return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
224 }
225 
227  const MachineFrameInfo &MFI = MF.getFrameInfo();
228 
229  if (!EnableBasePointer)
230  return false;
231 
232  // When we need stack realignment, we can't address the stack from the frame
233  // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
234  // can't address variables from the stack pointer. MS inline asm can
235  // reference locals while also adjusting the stack pointer. When we can't
236  // use both the SP and the FP, we need a separate base pointer register.
237  bool CantUseFP = hasStackRealignment(MF);
238  return CantUseFP && CantUseSP(MFI);
239 }
240 
243  return false;
244 
245  const MachineFrameInfo &MFI = MF.getFrameInfo();
246  const MachineRegisterInfo *MRI = &MF.getRegInfo();
247 
248  // Stack realignment requires a frame pointer. If we already started
249  // register allocation with frame pointer elimination, it is too late now.
250  if (!MRI->canReserveReg(FramePtr))
251  return false;
252 
253  // If a base pointer is necessary. Check that it isn't too late to reserve it.
254  if (CantUseSP(MFI))
255  return MRI->canReserveReg(BasePtr);
256 
257  return true;
258 }
259 
262  return TFI->hasFP(MF) ? FramePtr : StackPtr;
263 }
264 
266  return &M68k::DR32RegClass;
267 }
i
i
Definition: README.txt:29
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:353
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::M68kRegisterInfo::intRegClass
const TargetRegisterClass * intRegClass(unsigned Size) const
Definition: M68kRegisterInfo.cpp:265
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::M68kRegisterInfo::M68kRegisterInfo
M68kRegisterInfo(const M68kSubtarget &Subtarget)
Definition: M68kRegisterInfo.cpp:44
llvm::M68kRegisterInfo::getSpillRegisterOrder
int getSpillRegisterOrder(unsigned Reg) const
Return spill order index of a register, if there is none then trap.
Definition: M68kRegisterInfo.cpp:115
ErrorHandling.h
llvm::MachineRegisterInfo::canReserveReg
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
Definition: MachineRegisterInfo.h:897
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
CantUseSP
static bool CantUseSP(const MachineFrameInfo &MFI)
Definition: M68kRegisterInfo.cpp:222
llvm::M68kRegisterInfo::trackLivenessAfterRegAlloc
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
Definition: M68kRegisterInfo.cpp:217
llvm::M68kSubtarget::isRegisterReservedByUser
bool isRegisterReservedByUser(Register R) const
Definition: M68kSubtarget.h:105
llvm::M68kRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: M68kRegisterInfo.cpp:260
MachineRegisterInfo.h
llvm::M68kRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Definition: M68kRegisterInfo.cpp:59
M68k.h
llvm::M68kRegisterInfo::getMatchingMegaReg
unsigned getMatchingMegaReg(unsigned Reg, const TargetRegisterClass *RC) const
Return a mega-register of the specified register Reg so its sub-register of index SubIdx is Reg,...
Definition: M68kRegisterInfo.cpp:75
CommandLine.h
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:93
llvm::TargetRegisterInfo::canRealignStack
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Definition: TargetRegisterInfo.cpp:478
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::TargetFrameLowering::getOffsetOfLocalArea
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Definition: TargetFrameLowering.h:140
llvm::M68kRegisterInfo::getMaximalPhysRegClass
const TargetRegisterClass * getMaximalPhysRegClass(unsigned reg, MVT VT) const
Returns the Register Class of a physical register of the given type, picking the biggest register cla...
Definition: M68kRegisterInfo.cpp:84
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:156
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::M68kRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Definition: M68kRegisterInfo.cpp:212
llvm::TargetFrameLowering::hasFP
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
llvm::M68kRegisterInfo::canRealignStack
bool canRealignStack(const MachineFunction &MF) const override
True if the stack can be realigned for the target.
Definition: M68kRegisterInfo.cpp:241
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::M68kRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
FrameIndex represent objects inside a abstract stack.
Definition: M68kRegisterInfo.cpp:164
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:494
llvm::BitVector
Definition: BitVector.h:74
llvm::M68kFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
Return true if the specified function should have a dedicated frame pointer register.
Definition: M68kFrameLowering.cpp:43
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::M68kSubtarget
Definition: M68kSubtarget.h:45
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::cl::opt< bool >
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:617
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
M68kMCTargetDesc.h
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::M68kFrameLowering::getFrameIndexReference
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
This method should return the base register and offset used to reference a frame index location.
Definition: M68kFrameLowering.cpp:76
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1532
uint32_t
llvm::M68kFrameLowering
Definition: M68kFrameLowering.h:28
llvm::StackOffset::getFixed
static StackOffset getFixed(ScalarTy Fixed)
Definition: TypeSize.h:143
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
EnableBasePointer
static cl::opt< bool > EnableBasePointer("m68k-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
llvm::M68kRegisterInfo::getRegsForTailCall
const TargetRegisterClass * getRegsForTailCall(const MachineFunction &MF) const
Returns a register class with registers that can be used in forming tail calls.
Definition: M68kRegisterInfo.cpp:70
llvm::M68kRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: M68kRegisterInfo.cpp:121
llvm::TargetRegisterClass::getNumRegs
unsigned getNumRegs() const
Return the number of registers in this class.
Definition: TargetRegisterInfo.h:79
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:93
uint16_t
llvm::M68kRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: M68kRegisterInfo.cpp:226
llvm::M68kRegisterInfo::getRegisterOrder
int getRegisterOrder(unsigned Reg, const TargetRegisterClass &TRC) const
Return index of a register within a register class, otherwise return -1.
Definition: M68kRegisterInfo.cpp:105
llvm::TargetRegisterClass::getRegister
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
Definition: TargetRegisterInfo.h:87
Function.h
M68kMachineFunction.h
getRegClass
static int getRegClass(RegisterKind Is, unsigned RegWidth)
Definition: AMDGPUAsmParser.cpp:2185
llvm::M68kRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: M68kRegisterInfo.cpp:64
llvm::MCSubRegIterator
MCSubRegIterator enumerates all sub-registers of Reg.
Definition: MCRegisterInfo.h:594
llvm::TargetRegisterClass::hasSubClass
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Definition: TargetRegisterInfo.h:121
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
M68kSubtarget.h
M68kRegisterInfo.h
llvm::MachineFrameInfo::hasOpaqueSPAdjustment
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
Definition: MachineFrameInfo.h:585
llvm::M68kRegisterInfo::getBaseRegister
unsigned getBaseRegister() const
Definition: M68kRegisterInfo.h:101
llvm::cl::desc
Definition: CommandLine.h:414
raw_ostream.h
llvm::MachineInstrBundleIterator< MachineInstr >
Debug.h
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
M68kGenRegisterInfo