Go to the documentation of this file.
24 #include "llvm/IR/IntrinsicsPowerPC.h"
27 #define DEBUG_TYPE "ppc-gisel"
33 #define GET_GLOBALISEL_PREDICATE_BITSET
34 #include "PPCGenGlobalISel.inc"
35 #undef GET_GLOBALISEL_PREDICATE_BITSET
70 #define GET_GLOBALISEL_PREDICATES_DECL
71 #include "PPCGenGlobalISel.inc"
72 #undef GET_GLOBALISEL_PREDICATES_DECL
74 #define GET_GLOBALISEL_TEMPORARIES_DECL
75 #include "PPCGenGlobalISel.inc"
76 #undef GET_GLOBALISEL_TEMPORARIES_DECL
81 #define GET_GLOBALISEL_IMPL
82 #include "PPCGenGlobalISel.inc"
83 #undef GET_GLOBALISEL_IMPL
88 : STI(STI),
TII(*STI.getInstrInfo()),
TRI(*STI.getRegisterInfo()), RBI(RBI),
99 if (RB->
getID() == PPC::GPRRegBankID) {
101 return &PPC::G8RCRegClass;
103 return &PPC::GPRCRegClass;
105 if (RB->
getID() == PPC::FPRRegBankID) {
107 return &PPC::F4RCRegClass;
109 return &PPC::F8RCRegClass;
111 if (RB->
getID() == PPC::CRRegBankID) {
113 return &PPC::CRBITRCRegClass;
115 return &PPC::CRRCRegClass;
124 Register DstReg =
I.getOperand(0).getReg();
147 const bool IsStore = GenericOpc == TargetOpcode::G_STORE;
149 case PPC::GPRRegBankID:
152 return IsStore ? PPC::STW : PPC::LWZ;
154 return IsStore ? PPC::STD :
PPC::LD;
159 case PPC::FPRRegBankID:
162 return IsStore ? PPC::STFS : PPC::LFS;
164 return IsStore ? PPC::STFD : PPC::LFD;
178 if (!STI.hasDirectMove() || !STI.isPPC64() || !STI.hasFPCVT())
181 const DebugLoc &DbgLoc =
I.getDebugLoc();
182 const Register DstReg =
I.getOperand(0).getReg();
183 const Register SrcReg =
I.getOperand(1).getReg();
191 bool IsSigned =
I.getOpcode() == TargetOpcode::G_SITOFP;
192 unsigned ConvOp = IsSingle ? (IsSigned ? PPC::XSCVSXDSP : PPC::XSCVUXDSP)
193 : (IsSigned ? PPC::XSCVSXDDP : PPC::XSCVUXDDP);
205 if (!STI.hasDirectMove() || !STI.isPPC64() || !STI.hasFPCVT())
208 const DebugLoc &DbgLoc =
I.getDebugLoc();
209 const Register DstReg =
I.getOperand(0).getReg();
210 const Register SrcReg =
I.getOperand(1).getReg();
217 bool IsSigned =
I.getOpcode() == TargetOpcode::G_FPTOSI;
221 unsigned ConvOp = IsSigned ? PPC::XSCVDPSXDS : PPC::XSCVDPUXDS;
234 const Register DstReg =
I.getOperand(0).getReg();
238 const Register SrcReg =
I.getOperand(1).getReg();
271 if ((HiTZ + LoLZ) >= Num)
283 unsigned TZ = countTrailingZeros<uint64_t>(
Imm);
284 unsigned LZ = countLeadingZeros<uint64_t>(
Imm);
285 unsigned TO = countTrailingOnes<uint64_t>(
Imm);
286 unsigned LO = countLeadingOnes<uint64_t>(
Imm);
301 if (TZ > 15 && (LZ > 32 ||
LO > 32))
308 assert(LZ < 64 &&
"Unexpected leading zeros here.");
310 unsigned FO = countLeadingOnes<uint64_t>(
Imm << LZ);
313 if (isInt<32>(
Imm)) {
315 unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;
332 if ((LZ + FO + TZ) > 48) {
359 if ((LZ + TO) > 48) {
363 assert(LZ <= 32 &&
"Unexpected shift value.");
391 if ((LZ + FO + TO) > 48) {
407 if (LZ == 32 && ((Lo32 & 0x8000) == 0)) {
460 if ((LZ + FO + TZ) > 32) {
462 unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;
472 .constrainAllUses(
TII,
TRI, RBI))
485 if ((LZ + TO) > 32) {
489 assert(LZ <= 32 &&
"Unexpected shift value.");
513 if ((LZ + FO + TO) > 32) {
534 uint64_t ImmHi16 = (Lo32 >> 16) & 0xffff;
535 unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;
564 uint64_t ImmHi16 = (RotImm >> 16) & 0xffff;
565 unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;
593 assert(
I.getOpcode() == TargetOpcode::G_CONSTANT &&
"Unexpected G code");
595 Register DstReg =
I.getOperand(0).getReg();
596 int64_t
Imm =
I.getOperand(1).getCImm()->getValue().getZExtValue();
612 std::optional<bool> Res =
640 auto &
MBB = *
I.getParent();
642 auto &
MRI = MF.getRegInfo();
654 unsigned Opcode =
I.getOpcode();
659 case TargetOpcode::G_LOAD:
660 case TargetOpcode::G_STORE: {
670 auto SelectLoadStoreAddressingMode = [&]() ->
MachineInstr * {
672 I.getOpcode(), RBI.getRegBank(LdSt.
getReg(0),
MRI,
TRI)->getID(),
675 if (NewOpc ==
I.getOpcode())
680 I.setDesc(
TII.get(NewOpc));
681 Register AddrReg =
I.getOperand(1).getReg();
682 bool IsKill =
I.getOperand(1).isKill();
683 I.getOperand(1).ChangeToImmediate(0);
684 I.addOperand(*
I.getParent()->getParent(),
685 MachineOperand::CreateReg(AddrReg,
false,
696 case TargetOpcode::G_SITOFP:
697 case TargetOpcode::G_UITOFP:
698 return selectIntToFP(
I,
MBB,
MRI);
699 case TargetOpcode::G_FPTOSI:
700 case TargetOpcode::G_FPTOUI:
701 return selectFPToInt(
I,
MBB,
MRI);
703 case TargetOpcode::G_ZEXT:
704 return selectZExt(
I,
MBB,
MRI);
705 case TargetOpcode::G_CONSTANT:
716 return new PPCInstructionSelector(
TM, Subtarget, RBI);
static StringRef getName(Value *V)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
#define GET_GLOBALISEL_PREDICATES_INIT
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
APInt rotr(unsigned rotateAmt) const
Rotate right by rotateAmt.
Replace within non kernel function use of LDS with pointer
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
Reg
All possible values of the reg field in the ModR/M byte.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
uint64_t getMemSizeInBits() const
Returns the size in bits of the memory access.
constexpr uint32_t Lo_32(uint64_t Value)
Return the low 32 bits of a 64 bit value.
unsigned const TargetRegisterInfo * TRI
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
TargetInstrInfo - Interface to description of machine instruction set.
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in and only one load from a constant double ret double C the select is being which prevents the dag combiner from turning select(load CPI1)
This class implements the register bank concept.
#define GET_GLOBALISEL_TEMPORARIES_INIT
InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)
const HexagonInstrInfo * TII
uint64_t getZExtValue() const
Get zero extended value.
include(LLVM-Build) add_subdirectory(IR) add_subdirectory(FuzzMutate) add_subdirectory(FileCheck) add_subdirectory(InterfaceStub) add_subdirectory(IRPrinter) add_subdirectory(IRReader) add_subdirectory(CodeGen) add_subdirectory(BinaryFormat) add_subdirectory(Bitcode) add_subdirectory(Bitstream) add_subdirectory(DWARFLinker) add_subdirectory(DWARFLinkerParallel) add_subdirectory(Extensions) add_subdirectory(Frontend) add_subdirectory(Transforms) add_subdirectory(Linker) add_subdirectory(Analysis) add_subdirectory(LTO) add_subdirectory(MC) add_subdirectory(MCA) add_subdirectory(ObjCopy) add_subdirectory(Object) add_subdirectory(ObjectYAML) add_subdirectory(Option) add_subdirectory(Remarks) add_subdirectory(Debuginfod) add_subdirectory(DebugInfo) add_subdirectory(DWP) add_subdirectory(ExecutionEngine) add_subdirectory(Target) add_subdirectory(AsmParser) add_subdirectory(LineEditor) add_subdirectory(ProfileData) add_subdirectory(Passes) add_subdirectory(TargetParser) add_subdirectory(TextAPI) add_subdirectory(ToolDrivers) add_subdirectory(XRay) if(LLVM_INCLUDE_TESTS) add_subdirectory(Testing) endif() add_subdirectory(WindowsDriver) add_subdirectory(WindowsManifest) set(LLVMCONFIGLIBRARYDEPENDENCIESINC "$
unsigned getID() const
Get the identifier of this register bank.
Register getPointerReg() const
Get the source register of the pointer value.
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
Holds all the information related to register banks.
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static uint32_t findContiguousZerosAtLeast(uint64_t Imm, unsigned Num)
bool constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Class for arbitrary precision integers.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static SDNode * selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm, unsigned &InstCnt)
Register getReg(unsigned Idx) const
Access the Idx'th operand as a register and return it.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
static const TargetRegisterClass * getRegClass(const MachineInstr &MI, Register Reg)
static SDNode * selectI64Imm(SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm, unsigned *InstCnt=nullptr)
Represents any type of generic load or store.
static unsigned selectLoadStoreOp(unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
Common code between 32-bit and 64-bit PowerPC targets.
@ Kill
The last use of a register.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
const char LLVMTargetMachineRef TM
static uint64_t selectImpl(uint64_t CandidateMask, uint64_t &NextInSequenceMask)