LLVM  16.0.0git
ARMBaseInstrInfo.cpp
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1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMBaseInstrInfo.h"
14 #include "ARMBaseRegisterInfo.h"
15 #include "ARMConstantPoolValue.h"
16 #include "ARMFeatures.h"
17 #include "ARMHazardRecognizer.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
22 #include "MVETailPredUtils.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/ADT/Triple.h"
48 #include "llvm/IR/Attributes.h"
49 #include "llvm/IR/Constants.h"
50 #include "llvm/IR/DebugLoc.h"
51 #include "llvm/IR/Function.h"
52 #include "llvm/IR/GlobalValue.h"
53 #include "llvm/MC/MCAsmInfo.h"
54 #include "llvm/MC/MCInstrDesc.h"
57 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/Compiler.h"
60 #include "llvm/Support/Debug.h"
64 #include <algorithm>
65 #include <cassert>
66 #include <cstdint>
67 #include <iterator>
68 #include <new>
69 #include <utility>
70 #include <vector>
71 
72 using namespace llvm;
73 
74 #define DEBUG_TYPE "arm-instrinfo"
75 
76 #define GET_INSTRINFO_CTOR_DTOR
77 #include "ARMGenInstrInfo.inc"
78 
79 static cl::opt<bool>
80 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
81  cl::desc("Enable ARM 2-addr to 3-addr conv"));
82 
83 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
84 struct ARM_MLxEntry {
85  uint16_t MLxOpc; // MLA / MLS opcode
86  uint16_t MulOpc; // Expanded multiplication opcode
87  uint16_t AddSubOpc; // Expanded add / sub opcode
88  bool NegAcc; // True if the acc is negated before the add / sub.
89  bool HasLane; // True if instruction has an extra "lane" operand.
90 };
91 
92 static const ARM_MLxEntry ARM_MLxTable[] = {
93  // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
94  // fp scalar ops
95  { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
96  { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
97  { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
98  { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
99  { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
100  { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
101  { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
102  { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
103 
104  // fp SIMD ops
105  { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
106  { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
107  { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
108  { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
109  { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
110  { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
111  { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
112  { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
113 };
114 
116  : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
117  Subtarget(STI) {
118  for (unsigned i = 0, e = std::size(ARM_MLxTable); i != e; ++i) {
119  if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
120  llvm_unreachable("Duplicated entries?");
121  MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
122  MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
123  }
124 }
125 
126 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
127 // currently defaults to no prepass hazard recognizer.
130  const ScheduleDAG *DAG) const {
131  if (usePreRAHazardRecognizer()) {
132  const InstrItineraryData *II =
133  static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
134  return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
135  }
137 }
138 
139 // Called during:
140 // - pre-RA scheduling
141 // - post-RA scheduling when FeatureUseMISched is set
143  const InstrItineraryData *II, const ScheduleDAGMI *DAG) const {
145 
146  // We would like to restrict this hazard recognizer to only
147  // post-RA scheduling; we can tell that we're post-RA because we don't
148  // track VRegLiveness.
149  // Cortex-M7: TRM indicates that there is a single ITCM bank and two DTCM
150  // banks banked on bit 2. Assume that TCMs are in use.
151  if (Subtarget.isCortexM7() && !DAG->hasVRegLiveness())
152  MHR->AddHazardRecognizer(
153  std::make_unique<ARMBankConflictHazardRecognizer>(DAG, 0x4, true));
154 
155  // Not inserting ARMHazardRecognizerFPMLx because that would change
156  // legacy behavior
157 
159  MHR->AddHazardRecognizer(std::unique_ptr<ScheduleHazardRecognizer>(BHR));
160  return MHR;
161 }
162 
163 // Called during post-RA scheduling when FeatureUseMISched is not set
166  const ScheduleDAG *DAG) const {
168 
169  if (Subtarget.isThumb2() || Subtarget.hasVFP2Base())
170  MHR->AddHazardRecognizer(std::make_unique<ARMHazardRecognizerFPMLx>());
171 
173  if (BHR)
174  MHR->AddHazardRecognizer(std::unique_ptr<ScheduleHazardRecognizer>(BHR));
175  return MHR;
176 }
177 
178 MachineInstr *
180  LiveIntervals *LIS) const {
181  // FIXME: Thumb2 support.
182 
183  if (!EnableARM3Addr)
184  return nullptr;
185 
186  MachineFunction &MF = *MI.getParent()->getParent();
187  uint64_t TSFlags = MI.getDesc().TSFlags;
188  bool isPre = false;
190  default: return nullptr;
191  case ARMII::IndexModePre:
192  isPre = true;
193  break;
195  break;
196  }
197 
198  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
199  // operation.
200  unsigned MemOpc = getUnindexedOpcode(MI.getOpcode());
201  if (MemOpc == 0)
202  return nullptr;
203 
204  MachineInstr *UpdateMI = nullptr;
205  MachineInstr *MemMI = nullptr;
206  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
207  const MCInstrDesc &MCID = MI.getDesc();
208  unsigned NumOps = MCID.getNumOperands();
209  bool isLoad = !MI.mayStore();
210  const MachineOperand &WB = isLoad ? MI.getOperand(1) : MI.getOperand(0);
211  const MachineOperand &Base = MI.getOperand(2);
212  const MachineOperand &Offset = MI.getOperand(NumOps - 3);
213  Register WBReg = WB.getReg();
214  Register BaseReg = Base.getReg();
215  Register OffReg = Offset.getReg();
216  unsigned OffImm = MI.getOperand(NumOps - 2).getImm();
217  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm();
218  switch (AddrMode) {
219  default: llvm_unreachable("Unknown indexed op!");
220  case ARMII::AddrMode2: {
221  bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
222  unsigned Amt = ARM_AM::getAM2Offset(OffImm);
223  if (OffReg == 0) {
224  if (ARM_AM::getSOImmVal(Amt) == -1)
225  // Can't encode it in a so_imm operand. This transformation will
226  // add more than 1 instruction. Abandon!
227  return nullptr;
228  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
229  get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
230  .addReg(BaseReg)
231  .addImm(Amt)
232  .add(predOps(Pred))
233  .add(condCodeOp());
234  } else if (Amt != 0) {
236  unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
237  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
238  get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
239  .addReg(BaseReg)
240  .addReg(OffReg)
241  .addReg(0)
242  .addImm(SOOpc)
243  .add(predOps(Pred))
244  .add(condCodeOp());
245  } else
246  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
247  get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
248  .addReg(BaseReg)
249  .addReg(OffReg)
250  .add(predOps(Pred))
251  .add(condCodeOp());
252  break;
253  }
254  case ARMII::AddrMode3 : {
255  bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
256  unsigned Amt = ARM_AM::getAM3Offset(OffImm);
257  if (OffReg == 0)
258  // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
259  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
260  get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
261  .addReg(BaseReg)
262  .addImm(Amt)
263  .add(predOps(Pred))
264  .add(condCodeOp());
265  else
266  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
267  get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
268  .addReg(BaseReg)
269  .addReg(OffReg)
270  .add(predOps(Pred))
271  .add(condCodeOp());
272  break;
273  }
274  }
275 
276  std::vector<MachineInstr*> NewMIs;
277  if (isPre) {
278  if (isLoad)
279  MemMI =
280  BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
281  .addReg(WBReg)
282  .addImm(0)
283  .addImm(Pred);
284  else
285  MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
286  .addReg(MI.getOperand(1).getReg())
287  .addReg(WBReg)
288  .addReg(0)
289  .addImm(0)
290  .addImm(Pred);
291  NewMIs.push_back(MemMI);
292  NewMIs.push_back(UpdateMI);
293  } else {
294  if (isLoad)
295  MemMI =
296  BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
297  .addReg(BaseReg)
298  .addImm(0)
299  .addImm(Pred);
300  else
301  MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
302  .addReg(MI.getOperand(1).getReg())
303  .addReg(BaseReg)
304  .addReg(0)
305  .addImm(0)
306  .addImm(Pred);
307  if (WB.isDead())
308  UpdateMI->getOperand(0).setIsDead();
309  NewMIs.push_back(UpdateMI);
310  NewMIs.push_back(MemMI);
311  }
312 
313  // Transfer LiveVariables states, kill / dead info.
314  if (LV) {
315  for (const MachineOperand &MO : MI.operands()) {
316  if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
317  Register Reg = MO.getReg();
318 
320  if (MO.isDef()) {
321  MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
322  if (MO.isDead())
323  LV->addVirtualRegisterDead(Reg, *NewMI);
324  }
325  if (MO.isUse() && MO.isKill()) {
326  for (unsigned j = 0; j < 2; ++j) {
327  // Look at the two new MI's in reverse order.
328  MachineInstr *NewMI = NewMIs[j];
329  if (!NewMI->readsRegister(Reg))
330  continue;
331  LV->addVirtualRegisterKilled(Reg, *NewMI);
332  if (VI.removeKill(MI))
333  VI.Kills.push_back(NewMI);
334  break;
335  }
336  }
337  }
338  }
339  }
340 
341  MachineBasicBlock &MBB = *MI.getParent();
342  MBB.insert(MI, NewMIs[1]);
343  MBB.insert(MI, NewMIs[0]);
344  return NewMIs[0];
345 }
346 
347 // Branch analysis.
348 // Cond vector output format:
349 // 0 elements indicates an unconditional branch
350 // 2 elements indicates a conditional branch; the elements are
351 // the condition to check and the CPSR.
352 // 3 elements indicates a hardware loop end; the elements
353 // are the opcode, the operand value to test, and a dummy
354 // operand used to pad out to 3 operands.
357  MachineBasicBlock *&FBB,
359  bool AllowModify) const {
360  TBB = nullptr;
361  FBB = nullptr;
362 
364  if (I == MBB.instr_begin())
365  return false; // Empty blocks are easy.
366  --I;
367 
368  // Walk backwards from the end of the basic block until the branch is
369  // analyzed or we give up.
370  while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
371  // Flag to be raised on unanalyzeable instructions. This is useful in cases
372  // where we want to clean up on the end of the basic block before we bail
373  // out.
374  bool CantAnalyze = false;
375 
376  // Skip over DEBUG values, predicated nonterminators and speculation
377  // barrier terminators.
378  while (I->isDebugInstr() || !I->isTerminator() ||
379  isSpeculationBarrierEndBBOpcode(I->getOpcode()) ||
380  I->getOpcode() == ARM::t2DoLoopStartTP){
381  if (I == MBB.instr_begin())
382  return false;
383  --I;
384  }
385 
386  if (isIndirectBranchOpcode(I->getOpcode()) ||
387  isJumpTableBranchOpcode(I->getOpcode())) {
388  // Indirect branches and jump tables can't be analyzed, but we still want
389  // to clean up any instructions at the tail of the basic block.
390  CantAnalyze = true;
391  } else if (isUncondBranchOpcode(I->getOpcode())) {
392  TBB = I->getOperand(0).getMBB();
393  } else if (isCondBranchOpcode(I->getOpcode())) {
394  // Bail out if we encounter multiple conditional branches.
395  if (!Cond.empty())
396  return true;
397 
398  assert(!FBB && "FBB should have been null.");
399  FBB = TBB;
400  TBB = I->getOperand(0).getMBB();
401  Cond.push_back(I->getOperand(1));
402  Cond.push_back(I->getOperand(2));
403  } else if (I->isReturn()) {
404  // Returns can't be analyzed, but we should run cleanup.
405  CantAnalyze = true;
406  } else if (I->getOpcode() == ARM::t2LoopEnd &&
407  MBB.getParent()
410  if (!Cond.empty())
411  return true;
412  FBB = TBB;
413  TBB = I->getOperand(1).getMBB();
414  Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
415  Cond.push_back(I->getOperand(0));
416  Cond.push_back(MachineOperand::CreateImm(0));
417  } else {
418  // We encountered other unrecognized terminator. Bail out immediately.
419  return true;
420  }
421 
422  // Cleanup code - to be run for unpredicated unconditional branches and
423  // returns.
424  if (!isPredicated(*I) &&
425  (isUncondBranchOpcode(I->getOpcode()) ||
426  isIndirectBranchOpcode(I->getOpcode()) ||
427  isJumpTableBranchOpcode(I->getOpcode()) ||
428  I->isReturn())) {
429  // Forget any previous condition branch information - it no longer applies.
430  Cond.clear();
431  FBB = nullptr;
432 
433  // If we can modify the function, delete everything below this
434  // unconditional branch.
435  if (AllowModify) {
436  MachineBasicBlock::iterator DI = std::next(I);
437  while (DI != MBB.instr_end()) {
438  MachineInstr &InstToDelete = *DI;
439  ++DI;
440  // Speculation barriers must not be deleted.
441  if (isSpeculationBarrierEndBBOpcode(InstToDelete.getOpcode()))
442  continue;
443  InstToDelete.eraseFromParent();
444  }
445  }
446  }
447 
448  if (CantAnalyze) {
449  // We may not be able to analyze the block, but we could still have
450  // an unconditional branch as the last instruction in the block, which
451  // just branches to layout successor. If this is the case, then just
452  // remove it if we're allowed to make modifications.
453  if (AllowModify && !isPredicated(MBB.back()) &&
456  removeBranch(MBB);
457  return true;
458  }
459 
460  if (I == MBB.instr_begin())
461  return false;
462 
463  --I;
464  }
465 
466  // We made it past the terminators without bailing out - we must have
467  // analyzed this branch successfully.
468  return false;
469 }
470 
472  int *BytesRemoved) const {
473  assert(!BytesRemoved && "code size not handled");
474 
476  if (I == MBB.end())
477  return 0;
478 
479  if (!isUncondBranchOpcode(I->getOpcode()) &&
480  !isCondBranchOpcode(I->getOpcode()) && I->getOpcode() != ARM::t2LoopEnd)
481  return 0;
482 
483  // Remove the branch.
484  I->eraseFromParent();
485 
486  I = MBB.end();
487 
488  if (I == MBB.begin()) return 1;
489  --I;
490  if (!isCondBranchOpcode(I->getOpcode()) && I->getOpcode() != ARM::t2LoopEnd)
491  return 1;
492 
493  // Remove the branch.
494  I->eraseFromParent();
495  return 2;
496 }
497 
500  MachineBasicBlock *FBB,
502  const DebugLoc &DL,
503  int *BytesAdded) const {
504  assert(!BytesAdded && "code size not handled");
506  int BOpc = !AFI->isThumbFunction()
507  ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
508  int BccOpc = !AFI->isThumbFunction()
509  ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
510  bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
511 
512  // Shouldn't be a fall through.
513  assert(TBB && "insertBranch must not be told to insert a fallthrough");
514  assert((Cond.size() == 2 || Cond.size() == 0 || Cond.size() == 3) &&
515  "ARM branch conditions have two or three components!");
516 
517  // For conditional branches, we use addOperand to preserve CPSR flags.
518 
519  if (!FBB) {
520  if (Cond.empty()) { // Unconditional branch?
521  if (isThumb)
522  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL));
523  else
524  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
525  } else if (Cond.size() == 2) {
526  BuildMI(&MBB, DL, get(BccOpc))
527  .addMBB(TBB)
528  .addImm(Cond[0].getImm())
529  .add(Cond[1]);
530  } else
531  BuildMI(&MBB, DL, get(Cond[0].getImm())).add(Cond[1]).addMBB(TBB);
532  return 1;
533  }
534 
535  // Two-way conditional branch.
536  if (Cond.size() == 2)
537  BuildMI(&MBB, DL, get(BccOpc))
538  .addMBB(TBB)
539  .addImm(Cond[0].getImm())
540  .add(Cond[1]);
541  else if (Cond.size() == 3)
542  BuildMI(&MBB, DL, get(Cond[0].getImm())).add(Cond[1]).addMBB(TBB);
543  if (isThumb)
544  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL));
545  else
546  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
547  return 2;
548 }
549 
552  if (Cond.size() == 2) {
553  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
554  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
555  return false;
556  }
557  return true;
558 }
559 
561  if (MI.isBundle()) {
563  MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
564  while (++I != E && I->isInsideBundle()) {
565  int PIdx = I->findFirstPredOperandIdx();
566  if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
567  return true;
568  }
569  return false;
570  }
571 
572  int PIdx = MI.findFirstPredOperandIdx();
573  return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
574 }
575 
577  const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
578  const TargetRegisterInfo *TRI) const {
579 
580  // First, let's see if there is a generic comment for this operand
581  std::string GenericComment =
583  if (!GenericComment.empty())
584  return GenericComment;
585 
586  // If not, check if we have an immediate operand.
587  if (!Op.isImm())
588  return std::string();
589 
590  // And print its corresponding condition code if the immediate is a
591  // predicate.
592  int FirstPredOp = MI.findFirstPredOperandIdx();
593  if (FirstPredOp != (int) OpIdx)
594  return std::string();
595 
596  std::string CC = "CC::";
598  return CC;
599 }
600 
603  unsigned Opc = MI.getOpcode();
604  if (isUncondBranchOpcode(Opc)) {
605  MI.setDesc(get(getMatchingCondBranchOpcode(Opc)));
606  MachineInstrBuilder(*MI.getParent()->getParent(), MI)
607  .addImm(Pred[0].getImm())
608  .addReg(Pred[1].getReg());
609  return true;
610  }
611 
612  int PIdx = MI.findFirstPredOperandIdx();
613  if (PIdx != -1) {
614  MachineOperand &PMO = MI.getOperand(PIdx);
615  PMO.setImm(Pred[0].getImm());
616  MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
617 
618  // Thumb 1 arithmetic instructions do not set CPSR when executed inside an
619  // IT block. This affects how they are printed.
620  const MCInstrDesc &MCID = MI.getDesc();
622  assert(MCID.OpInfo[1].isOptionalDef() && "CPSR def isn't expected operand");
623  assert((MI.getOperand(1).isDead() ||
624  MI.getOperand(1).getReg() != ARM::CPSR) &&
625  "if conversion tried to stop defining used CPSR");
626  MI.getOperand(1).setReg(ARM::NoRegister);
627  }
628 
629  return true;
630  }
631  return false;
632 }
633 
635  ArrayRef<MachineOperand> Pred2) const {
636  if (Pred1.size() > 2 || Pred2.size() > 2)
637  return false;
638 
639  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
640  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
641  if (CC1 == CC2)
642  return true;
643 
644  switch (CC1) {
645  default:
646  return false;
647  case ARMCC::AL:
648  return true;
649  case ARMCC::HS:
650  return CC2 == ARMCC::HI;
651  case ARMCC::LS:
652  return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
653  case ARMCC::GE:
654  return CC2 == ARMCC::GT;
655  case ARMCC::LE:
656  return CC2 == ARMCC::LT;
657  }
658 }
659 
661  std::vector<MachineOperand> &Pred,
662  bool SkipDead) const {
663  bool Found = false;
664  for (const MachineOperand &MO : MI.operands()) {
665  bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR);
666  bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR;
667  if (ClobbersCPSR || IsCPSR) {
668 
669  // Filter out T1 instructions that have a dead CPSR,
670  // allowing IT blocks to be generated containing T1 instructions
671  const MCInstrDesc &MCID = MI.getDesc();
672  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting && MO.isDead() &&
673  SkipDead)
674  continue;
675 
676  Pred.push_back(MO);
677  Found = true;
678  }
679  }
680 
681  return Found;
682 }
683 
685  for (const auto &MO : MI.operands())
686  if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
687  return true;
688  return false;
689 }
690 
691 static bool isEligibleForITBlock(const MachineInstr *MI) {
692  switch (MI->getOpcode()) {
693  default: return true;
694  case ARM::tADC: // ADC (register) T1
695  case ARM::tADDi3: // ADD (immediate) T1
696  case ARM::tADDi8: // ADD (immediate) T2
697  case ARM::tADDrr: // ADD (register) T1
698  case ARM::tAND: // AND (register) T1
699  case ARM::tASRri: // ASR (immediate) T1
700  case ARM::tASRrr: // ASR (register) T1
701  case ARM::tBIC: // BIC (register) T1
702  case ARM::tEOR: // EOR (register) T1
703  case ARM::tLSLri: // LSL (immediate) T1
704  case ARM::tLSLrr: // LSL (register) T1
705  case ARM::tLSRri: // LSR (immediate) T1
706  case ARM::tLSRrr: // LSR (register) T1
707  case ARM::tMUL: // MUL T1
708  case ARM::tMVN: // MVN (register) T1
709  case ARM::tORR: // ORR (register) T1
710  case ARM::tROR: // ROR (register) T1
711  case ARM::tRSB: // RSB (immediate) T1
712  case ARM::tSBC: // SBC (register) T1
713  case ARM::tSUBi3: // SUB (immediate) T1
714  case ARM::tSUBi8: // SUB (immediate) T2
715  case ARM::tSUBrr: // SUB (register) T1
717  }
718 }
719 
720 /// isPredicable - Return true if the specified instruction can be predicated.
721 /// By default, this returns true for every instruction with a
722 /// PredicateOperand.
724  if (!MI.isPredicable())
725  return false;
726 
727  if (MI.isBundle())
728  return false;
729 
730  if (!isEligibleForITBlock(&MI))
731  return false;
732 
733  const MachineFunction *MF = MI.getParent()->getParent();
734  const ARMFunctionInfo *AFI =
735  MF->getInfo<ARMFunctionInfo>();
736 
737  // Neon instructions in Thumb2 IT blocks are deprecated, see ARMARM.
738  // In their ARM encoding, they can't be encoded in a conditional form.
739  if ((MI.getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
740  return false;
741 
742  // Make indirect control flow changes unpredicable when SLS mitigation is
743  // enabled.
744  const ARMSubtarget &ST = MF->getSubtarget<ARMSubtarget>();
745  if (ST.hardenSlsRetBr() && isIndirectControlFlowNotComingBack(MI))
746  return false;
747  if (ST.hardenSlsBlr() && isIndirectCall(MI))
748  return false;
749 
750  if (AFI->isThumb2Function()) {
751  if (getSubtarget().restrictIT())
752  return isV8EligibleForIT(&MI);
753  }
754 
755  return true;
756 }
757 
758 namespace llvm {
759 
760 template <> bool IsCPSRDead<MachineInstr>(const MachineInstr *MI) {
761  for (const MachineOperand &MO : MI->operands()) {
762  if (!MO.isReg() || MO.isUndef() || MO.isUse())
763  continue;
764  if (MO.getReg() != ARM::CPSR)
765  continue;
766  if (!MO.isDead())
767  return false;
768  }
769  // all definitions of CPSR are dead
770  return true;
771 }
772 
773 } // end namespace llvm
774 
775 /// GetInstSize - Return the size of the specified MachineInstr.
776 ///
778  const MachineBasicBlock &MBB = *MI.getParent();
779  const MachineFunction *MF = MBB.getParent();
780  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
781 
782  const MCInstrDesc &MCID = MI.getDesc();
783 
784  switch (MI.getOpcode()) {
785  default:
786  // Return the size specified in .td file. If there's none, return 0, as we
787  // can't define a default size (Thumb1 instructions are 2 bytes, Thumb2
788  // instructions are 2-4 bytes, and ARM instructions are 4 bytes), in
789  // contrast to AArch64 instructions which have a default size of 4 bytes for
790  // example.
791  return MCID.getSize();
792  case TargetOpcode::BUNDLE:
793  return getInstBundleLength(MI);
794  case ARM::CONSTPOOL_ENTRY:
795  case ARM::JUMPTABLE_INSTS:
796  case ARM::JUMPTABLE_ADDRS:
797  case ARM::JUMPTABLE_TBB:
798  case ARM::JUMPTABLE_TBH:
799  // If this machine instr is a constant pool entry, its size is recorded as
800  // operand #2.
801  return MI.getOperand(2).getImm();
802  case ARM::SPACE:
803  return MI.getOperand(1).getImm();
804  case ARM::INLINEASM:
805  case ARM::INLINEASM_BR: {
806  // If this machine instr is an inline asm, measure it.
807  unsigned Size = getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
808  if (!MF->getInfo<ARMFunctionInfo>()->isThumbFunction())
809  Size = alignTo(Size, 4);
810  return Size;
811  }
812  }
813 }
814 
815 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
816  unsigned Size = 0;
818  MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
819  while (++I != E && I->isInsideBundle()) {
820  assert(!I->isBundle() && "No nested bundle!");
821  Size += getInstSizeInBytes(*I);
822  }
823  return Size;
824 }
825 
828  unsigned DestReg, bool KillSrc,
829  const ARMSubtarget &Subtarget) const {
830  unsigned Opc = Subtarget.isThumb()
831  ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
832  : ARM::MRS;
833 
834  MachineInstrBuilder MIB =
835  BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
836 
837  // There is only 1 A/R class MRS instruction, and it always refers to
838  // APSR. However, there are lots of other possibilities on M-class cores.
839  if (Subtarget.isMClass())
840  MIB.addImm(0x800);
841 
842  MIB.add(predOps(ARMCC::AL))
843  .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
844 }
845 
848  unsigned SrcReg, bool KillSrc,
849  const ARMSubtarget &Subtarget) const {
850  unsigned Opc = Subtarget.isThumb()
851  ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
852  : ARM::MSR;
853 
854  MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
855 
856  if (Subtarget.isMClass())
857  MIB.addImm(0x800);
858  else
859  MIB.addImm(8);
860 
861  MIB.addReg(SrcReg, getKillRegState(KillSrc))
864 }
865 
867  MIB.addImm(ARMVCC::None);
868  MIB.addReg(0);
869  MIB.addReg(0); // tp_reg
870 }
871 
873  Register DestReg) {
875  MIB.addReg(DestReg, RegState::Undef);
876 }
877 
879  MIB.addImm(Cond);
880  MIB.addReg(ARM::VPR, RegState::Implicit);
881  MIB.addReg(0); // tp_reg
882 }
883 
885  unsigned Cond, unsigned Inactive) {
887  MIB.addReg(Inactive);
888 }
889 
892  const DebugLoc &DL, MCRegister DestReg,
893  MCRegister SrcReg, bool KillSrc) const {
894  bool GPRDest = ARM::GPRRegClass.contains(DestReg);
895  bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
896 
897  if (GPRDest && GPRSrc) {
898  BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
899  .addReg(SrcReg, getKillRegState(KillSrc))
901  .add(condCodeOp());
902  return;
903  }
904 
905  bool SPRDest = ARM::SPRRegClass.contains(DestReg);
906  bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
907 
908  unsigned Opc = 0;
909  if (SPRDest && SPRSrc)
910  Opc = ARM::VMOVS;
911  else if (GPRDest && SPRSrc)
912  Opc = ARM::VMOVRS;
913  else if (SPRDest && GPRSrc)
914  Opc = ARM::VMOVSR;
915  else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.hasFP64())
916  Opc = ARM::VMOVD;
917  else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
918  Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MQPRCopy;
919 
920  if (Opc) {
921  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
922  MIB.addReg(SrcReg, getKillRegState(KillSrc));
923  if (Opc == ARM::VORRq || Opc == ARM::MVE_VORR)
924  MIB.addReg(SrcReg, getKillRegState(KillSrc));
925  if (Opc == ARM::MVE_VORR)
926  addUnpredicatedMveVpredROp(MIB, DestReg);
927  else if (Opc != ARM::MQPRCopy)
928  MIB.add(predOps(ARMCC::AL));
929  return;
930  }
931 
932  // Handle register classes that require multiple instructions.
933  unsigned BeginIdx = 0;
934  unsigned SubRegs = 0;
935  int Spacing = 1;
936 
937  // Use VORRq when possible.
938  if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
939  Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR;
940  BeginIdx = ARM::qsub_0;
941  SubRegs = 2;
942  } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
943  Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR;
944  BeginIdx = ARM::qsub_0;
945  SubRegs = 4;
946  // Fall back to VMOVD.
947  } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
948  Opc = ARM::VMOVD;
949  BeginIdx = ARM::dsub_0;
950  SubRegs = 2;
951  } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
952  Opc = ARM::VMOVD;
953  BeginIdx = ARM::dsub_0;
954  SubRegs = 3;
955  } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
956  Opc = ARM::VMOVD;
957  BeginIdx = ARM::dsub_0;
958  SubRegs = 4;
959  } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
960  Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
961  BeginIdx = ARM::gsub_0;
962  SubRegs = 2;
963  } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
964  Opc = ARM::VMOVD;
965  BeginIdx = ARM::dsub_0;
966  SubRegs = 2;
967  Spacing = 2;
968  } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
969  Opc = ARM::VMOVD;
970  BeginIdx = ARM::dsub_0;
971  SubRegs = 3;
972  Spacing = 2;
973  } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
974  Opc = ARM::VMOVD;
975  BeginIdx = ARM::dsub_0;
976  SubRegs = 4;
977  Spacing = 2;
978  } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) &&
979  !Subtarget.hasFP64()) {
980  Opc = ARM::VMOVS;
981  BeginIdx = ARM::ssub_0;
982  SubRegs = 2;
983  } else if (SrcReg == ARM::CPSR) {
984  copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
985  return;
986  } else if (DestReg == ARM::CPSR) {
987  copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
988  return;
989  } else if (DestReg == ARM::VPR) {
990  assert(ARM::GPRRegClass.contains(SrcReg));
991  BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg)
992  .addReg(SrcReg, getKillRegState(KillSrc))
993  .add(predOps(ARMCC::AL));
994  return;
995  } else if (SrcReg == ARM::VPR) {
996  assert(ARM::GPRRegClass.contains(DestReg));
997  BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg)
998  .addReg(SrcReg, getKillRegState(KillSrc))
999  .add(predOps(ARMCC::AL));
1000  return;
1001  } else if (DestReg == ARM::FPSCR_NZCV) {
1002  assert(ARM::GPRRegClass.contains(SrcReg));
1003  BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg)
1004  .addReg(SrcReg, getKillRegState(KillSrc))
1005  .add(predOps(ARMCC::AL));
1006  return;
1007  } else if (SrcReg == ARM::FPSCR_NZCV) {
1008  assert(ARM::GPRRegClass.contains(DestReg));
1009  BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg)
1010  .addReg(SrcReg, getKillRegState(KillSrc))
1011  .add(predOps(ARMCC::AL));
1012  return;
1013  }
1014 
1015  assert(Opc && "Impossible reg-to-reg copy");
1016 
1018  MachineInstrBuilder Mov;
1019 
1020  // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
1021  if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
1022  BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
1023  Spacing = -Spacing;
1024  }
1025 #ifndef NDEBUG
1026  SmallSet<unsigned, 4> DstRegs;
1027 #endif
1028  for (unsigned i = 0; i != SubRegs; ++i) {
1029  Register Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
1030  Register Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
1031  assert(Dst && Src && "Bad sub-register");
1032 #ifndef NDEBUG
1033  assert(!DstRegs.count(Src) && "destructive vector copy");
1034  DstRegs.insert(Dst);
1035 #endif
1036  Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
1037  // VORR (NEON or MVE) takes two source operands.
1038  if (Opc == ARM::VORRq || Opc == ARM::MVE_VORR) {
1039  Mov.addReg(Src);
1040  }
1041  // MVE VORR takes predicate operands in place of an ordinary condition.
1042  if (Opc == ARM::MVE_VORR)
1043  addUnpredicatedMveVpredROp(Mov, Dst);
1044  else
1045  Mov = Mov.add(predOps(ARMCC::AL));
1046  // MOVr can set CC.
1047  if (Opc == ARM::MOVr)
1048  Mov = Mov.add(condCodeOp());
1049  }
1050  // Add implicit super-register defs and kills to the last instruction.
1051  Mov->addRegisterDefined(DestReg, TRI);
1052  if (KillSrc)
1053  Mov->addRegisterKilled(SrcReg, TRI);
1054 }
1055 
1058  // VMOVRRD is also a copy instruction but it requires
1059  // special way of handling. It is more complex copy version
1060  // and since that we are not considering it. For recognition
1061  // of such instruction isExtractSubregLike MI interface fuction
1062  // could be used.
1063  // VORRq is considered as a move only if two inputs are
1064  // the same register.
1065  if (!MI.isMoveReg() ||
1066  (MI.getOpcode() == ARM::VORRq &&
1067  MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
1068  return None;
1069  return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
1070 }
1071 
1074  Register Reg) const {
1075  if (auto DstSrcPair = isCopyInstrImpl(MI)) {
1076  Register DstReg = DstSrcPair->Destination->getReg();
1077 
1078  // TODO: We don't handle cases where the forwarding reg is narrower/wider
1079  // than the copy registers. Consider for example:
1080  //
1081  // s16 = VMOVS s0
1082  // s17 = VMOVS s1
1083  // call @callee(d0)
1084  //
1085  // We'd like to describe the call site value of d0 as d8, but this requires
1086  // gathering and merging the descriptions for the two VMOVS instructions.
1087  //
1088  // We also don't handle the reverse situation, where the forwarding reg is
1089  // narrower than the copy destination:
1090  //
1091  // d8 = VMOVD d0
1092  // call @callee(s1)
1093  //
1094  // We need to produce a fragment description (the call site value of s1 is
1095  // /not/ just d8).
1096  if (DstReg != Reg)
1097  return None;
1098  }
1100 }
1101 
1102 const MachineInstrBuilder &
1104  unsigned SubIdx, unsigned State,
1105  const TargetRegisterInfo *TRI) const {
1106  if (!SubIdx)
1107  return MIB.addReg(Reg, State);
1108 
1110  return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1111  return MIB.addReg(Reg, State, SubIdx);
1112 }
1113 
1114 void ARMBaseInstrInfo::
1116  Register SrcReg, bool isKill, int FI,
1117  const TargetRegisterClass *RC,
1118  const TargetRegisterInfo *TRI) const {
1119  MachineFunction &MF = *MBB.getParent();
1120  MachineFrameInfo &MFI = MF.getFrameInfo();
1121  Align Alignment = MFI.getObjectAlign(FI);
1122 
1125  MFI.getObjectSize(FI), Alignment);
1126 
1127  switch (TRI->getSpillSize(*RC)) {
1128  case 2:
1129  if (ARM::HPRRegClass.hasSubClassEq(RC)) {
1130  BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH))
1131  .addReg(SrcReg, getKillRegState(isKill))
1132  .addFrameIndex(FI)
1133  .addImm(0)
1134  .addMemOperand(MMO)
1135  .add(predOps(ARMCC::AL));
1136  } else
1137  llvm_unreachable("Unknown reg class!");
1138  break;
1139  case 4:
1140  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1141  BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12))
1142  .addReg(SrcReg, getKillRegState(isKill))
1143  .addFrameIndex(FI)
1144  .addImm(0)
1145  .addMemOperand(MMO)
1146  .add(predOps(ARMCC::AL));
1147  } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1148  BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS))
1149  .addReg(SrcReg, getKillRegState(isKill))
1150  .addFrameIndex(FI)
1151  .addImm(0)
1152  .addMemOperand(MMO)
1153  .add(predOps(ARMCC::AL));
1154  } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {
1155  BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_P0_off))
1156  .addReg(SrcReg, getKillRegState(isKill))
1157  .addFrameIndex(FI)
1158  .addImm(0)
1159  .addMemOperand(MMO)
1160  .add(predOps(ARMCC::AL));
1161  } else
1162  llvm_unreachable("Unknown reg class!");
1163  break;
1164  case 8:
1165  if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1166  BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD))
1167  .addReg(SrcReg, getKillRegState(isKill))
1168  .addFrameIndex(FI)
1169  .addImm(0)
1170  .addMemOperand(MMO)
1171  .add(predOps(ARMCC::AL));
1172  } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1173  if (Subtarget.hasV5TEOps()) {
1175  AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1176  AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1177  MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1178  .add(predOps(ARMCC::AL));
1179  } else {
1180  // Fallback to STM instruction, which has existed since the dawn of
1181  // time.
1182  MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
1183  .addFrameIndex(FI)
1184  .addMemOperand(MMO)
1185  .add(predOps(ARMCC::AL));
1186  AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1187  AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1188  }
1189  } else
1190  llvm_unreachable("Unknown reg class!");
1191  break;
1192  case 16:
1193  if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {
1194  // Use aligned spills if the stack can be realigned.
1195  if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF)) {
1196  BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64))
1197  .addFrameIndex(FI)
1198  .addImm(16)
1199  .addReg(SrcReg, getKillRegState(isKill))
1200  .addMemOperand(MMO)
1201  .add(predOps(ARMCC::AL));
1202  } else {
1203  BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA))
1204  .addReg(SrcReg, getKillRegState(isKill))
1205  .addFrameIndex(FI)
1206  .addMemOperand(MMO)
1207  .add(predOps(ARMCC::AL));
1208  }
1209  } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&
1210  Subtarget.hasMVEIntegerOps()) {
1211  auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32));
1212  MIB.addReg(SrcReg, getKillRegState(isKill))
1213  .addFrameIndex(FI)
1214  .addImm(0)
1215  .addMemOperand(MMO);
1217  } else
1218  llvm_unreachable("Unknown reg class!");
1219  break;
1220  case 24:
1221  if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1222  // Use aligned spills if the stack can be realigned.
1223  if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) &&
1224  Subtarget.hasNEON()) {
1225  BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo))
1226  .addFrameIndex(FI)
1227  .addImm(16)
1228  .addReg(SrcReg, getKillRegState(isKill))
1229  .addMemOperand(MMO)
1230  .add(predOps(ARMCC::AL));
1231  } else {
1233  get(ARM::VSTMDIA))
1234  .addFrameIndex(FI)
1235  .add(predOps(ARMCC::AL))
1236  .addMemOperand(MMO);
1237  MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1238  MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1239  AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1240  }
1241  } else
1242  llvm_unreachable("Unknown reg class!");
1243  break;
1244  case 32:
1245  if (ARM::QQPRRegClass.hasSubClassEq(RC) ||
1246  ARM::MQQPRRegClass.hasSubClassEq(RC) ||
1247  ARM::DQuadRegClass.hasSubClassEq(RC)) {
1248  if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) &&
1249  Subtarget.hasNEON()) {
1250  // FIXME: It's possible to only store part of the QQ register if the
1251  // spilled def has a sub-register index.
1252  BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo))
1253  .addFrameIndex(FI)
1254  .addImm(16)
1255  .addReg(SrcReg, getKillRegState(isKill))
1256  .addMemOperand(MMO)
1257  .add(predOps(ARMCC::AL));
1258  } else if (Subtarget.hasMVEIntegerOps()) {
1259  BuildMI(MBB, I, DebugLoc(), get(ARM::MQQPRStore))
1260  .addReg(SrcReg, getKillRegState(isKill))
1261  .addFrameIndex(FI)
1262  .addMemOperand(MMO);
1263  } else {
1265  get(ARM::VSTMDIA))
1266  .addFrameIndex(FI)
1267  .add(predOps(ARMCC::AL))
1268  .addMemOperand(MMO);
1269  MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1270  MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1271  MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1272  AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1273  }
1274  } else
1275  llvm_unreachable("Unknown reg class!");
1276  break;
1277  case 64:
1278  if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) &&
1279  Subtarget.hasMVEIntegerOps()) {
1280  BuildMI(MBB, I, DebugLoc(), get(ARM::MQQQQPRStore))
1281  .addReg(SrcReg, getKillRegState(isKill))
1282  .addFrameIndex(FI)
1283  .addMemOperand(MMO);
1284  } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1285  MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
1286  .addFrameIndex(FI)
1287  .add(predOps(ARMCC::AL))
1288  .addMemOperand(MMO);
1289  MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1290  MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1291  MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1292  MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1293  MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
1294  MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
1295  MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
1296  AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1297  } else
1298  llvm_unreachable("Unknown reg class!");
1299  break;
1300  default:
1301  llvm_unreachable("Unknown reg class!");
1302  }
1303 }
1304 
1306  int &FrameIndex) const {
1307  switch (MI.getOpcode()) {
1308  default: break;
1309  case ARM::STRrs:
1310  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
1311  if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1312  MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1313  MI.getOperand(3).getImm() == 0) {
1314  FrameIndex = MI.getOperand(1).getIndex();
1315  return MI.getOperand(0).getReg();
1316  }
1317  break;
1318  case ARM::STRi12:
1319  case ARM::t2STRi12:
1320  case ARM::tSTRspi:
1321  case ARM::VSTRD:
1322  case ARM::VSTRS:
1323  case ARM::VSTR_P0_off:
1324  case ARM::MVE_VSTRWU32:
1325  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1326  MI.getOperand(2).getImm() == 0) {
1327  FrameIndex = MI.getOperand(1).getIndex();
1328  return MI.getOperand(0).getReg();
1329  }
1330  break;
1331  case ARM::VST1q64:
1332  case ARM::VST1d64TPseudo:
1333  case ARM::VST1d64QPseudo:
1334  if (MI.getOperand(0).isFI() && MI.getOperand(2).getSubReg() == 0) {
1335  FrameIndex = MI.getOperand(0).getIndex();
1336  return MI.getOperand(2).getReg();
1337  }
1338  break;
1339  case ARM::VSTMQIA:
1340  if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1341  FrameIndex = MI.getOperand(1).getIndex();
1342  return MI.getOperand(0).getReg();
1343  }
1344  break;
1345  case ARM::MQQPRStore:
1346  case ARM::MQQQQPRStore:
1347  if (MI.getOperand(1).isFI()) {
1348  FrameIndex = MI.getOperand(1).getIndex();
1349  return MI.getOperand(0).getReg();
1350  }
1351  break;
1352  }
1353 
1354  return 0;
1355 }
1356 
1358  int &FrameIndex) const {
1360  if (MI.mayStore() && hasStoreToStackSlot(MI, Accesses) &&
1361  Accesses.size() == 1) {
1362  FrameIndex =
1363  cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
1364  ->getFrameIndex();
1365  return true;
1366  }
1367  return false;
1368 }
1369 
1370 void ARMBaseInstrInfo::
1372  Register DestReg, int FI,
1373  const TargetRegisterClass *RC,
1374  const TargetRegisterInfo *TRI) const {
1375  DebugLoc DL;
1376  if (I != MBB.end()) DL = I->getDebugLoc();
1377  MachineFunction &MF = *MBB.getParent();
1378  MachineFrameInfo &MFI = MF.getFrameInfo();
1379  const Align Alignment = MFI.getObjectAlign(FI);
1382  MFI.getObjectSize(FI), Alignment);
1383 
1384  switch (TRI->getSpillSize(*RC)) {
1385  case 2:
1386  if (ARM::HPRRegClass.hasSubClassEq(RC)) {
1387  BuildMI(MBB, I, DL, get(ARM::VLDRH), DestReg)
1388  .addFrameIndex(FI)
1389  .addImm(0)
1390  .addMemOperand(MMO)
1391  .add(predOps(ARMCC::AL));
1392  } else
1393  llvm_unreachable("Unknown reg class!");
1394  break;
1395  case 4:
1396  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1397  BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1398  .addFrameIndex(FI)
1399  .addImm(0)
1400  .addMemOperand(MMO)
1401  .add(predOps(ARMCC::AL));
1402  } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1403  BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1404  .addFrameIndex(FI)
1405  .addImm(0)
1406  .addMemOperand(MMO)
1407  .add(predOps(ARMCC::AL));
1408  } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {
1409  BuildMI(MBB, I, DL, get(ARM::VLDR_P0_off), DestReg)
1410  .addFrameIndex(FI)
1411  .addImm(0)
1412  .addMemOperand(MMO)
1413  .add(predOps(ARMCC::AL));
1414  } else
1415  llvm_unreachable("Unknown reg class!");
1416  break;
1417  case 8:
1418  if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1419  BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1420  .addFrameIndex(FI)
1421  .addImm(0)
1422  .addMemOperand(MMO)
1423  .add(predOps(ARMCC::AL));
1424  } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1425  MachineInstrBuilder MIB;
1426 
1427  if (Subtarget.hasV5TEOps()) {
1428  MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1429  AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1430  AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1431  MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1432  .add(predOps(ARMCC::AL));
1433  } else {
1434  // Fallback to LDM instruction, which has existed since the dawn of
1435  // time.
1436  MIB = BuildMI(MBB, I, DL, get(ARM::LDMIA))
1437  .addFrameIndex(FI)
1438  .addMemOperand(MMO)
1439  .add(predOps(ARMCC::AL));
1440  MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1441  MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1442  }
1443 
1444  if (Register::isPhysicalRegister(DestReg))
1445  MIB.addReg(DestReg, RegState::ImplicitDefine);
1446  } else
1447  llvm_unreachable("Unknown reg class!");
1448  break;
1449  case 16:
1450  if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {
1451  if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF)) {
1452  BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1453  .addFrameIndex(FI)
1454  .addImm(16)
1455  .addMemOperand(MMO)
1456  .add(predOps(ARMCC::AL));
1457  } else {
1458  BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1459  .addFrameIndex(FI)
1460  .addMemOperand(MMO)
1461  .add(predOps(ARMCC::AL));
1462  }
1463  } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&
1464  Subtarget.hasMVEIntegerOps()) {
1465  auto MIB = BuildMI(MBB, I, DL, get(ARM::MVE_VLDRWU32), DestReg);
1466  MIB.addFrameIndex(FI)
1467  .addImm(0)
1468  .addMemOperand(MMO);
1470  } else
1471  llvm_unreachable("Unknown reg class!");
1472  break;
1473  case 24:
1474  if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1475  if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) &&
1476  Subtarget.hasNEON()) {
1477  BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1478  .addFrameIndex(FI)
1479  .addImm(16)
1480  .addMemOperand(MMO)
1481  .add(predOps(ARMCC::AL));
1482  } else {
1483  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1484  .addFrameIndex(FI)
1485  .addMemOperand(MMO)
1486  .add(predOps(ARMCC::AL));
1487  MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1488  MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1489  MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1490  if (Register::isPhysicalRegister(DestReg))
1491  MIB.addReg(DestReg, RegState::ImplicitDefine);
1492  }
1493  } else
1494  llvm_unreachable("Unknown reg class!");
1495  break;
1496  case 32:
1497  if (ARM::QQPRRegClass.hasSubClassEq(RC) ||
1498  ARM::MQQPRRegClass.hasSubClassEq(RC) ||
1499  ARM::DQuadRegClass.hasSubClassEq(RC)) {
1500  if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) &&
1501  Subtarget.hasNEON()) {
1502  BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1503  .addFrameIndex(FI)
1504  .addImm(16)
1505  .addMemOperand(MMO)
1506  .add(predOps(ARMCC::AL));
1507  } else if (Subtarget.hasMVEIntegerOps()) {
1508  BuildMI(MBB, I, DL, get(ARM::MQQPRLoad), DestReg)
1509  .addFrameIndex(FI)
1510  .addMemOperand(MMO);
1511  } else {
1512  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1513  .addFrameIndex(FI)
1514  .add(predOps(ARMCC::AL))
1515  .addMemOperand(MMO);
1516  MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1517  MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1518  MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1519  MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1520  if (Register::isPhysicalRegister(DestReg))
1521  MIB.addReg(DestReg, RegState::ImplicitDefine);
1522  }
1523  } else
1524  llvm_unreachable("Unknown reg class!");
1525  break;
1526  case 64:
1527  if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) &&
1528  Subtarget.hasMVEIntegerOps()) {
1529  BuildMI(MBB, I, DL, get(ARM::MQQQQPRLoad), DestReg)
1530  .addFrameIndex(FI)
1531  .addMemOperand(MMO);
1532  } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1533  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1534  .addFrameIndex(FI)
1535  .add(predOps(ARMCC::AL))
1536  .addMemOperand(MMO);
1537  MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1538  MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1539  MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1540  MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1541  MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1542  MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1543  MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1544  MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1545  if (Register::isPhysicalRegister(DestReg))
1546  MIB.addReg(DestReg, RegState::ImplicitDefine);
1547  } else
1548  llvm_unreachable("Unknown reg class!");
1549  break;
1550  default:
1551  llvm_unreachable("Unknown regclass!");
1552  }
1553 }
1554 
1556  int &FrameIndex) const {
1557  switch (MI.getOpcode()) {
1558  default: break;
1559  case ARM::LDRrs:
1560  case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1561  if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1562  MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1563  MI.getOperand(3).getImm() == 0) {
1564  FrameIndex = MI.getOperand(1).getIndex();
1565  return MI.getOperand(0).getReg();
1566  }
1567  break;
1568  case ARM::LDRi12:
1569  case ARM::t2LDRi12:
1570  case ARM::tLDRspi:
1571  case ARM::VLDRD:
1572  case ARM::VLDRS:
1573  case ARM::VLDR_P0_off:
1574  case ARM::MVE_VLDRWU32:
1575  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1576  MI.getOperand(2).getImm() == 0) {
1577  FrameIndex = MI.getOperand(1).getIndex();
1578  return MI.getOperand(0).getReg();
1579  }
1580  break;
1581  case ARM::VLD1q64:
1582  case ARM::VLD1d8TPseudo:
1583  case ARM::VLD1d16TPseudo:
1584  case ARM::VLD1d32TPseudo:
1585  case ARM::VLD1d64TPseudo:
1586  case ARM::VLD1d8QPseudo:
1587  case ARM::VLD1d16QPseudo:
1588  case ARM::VLD1d32QPseudo:
1589  case ARM::VLD1d64QPseudo:
1590  if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1591  FrameIndex = MI.getOperand(1).getIndex();
1592  return MI.getOperand(0).getReg();
1593  }
1594  break;
1595  case ARM::VLDMQIA:
1596  if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1597  FrameIndex = MI.getOperand(1).getIndex();
1598  return MI.getOperand(0).getReg();
1599  }
1600  break;
1601  case ARM::MQQPRLoad:
1602  case ARM::MQQQQPRLoad:
1603  if (MI.getOperand(1).isFI()) {
1604  FrameIndex = MI.getOperand(1).getIndex();
1605  return MI.getOperand(0).getReg();
1606  }
1607  break;
1608  }
1609 
1610  return 0;
1611 }
1612 
1614  int &FrameIndex) const {
1616  if (MI.mayLoad() && hasLoadFromStackSlot(MI, Accesses) &&
1617  Accesses.size() == 1) {
1618  FrameIndex =
1619  cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
1620  ->getFrameIndex();
1621  return true;
1622  }
1623  return false;
1624 }
1625 
1626 /// Expands MEMCPY to either LDMIA/STMIA or LDMIA_UPD/STMID_UPD
1627 /// depending on whether the result is used.
1628 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
1629  bool isThumb1 = Subtarget.isThumb1Only();
1630  bool isThumb2 = Subtarget.isThumb2();
1631  const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
1632 
1633  DebugLoc dl = MI->getDebugLoc();
1634  MachineBasicBlock *BB = MI->getParent();
1635 
1636  MachineInstrBuilder LDM, STM;
1637  if (isThumb1 || !MI->getOperand(1).isDead()) {
1638  MachineOperand LDWb(MI->getOperand(1));
1639  LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
1640  : isThumb1 ? ARM::tLDMIA_UPD
1641  : ARM::LDMIA_UPD))
1642  .add(LDWb);
1643  } else {
1644  LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
1645  }
1646 
1647  if (isThumb1 || !MI->getOperand(0).isDead()) {
1648  MachineOperand STWb(MI->getOperand(0));
1649  STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
1650  : isThumb1 ? ARM::tSTMIA_UPD
1651  : ARM::STMIA_UPD))
1652  .add(STWb);
1653  } else {
1654  STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
1655  }
1656 
1657  MachineOperand LDBase(MI->getOperand(3));
1658  LDM.add(LDBase).add(predOps(ARMCC::AL));
1659 
1660  MachineOperand STBase(MI->getOperand(2));
1661  STM.add(STBase).add(predOps(ARMCC::AL));
1662 
1663  // Sort the scratch registers into ascending order.
1665  SmallVector<unsigned, 6> ScratchRegs;
1666  for(unsigned I = 5; I < MI->getNumOperands(); ++I)
1667  ScratchRegs.push_back(MI->getOperand(I).getReg());
1668  llvm::sort(ScratchRegs,
1669  [&TRI](const unsigned &Reg1, const unsigned &Reg2) -> bool {
1670  return TRI.getEncodingValue(Reg1) <
1671  TRI.getEncodingValue(Reg2);
1672  });
1673 
1674  for (const auto &Reg : ScratchRegs) {
1675  LDM.addReg(Reg, RegState::Define);
1676  STM.addReg(Reg, RegState::Kill);
1677  }
1678 
1679  BB->erase(MI);
1680 }
1681 
1683  if (MI.getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1684  expandLoadStackGuard(MI);
1685  MI.getParent()->erase(MI);
1686  return true;
1687  }
1688 
1689  if (MI.getOpcode() == ARM::MEMCPY) {
1690  expandMEMCPY(MI);
1691  return true;
1692  }
1693 
1694  // This hook gets to expand COPY instructions before they become
1695  // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1696  // widened to VMOVD. We prefer the VMOVD when possible because it may be
1697  // changed into a VORR that can go down the NEON pipeline.
1698  if (!MI.isCopy() || Subtarget.dontWidenVMOVS() || !Subtarget.hasFP64())
1699  return false;
1700 
1701  // Look for a copy between even S-registers. That is where we keep floats
1702  // when using NEON v2f32 instructions for f32 arithmetic.
1703  Register DstRegS = MI.getOperand(0).getReg();
1704  Register SrcRegS = MI.getOperand(1).getReg();
1705  if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1706  return false;
1707 
1709  unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1710  &ARM::DPRRegClass);
1711  unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1712  &ARM::DPRRegClass);
1713  if (!DstRegD || !SrcRegD)
1714  return false;
1715 
1716  // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1717  // legal if the COPY already defines the full DstRegD, and it isn't a
1718  // sub-register insertion.
1719  if (!MI.definesRegister(DstRegD, TRI) || MI.readsRegister(DstRegD, TRI))
1720  return false;
1721 
1722  // A dead copy shouldn't show up here, but reject it just in case.
1723  if (MI.getOperand(0).isDead())
1724  return false;
1725 
1726  // All clear, widen the COPY.
1727  LLVM_DEBUG(dbgs() << "widening: " << MI);
1728  MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1729 
1730  // Get rid of the old implicit-def of DstRegD. Leave it if it defines a Q-reg
1731  // or some other super-register.
1732  int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD);
1733  if (ImpDefIdx != -1)
1734  MI.removeOperand(ImpDefIdx);
1735 
1736  // Change the opcode and operands.
1737  MI.setDesc(get(ARM::VMOVD));
1738  MI.getOperand(0).setReg(DstRegD);
1739  MI.getOperand(1).setReg(SrcRegD);
1740  MIB.add(predOps(ARMCC::AL));
1741 
1742  // We are now reading SrcRegD instead of SrcRegS. This may upset the
1743  // register scavenger and machine verifier, so we need to indicate that we
1744  // are reading an undefined value from SrcRegD, but a proper value from
1745  // SrcRegS.
1746  MI.getOperand(1).setIsUndef();
1747  MIB.addReg(SrcRegS, RegState::Implicit);
1748 
1749  // SrcRegD may actually contain an unrelated value in the ssub_1
1750  // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1751  if (MI.getOperand(1).isKill()) {
1752  MI.getOperand(1).setIsKill(false);
1753  MI.addRegisterKilled(SrcRegS, TRI, true);
1754  }
1755 
1756  LLVM_DEBUG(dbgs() << "replaced by: " << MI);
1757  return true;
1758 }
1759 
1760 /// Create a copy of a const pool value. Update CPI to the new index and return
1761 /// the label UID.
1762 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1765 
1766  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1767  assert(MCPE.isMachineConstantPoolEntry() &&
1768  "Expecting a machine constantpool entry!");
1769  ARMConstantPoolValue *ACPV =
1770  static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1771 
1772  unsigned PCLabelId = AFI->createPICLabelUId();
1773  ARMConstantPoolValue *NewCPV = nullptr;
1774 
1775  // FIXME: The below assumes PIC relocation model and that the function
1776  // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1777  // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1778  // instructions, so that's probably OK, but is PIC always correct when
1779  // we get here?
1780  if (ACPV->isGlobalValue())
1782  cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, ARMCP::CPValue,
1783  4, ACPV->getModifier(), ACPV->mustAddCurrentAddress());
1784  else if (ACPV->isExtSymbol())
1785  NewCPV = ARMConstantPoolSymbol::
1786  Create(MF.getFunction().getContext(),
1787  cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1788  else if (ACPV->isBlockAddress())
1789  NewCPV = ARMConstantPoolConstant::
1790  Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1792  else if (ACPV->isLSDA())
1793  NewCPV = ARMConstantPoolConstant::Create(&MF.getFunction(), PCLabelId,
1794  ARMCP::CPLSDA, 4);
1795  else if (ACPV->isMachineBasicBlock())
1796  NewCPV = ARMConstantPoolMBB::
1797  Create(MF.getFunction().getContext(),
1798  cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1799  else
1800  llvm_unreachable("Unexpected ARM constantpool value type!!");
1801  CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlign());
1802  return PCLabelId;
1803 }
1804 
1807  Register DestReg, unsigned SubIdx,
1808  const MachineInstr &Orig,
1809  const TargetRegisterInfo &TRI) const {
1810  unsigned Opcode = Orig.getOpcode();
1811  switch (Opcode) {
1812  default: {
1814  MI->substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1815  MBB.insert(I, MI);
1816  break;
1817  }
1818  case ARM::tLDRpci_pic:
1819  case ARM::t2LDRpci_pic: {
1820  MachineFunction &MF = *MBB.getParent();
1821  unsigned CPI = Orig.getOperand(1).getIndex();
1822  unsigned PCLabelId = duplicateCPV(MF, CPI);
1823  BuildMI(MBB, I, Orig.getDebugLoc(), get(Opcode), DestReg)
1824  .addConstantPoolIndex(CPI)
1825  .addImm(PCLabelId)
1826  .cloneMemRefs(Orig);
1827  break;
1828  }
1829  }
1830 }
1831 
1832 MachineInstr &
1834  MachineBasicBlock::iterator InsertBefore,
1835  const MachineInstr &Orig) const {
1836  MachineInstr &Cloned = TargetInstrInfo::duplicate(MBB, InsertBefore, Orig);
1838  for (;;) {
1839  switch (I->getOpcode()) {
1840  case ARM::tLDRpci_pic:
1841  case ARM::t2LDRpci_pic: {
1842  MachineFunction &MF = *MBB.getParent();
1843  unsigned CPI = I->getOperand(1).getIndex();
1844  unsigned PCLabelId = duplicateCPV(MF, CPI);
1845  I->getOperand(1).setIndex(CPI);
1846  I->getOperand(2).setImm(PCLabelId);
1847  break;
1848  }
1849  }
1850  if (!I->isBundledWithSucc())
1851  break;
1852  ++I;
1853  }
1854  return Cloned;
1855 }
1856 
1858  const MachineInstr &MI1,
1859  const MachineRegisterInfo *MRI) const {
1860  unsigned Opcode = MI0.getOpcode();
1861  if (Opcode == ARM::t2LDRpci || Opcode == ARM::t2LDRpci_pic ||
1862  Opcode == ARM::tLDRpci || Opcode == ARM::tLDRpci_pic ||
1863  Opcode == ARM::LDRLIT_ga_pcrel || Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1864  Opcode == ARM::tLDRLIT_ga_pcrel || Opcode == ARM::t2LDRLIT_ga_pcrel ||
1865  Opcode == ARM::MOV_ga_pcrel || Opcode == ARM::MOV_ga_pcrel_ldr ||
1866  Opcode == ARM::t2MOV_ga_pcrel) {
1867  if (MI1.getOpcode() != Opcode)
1868  return false;
1869  if (MI0.getNumOperands() != MI1.getNumOperands())
1870  return false;
1871 
1872  const MachineOperand &MO0 = MI0.getOperand(1);
1873  const MachineOperand &MO1 = MI1.getOperand(1);
1874  if (MO0.getOffset() != MO1.getOffset())
1875  return false;
1876 
1877  if (Opcode == ARM::LDRLIT_ga_pcrel || Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1878  Opcode == ARM::tLDRLIT_ga_pcrel || Opcode == ARM::t2LDRLIT_ga_pcrel ||
1879  Opcode == ARM::MOV_ga_pcrel || Opcode == ARM::MOV_ga_pcrel_ldr ||
1880  Opcode == ARM::t2MOV_ga_pcrel)
1881  // Ignore the PC labels.
1882  return MO0.getGlobal() == MO1.getGlobal();
1883 
1884  const MachineFunction *MF = MI0.getParent()->getParent();
1885  const MachineConstantPool *MCP = MF->getConstantPool();
1886  int CPI0 = MO0.getIndex();
1887  int CPI1 = MO1.getIndex();
1888  const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1889  const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1890  bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1891  bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1892  if (isARMCP0 && isARMCP1) {
1893  ARMConstantPoolValue *ACPV0 =
1894  static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1895  ARMConstantPoolValue *ACPV1 =
1896  static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1897  return ACPV0->hasSameValue(ACPV1);
1898  } else if (!isARMCP0 && !isARMCP1) {
1899  return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1900  }
1901  return false;
1902  } else if (Opcode == ARM::PICLDR) {
1903  if (MI1.getOpcode() != Opcode)
1904  return false;
1905  if (MI0.getNumOperands() != MI1.getNumOperands())
1906  return false;
1907 
1908  Register Addr0 = MI0.getOperand(1).getReg();
1909  Register Addr1 = MI1.getOperand(1).getReg();
1910  if (Addr0 != Addr1) {
1911  if (!MRI || !Register::isVirtualRegister(Addr0) ||
1913  return false;
1914 
1915  // This assumes SSA form.
1916  MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1917  MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1918  // Check if the loaded value, e.g. a constantpool of a global address, are
1919  // the same.
1920  if (!produceSameValue(*Def0, *Def1, MRI))
1921  return false;
1922  }
1923 
1924  for (unsigned i = 3, e = MI0.getNumOperands(); i != e; ++i) {
1925  // %12 = PICLDR %11, 0, 14, %noreg
1926  const MachineOperand &MO0 = MI0.getOperand(i);
1927  const MachineOperand &MO1 = MI1.getOperand(i);
1928  if (!MO0.isIdenticalTo(MO1))
1929  return false;
1930  }
1931  return true;
1932  }
1933 
1935 }
1936 
1937 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1938 /// determine if two loads are loading from the same base address. It should
1939 /// only return true if the base pointers are the same and the only differences
1940 /// between the two addresses is the offset. It also returns the offsets by
1941 /// reference.
1942 ///
1943 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1944 /// is permanently disabled.
1946  int64_t &Offset1,
1947  int64_t &Offset2) const {
1948  // Don't worry about Thumb: just ARM and Thumb2.
1949  if (Subtarget.isThumb1Only()) return false;
1950 
1951  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1952  return false;
1953 
1954  switch (Load1->getMachineOpcode()) {
1955  default:
1956  return false;
1957  case ARM::LDRi12:
1958  case ARM::LDRBi12:
1959  case ARM::LDRD:
1960  case ARM::LDRH:
1961  case ARM::LDRSB:
1962  case ARM::LDRSH:
1963  case ARM::VLDRD:
1964  case ARM::VLDRS:
1965  case ARM::t2LDRi8:
1966  case ARM::t2LDRBi8:
1967  case ARM::t2LDRDi8:
1968  case ARM::t2LDRSHi8:
1969  case ARM::t2LDRi12:
1970  case ARM::t2LDRBi12:
1971  case ARM::t2LDRSHi12:
1972  break;
1973  }
1974 
1975  switch (Load2->getMachineOpcode()) {
1976  default:
1977  return false;
1978  case ARM::LDRi12:
1979  case ARM::LDRBi12:
1980  case ARM::LDRD:
1981  case ARM::LDRH:
1982  case ARM::LDRSB:
1983  case ARM::LDRSH:
1984  case ARM::VLDRD:
1985  case ARM::VLDRS:
1986  case ARM::t2LDRi8:
1987  case ARM::t2LDRBi8:
1988  case ARM::t2LDRSHi8:
1989  case ARM::t2LDRi12:
1990  case ARM::t2LDRBi12:
1991  case ARM::t2LDRSHi12:
1992  break;
1993  }
1994 
1995  // Check if base addresses and chain operands match.
1996  if (Load1->getOperand(0) != Load2->getOperand(0) ||
1997  Load1->getOperand(4) != Load2->getOperand(4))
1998  return false;
1999 
2000  // Index should be Reg0.
2001  if (Load1->getOperand(3) != Load2->getOperand(3))
2002  return false;
2003 
2004  // Determine the offsets.
2005  if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
2006  isa<ConstantSDNode>(Load2->getOperand(1))) {
2007  Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
2008  Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
2009  return true;
2010  }
2011 
2012  return false;
2013 }
2014 
2015 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
2016 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
2017 /// be scheduled togther. On some targets if two loads are loading from
2018 /// addresses in the same cache line, it's better if they are scheduled
2019 /// together. This function takes two integers that represent the load offsets
2020 /// from the common base address. It returns true if it decides it's desirable
2021 /// to schedule the two loads together. "NumLoads" is the number of loads that
2022 /// have already been scheduled after Load1.
2023 ///
2024 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
2025 /// is permanently disabled.
2027  int64_t Offset1, int64_t Offset2,
2028  unsigned NumLoads) const {
2029  // Don't worry about Thumb: just ARM and Thumb2.
2030  if (Subtarget.isThumb1Only()) return false;
2031 
2032  assert(Offset2 > Offset1);
2033 
2034  if ((Offset2 - Offset1) / 8 > 64)
2035  return false;
2036 
2037  // Check if the machine opcodes are different. If they are different
2038  // then we consider them to not be of the same base address,
2039  // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
2040  // In this case, they are considered to be the same because they are different
2041  // encoding forms of the same basic instruction.
2042  if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
2043  !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
2044  Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
2045  (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
2046  Load2->getMachineOpcode() == ARM::t2LDRBi8)))
2047  return false; // FIXME: overly conservative?
2048 
2049  // Four loads in a row should be sufficient.
2050  if (NumLoads >= 3)
2051  return false;
2052 
2053  return true;
2054 }
2055 
2057  const MachineBasicBlock *MBB,
2058  const MachineFunction &MF) const {
2059  // Debug info is never a scheduling boundary. It's necessary to be explicit
2060  // due to the special treatment of IT instructions below, otherwise a
2061  // dbg_value followed by an IT will result in the IT instruction being
2062  // considered a scheduling hazard, which is wrong. It should be the actual
2063  // instruction preceding the dbg_value instruction(s), just like it is
2064  // when debug info is not present.
2065  if (MI.isDebugInstr())
2066  return false;
2067 
2068  // Terminators and labels can't be scheduled around.
2069  if (MI.isTerminator() || MI.isPosition())
2070  return true;
2071 
2072  // INLINEASM_BR can jump to another block
2073  if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
2074  return true;
2075 
2076  if (isSEHInstruction(MI))
2077  return true;
2078 
2079  // Treat the start of the IT block as a scheduling boundary, but schedule
2080  // t2IT along with all instructions following it.
2081  // FIXME: This is a big hammer. But the alternative is to add all potential
2082  // true and anti dependencies to IT block instructions as implicit operands
2083  // to the t2IT instruction. The added compile time and complexity does not
2084  // seem worth it.
2086  // Make sure to skip any debug instructions
2087  while (++I != MBB->end() && I->isDebugInstr())
2088  ;
2089  if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
2090  return true;
2091 
2092  // Don't attempt to schedule around any instruction that defines
2093  // a stack-oriented pointer, as it's unlikely to be profitable. This
2094  // saves compile time, because it doesn't require every single
2095  // stack slot reference to depend on the instruction that does the
2096  // modification.
2097  // Calls don't actually change the stack pointer, even if they have imp-defs.
2098  // No ARM calling conventions change the stack pointer. (X86 calling
2099  // conventions sometimes do).
2100  if (!MI.isCall() && MI.definesRegister(ARM::SP))
2101  return true;
2102 
2103  return false;
2104 }
2105 
2106 bool ARMBaseInstrInfo::
2108  unsigned NumCycles, unsigned ExtraPredCycles,
2109  BranchProbability Probability) const {
2110  if (!NumCycles)
2111  return false;
2112 
2113  // If we are optimizing for size, see if the branch in the predecessor can be
2114  // lowered to cbn?z by the constant island lowering pass, and return false if
2115  // so. This results in a shorter instruction sequence.
2116  if (MBB.getParent()->getFunction().hasOptSize()) {
2117  MachineBasicBlock *Pred = *MBB.pred_begin();
2118  if (!Pred->empty()) {
2119  MachineInstr *LastMI = &*Pred->rbegin();
2120  if (LastMI->getOpcode() == ARM::t2Bcc) {
2122  MachineInstr *CmpMI = findCMPToFoldIntoCBZ(LastMI, TRI);
2123  if (CmpMI)
2124  return false;
2125  }
2126  }
2127  }
2128  return isProfitableToIfCvt(MBB, NumCycles, ExtraPredCycles,
2129  MBB, 0, 0, Probability);
2130 }
2131 
2132 bool ARMBaseInstrInfo::
2134  unsigned TCycles, unsigned TExtra,
2135  MachineBasicBlock &FBB,
2136  unsigned FCycles, unsigned FExtra,
2137  BranchProbability Probability) const {
2138  if (!TCycles)
2139  return false;
2140 
2141  // In thumb code we often end up trading one branch for a IT block, and
2142  // if we are cloning the instruction can increase code size. Prevent
2143  // blocks with multiple predecesors from being ifcvted to prevent this
2144  // cloning.
2145  if (Subtarget.isThumb2() && TBB.getParent()->getFunction().hasMinSize()) {
2146  if (TBB.pred_size() != 1 || FBB.pred_size() != 1)
2147  return false;
2148  }
2149 
2150  // Attempt to estimate the relative costs of predication versus branching.
2151  // Here we scale up each component of UnpredCost to avoid precision issue when
2152  // scaling TCycles/FCycles by Probability.
2153  const unsigned ScalingUpFactor = 1024;
2154 
2155  unsigned PredCost = (TCycles + FCycles + TExtra + FExtra) * ScalingUpFactor;
2156  unsigned UnpredCost;
2157  if (!Subtarget.hasBranchPredictor()) {
2158  // When we don't have a branch predictor it's always cheaper to not take a
2159  // branch than take it, so we have to take that into account.
2160  unsigned NotTakenBranchCost = 1;
2161  unsigned TakenBranchCost = Subtarget.getMispredictionPenalty();
2162  unsigned TUnpredCycles, FUnpredCycles;
2163  if (!FCycles) {
2164  // Triangle: TBB is the fallthrough
2165  TUnpredCycles = TCycles + NotTakenBranchCost;
2166  FUnpredCycles = TakenBranchCost;
2167  } else {
2168  // Diamond: TBB is the block that is branched to, FBB is the fallthrough
2169  TUnpredCycles = TCycles + TakenBranchCost;
2170  FUnpredCycles = FCycles + NotTakenBranchCost;
2171  // The branch at the end of FBB will disappear when it's predicated, so
2172  // discount it from PredCost.
2173  PredCost -= 1 * ScalingUpFactor;
2174  }
2175  // The total cost is the cost of each path scaled by their probabilites
2176  unsigned TUnpredCost = Probability.scale(TUnpredCycles * ScalingUpFactor);
2177  unsigned FUnpredCost = Probability.getCompl().scale(FUnpredCycles * ScalingUpFactor);
2178  UnpredCost = TUnpredCost + FUnpredCost;
2179  // When predicating assume that the first IT can be folded away but later
2180  // ones cost one cycle each
2181  if (Subtarget.isThumb2() && TCycles + FCycles > 4) {
2182  PredCost += ((TCycles + FCycles - 4) / 4) * ScalingUpFactor;
2183  }
2184  } else {
2185  unsigned TUnpredCost = Probability.scale(TCycles * ScalingUpFactor);
2186  unsigned FUnpredCost =
2187  Probability.getCompl().scale(FCycles * ScalingUpFactor);
2188  UnpredCost = TUnpredCost + FUnpredCost;
2189  UnpredCost += 1 * ScalingUpFactor; // The branch itself
2190  UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
2191  }
2192 
2193  return PredCost <= UnpredCost;
2194 }
2195 
2196 unsigned
2198  unsigned NumInsts) const {
2199  // Thumb2 needs a 2-byte IT instruction to predicate up to 4 instructions.
2200  // ARM has a condition code field in every predicable instruction, using it
2201  // doesn't change code size.
2202  if (!Subtarget.isThumb2())
2203  return 0;
2204 
2205  // It's possible that the size of the IT is restricted to a single block.
2206  unsigned MaxInsts = Subtarget.restrictIT() ? 1 : 4;
2207  return divideCeil(NumInsts, MaxInsts) * 2;
2208 }
2209 
2210 unsigned
2212  // If this branch is likely to be folded into the comparison to form a
2213  // CB(N)Z, then removing it won't reduce code size at all, because that will
2214  // just replace the CB(N)Z with a CMP.
2215  if (MI.getOpcode() == ARM::t2Bcc &&
2217  return 0;
2218 
2219  unsigned Size = getInstSizeInBytes(MI);
2220 
2221  // For Thumb2, all branches are 32-bit instructions during the if conversion
2222  // pass, but may be replaced with 16-bit instructions during size reduction.
2223  // Since the branches considered by if conversion tend to be forward branches
2224  // over small basic blocks, they are very likely to be in range for the
2225  // narrow instructions, so we assume the final code size will be half what it
2226  // currently is.
2227  if (Subtarget.isThumb2())
2228  Size /= 2;
2229 
2230  return Size;
2231 }
2232 
2233 bool
2235  MachineBasicBlock &FMBB) const {
2236  // Reduce false anti-dependencies to let the target's out-of-order execution
2237  // engine do its thing.
2238  return Subtarget.isProfitableToUnpredicate();
2239 }
2240 
2241 /// getInstrPredicate - If instruction is predicated, returns its predicate
2242 /// condition, otherwise returns AL. It also returns the condition code
2243 /// register by reference.
2245  Register &PredReg) {
2246  int PIdx = MI.findFirstPredOperandIdx();
2247  if (PIdx == -1) {
2248  PredReg = 0;
2249  return ARMCC::AL;
2250  }
2251 
2252  PredReg = MI.getOperand(PIdx+1).getReg();
2253  return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
2254 }
2255 
2256 unsigned llvm::getMatchingCondBranchOpcode(unsigned Opc) {
2257  if (Opc == ARM::B)
2258  return ARM::Bcc;
2259  if (Opc == ARM::tB)
2260  return ARM::tBcc;
2261  if (Opc == ARM::t2B)
2262  return ARM::t2Bcc;
2263 
2264  llvm_unreachable("Unknown unconditional branch opcode!");
2265 }
2266 
2268  bool NewMI,
2269  unsigned OpIdx1,
2270  unsigned OpIdx2) const {
2271  switch (MI.getOpcode()) {
2272  case ARM::MOVCCr:
2273  case ARM::t2MOVCCr: {
2274  // MOVCC can be commuted by inverting the condition.
2275  Register PredReg;
2277  // MOVCC AL can't be inverted. Shouldn't happen.
2278  if (CC == ARMCC::AL || PredReg != ARM::CPSR)
2279  return nullptr;
2280  MachineInstr *CommutedMI =
2281  TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2282  if (!CommutedMI)
2283  return nullptr;
2284  // After swapping the MOVCC operands, also invert the condition.
2285  CommutedMI->getOperand(CommutedMI->findFirstPredOperandIdx())
2287  return CommutedMI;
2288  }
2289  }
2290  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2291 }
2292 
2293 /// Identify instructions that can be folded into a MOVCC instruction, and
2294 /// return the defining instruction.
2295 MachineInstr *
2296 ARMBaseInstrInfo::canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
2297  const TargetInstrInfo *TII) const {
2298  if (!Reg.isVirtual())
2299  return nullptr;
2300  if (!MRI.hasOneNonDBGUse(Reg))
2301  return nullptr;
2303  if (!MI)
2304  return nullptr;
2305  // Check if MI can be predicated and folded into the MOVCC.
2306  if (!isPredicable(*MI))
2307  return nullptr;
2308  // Check if MI has any non-dead defs or physreg uses. This also detects
2309  // predicated instructions which will be reading CPSR.
2310  for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 1)) {
2311  // Reject frame index operands, PEI can't handle the predicated pseudos.
2312  if (MO.isFI() || MO.isCPI() || MO.isJTI())
2313  return nullptr;
2314  if (!MO.isReg())
2315  continue;
2316  // MI can't have any tied operands, that would conflict with predication.
2317  if (MO.isTied())
2318  return nullptr;
2319  if (Register::isPhysicalRegister(MO.getReg()))
2320  return nullptr;
2321  if (MO.isDef() && !MO.isDead())
2322  return nullptr;
2323  }
2324  bool DontMoveAcrossStores = true;
2325  if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores))
2326  return nullptr;
2327  return MI;
2328 }
2329 
2332  unsigned &TrueOp, unsigned &FalseOp,
2333  bool &Optimizable) const {
2334  assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
2335  "Unknown select instruction");
2336  // MOVCC operands:
2337  // 0: Def.
2338  // 1: True use.
2339  // 2: False use.
2340  // 3: Condition code.
2341  // 4: CPSR use.
2342  TrueOp = 1;
2343  FalseOp = 2;
2344  Cond.push_back(MI.getOperand(3));
2345  Cond.push_back(MI.getOperand(4));
2346  // We can always fold a def.
2347  Optimizable = true;
2348  return false;
2349 }
2350 
2351 MachineInstr *
2354  bool PreferFalse) const {
2355  assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
2356  "Unknown select instruction");
2357  MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2358  MachineInstr *DefMI = canFoldIntoMOVCC(MI.getOperand(2).getReg(), MRI, this);
2359  bool Invert = !DefMI;
2360  if (!DefMI)
2361  DefMI = canFoldIntoMOVCC(MI.getOperand(1).getReg(), MRI, this);
2362  if (!DefMI)
2363  return nullptr;
2364 
2365  // Find new register class to use.
2366  MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1);
2367  MachineOperand TrueReg = MI.getOperand(Invert ? 1 : 2);
2368  Register DestReg = MI.getOperand(0).getReg();
2369  const TargetRegisterClass *FalseClass = MRI.getRegClass(FalseReg.getReg());
2370  const TargetRegisterClass *TrueClass = MRI.getRegClass(TrueReg.getReg());
2371  if (!MRI.constrainRegClass(DestReg, FalseClass))
2372  return nullptr;
2373  if (!MRI.constrainRegClass(DestReg, TrueClass))
2374  return nullptr;
2375 
2376  // Create a new predicated version of DefMI.
2377  // Rfalse is the first use.
2378  MachineInstrBuilder NewMI =
2379  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
2380 
2381  // Copy all the DefMI operands, excluding its (null) predicate.
2382  const MCInstrDesc &DefDesc = DefMI->getDesc();
2383  for (unsigned i = 1, e = DefDesc.getNumOperands();
2384  i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
2385  NewMI.add(DefMI->getOperand(i));
2386 
2387  unsigned CondCode = MI.getOperand(3).getImm();
2388  if (Invert)
2390  else
2391  NewMI.addImm(CondCode);
2392  NewMI.add(MI.getOperand(4));
2393 
2394  // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
2395  if (NewMI->hasOptionalDef())
2396  NewMI.add(condCodeOp());
2397 
2398  // The output register value when the predicate is false is an implicit
2399  // register operand tied to the first def.
2400  // The tie makes the register allocator ensure the FalseReg is allocated the
2401  // same register as operand 0.
2402  FalseReg.setImplicit();
2403  NewMI.add(FalseReg);
2404  NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
2405 
2406  // Update SeenMIs set: register newly created MI and erase removed DefMI.
2407  SeenMIs.insert(NewMI);
2408  SeenMIs.erase(DefMI);
2409 
2410  // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
2411  // DefMI would be invalid when tranferred inside the loop. Checking for a
2412  // loop is expensive, but at least remove kill flags if they are in different
2413  // BBs.
2414  if (DefMI->getParent() != MI.getParent())
2415  NewMI->clearKillInfo();
2416 
2417  // The caller will erase MI, but not DefMI.
2419  return NewMI;
2420 }
2421 
2422 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
2423 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
2424 /// def operand.
2425 ///
2426 /// This will go away once we can teach tblgen how to set the optional CPSR def
2427 /// operand itself.
2431 };
2432 
2434  {ARM::ADDSri, ARM::ADDri},
2435  {ARM::ADDSrr, ARM::ADDrr},
2436  {ARM::ADDSrsi, ARM::ADDrsi},
2437  {ARM::ADDSrsr, ARM::ADDrsr},
2438 
2439  {ARM::SUBSri, ARM::SUBri},
2440  {ARM::SUBSrr, ARM::SUBrr},
2441  {ARM::SUBSrsi, ARM::SUBrsi},
2442  {ARM::SUBSrsr, ARM::SUBrsr},
2443 
2444  {ARM::RSBSri, ARM::RSBri},
2445  {ARM::RSBSrsi, ARM::RSBrsi},
2446  {ARM::RSBSrsr, ARM::RSBrsr},
2447 
2448  {ARM::tADDSi3, ARM::tADDi3},
2449  {ARM::tADDSi8, ARM::tADDi8},
2450  {ARM::tADDSrr, ARM::tADDrr},
2451  {ARM::tADCS, ARM::tADC},
2452 
2453  {ARM::tSUBSi3, ARM::tSUBi3},
2454  {ARM::tSUBSi8, ARM::tSUBi8},
2455  {ARM::tSUBSrr, ARM::tSUBrr},
2456  {ARM::tSBCS, ARM::tSBC},
2457  {ARM::tRSBS, ARM::tRSB},
2458  {ARM::tLSLSri, ARM::tLSLri},
2459 
2460  {ARM::t2ADDSri, ARM::t2ADDri},
2461  {ARM::t2ADDSrr, ARM::t2ADDrr},
2462  {ARM::t2ADDSrs, ARM::t2ADDrs},
2463 
2464  {ARM::t2SUBSri, ARM::t2SUBri},
2465  {ARM::t2SUBSrr, ARM::t2SUBrr},
2466  {ARM::t2SUBSrs, ARM::t2SUBrs},
2467 
2468  {ARM::t2RSBSri, ARM::t2RSBri},
2469  {ARM::t2RSBSrs, ARM::t2RSBrs},
2470 };
2471 
2472 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
2473  for (const auto &Entry : AddSubFlagsOpcodeMap)
2474  if (OldOpc == Entry.PseudoOpc)
2475  return Entry.MachineOpc;
2476  return 0;
2477 }
2478 
2481  const DebugLoc &dl, Register DestReg,
2482  Register BaseReg, int NumBytes,
2483  ARMCC::CondCodes Pred, Register PredReg,
2484  const ARMBaseInstrInfo &TII,
2485  unsigned MIFlags) {
2486  if (NumBytes == 0 && DestReg != BaseReg) {
2487  BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
2488  .addReg(BaseReg, RegState::Kill)
2489  .add(predOps(Pred, PredReg))
2490  .add(condCodeOp())
2491  .setMIFlags(MIFlags);
2492  return;
2493  }
2494 
2495  bool isSub = NumBytes < 0;
2496  if (isSub) NumBytes = -NumBytes;
2497 
2498  while (NumBytes) {
2499  unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
2500  unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
2501  assert(ThisVal && "Didn't extract field correctly");
2502 
2503  // We will handle these bits from offset, clear them.
2504  NumBytes &= ~ThisVal;
2505 
2506  assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
2507 
2508  // Build the new ADD / SUB.
2509  unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
2510  BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
2511  .addReg(BaseReg, RegState::Kill)
2512  .addImm(ThisVal)
2513  .add(predOps(Pred, PredReg))
2514  .add(condCodeOp())
2515  .setMIFlags(MIFlags);
2516  BaseReg = DestReg;
2517  }
2518 }
2519 
2522  unsigned NumBytes) {
2523  // This optimisation potentially adds lots of load and store
2524  // micro-operations, it's only really a great benefit to code-size.
2525  if (!Subtarget.hasMinSize())
2526  return false;
2527 
2528  // If only one register is pushed/popped, LLVM can use an LDR/STR
2529  // instead. We can't modify those so make sure we're dealing with an
2530  // instruction we understand.
2531  bool IsPop = isPopOpcode(MI->getOpcode());
2532  bool IsPush = isPushOpcode(MI->getOpcode());
2533  if (!IsPush && !IsPop)
2534  return false;
2535 
2536  bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
2537  MI->getOpcode() == ARM::VLDMDIA_UPD;
2538  bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2539  MI->getOpcode() == ARM::tPOP ||
2540  MI->getOpcode() == ARM::tPOP_RET;
2541 
2542  assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2543  MI->getOperand(1).getReg() == ARM::SP)) &&
2544  "trying to fold sp update into non-sp-updating push/pop");
2545 
2546  // The VFP push & pop act on D-registers, so we can only fold an adjustment
2547  // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2548  // if this is violated.
2549  if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2550  return false;
2551 
2552  // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2553  // pred) so the list starts at 4. Thumb1 starts after the predicate.
2554  int RegListIdx = IsT1PushPop ? 2 : 4;
2555 
2556  // Calculate the space we'll need in terms of registers.
2557  unsigned RegsNeeded;
2558  const TargetRegisterClass *RegClass;
2559  if (IsVFPPushPop) {
2560  RegsNeeded = NumBytes / 8;
2561  RegClass = &ARM::DPRRegClass;
2562  } else {
2563  RegsNeeded = NumBytes / 4;
2564  RegClass = &ARM::GPRRegClass;
2565  }
2566 
2567  // We're going to have to strip all list operands off before
2568  // re-adding them since the order matters, so save the existing ones
2569  // for later.
2571 
2572  // We're also going to need the first register transferred by this
2573  // instruction, which won't necessarily be the first register in the list.
2574  unsigned FirstRegEnc = -1;
2575 
2577  for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) {
2578  MachineOperand &MO = MI->getOperand(i);
2579  RegList.push_back(MO);
2580 
2581  if (MO.isReg() && !MO.isImplicit() &&
2582  TRI->getEncodingValue(MO.getReg()) < FirstRegEnc)
2583  FirstRegEnc = TRI->getEncodingValue(MO.getReg());
2584  }
2585 
2586  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2587 
2588  // Now try to find enough space in the reglist to allocate NumBytes.
2589  for (int CurRegEnc = FirstRegEnc - 1; CurRegEnc >= 0 && RegsNeeded;
2590  --CurRegEnc) {
2591  unsigned CurReg = RegClass->getRegister(CurRegEnc);
2592  if (IsT1PushPop && CurRegEnc > TRI->getEncodingValue(ARM::R7))
2593  continue;
2594  if (!IsPop) {
2595  // Pushing any register is completely harmless, mark the register involved
2596  // as undef since we don't care about its value and must not restore it
2597  // during stack unwinding.
2598  RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2599  false, false, true));
2600  --RegsNeeded;
2601  continue;
2602  }
2603 
2604  // However, we can only pop an extra register if it's not live. For
2605  // registers live within the function we might clobber a return value
2606  // register; the other way a register can be live here is if it's
2607  // callee-saved.
2608  if (isCalleeSavedRegister(CurReg, CSRegs) ||
2609  MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2611  // VFP pops don't allow holes in the register list, so any skip is fatal
2612  // for our transformation. GPR pops do, so we should just keep looking.
2613  if (IsVFPPushPop)
2614  return false;
2615  else
2616  continue;
2617  }
2618 
2619  // Mark the unimportant registers as <def,dead> in the POP.
2620  RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2621  true));
2622  --RegsNeeded;
2623  }
2624 
2625  if (RegsNeeded > 0)
2626  return false;
2627 
2628  // Finally we know we can profitably perform the optimisation so go
2629  // ahead: strip all existing registers off and add them back again
2630  // in the right order.
2631  for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2632  MI->removeOperand(i);
2633 
2634  // Add the complete list back in.
2635  MachineInstrBuilder MIB(MF, &*MI);
2636  for (const MachineOperand &MO : llvm::reverse(RegList))
2637  MIB.add(MO);
2638 
2639  return true;
2640 }
2641 
2642 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2643  Register FrameReg, int &Offset,
2644  const ARMBaseInstrInfo &TII) {
2645  unsigned Opcode = MI.getOpcode();
2646  const MCInstrDesc &Desc = MI.getDesc();
2647  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2648  bool isSub = false;
2649 
2650  // Memory operands in inline assembly always use AddrMode2.
2651  if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
2653 
2654  if (Opcode == ARM::ADDri) {
2655  Offset += MI.getOperand(FrameRegIdx+1).getImm();
2656  if (Offset == 0) {
2657  // Turn it into a move.
2658  MI.setDesc(TII.get(ARM::MOVr));
2659  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2660  MI.removeOperand(FrameRegIdx+1);
2661  Offset = 0;
2662  return true;
2663  } else if (Offset < 0) {
2664  Offset = -Offset;
2665  isSub = true;
2666  MI.setDesc(TII.get(ARM::SUBri));
2667  }
2668 
2669  // Common case: small offset, fits into instruction.
2670  if (ARM_AM::getSOImmVal(Offset) != -1) {
2671  // Replace the FrameIndex with sp / fp
2672  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2673  MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2674  Offset = 0;
2675  return true;
2676  }
2677 
2678  // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2679  // as possible.
2680  unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2681  unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2682 
2683  // We will handle these bits from offset, clear them.
2684  Offset &= ~ThisImmVal;
2685 
2686  // Get the properly encoded SOImmVal field.
2687  assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2688  "Bit extraction didn't work?");
2689  MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2690  } else {
2691  unsigned ImmIdx = 0;
2692  int InstrOffs = 0;
2693  unsigned NumBits = 0;
2694  unsigned Scale = 1;
2695  switch (AddrMode) {
2696  case ARMII::AddrMode_i12:
2697  ImmIdx = FrameRegIdx + 1;
2698  InstrOffs = MI.getOperand(ImmIdx).getImm();
2699  NumBits = 12;
2700  break;
2701  case ARMII::AddrMode2:
2702  ImmIdx = FrameRegIdx+2;
2703  InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2704  if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2705  InstrOffs *= -1;
2706  NumBits = 12;
2707  break;
2708  case ARMII::AddrMode3:
2709  ImmIdx = FrameRegIdx+2;
2710  InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2711  if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2712  InstrOffs *= -1;
2713  NumBits = 8;
2714  break;
2715  case ARMII::AddrMode4:
2716  case ARMII::AddrMode6:
2717  // Can't fold any offset even if it's zero.
2718  return false;
2719  case ARMII::AddrMode5:
2720  ImmIdx = FrameRegIdx+1;
2721  InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2722  if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2723  InstrOffs *= -1;
2724  NumBits = 8;
2725  Scale = 4;
2726  break;
2727  case ARMII::AddrMode5FP16:
2728  ImmIdx = FrameRegIdx+1;
2729  InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2730  if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2731  InstrOffs *= -1;
2732  NumBits = 8;
2733  Scale = 2;
2734  break;
2735  case ARMII::AddrModeT2_i7:
2738  ImmIdx = FrameRegIdx+1;
2739  InstrOffs = MI.getOperand(ImmIdx).getImm();
2740  NumBits = 7;
2741  Scale = (AddrMode == ARMII::AddrModeT2_i7s2 ? 2 :
2742  AddrMode == ARMII::AddrModeT2_i7s4 ? 4 : 1);
2743  break;
2744  default:
2745  llvm_unreachable("Unsupported addressing mode!");
2746  }
2747 
2748  Offset += InstrOffs * Scale;
2749  assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2750  if (Offset < 0) {
2751  Offset = -Offset;
2752  isSub = true;
2753  }
2754 
2755  // Attempt to fold address comp. if opcode has offset bits
2756  if (NumBits > 0) {
2757  // Common case: small offset, fits into instruction.
2758  MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2759  int ImmedOffset = Offset / Scale;
2760  unsigned Mask = (1 << NumBits) - 1;
2761  if ((unsigned)Offset <= Mask * Scale) {
2762  // Replace the FrameIndex with sp
2763  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2764  // FIXME: When addrmode2 goes away, this will simplify (like the
2765  // T2 version), as the LDR.i12 versions don't need the encoding
2766  // tricks for the offset value.
2767  if (isSub) {
2769  ImmedOffset = -ImmedOffset;
2770  else
2771  ImmedOffset |= 1 << NumBits;
2772  }
2773  ImmOp.ChangeToImmediate(ImmedOffset);
2774  Offset = 0;
2775  return true;
2776  }
2777 
2778  // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2779  ImmedOffset = ImmedOffset & Mask;
2780  if (isSub) {
2782  ImmedOffset = -ImmedOffset;
2783  else
2784  ImmedOffset |= 1 << NumBits;
2785  }
2786  ImmOp.ChangeToImmediate(ImmedOffset);
2787  Offset &= ~(Mask*Scale);
2788  }
2789  }
2790 
2791  Offset = (isSub) ? -Offset : Offset;
2792  return Offset == 0;
2793 }
2794 
2795 /// analyzeCompare - For a comparison instruction, return the source registers
2796 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2797 /// compares against in CmpValue. Return true if the comparison instruction
2798 /// can be analyzed.
2800  Register &SrcReg2, int64_t &CmpMask,
2801  int64_t &CmpValue) const {
2802  switch (MI.getOpcode()) {
2803  default: break;
2804  case ARM::CMPri:
2805  case ARM::t2CMPri:
2806  case ARM::tCMPi8:
2807  SrcReg = MI.getOperand(0).getReg();
2808  SrcReg2 = 0;
2809  CmpMask = ~0;
2810  CmpValue = MI.getOperand(1).getImm();
2811  return true;
2812  case ARM::CMPrr:
2813  case ARM::t2CMPrr:
2814  case ARM::tCMPr:
2815  SrcReg = MI.getOperand(0).getReg();
2816  SrcReg2 = MI.getOperand(1).getReg();
2817  CmpMask = ~0;
2818  CmpValue = 0;
2819  return true;
2820  case ARM::TSTri:
2821  case ARM::t2TSTri:
2822  SrcReg = MI.getOperand(0).getReg();
2823  SrcReg2 = 0;
2824  CmpMask = MI.getOperand(1).getImm();
2825  CmpValue = 0;
2826  return true;
2827  }
2828 
2829  return false;
2830 }
2831 
2832 /// isSuitableForMask - Identify a suitable 'and' instruction that
2833 /// operates on the given source register and applies the same mask
2834 /// as a 'tst' instruction. Provide a limited look-through for copies.
2835 /// When successful, MI will hold the found instruction.
2837  int CmpMask, bool CommonUse) {
2838  switch (MI->getOpcode()) {
2839  case ARM::ANDri:
2840  case ARM::t2ANDri:
2841  if (CmpMask != MI->getOperand(2).getImm())
2842  return false;
2843  if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2844  return true;
2845  break;
2846  }
2847 
2848  return false;
2849 }
2850 
2851 /// getCmpToAddCondition - assume the flags are set by CMP(a,b), return
2852 /// the condition code if we modify the instructions such that flags are
2853 /// set by ADD(a,b,X).
2855  switch (CC) {
2856  default: return ARMCC::AL;
2857  case ARMCC::HS: return ARMCC::LO;
2858  case ARMCC::LO: return ARMCC::HS;
2859  case ARMCC::VS: return ARMCC::VS;
2860  case ARMCC::VC: return ARMCC::VC;
2861  }
2862 }
2863 
2864 /// isRedundantFlagInstr - check whether the first instruction, whose only
2865 /// purpose is to update flags, can be made redundant.
2866 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2867 /// CMPri can be made redundant by SUBri if the operands are the same.
2868 /// CMPrr(r0, r1) can be made redundant by ADDr[ri](r0, r1, X).
2869 /// This function can be extended later on.
2870 inline static bool isRedundantFlagInstr(const MachineInstr *CmpI,
2871  Register SrcReg, Register SrcReg2,
2872  int64_t ImmValue,
2873  const MachineInstr *OI,
2874  bool &IsThumb1) {
2875  if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) &&
2876  (OI->getOpcode() == ARM::SUBrr || OI->getOpcode() == ARM::t2SUBrr) &&
2877  ((OI->getOperand(1).getReg() == SrcReg &&
2878  OI->getOperand(2).getReg() == SrcReg2) ||
2879  (OI->getOperand(1).getReg() == SrcReg2 &&
2880  OI->getOperand(2).getReg() == SrcReg))) {
2881  IsThumb1 = false;
2882  return true;
2883  }
2884 
2885  if (CmpI->getOpcode() == ARM::tCMPr && OI->getOpcode() == ARM::tSUBrr &&
2886  ((OI->getOperand(2).getReg() == SrcReg &&
2887  OI->getOperand(3).getReg() == SrcReg2) ||
2888  (OI->getOperand(2).getReg() == SrcReg2 &&
2889  OI->getOperand(3).getReg() == SrcReg))) {
2890  IsThumb1 = true;
2891  return true;
2892  }
2893 
2894  if ((CmpI->getOpcode() == ARM::CMPri || CmpI->getOpcode() == ARM::t2CMPri) &&
2895  (OI->getOpcode() == ARM::SUBri || OI->getOpcode() == ARM::t2SUBri) &&
2896  OI->getOperand(1).getReg() == SrcReg &&
2897  OI->getOperand(2).getImm() == ImmValue) {
2898  IsThumb1 = false;
2899  return true;
2900  }
2901 
2902  if (CmpI->getOpcode() == ARM::tCMPi8 &&
2903  (OI->getOpcode() == ARM::tSUBi8 || OI->getOpcode() == ARM::tSUBi3) &&
2904  OI->getOperand(2).getReg() == SrcReg &&
2905  OI->getOperand(3).getImm() == ImmValue) {
2906  IsThumb1 = true;
2907  return true;
2908  }
2909 
2910  if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) &&
2911  (OI->getOpcode() == ARM::ADDrr || OI->getOpcode() == ARM::t2ADDrr ||
2912  OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) &&
2913  OI->getOperand(0).isReg() && OI->getOperand(1).isReg() &&
2914  OI->getOperand(0).getReg() == SrcReg &&
2915  OI->getOperand(1).getReg() == SrcReg2) {
2916  IsThumb1 = false;
2917  return true;
2918  }
2919 
2920  if (CmpI->getOpcode() == ARM::tCMPr &&
2921  (OI->getOpcode() == ARM::tADDi3 || OI->getOpcode() == ARM::tADDi8 ||
2922  OI->getOpcode() == ARM::tADDrr) &&
2923  OI->getOperand(0).getReg() == SrcReg &&
2924  OI->getOperand(2).getReg() == SrcReg2) {
2925  IsThumb1 = true;
2926  return true;
2927  }
2928 
2929  return false;
2930 }
2931 
2932 static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
2933  switch (MI->getOpcode()) {
2934  default: return false;
2935  case ARM::tLSLri:
2936  case ARM::tLSRri:
2937  case ARM::tLSLrr:
2938  case ARM::tLSRrr:
2939  case ARM::tSUBrr:
2940  case ARM::tADDrr:
2941  case ARM::tADDi3:
2942  case ARM::tADDi8:
2943  case ARM::tSUBi3:
2944  case ARM::tSUBi8:
2945  case ARM::tMUL:
2946  case ARM::tADC:
2947  case ARM::tSBC:
2948  case ARM::tRSB:
2949  case ARM::tAND:
2950  case ARM::tORR:
2951  case ARM::tEOR:
2952  case ARM::tBIC:
2953  case ARM::tMVN:
2954  case ARM::tASRri:
2955  case ARM::tASRrr:
2956  case ARM::tROR:
2957  IsThumb1 = true;
2958  [[fallthrough]];
2959  case ARM::RSBrr:
2960  case ARM::RSBri:
2961  case ARM::RSCrr:
2962  case ARM::RSCri:
2963  case ARM::ADDrr:
2964  case ARM::ADDri:
2965  case ARM::ADCrr:
2966  case ARM::ADCri:
2967  case ARM::SUBrr:
2968  case ARM::SUBri:
2969  case ARM::SBCrr:
2970  case ARM::SBCri:
2971  case ARM::t2RSBri:
2972  case ARM::t2ADDrr:
2973  case ARM::t2ADDri:
2974  case ARM::t2ADCrr:
2975  case ARM::t2ADCri:
2976  case ARM::t2SUBrr:
2977  case ARM::t2SUBri:
2978  case ARM::t2SBCrr:
2979  case ARM::t2SBCri:
2980  case ARM::ANDrr:
2981  case ARM::ANDri:
2982  case ARM::ANDrsr:
2983  case ARM::ANDrsi:
2984  case ARM::t2ANDrr:
2985  case ARM::t2ANDri:
2986  case ARM::t2ANDrs:
2987  case ARM::ORRrr:
2988  case ARM::ORRri:
2989  case ARM::ORRrsr:
2990  case ARM::ORRrsi:
2991  case ARM::t2ORRrr:
2992  case ARM::t2ORRri:
2993  case ARM::t2ORRrs:
2994  case ARM::EORrr:
2995  case ARM::EORri:
2996  case ARM::EORrsr:
2997  case ARM::EORrsi:
2998  case ARM::t2EORrr:
2999  case ARM::t2EORri:
3000  case ARM::t2EORrs:
3001  case ARM::BICri:
3002  case ARM::BICrr:
3003  case ARM::BICrsi:
3004  case ARM::BICrsr:
3005  case ARM::t2BICri:
3006  case ARM::t2BICrr:
3007  case ARM::t2BICrs:
3008  case ARM::t2LSRri:
3009  case ARM::t2LSRrr:
3010  case ARM::t2LSLri:
3011  case ARM::t2LSLrr:
3012  case ARM::MOVsr:
3013  case ARM::MOVsi:
3014  return true;
3015  }
3016 }
3017 
3018 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
3019 /// comparison into one that sets the zero bit in the flags register;
3020 /// Remove a redundant Compare instruction if an earlier instruction can set the
3021 /// flags in the same way as Compare.
3022 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
3023 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
3024 /// condition code of instructions which use the flags.
3026  MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask,
3027  int64_t CmpValue, const MachineRegisterInfo *MRI) const {
3028  // Get the unique definition of SrcReg.
3029  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3030  if (!MI) return false;
3031 
3032  // Masked compares sometimes use the same register as the corresponding 'and'.
3033  if (CmpMask != ~0) {
3034  if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) {
3035  MI = nullptr;
3037  UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
3038  UI != UE; ++UI) {
3039  if (UI->getParent() != CmpInstr.getParent())
3040  continue;
3041  MachineInstr *PotentialAND = &*UI;
3042  if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
3043  isPredicated(*PotentialAND))
3044  continue;
3045  MI = PotentialAND;
3046  break;
3047  }
3048  if (!MI) return false;
3049  }
3050  }
3051 
3052  // Get ready to iterate backward from CmpInstr.
3053  MachineBasicBlock::iterator I = CmpInstr, E = MI,
3054  B = CmpInstr.getParent()->begin();
3055 
3056  // Early exit if CmpInstr is at the beginning of the BB.
3057  if (I == B) return false;
3058 
3059  // There are two possible candidates which can be changed to set CPSR:
3060  // One is MI, the other is a SUB or ADD instruction.
3061  // For CMPrr(r1,r2), we are looking for SUB(r1,r2), SUB(r2,r1), or
3062  // ADDr[ri](r1, r2, X).
3063  // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
3064  MachineInstr *SubAdd = nullptr;
3065  if (SrcReg2 != 0)
3066  // MI is not a candidate for CMPrr.
3067  MI = nullptr;
3068  else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
3069  // Conservatively refuse to convert an instruction which isn't in the same
3070  // BB as the comparison.
3071  // For CMPri w/ CmpValue != 0, a SubAdd may still be a candidate.
3072  // Thus we cannot return here.
3073  if (CmpInstr.getOpcode() == ARM::CMPri ||
3074  CmpInstr.getOpcode() == ARM::t2CMPri ||
3075  CmpInstr.getOpcode() == ARM::tCMPi8)
3076  MI = nullptr;
3077  else
3078  return false;
3079  }
3080 
3081  bool IsThumb1 = false;
3082  if (MI && !isOptimizeCompareCandidate(MI, IsThumb1))
3083  return false;
3084 
3085  // We also want to do this peephole for cases like this: if (a*b == 0),
3086  // and optimise away the CMP instruction from the generated code sequence:
3087  // MULS, MOVS, MOVS, CMP. Here the MOVS instructions load the boolean values
3088  // resulting from the select instruction, but these MOVS instructions for
3089  // Thumb1 (V6M) are flag setting and are thus preventing this optimisation.
3090  // However, if we only have MOVS instructions in between the CMP and the
3091  // other instruction (the MULS in this example), then the CPSR is dead so we
3092  // can safely reorder the sequence into: MOVS, MOVS, MULS, CMP. We do this
3093  // reordering and then continue the analysis hoping we can eliminate the
3094  // CMP. This peephole works on the vregs, so is still in SSA form. As a
3095  // consequence, the movs won't redefine/kill the MUL operands which would
3096  // make this reordering illegal.
3098  if (MI && IsThumb1) {
3099  --I;
3100  if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) {
3101  bool CanReorder = true;
3102  for (; I != E; --I) {
3103  if (I->getOpcode() != ARM::tMOVi8) {
3104  CanReorder = false;
3105  break;
3106  }
3107  }
3108  if (CanReorder) {
3109  MI = MI->removeFromParent();
3110  E = CmpInstr;
3111  CmpInstr.getParent()->insert(E, MI);
3112  }
3113  }
3114  I = CmpInstr;
3115  E = MI;
3116  }
3117 
3118  // Check that CPSR isn't set between the comparison instruction and the one we
3119  // want to change. At the same time, search for SubAdd.
3120  bool SubAddIsThumb1 = false;
3121  do {
3122  const MachineInstr &Instr = *--I;
3123 
3124  // Check whether CmpInstr can be made redundant by the current instruction.
3125  if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &Instr,
3126  SubAddIsThumb1)) {
3127  SubAdd = &*I;
3128  break;
3129  }
3130 
3131  // Allow E (which was initially MI) to be SubAdd but do not search before E.
3132  if (I == E)
3133  break;
3134 
3135  if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
3136  Instr.readsRegister(ARM::CPSR, TRI))
3137  // This instruction modifies or uses CPSR after the one we want to
3138  // change. We can't do this transformation.
3139  return false;
3140 
3141  if (I == B) {
3142  // In some cases, we scan the use-list of an instruction for an AND;
3143  // that AND is in the same BB, but may not be scheduled before the
3144  // corresponding TST. In that case, bail out.
3145  //
3146  // FIXME: We could try to reschedule the AND.
3147  return false;
3148  }
3149  } while (true);
3150 
3151  // Return false if no candidates exist.
3152  if (!MI && !SubAdd)
3153  return false;
3154 
3155  // If we found a SubAdd, use it as it will be closer to the CMP
3156  if (SubAdd) {
3157  MI = SubAdd;
3158  IsThumb1 = SubAddIsThumb1;
3159  }
3160 
3161  // We can't use a predicated instruction - it doesn't always write the flags.
3162  if (isPredicated(*MI))
3163  return false;
3164 
3165  // Scan forward for the use of CPSR
3166  // When checking against MI: if it's a conditional code that requires
3167  // checking of the V bit or C bit, then this is not safe to do.
3168  // It is safe to remove CmpInstr if CPSR is redefined or killed.
3169  // If we are done with the basic block, we need to check whether CPSR is
3170  // live-out.
3172  OperandsToUpdate;
3173  bool isSafe = false;
3174  I = CmpInstr;
3175  E = CmpInstr.getParent()->end();
3176  while (!isSafe && ++I != E) {
3177  const MachineInstr &Instr = *I;
3178  for (unsigned IO = 0, EO = Instr.getNumOperands();
3179  !isSafe && IO != EO; ++IO) {
3180  const MachineOperand &MO = Instr.getOperand(IO);
3181  if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
3182  isSafe = true;
3183  break;
3184  }
3185  if (!MO.isReg() || MO.getReg() != ARM::CPSR)
3186  continue;
3187  if (MO.isDef()) {
3188  isSafe = true;
3189  break;
3190  }
3191  // Condition code is after the operand before CPSR except for VSELs.
3193  bool IsInstrVSel = true;
3194  switch (Instr.getOpcode()) {
3195  default:
3196  IsInstrVSel = false;
3197  CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
3198  break;
3199  case ARM::VSELEQD:
3200  case ARM::VSELEQS:
3201  case ARM::VSELEQH:
3202  CC = ARMCC::EQ;
3203  break;
3204  case ARM::VSELGTD:
3205  case ARM::VSELGTS:
3206  case ARM::VSELGTH:
3207  CC = ARMCC::GT;
3208  break;
3209  case ARM::VSELGED:
3210  case ARM::VSELGES:
3211  case ARM::VSELGEH:
3212  CC = ARMCC::GE;
3213  break;
3214  case ARM::VSELVSD:
3215  case ARM::VSELVSS:
3216  case ARM::VSELVSH:
3217  CC = ARMCC::VS;
3218  break;
3219  }
3220 
3221  if (SubAdd) {
3222  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
3223  // on CMP needs to be updated to be based on SUB.
3224  // If we have ADD(r1, r2, X) and CMP(r1, r2), the condition code also
3225  // needs to be modified.
3226  // Push the condition code operands to OperandsToUpdate.
3227  // If it is safe to remove CmpInstr, the condition code of these
3228  // operands will be modified.
3229  unsigned Opc = SubAdd->getOpcode();
3230  bool IsSub = Opc == ARM::SUBrr || Opc == ARM::t2SUBrr ||
3231  Opc == ARM::SUBri || Opc == ARM::t2SUBri ||
3232  Opc == ARM::tSUBrr || Opc == ARM::tSUBi3 ||
3233  Opc == ARM::tSUBi8;
3234  unsigned OpI = Opc != ARM::tSUBrr ? 1 : 2;
3235  if (!IsSub ||
3236  (SrcReg2 != 0 && SubAdd->getOperand(OpI).getReg() == SrcReg2 &&
3237  SubAdd->getOperand(OpI + 1).getReg() == SrcReg)) {
3238  // VSel doesn't support condition code update.
3239  if (IsInstrVSel)
3240  return false;
3241  // Ensure we can swap the condition.
3243  if (NewCC == ARMCC::AL)
3244  return false;
3245  OperandsToUpdate.push_back(
3246  std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
3247  }
3248  } else {
3249  // No SubAdd, so this is x = <op> y, z; cmp x, 0.
3250  switch (CC) {
3251  case ARMCC::EQ: // Z
3252  case ARMCC::NE: // Z
3253  case ARMCC::MI: // N
3254  case ARMCC::PL: // N
3255  case ARMCC::AL: // none
3256  // CPSR can be used multiple times, we should continue.
3257  break;
3258  case ARMCC::HS: // C
3259  case ARMCC::LO: // C
3260  case ARMCC::VS: // V
3261  case ARMCC::VC: // V
3262  case ARMCC::HI: // C Z
3263  case ARMCC::LS: // C Z
3264  case ARMCC::GE: // N V
3265  case ARMCC::LT: // N V
3266  case ARMCC::GT: // Z N V
3267  case ARMCC::LE: // Z N V
3268  // The instruction uses the V bit or C bit which is not safe.
3269  return false;
3270  }
3271  }
3272  }
3273  }
3274 
3275  // If CPSR is not killed nor re-defined, we should check whether it is
3276  // live-out. If it is live-out, do not optimize.
3277  if (!isSafe) {
3278  MachineBasicBlock *MBB = CmpInstr.getParent();
3279  for (MachineBasicBlock *Succ : MBB->successors())
3280  if (Succ->isLiveIn(ARM::CPSR))
3281  return false;
3282  }
3283 
3284  // Toggle the optional operand to CPSR (if it exists - in Thumb1 we always
3285  // set CPSR so this is represented as an explicit output)
3286  if (!IsThumb1) {
3287  unsigned CPSRRegNum = MI->getNumExplicitOperands() - 1;
3288  MI->getOperand(CPSRRegNum).setReg(ARM::CPSR);
3289  MI->getOperand(CPSRRegNum).setIsDef(true);
3290  }
3291  assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
3292  CmpInstr.eraseFromParent();
3293 
3294  // Modify the condition code of operands in OperandsToUpdate.
3295  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
3296  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3297  for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
3298  OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
3299 
3300  MI->clearRegisterDeads(ARM::CPSR);
3301 
3302  return true;
3303 }
3304 
3306  // Do not sink MI if it might be used to optimize a redundant compare.
3307  // We heuristically only look at the instruction immediately following MI to
3308  // avoid potentially searching the entire basic block.
3309  if (isPredicated(MI))
3310  return true;
3312  ++Next;
3313  Register SrcReg, SrcReg2;
3314  int64_t CmpMask, CmpValue;
3315  bool IsThumb1;
3316  if (Next != MI.getParent()->end() &&
3317  analyzeCompare(*Next, SrcReg, SrcReg2, CmpMask, CmpValue) &&
3318  isRedundantFlagInstr(&*Next, SrcReg, SrcReg2, CmpValue, &MI, IsThumb1))
3319  return false;
3320  return true;
3321 }
3322 
3324  Register Reg,
3325  MachineRegisterInfo *MRI) const {
3326  // Fold large immediates into add, sub, or, xor.
3327  unsigned DefOpc = DefMI.getOpcode();
3328  if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
3329  return false;
3330  if (!DefMI.getOperand(1).isImm())
3331  // Could be t2MOVi32imm @xx
3332  return false;
3333 
3334  if (!MRI->hasOneNonDBGUse(Reg))
3335  return false;
3336 
3337  const MCInstrDesc &DefMCID = DefMI.getDesc();
3338  if (DefMCID.hasOptionalDef()) {
3339  unsigned NumOps = DefMCID.getNumOperands();
3340  const MachineOperand &MO = DefMI.getOperand(NumOps - 1);
3341  if (MO.getReg() == ARM::CPSR && !MO.isDead())
3342  // If DefMI defines CPSR and it is not dead, it's obviously not safe
3343  // to delete DefMI.
3344  return false;
3345  }
3346 
3347  const MCInstrDesc &UseMCID = UseMI.getDesc();
3348  if (UseMCID.hasOptionalDef()) {
3349  unsigned NumOps = UseMCID.getNumOperands();
3350  if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR)
3351  // If the instruction sets the flag, do not attempt this optimization
3352  // since it may change the semantics of the code.
3353  return false;
3354  }
3355 
3356  unsigned UseOpc = UseMI.getOpcode();
3357  unsigned NewUseOpc = 0;
3358  uint32_t ImmVal = (uint32_t)DefMI.getOperand(1).getImm();
3359  uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
3360  bool Commute = false;
3361  switch (UseOpc) {
3362  default: return false;
3363  case ARM::SUBrr:
3364  case ARM::ADDrr:
3365  case ARM::ORRrr:
3366  case ARM::EORrr:
3367  case ARM::t2SUBrr:
3368  case ARM::t2ADDrr:
3369  case ARM::t2ORRrr:
3370  case ARM::t2EORrr: {
3371  Commute = UseMI.getOperand(2).getReg() != Reg;
3372  switch (UseOpc) {
3373  default: break;
3374  case ARM::ADDrr:
3375  case ARM::SUBrr:
3376  if (UseOpc == ARM::SUBrr && Commute)
3377  return false;
3378 
3379  // ADD/SUB are special because they're essentially the same operation, so
3380  // we can handle a larger range of immediates.
3381  if (ARM_AM::isSOImmTwoPartVal(ImmVal))
3382  NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
3383  else if (ARM_AM::isSOImmTwoPartVal(-ImmVal)) {
3384  ImmVal = -ImmVal;
3385  NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
3386  } else
3387  return false;
3388  SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
3389  SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
3390  break;
3391  case ARM::ORRrr:
3392  case ARM::EORrr:
3393  if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
3394  return false;
3395  SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
3396  SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
3397  switch (UseOpc) {
3398  default: break;
3399  case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
3400  case ARM::EORrr: NewUseOpc = ARM::EORri; break;
3401  }
3402  break;
3403  case ARM::t2ADDrr:
3404  case ARM::t2SUBrr: {
3405  if (UseOpc == ARM::t2SUBrr && Commute)
3406  return false;
3407 
3408  // ADD/SUB are special because they're essentially the same operation, so
3409  // we can handle a larger range of immediates.
3410  const bool ToSP = DefMI.getOperand(0).getReg() == ARM::SP;
3411  const unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri;
3412  const unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri;
3413  if (ARM_AM::isT2SOImmTwoPartVal(ImmVal))
3414  NewUseOpc = UseOpc == ARM::t2ADDrr ? t2ADD : t2SUB;
3415  else if (ARM_AM::isT2SOImmTwoPartVal(-ImmVal)) {
3416  ImmVal = -ImmVal;
3417  NewUseOpc = UseOpc == ARM::t2ADDrr ? t2SUB : t2ADD;
3418  } else
3419  return false;
3420  SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
3421  SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
3422  break;
3423  }
3424  case ARM::t2ORRrr:
3425  case ARM::t2EORrr:
3426  if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
3427  return false;
3428  SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
3429  SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
3430  switch (UseOpc) {
3431  default: break;
3432  case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
3433  case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
3434  }
3435  break;
3436  }
3437  }
3438  }
3439 
3440  unsigned OpIdx = Commute ? 2 : 1;
3441  Register Reg1 = UseMI.getOperand(OpIdx).getReg();
3442  bool isKill = UseMI.getOperand(OpIdx).isKill();
3443  const TargetRegisterClass *TRC = MRI->getRegClass(Reg);
3444  Register NewReg = MRI->createVirtualRegister(TRC);
3445  BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
3446  NewReg)
3447  .addReg(Reg1, getKillRegState(isKill))
3448  .addImm(SOImmValV1)
3449  .add(predOps(ARMCC::AL))
3450  .add(condCodeOp());
3451  UseMI.setDesc(get(NewUseOpc));
3452  UseMI.getOperand(1).setReg(NewReg);
3453  UseMI.getOperand(1).setIsKill();
3454  UseMI.getOperand(2).ChangeToImmediate(SOImmValV2);
3455  DefMI.eraseFromParent();
3456  // FIXME: t2ADDrr should be split, as different rulles apply when writing to SP.
3457  // Just as t2ADDri, that was split to [t2ADDri, t2ADDspImm].
3458  // Then the below code will not be needed, as the input/output register
3459  // classes will be rgpr or gprSP.
3460  // For now, we fix the UseMI operand explicitly here:
3461  switch(NewUseOpc){
3462  case ARM::t2ADDspImm:
3463  case ARM::t2SUBspImm:
3464  case ARM::t2ADDri:
3465  case ARM::t2SUBri:
3466  MRI->constrainRegClass(UseMI.getOperand(0).getReg(), TRC);
3467  }
3468  return true;
3469 }
3470 
3471 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
3472  const MachineInstr &MI) {
3473  switch (MI.getOpcode()) {
3474  default: {
3475  const MCInstrDesc &Desc = MI.getDesc();
3476  int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
3477  assert(UOps >= 0 && "bad # UOps");
3478  return UOps;
3479  }
3480 
3481  case ARM::LDRrs:
3482  case ARM::LDRBrs:
3483  case ARM::STRrs:
3484  case ARM::STRBrs: {
3485  unsigned ShOpVal = MI.getOperand(3).getImm();
3486  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3487  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3488  if (!isSub &&
3489  (ShImm == 0 ||
3490  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3491  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3492  return 1;
3493  return 2;
3494  }
3495 
3496  case ARM::LDRH:
3497  case ARM::STRH: {
3498  if (!MI.getOperand(2).getReg())
3499  return 1;
3500 
3501  unsigned ShOpVal = MI.getOperand(3).getImm();
3502  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3503  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3504  if (!isSub &&
3505  (ShImm == 0 ||
3506  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3507  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3508  return 1;
3509  return 2;
3510  }
3511 
3512  case ARM::LDRSB:
3513  case ARM::LDRSH:
3514  return (ARM_AM::getAM3Op(MI.getOperand(3).getImm()) == ARM_AM::sub) ? 3 : 2;
3515 
3516  case ARM::LDRSB_POST:
3517  case ARM::LDRSH_POST: {
3518  Register Rt = MI.getOperand(0).getReg();
3519  Register Rm = MI.getOperand(3).getReg();
3520  return (Rt == Rm) ? 4 : 3;
3521  }
3522 
3523  case ARM::LDR_PRE_REG:
3524  case ARM::LDRB_PRE_REG: {
3525  Register Rt = MI.getOperand(0).getReg();
3526  Register Rm = MI.getOperand(3).getReg();
3527  if (Rt == Rm)
3528  return 3;
3529  unsigned ShOpVal = MI.getOperand(4).getImm();
3530  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3531  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3532  if (!isSub &&
3533  (ShImm == 0 ||
3534  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3535  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3536  return 2;
3537  return 3;
3538  }
3539 
3540  case ARM::STR_PRE_REG:
3541  case ARM::STRB_PRE_REG: {
3542  unsigned ShOpVal = MI.getOperand(4).getImm();
3543  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3544  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3545  if (!isSub &&
3546  (ShImm == 0 ||
3547  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3548  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3549  return 2;
3550  return 3;
3551  }
3552 
3553  case ARM::LDRH_PRE:
3554  case ARM::STRH_PRE: {
3555  Register Rt = MI.getOperand(0).getReg();
3556  Register Rm = MI.getOperand(3).getReg();
3557  if (!Rm)
3558  return 2;
3559  if (Rt == Rm)
3560  return 3;
3561  return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 3 : 2;
3562  }
3563 
3564  case ARM::LDR_POST_REG:
3565  case ARM::LDRB_POST_REG:
3566  case ARM::LDRH_POST: {
3567  Register Rt = MI.getOperand(0).getReg();
3568  Register Rm = MI.getOperand(3).getReg();
3569  return (Rt == Rm) ? 3 : 2;
3570  }
3571 
3572  case ARM::LDR_PRE_IMM:
3573  case ARM::LDRB_PRE_IMM:
3574  case ARM::LDR_POST_IMM:
3575  case ARM::LDRB_POST_IMM:
3576  case ARM::STRB_POST_IMM:
3577  case ARM::STRB_POST_REG:
3578  case ARM::STRB_PRE_IMM:
3579  case ARM::STRH_POST:
3580  case ARM::STR_POST_IMM:
3581  case ARM::STR_POST_REG:
3582  case ARM::STR_PRE_IMM:
3583  return 2;
3584 
3585  case ARM::LDRSB_PRE:
3586  case ARM::LDRSH_PRE: {
3587  Register Rm = MI.getOperand(3).getReg();
3588  if (Rm == 0)
3589  return 3;
3590  Register Rt = MI.getOperand(0).getReg();
3591  if (Rt == Rm)
3592  return 4;
3593  unsigned ShOpVal = MI.getOperand(4).getImm();
3594  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3595  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3596  if (!isSub &&
3597  (ShImm == 0 ||
3598  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3599  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3600  return 3;
3601  return 4;
3602  }
3603 
3604  case ARM::LDRD: {
3605  Register Rt = MI.getOperand(0).getReg();
3606  Register Rn = MI.getOperand(2).getReg();
3607  Register Rm = MI.getOperand(3).getReg();
3608  if (Rm)
3609  return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3610  : 3;
3611  return (Rt == Rn) ? 3 : 2;
3612  }
3613 
3614  case ARM::STRD: {
3615  Register Rm = MI.getOperand(3).getReg();
3616  if (Rm)
3617  return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3618  : 3;
3619  return 2;
3620  }
3621 
3622  case ARM::LDRD_POST:
3623  case ARM::t2LDRD_POST:
3624  return 3;
3625 
3626  case ARM::STRD_POST:
3627  case ARM::t2STRD_POST:
3628  return 4;
3629 
3630  case ARM::LDRD_PRE: {
3631  Register Rt = MI.getOperand(0).getReg();
3632  Register Rn = MI.getOperand(3).getReg();
3633  Register Rm = MI.getOperand(4).getReg();
3634  if (Rm)
3635  return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3636  : 4;
3637  return (Rt == Rn) ? 4 : 3;
3638  }
3639 
3640  case ARM::t2LDRD_PRE: {
3641  Register Rt = MI.getOperand(0).getReg();
3642  Register Rn = MI.getOperand(3).getReg();
3643  return (Rt == Rn) ? 4 : 3;
3644  }
3645 
3646  case ARM::STRD_PRE: {
3647  Register Rm = MI.getOperand(4).getReg();
3648  if (Rm)
3649  return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3650  : 4;
3651  return 3;
3652  }
3653 
3654  case ARM::t2STRD_PRE:
3655  return 3;
3656 
3657  case ARM::t2LDR_POST:
3658  case ARM::t2LDRB_POST:
3659  case ARM::t2LDRB_PRE:
3660  case ARM::t2LDRSBi12:
3661  case ARM::t2LDRSBi8:
3662  case ARM::t2LDRSBpci:
3663  case ARM::t2LDRSBs:
3664  case ARM::t2LDRH_POST:
3665  case ARM::t2LDRH_PRE:
3666  case ARM::t2LDRSBT:
3667  case ARM::t2LDRSB_POST:
3668  case ARM::t2LDRSB_PRE:
3669  case ARM::t2LDRSH_POST:
3670  case ARM::t2LDRSH_PRE:
3671  case ARM::t2LDRSHi12:
3672  case ARM::t2LDRSHi8:
3673  case ARM::t2LDRSHpci:
3674  case ARM::t2LDRSHs:
3675  return 2;
3676 
3677  case ARM::t2LDRDi8: {
3678  Register Rt = MI.getOperand(0).getReg();
3679  Register Rn = MI.getOperand(2).getReg();
3680  return (Rt == Rn) ? 3 : 2;
3681  }
3682 
3683  case ARM::t2STRB_POST:
3684  case ARM::t2STRB_PRE:
3685  case ARM::t2STRBs:
3686  case ARM::t2STRDi8:
3687  case ARM::t2STRH_POST:
3688  case ARM::t2STRH_PRE:
3689  case ARM::t2STRHs:
3690  case ARM::t2STR_POST:
3691  case ARM::t2STR_PRE:
3692  case ARM::t2STRs:
3693  return 2;
3694  }
3695 }
3696 
3697 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
3698 // can't be easily determined return 0 (missing MachineMemOperand).
3699 //
3700 // FIXME: The current MachineInstr design does not support relying on machine
3701 // mem operands to determine the width of a memory access. Instead, we expect
3702 // the target to provide this information based on the instruction opcode and
3703 // operands. However, using MachineMemOperand is the best solution now for
3704 // two reasons:
3705 //
3706 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
3707 // operands. This is much more dangerous than using the MachineMemOperand
3708 // sizes because CodeGen passes can insert/remove optional machine operands. In
3709 // fact, it's totally incorrect for preRA passes and appears to be wrong for
3710 // postRA passes as well.
3711 //
3712 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
3713 // machine model that calls this should handle the unknown (zero size) case.
3714 //
3715 // Long term, we should require a target hook that verifies MachineMemOperand
3716 // sizes during MC lowering. That target hook should be local to MC lowering
3717 // because we can't ensure that it is aware of other MI forms. Doing this will
3718 // ensure that MachineMemOperands are correctly propagated through all passes.
3720  unsigned Size = 0;
3721  for (MachineInstr::mmo_iterator I = MI.memoperands_begin(),
3722  E = MI.memoperands_end();
3723  I != E; ++I) {
3724  Size += (*I)->getSize();
3725  }
3726  // FIXME: The scheduler currently can't handle values larger than 16. But
3727  // the values can actually go up to 32 for floating-point load/store
3728  // multiple (VLDMIA etc.). Also, the way this code is reasoning about memory
3729  // operations isn't right; we could end up with "extra" memory operands for
3730  // various reasons, like tail merge merging two memory operations.
3731  return std::min(Size / 4, 16U);
3732 }
3733 
3734 static unsigned getNumMicroOpsSingleIssuePlusExtras(unsigned Opc,
3735  unsigned NumRegs) {
3736  unsigned UOps = 1 + NumRegs; // 1 for address computation.
3737  switch (Opc) {
3738  default:
3739  break;
3740  case ARM::VLDMDIA_UPD:
3741  case ARM::VLDMDDB_UPD:
3742  case ARM::VLDMSIA_UPD:
3743  case ARM::VLDMSDB_UPD:
3744  case ARM::VSTMDIA_UPD:
3745  case ARM::VSTMDDB_UPD:
3746  case ARM::VSTMSIA_UPD:
3747  case ARM::VSTMSDB_UPD:
3748  case ARM::LDMIA_UPD:
3749  case ARM::LDMDA_UPD:
3750  case ARM::LDMDB_UPD:
3751  case ARM::LDMIB_UPD:
3752  case ARM::STMIA_UPD:
3753  case ARM::STMDA_UPD:
3754  case ARM::STMDB_UPD:
3755  case ARM::STMIB_UPD:
3756  case ARM::tLDMIA_UPD:
3757  case ARM::tSTMIA_UPD:
3758  case ARM::t2LDMIA_UPD:
3759  case ARM::t2LDMDB_UPD:
3760  case ARM::t2STMIA_UPD:
3761  case ARM::t2STMDB_UPD:
3762  ++UOps; // One for base register writeback.
3763  break;
3764  case ARM::LDMIA_RET:
3765  case ARM::tPOP_RET:
3766  case ARM::t2LDMIA_RET:
3767  UOps += 2; // One for base reg wb, one for write to pc.
3768  break;
3769  }
3770  return UOps;
3771 }
3772 
3774  const MachineInstr &MI) const {
3775  if (!ItinData || ItinData->isEmpty())
3776  return 1;
3777 
3778  const MCInstrDesc &Desc = MI.getDesc();
3779  unsigned Class = Desc.getSchedClass();
3780  int ItinUOps = ItinData->getNumMicroOps(Class);
3781  if (ItinUOps >= 0) {
3782  if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
3783  return getNumMicroOpsSwiftLdSt(ItinData, MI);
3784 
3785  return ItinUOps;
3786  }
3787 
3788  unsigned Opc = MI.getOpcode();
3789  switch (Opc) {
3790  default:
3791  llvm_unreachable("Unexpected multi-uops instruction!");
3792  case ARM::VLDMQIA:
3793  case ARM::VSTMQIA:
3794  return 2;
3795 
3796  // The number of uOps for load / store multiple are determined by the number
3797  // registers.
3798  //
3799  // On Cortex-A8, each pair of register loads / stores can be scheduled on the
3800  // same cycle. The scheduling for the first load / store must be done
3801  // separately by assuming the address is not 64-bit aligned.
3802  //
3803  // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
3804  // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
3805  // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
3806  case ARM::VLDMDIA:
3807  case ARM::VLDMDIA_UPD:
3808  case ARM::VLDMDDB_UPD:
3809  case ARM::VLDMSIA:
3810  case ARM::VLDMSIA_UPD:
3811  case ARM::VLDMSDB_UPD:
3812  case ARM::VSTMDIA:
3813  case ARM::VSTMDIA_UPD:
3814  case ARM::VSTMDDB_UPD:
3815  case ARM::VSTMSIA:
3816  case ARM::VSTMSIA_UPD:
3817  case ARM::VSTMSDB_UPD: {
3818  unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands();
3819  return (NumRegs / 2) + (NumRegs % 2) + 1;
3820  }
3821 
3822  case ARM::LDMIA_RET:
3823  case ARM::LDMIA:
3824  case ARM::LDMDA:
3825  case ARM::LDMDB:
3826  case ARM::LDMIB:
3827  case ARM::LDMIA_UPD:
3828  case ARM::LDMDA_UPD:
3829  case ARM::LDMDB_UPD:
3830  case ARM::LDMIB_UPD:
3831  case ARM::STMIA:
3832  case ARM::STMDA:
3833  case ARM::STMDB:
3834  case ARM::STMIB:
3835  case ARM::STMIA_UPD:
3836  case ARM::STMDA_UPD:
3837  case ARM::STMDB_UPD:
3838  case ARM::STMIB_UPD:
3839  case ARM::tLDMIA:
3840  case ARM::tLDMIA_UPD:
3841  case ARM::tSTMIA_UPD:
3842  case ARM::tPOP_RET:
3843  case ARM::tPOP:
3844  case ARM::tPUSH:
3845  case ARM::t2LDMIA_RET:
3846  case ARM::t2LDMIA:
3847  case ARM::t2LDMDB:
3848  case ARM::t2LDMIA_UPD:
3849  case ARM::t2LDMDB_UPD:
3850  case ARM::t2STMIA:
3851  case ARM::t2STMDB:
3852  case ARM::t2STMIA_UPD:
3853  case ARM::t2STMDB_UPD: {
3854  unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands() + 1;
3855  switch (Subtarget.getLdStMultipleTiming()) {
3857  return getNumMicroOpsSingleIssuePlusExtras(Opc, NumRegs);
3859  // Assume the worst.
3860  return NumRegs;
3862  if (NumRegs < 4)
3863  return 2;
3864  // 4 registers would be issued: 2, 2.
3865  // 5 registers would be issued: 2, 2, 1.
3866  unsigned UOps = (NumRegs / 2);
3867  if (NumRegs % 2)
3868  ++UOps;
3869  return UOps;
3870  }
3872  unsigned UOps = (NumRegs / 2);
3873  // If there are odd number of registers or if it's not 64-bit aligned,
3874  // then it takes an extra AGU (Address Generation Unit) cycle.
3875  if ((NumRegs % 2) || !MI.hasOneMemOperand() ||
3876  (*MI.memoperands_begin())->getAlign() < Align(8))
3877  ++UOps;
3878  return UOps;
3879  }
3880  }
3881  }
3882  }
3883  llvm_unreachable("Didn't find the number of microops");
3884 }
3885 
3886 int
3887 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3888  const MCInstrDesc &DefMCID,
3889  unsigned DefClass,
3890  unsigned DefIdx, unsigned DefAlign) const {
3891  int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3892  if (RegNo <= 0)
3893  // Def is the address writeback.
3894  return ItinData->getOperandCycle(DefClass, DefIdx);
3895 
3896  int DefCycle;
3897  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3898  // (regno / 2) + (regno % 2) + 1
3899  DefCycle = RegNo / 2 + 1;
3900  if (RegNo % 2)
3901  ++DefCycle;
3902  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3903  DefCycle = RegNo;
3904  bool isSLoad = false;
3905 
3906  switch (DefMCID.getOpcode()) {
3907  default: break;
3908  case ARM::VLDMSIA:
3909  case ARM::VLDMSIA_UPD:
3910  case ARM::VLDMSDB_UPD:
3911  isSLoad = true;
3912  break;
3913  }
3914 
3915  // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3916  // then it takes an extra cycle.
3917  if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3918  ++DefCycle;
3919  } else {
3920  // Assume the worst.
3921  DefCycle = RegNo + 2;
3922  }
3923 
3924  return DefCycle;
3925 }
3926 
3927 int
3928 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3929  const MCInstrDesc &DefMCID,
3930  unsigned DefClass,
3931  unsigned DefIdx, unsigned DefAlign) const {
3932  int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3933  if (RegNo <= 0)
3934  // Def is the address writeback.
3935  return ItinData->getOperandCycle(DefClass, DefIdx);
3936 
3937  int DefCycle;
3938  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3939  // 4 registers would be issued: 1, 2, 1.
3940  // 5 registers would be issued: 1, 2, 2.
3941  DefCycle = RegNo / 2;
3942  if (DefCycle < 1)
3943  DefCycle = 1;
3944  // Result latency is issue cycle + 2: E2.
3945  DefCycle += 2;
3946  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3947  DefCycle = (RegNo / 2);
3948  // If there are odd number of registers or if it's not 64-bit aligned,
3949  // then it takes an extra AGU (Address Generation Unit) cycle.
3950  if ((RegNo % 2) || DefAlign < 8)
3951  ++DefCycle;
3952  // Result latency is AGU cycles + 2.
3953  DefCycle += 2;
3954  } else {
3955  // Assume the worst.
3956  DefCycle = RegNo + 2;
3957  }
3958 
3959  return DefCycle;
3960 }
3961 
3962 int
3963 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3964  const MCInstrDesc &UseMCID,
3965  unsigned UseClass,
3966  unsigned UseIdx, unsigned UseAlign) const {
3967  int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3968  if (RegNo <= 0)
3969  return ItinData->getOperandCycle(UseClass, UseIdx);
3970 
3971  int UseCycle;
3972  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3973  // (regno / 2) + (regno % 2) + 1
3974  UseCycle = RegNo / 2 + 1;
3975  if (RegNo % 2)
3976  ++UseCycle;
3977  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3978  UseCycle = RegNo;
3979  bool isSStore = false;
3980 
3981  switch (UseMCID.getOpcode()) {
3982  default: break;
3983  case ARM::VSTMSIA:
3984  case ARM::VSTMSIA_UPD:
3985  case ARM::VSTMSDB_UPD:
3986  isSStore = true;
3987  break;
3988  }
3989 
3990  // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3991  // then it takes an extra cycle.
3992  if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3993  ++UseCycle;
3994  } else {
3995  // Assume the worst.
3996  UseCycle = RegNo + 2;
3997  }
3998 
3999  return UseCycle;
4000 }
4001 
4002 int
4003 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
4004  const MCInstrDesc &UseMCID,
4005  unsigned UseClass,
4006  unsigned UseIdx, unsigned UseAlign) const {
4007  int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
4008  if (RegNo <= 0)
4009  return ItinData->getOperandCycle(UseClass, UseIdx);
4010 
4011  int UseCycle;
4012  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
4013  UseCycle = RegNo / 2;
4014  if (UseCycle < 2)
4015  UseCycle = 2;
4016  // Read in E3.
4017  UseCycle += 2;
4018  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
4019  UseCycle = (RegNo / 2);
4020  // If there are odd number of registers or if it's not 64-bit aligned,
4021  // then it takes an extra AGU (Address Generation Unit) cycle.
4022  if ((RegNo % 2) || UseAlign < 8)
4023  ++UseCycle;
4024  } else {
4025  // Assume the worst.
4026  UseCycle = 1;
4027  }
4028  return UseCycle;
4029 }
4030 
4031 int
4033  const MCInstrDesc &DefMCID,
4034  unsigned DefIdx, unsigned DefAlign,
4035  const MCInstrDesc &UseMCID,
4036  unsigned UseIdx, unsigned UseAlign) const {
4037  unsigned DefClass = DefMCID.getSchedClass();
4038  unsigned UseClass = UseMCID.getSchedClass();
4039 
4040  if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
4041  return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
4042 
4043  // This may be a def / use of a variable_ops instruction, the operand
4044  // latency might be determinable dynamically. Let the target try to
4045  // figure it out.
4046  int DefCycle = -1;
4047  bool LdmBypass = false;
4048  switch (DefMCID.getOpcode()) {
4049  default:
4050  DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4051  break;
4052 
4053  case ARM::VLDMDIA:
4054  case ARM::VLDMDIA_UPD:
4055  case ARM::VLDMDDB_UPD:
4056  case ARM::VLDMSIA:
4057  case ARM::VLDMSIA_UPD:
4058  case ARM::VLDMSDB_UPD:
4059  DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4060  break;
4061 
4062  case ARM::LDMIA_RET:
4063  case ARM::LDMIA:
4064  case ARM::LDMDA:
4065  case ARM::LDMDB:
4066  case ARM::LDMIB:
4067  case ARM::LDMIA_UPD:
4068  case ARM::LDMDA_UPD:
4069  case ARM::LDMDB_UPD:
4070  case ARM::LDMIB_UPD:
4071  case ARM::tLDMIA:
4072  case ARM::tLDMIA_UPD:
4073  case ARM::tPUSH:
4074  case ARM::t2LDMIA_RET:
4075  case ARM::t2LDMIA:
4076  case ARM::t2LDMDB:
4077  case ARM::t2LDMIA_UPD:
4078  case ARM::t2LDMDB_UPD:
4079  LdmBypass = true;
4080  DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4081  break;
4082  }
4083 
4084  if (DefCycle == -1)
4085  // We can't seem to determine the result latency of the def, assume it's 2.
4086  DefCycle = 2;
4087 
4088  int UseCycle = -1;
4089  switch (UseMCID.getOpcode()) {
4090  default:
4091  UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
4092  break;
4093 
4094  case ARM::VSTMDIA:
4095  case ARM::VSTMDIA_UPD:
4096  case ARM::VSTMDDB_UPD:
4097  case ARM::VSTMSIA:
4098  case ARM::VSTMSIA_UPD:
4099  case ARM::VSTMSDB_UPD:
4100  UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4101  break;
4102 
4103  case ARM::STMIA:
4104  case ARM::STMDA:
4105  case ARM::STMDB:
4106  case ARM::STMIB:
4107  case ARM::STMIA_UPD:
4108  case ARM::STMDA_UPD:
4109  case ARM::STMDB_UPD:
4110  case ARM::STMIB_UPD:
4111  case ARM::tSTMIA_UPD:
4112  case ARM::tPOP_RET:
4113  case ARM::tPOP:
4114  case ARM::t2STMIA:
4115  case ARM::t2STMDB:
4116  case ARM::t2STMIA_UPD:
4117  case ARM::t2STMDB_UPD:
4118  UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4119  break;
4120  }
4121 
4122  if (UseCycle == -1)
4123  // Assume it's read in the first stage.
4124  UseCycle = 1;
4125 
4126  UseCycle = DefCycle - UseCycle + 1;
4127  if (UseCycle > 0) {
4128  if (LdmBypass) {
4129  // It's a variable_ops instruction so we can't use DefIdx here. Just use
4130  // first def operand.
4131  if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
4132  UseClass, UseIdx))
4133  --UseCycle;
4134  } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
4135  UseClass, UseIdx)) {
4136  --UseCycle;
4137  }
4138  }
4139 
4140  return UseCycle;
4141 }
4142 
4144  const MachineInstr *MI, unsigned Reg,
4145  unsigned &DefIdx, unsigned &Dist) {
4146  Dist = 0;
4147 
4149  MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
4150  assert(II->isInsideBundle() && "Empty bundle?");
4151 
4152  int Idx = -1;
4153  while (II->isInsideBundle()) {
4154  Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
4155  if (Idx != -1)
4156  break;
4157  --II;
4158  ++Dist;
4159  }
4160 
4161  assert(Idx != -1 && "Cannot find bundled definition!");
4162  DefIdx = Idx;
4163  return &*II;
4164 }
4165 
4167  const MachineInstr &MI, unsigned Reg,
4168  unsigned &UseIdx, unsigned &Dist) {
4169  Dist = 0;
4170 
4171  MachineBasicBlock::const_instr_iterator II = ++MI.getIterator();
4172  assert(II->isInsideBundle() && "Empty bundle?");
4173  MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
4174 
4175  // FIXME: This doesn't properly handle multiple uses.
4176  int Idx = -1;
4177  while (II != E && II->isInsideBundle()) {
4178  Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
4179  if (Idx != -1)
4180  break;
4181  if (II->getOpcode() != ARM::t2IT)
4182  ++Dist;
4183  ++II;
4184  }
4185 
4186  if (Idx == -1) {
4187  Dist = 0;
4188  return nullptr;
4189  }
4190 
4191  UseIdx = Idx;
4192  return &*II;
4193 }
4194 
4195 /// Return the number of cycles to add to (or subtract from) the static
4196 /// itinerary based on the def opcode and alignment. The caller will ensure that
4197 /// adjusted latency is at least one cycle.
4198 static int adjustDefLatency(const ARMSubtarget &Subtarget,
4199  const MachineInstr &DefMI,
4200  const MCInstrDesc &DefMCID, unsigned DefAlign) {
4201  int Adjust = 0;
4202  if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
4203  // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
4204  // variants are one cycle cheaper.
4205  switch (DefMCID.getOpcode()) {
4206  default: break;
4207  case ARM::LDRrs:
4208  case ARM::LDRBrs: {
4209  unsigned ShOpVal = DefMI.getOperand(3).getImm();
4210  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4211  if (ShImm == 0 ||
4212  (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
4213  --Adjust;
4214  break;
4215  }
4216  case ARM::t2LDRs:
4217  case ARM::t2LDRBs:
4218  case ARM::t2LDRHs:
4219  case ARM::t2LDRSHs: {
4220  // Thumb2 mode: lsl only.
4221  unsigned ShAmt = DefMI.getOperand(3).getImm();
4222  if (ShAmt == 0 || ShAmt == 2)
4223  --Adjust;
4224  break;
4225  }
4226  }
4227  } else if (Subtarget.isSwift()) {
4228  // FIXME: Properly handle all of the latency adjustments for address
4229  // writeback.
4230  switch (DefMCID.getOpcode()) {
4231  default: break;
4232  case ARM::LDRrs:
4233  case ARM::LDRBrs: {
4234  unsigned ShOpVal = DefMI.getOperand(3).getImm();
4235  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
4236  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4237  if (!isSub &&
4238  (ShImm == 0 ||
4239  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
4240  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
4241  Adjust -= 2;
4242  else if (!isSub &&
4243  ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
4244  --Adjust;
4245  break;
4246  }
4247  case ARM::t2LDRs:
4248  case ARM::t2LDRBs:
4249  case ARM::t2LDRHs:
4250  case ARM::t2LDRSHs: {
4251  // Thumb2 mode: lsl only.
4252  unsigned ShAmt = DefMI.getOperand(3).getImm();
4253  if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
4254  Adjust -= 2;
4255  break;
4256  }
4257  }
4258  }
4259 
4260  if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment()) {
4261  switch (DefMCID.getOpcode()) {
4262  default: break;
4263  case ARM::VLD1q8:
4264  case ARM::VLD1q16:
4265  case ARM::VLD1q32:
4266  case ARM::VLD1q64:
4267  case ARM::VLD1q8wb_fixed:
4268  case ARM::VLD1q16wb_fixed:
4269  case ARM::VLD1q32wb_fixed:
4270  case ARM::VLD1q64wb_fixed:
4271  case ARM::VLD1q8wb_register:
4272  case ARM::VLD1q16wb_register:
4273  case ARM::VLD1q32wb_register:
4274  case ARM::VLD1q64wb_register:
4275  case ARM::VLD2d8:
4276  case ARM::VLD2d16:
4277  case ARM::VLD2d32:
4278  case ARM::VLD2q8:
4279  case ARM::VLD2q16:
4280  case ARM::VLD2q32:
4281  case ARM::VLD2d8wb_fixed:
4282  case ARM::VLD2d16wb_fixed:
4283  case ARM::VLD2d32wb_fixed:
4284  case ARM::VLD2q8wb_fixed:
4285  case ARM::VLD2q16wb_fixed:
4286  case ARM::VLD2q32wb_fixed:
4287  case ARM::VLD2d8wb_register:
4288  case ARM::VLD2d16wb_register:
4289  case ARM::VLD2d32wb_register:
4290  case ARM::VLD2q8wb_register:
4291  case ARM::VLD2q16wb_register:
4292  case ARM::VLD2q32wb_register:
4293  case ARM::VLD3d8:
4294  case ARM::VLD3d16:
4295  case ARM::VLD3d32:
4296  case ARM::VLD1d64T:
4297  case ARM::VLD3d8_UPD:
4298  case ARM::VLD3d16_UPD:
4299  case ARM::VLD3d32_UPD:
4300  case ARM::VLD1d64Twb_fixed:
4301  case ARM::VLD1d64Twb_register:
4302  case ARM::VLD3q8_UPD:
4303  case ARM::VLD3q16_UPD:
4304  case ARM::VLD3q32_UPD:
4305  case ARM::VLD4d8:
4306  case ARM::VLD4d16:
4307  case ARM::VLD4d32:
4308  case ARM::VLD1d64Q:
4309  case ARM::VLD4d8_UPD:
4310  case ARM::VLD4d16_UPD:
4311  case ARM::VLD4d32_UPD:
4312  case ARM::VLD1d64Qwb_fixed:
4313  case ARM::VLD1d64Qwb_register:
4314  case ARM::VLD4q8_UPD:
4315  case ARM::VLD4q16_UPD:
4316  case ARM::VLD4q32_UPD:
4317  case ARM::VLD1DUPq8:
4318  case ARM::VLD1DUPq16:
4319  case ARM::VLD1DUPq32:
4320  case ARM::VLD1DUPq8wb_fixed:
4321  case ARM::VLD1DUPq16wb_fixed:
4322  case ARM::VLD1DUPq32wb_fixed:
4323  case ARM::VLD1DUPq8wb_register:
4324  case ARM::VLD1DUPq16wb_register:
4325  case ARM::VLD1DUPq32wb_register:
4326  case ARM::VLD2DUPd8:
4327  case ARM::VLD2DUPd16:
4328  case ARM::VLD2DUPd32:
4329  case ARM::VLD2DUPd8wb_fixed:
4330  case ARM::VLD2DUPd16wb_fixed:
4331  case ARM::VLD2DUPd32wb_fixed:
4332  case ARM::VLD2DUPd8wb_register:
4333  case ARM::VLD2DUPd16wb_register:
4334  case ARM::VLD2DUPd32wb_register:
4335  case ARM::VLD4DUPd8:
4336  case ARM::VLD4DUPd16:
4337  case ARM::VLD4DUPd32:
4338  case ARM::VLD4DUPd8_UPD:
4339  case ARM::VLD4DUPd16_UPD:
4340  case ARM::VLD4DUPd32_UPD:
4341  case ARM::VLD1LNd8:
4342  case ARM::VLD1LNd16:
4343  case ARM::VLD1LNd32:
4344  case ARM::VLD1LNd8_UPD:
4345  case ARM::VLD1LNd16_UPD:
4346  case ARM::VLD1LNd32_UPD:
4347  case ARM::VLD2LNd8:
4348  case ARM::VLD2LNd16:
4349  case ARM::VLD2LNd32:
4350  case ARM::VLD2LNq16:
4351  case ARM::VLD2LNq32:
4352  case ARM::VLD2LNd8_UPD:
4353  case ARM::VLD2LNd16_UPD:
4354  case ARM::VLD2LNd32_UPD:
4355  case ARM::VLD2LNq16_UPD:
4356  case ARM::VLD2LNq32_UPD:
4357  case ARM::VLD4LNd8:
4358  case ARM::VLD4LNd16:
4359  case ARM::VLD4LNd32:
4360  case ARM::VLD4LNq16:
4361  case ARM::VLD4LNq32:
4362  case ARM::VLD4LNd8_UPD:
4363  case ARM::VLD4LNd16_UPD:
4364  case ARM::VLD4LNd32_UPD:
4365  case ARM::VLD4LNq16_UPD:
4366  case ARM::VLD4LNq32_UPD:
4367  // If the address is not 64-bit aligned, the latencies of these
4368  // instructions increases by one.
4369  ++Adjust;
4370  break;
4371  }
4372  }
4373  return Adjust;
4374 }
4375 
4377  const MachineInstr &DefMI,
4378  unsigned DefIdx,
4379  const MachineInstr &UseMI,
4380  unsigned UseIdx) const {
4381  // No operand latency. The caller may fall back to getInstrLatency.
4382  if (!ItinData || ItinData->isEmpty())
4383  return -1;
4384 
4385  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4386  Register Reg = DefMO.getReg();
4387 
4388  const MachineInstr *ResolvedDefMI = &DefMI;
4389  unsigned DefAdj = 0;
4390  if (DefMI.isBundle())
4391  ResolvedDefMI =
4392  getBundledDefMI(&getRegisterInfo(), &DefMI, Reg, DefIdx, DefAdj);
4393  if (ResolvedDefMI->isCopyLike() || ResolvedDefMI->isInsertSubreg() ||
4394  ResolvedDefMI->isRegSequence() || ResolvedDefMI->isImplicitDef()) {
4395  return 1;
4396  }
4397 
4398  const MachineInstr *ResolvedUseMI = &UseMI;
4399  unsigned UseAdj = 0;
4400  if (UseMI.isBundle()) {
4401  ResolvedUseMI =
4402  getBundledUseMI(&getRegisterInfo(), UseMI, Reg, UseIdx, UseAdj);
4403  if (!ResolvedUseMI)
4404  return -1;
4405  }
4406 
4407  return getOperandLatencyImpl(
4408  ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,
4409  Reg, *ResolvedUseMI, UseIdx, ResolvedUseMI->getDesc(), UseAdj);
4410 }
4411 
4412 int ARMBaseInstrInfo::getOperandLatencyImpl(
4413  const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4414  unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
4415  const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
4416  unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const {
4417  if (Reg == ARM::CPSR) {
4418  if (DefMI.getOpcode() == ARM::FMSTAT) {
4419  // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
4420  return Subtarget.isLikeA9() ? 1 : 20;
4421  }
4422 
4423  // CPSR set and branch can be paired in the same cycle.
4424  if (UseMI.isBranch())
4425  return 0;
4426 
4427  // Otherwise it takes the instruction latency (generally one).
4428  unsigned Latency = getInstrLatency(ItinData, DefMI);
4429 
4430  // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
4431  // its uses. Instructions which are otherwise scheduled between them may
4432  // incur a code size penalty (not able to use the CPSR setting 16-bit
4433  // instructions).
4434  if (Latency > 0 && Subtarget.isThumb2()) {
4435  const MachineFunction *MF = DefMI.getParent()->getParent();
4436  // FIXME: Use Function::hasOptSize().
4437  if (MF->getFunction().hasFnAttribute(Attribute::OptimizeForSize))
4438  --Latency;
4439  }
4440  return Latency;
4441  }
4442 
4443  if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
4444  return -1;
4445 
4446  unsigned DefAlign = DefMI.hasOneMemOperand()
4447  ? (*DefMI.memoperands_begin())->getAlign().value()
4448  : 0;
4449  unsigned UseAlign = UseMI.hasOneMemOperand()
4450  ? (*UseMI.memoperands_begin())->getAlign().value()
4451  : 0;
4452 
4453  // Get the itinerary's latency if possible, and handle variable_ops.
4454  int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID,
4455  UseIdx, UseAlign);
4456  // Unable to find operand latency. The caller may resort to getInstrLatency.
4457  if (Latency < 0)
4458  return Latency;
4459 
4460  // Adjust for IT block position.
4461  int Adj = DefAdj + UseAdj;
4462 
4463  // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4464  Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
4465  if (Adj >= 0 || (int)Latency > -Adj) {
4466  return Latency + Adj;
4467  }
4468  // Return the itinerary latency, which may be zero but not less than zero.
4469  return Latency;
4470 }
4471 
4472 int
4474  SDNode *DefNode, unsigned DefIdx,
4475  SDNode *UseNode, unsigned UseIdx) const {
4476  if (!DefNode->isMachineOpcode())
4477  return 1;
4478 
4479  const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
4480 
4481  if (isZeroCost(DefMCID.Opcode))
4482  return 0;
4483 
4484  if (!ItinData || ItinData->isEmpty())
4485  return DefMCID.mayLoad() ? 3 : 1;
4486 
4487  if (!UseNode->isMachineOpcode()) {
4488  int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
4489  int Adj = Subtarget.getPreISelOperandLatencyAdjustment();
4490  int Threshold = 1 + Adj;
4491  return Latency <= Threshold ? 1 : Latency - Adj;
4492  }
4493 
4494  const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
4495  auto *DefMN = cast<MachineSDNode>(DefNode);
4496  unsigned DefAlign = !DefMN->memoperands_empty()
4497  ? (*DefMN->memoperands_begin())->getAlign().value()
4498  : 0;
4499  auto *UseMN = cast<MachineSDNode>(UseNode);
4500  unsigned UseAlign = !UseMN->memoperands_empty()
4501  ? (*UseMN->memoperands_begin())->getAlign().value()
4502  : 0;
4503  int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
4504  UseMCID, UseIdx, UseAlign);
4505 
4506  if (Latency > 1 &&
4507  (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
4508  Subtarget.isCortexA7())) {
4509  // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
4510  // variants are one cycle cheaper.
4511  switch (DefMCID.getOpcode()) {
4512  default: break;
4513  case ARM::LDRrs:
4514  case ARM::LDRBrs: {
4515  unsigned ShOpVal =
4516  cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
4517  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4518  if (ShImm == 0 ||
4519  (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
4520  --Latency;
4521  break;
4522  }
4523  case ARM::t2LDRs:
4524  case ARM::t2LDRBs:
4525  case ARM::t2LDRHs:
4526  case ARM::t2LDRSHs: {
4527  // Thumb2 mode: lsl only.
4528  unsigned ShAmt =
4529  cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
4530  if (ShAmt == 0 || ShAmt == 2)
4531  --Latency;
4532  break;
4533  }
4534  }
4535  } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
4536  // FIXME: Properly handle all of the latency adjustments for address
4537  // writeback.
4538  switch (DefMCID.getOpcode()) {
4539  default: break;
4540  case ARM::LDRrs:
4541  case ARM::LDRBrs: {
4542  unsigned ShOpVal =
4543  cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
4544  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4545  if (ShImm == 0 ||
4546  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
4547  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
4548  Latency -= 2;
4549  else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
4550  --Latency;
4551  break;
4552  }
4553  case ARM::t2LDRs:
4554  case ARM::t2LDRBs:
4555  case ARM::t2LDRHs:
4556  case ARM::t2LDRSHs:
4557  // Thumb2 mode: lsl 0-3 only.
4558  Latency -= 2;
4559  break;
4560  }
4561  }
4562 
4563  if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment())
4564  switch (DefMCID.getOpcode()) {
4565  default: break;
4566  case ARM::VLD1q8:
4567  case ARM::VLD1q16:
4568  case ARM::VLD1q32:
4569  case ARM::VLD1q64:
4570  case ARM::VLD1q8wb_register:
4571  case ARM::VLD1q16wb_register:
4572  case ARM::VLD1q32wb_register:
4573  case ARM::VLD1q64wb_register:
4574  case ARM::VLD1q8wb_fixed:
4575  case ARM::VLD1q16wb_fixed:
4576  case ARM::VLD1q32wb_fixed:
4577  case ARM::VLD1q64wb_fixed:
4578  case ARM::VLD2d8:
4579  case ARM::VLD2d16:
4580  case ARM::VLD2d32:
4581  case ARM::VLD2q8Pseudo:
4582  case ARM::VLD2q16Pseudo:
4583  case ARM::VLD2q32Pseudo:
4584  case ARM::VLD2d8wb_fixed:
4585  case ARM::VLD2d16wb_fixed:
4586  case ARM::VLD2d32wb_fixed:
4587  case ARM::VLD2q8PseudoWB_fixed:
4588  case ARM::VLD2q16PseudoWB_fixed:
4589  case ARM::VLD2q32PseudoWB_fixed:
4590  case ARM::VLD2d8wb_register:
4591  case ARM::VLD2d16wb_register:
4592  case ARM::VLD2d32wb_register:
4593  case ARM::VLD2q8PseudoWB_register:
4594  case ARM::VLD2q16PseudoWB_register:
4595  case ARM::VLD2q32PseudoWB_register:
4596  case ARM::VLD3d8Pseudo:
4597  case ARM::VLD3d16Pseudo:
4598  case ARM::VLD3d32Pseudo:
4599  case ARM::VLD1d8TPseudo:
4600  case ARM::VLD1d16TPseudo:
4601  case ARM::VLD1d32TPseudo:
4602  case ARM::VLD1d64TPseudo:
4603  case ARM::VLD1d64TPseudoWB_fixed:
4604  case ARM::VLD1d64TPseudoWB_register:
4605  case ARM::VLD3d8Pseudo_UPD:
4606  case ARM::VLD3d16Pseudo_UPD:
4607  case ARM::VLD3d32Pseudo_UPD:
4608  case ARM::VLD3q8Pseudo_UPD:
4609  case ARM::VLD3q16Pseudo_UPD:
4610  case ARM::VLD3q32Pseudo_UPD:
4611  case ARM::VLD3q8oddPseudo:
4612  case ARM::VLD3q16oddPseudo:
4613  case ARM::VLD3q32oddPseudo:
4614  case ARM::VLD3q8oddPseudo_UPD:
4615  case ARM::VLD3q16oddPseudo_UPD:
4616  case ARM::VLD3q32oddPseudo_UPD:
4617  case ARM::VLD4d8Pseudo:
4618  case ARM::VLD4d16Pseudo:
4619  case ARM::VLD4d32Pseudo:
4620  case ARM::VLD1d8QPseudo:
4621  case ARM::VLD1d16QPseudo:
4622  case ARM::VLD1d32QPseudo:
4623  case ARM::VLD1d64QPseudo:
4624  case ARM::VLD1d64QPseudoWB_fixed:
4625  case ARM::VLD1d64QPseudoWB_register:
4626  case ARM::VLD1q8HighQPseudo:
4627  case ARM::VLD1q8LowQPseudo_UPD:
4628  case ARM::VLD1q8HighTPseudo:
4629  case ARM::VLD1q8LowTPseudo_UPD:
4630  case ARM::VLD1q16HighQPseudo:
4631  case ARM::VLD1q16LowQPseudo_UPD:
4632  case ARM::VLD1q16HighTPseudo:
4633  case ARM::VLD1q16LowTPseudo_UPD:
4634  case ARM::VLD1q32HighQPseudo:
4635  case ARM::VLD1q32LowQPseudo_UPD:
4636  case ARM::VLD1q32HighTPseudo:
4637  case ARM::VLD1q32LowTPseudo_UPD:
4638  case ARM::VLD1q64HighQPseudo:
4639  case ARM::VLD1q64LowQPseudo_UPD:
4640  case ARM::VLD1q64HighTPseudo:
4641  case ARM::VLD1q64LowTPseudo_UPD:
4642  case ARM::VLD4d8Pseudo_UPD:
4643  case ARM::VLD4d16Pseudo_UPD:
4644  case ARM::VLD4d32Pseudo_UPD:
4645  case ARM::VLD4q8Pseudo_UPD:
4646  case ARM::VLD4q16Pseudo_UPD:
4647  case ARM::VLD4q32Pseudo_UPD:
4648  case ARM::VLD4q8oddPseudo:
4649  case ARM::VLD4q16oddPseudo:
4650  case ARM::VLD4q32oddPseudo:
4651  case ARM::VLD4q8oddPseudo_UPD:
4652  case ARM::VLD4q16oddPseudo_UPD:
4653  case ARM::VLD4q32oddPseudo_UPD:
4654  case ARM::VLD1DUPq8:
4655  case ARM::VLD1DUPq16:
4656  case ARM::VLD1DUPq32:
4657  case ARM::VLD1DUPq8wb_fixed:
4658  case ARM::VLD1DUPq16wb_fixed:
4659  case ARM::VLD1DUPq32wb_fixed:
4660  case ARM::VLD1DUPq8wb_register:
4661  case ARM::VLD1DUPq16wb_register:
4662  case ARM::VLD1DUPq32wb_register:
4663  case ARM::VLD2DUPd8:
4664  case ARM::VLD2DUPd16:
4665  case ARM::VLD2DUPd32:
4666  case ARM::VLD2DUPd8wb_fixed:
4667  case ARM::VLD2DUPd16wb_fixed:
4668  case ARM::VLD2DUPd32wb_fixed:
4669  case ARM::VLD2DUPd8wb_register:
4670  case ARM::VLD2DUPd16wb_register:
4671  case ARM::VLD2DUPd32wb_register:
4672  case ARM::VLD2DUPq8EvenPseudo:
4673  case ARM::VLD2DUPq8OddPseudo:
4674  case ARM::VLD2DUPq16EvenPseudo:
4675  case ARM::VLD2DUPq16OddPseudo:
4676  case ARM::VLD2DUPq32EvenPseudo:
4677  case ARM::VLD2DUPq32OddPseudo:
4678  case ARM::VLD3DUPq8EvenPseudo:
4679  case ARM::VLD3DUPq8OddPseudo:
4680  case ARM::VLD3DUPq16EvenPseudo:
4681  case ARM::VLD3DUPq16OddPseudo:
4682  case ARM::VLD3DUPq32EvenPseudo:
4683  case ARM::VLD3DUPq32OddPseudo:
4684  case ARM::VLD4DUPd8Pseudo:
4685  case ARM::VLD4DUPd16Pseudo:
4686  case ARM::VLD4DUPd32Pseudo:
4687  case ARM::VLD4DUPd8Pseudo_UPD:
4688  case ARM::VLD4DUPd16Pseudo_UPD:
4689  case ARM::VLD4DUPd32Pseudo_UPD:
4690  case ARM::VLD4DUPq8EvenPseudo:
4691  case ARM::VLD4DUPq8OddPseudo:
4692  case ARM::VLD4DUPq16EvenPseudo:
4693  case ARM::VLD4DUPq16OddPseudo:
4694  case ARM::VLD4DUPq32EvenPseudo:
4695  case ARM::VLD4DUPq32OddPseudo:
4696  case ARM::VLD1LNq8Pseudo:
4697  case ARM::VLD1LNq16Pseudo:
4698  case ARM::VLD1LNq32Pseudo:
4699  case ARM::VLD1LNq8Pseudo_UPD:
4700  case ARM::VLD1LNq16Pseudo_UPD:
4701  case ARM::VLD1LNq32Pseudo_UPD:
4702  case ARM::VLD2LNd8Pseudo:
4703  case ARM::VLD2LNd16Pseudo:
4704  case ARM::VLD2LNd32Pseudo:
4705  case ARM::VLD2LNq16Pseudo:
4706  case ARM::VLD2LNq32Pseudo:
4707  case ARM::VLD2LNd8Pseudo_UPD:
4708  case ARM::VLD2LNd16Pseudo_UPD:
4709  case ARM::VLD2LNd32Pseudo_UPD:
4710  case ARM::VLD2LNq16Pseudo_UPD:
4711  case ARM::VLD2LNq32Pseudo_UPD:
4712  case ARM::VLD4LNd8Pseudo:
4713  case ARM::VLD4LNd16Pseudo:
4714  case ARM::VLD4LNd32Pseudo:
4715  case ARM::VLD4LNq16Pseudo:
4716  case ARM::VLD4LNq32Pseudo:
4717  case ARM::VLD4LNd8Pseudo_UPD:
4718  case ARM::VLD4LNd16Pseudo_UPD:
4719  case ARM::VLD4LNd32Pseudo_UPD:
4720  case ARM::VLD4LNq16Pseudo_UPD:
4721  case ARM::VLD4LNq32Pseudo_UPD:
4722  // If the address is not 64-bit aligned, the latencies of these
4723  // instructions increases by one.
4724  ++Latency;
4725  break;
4726  }
4727 
4728  return Latency;
4729 }
4730 
4731 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {
4732  if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4733  MI.isImplicitDef())
4734  return 0;
4735 
4736  if (MI.isBundle())
4737  return 0;
4738 
4739  const MCInstrDesc &MCID = MI.getDesc();
4740 
4741  if (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) &&
4742  !Subtarget.cheapPredicableCPSRDef())) {
4743  // When predicated, CPSR is an additional source operand for CPSR updating
4744  // instructions, this apparently increases their latencies.
4745  return 1;
4746  }
4747  return 0;
4748 }
4749 
4750 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4751  const MachineInstr &MI,
4752  unsigned *PredCost) const {
4753  if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4754  MI.isImplicitDef())
4755  return 1;
4756 
4757  // An instruction scheduler typically runs on unbundled instructions, however
4758  // other passes may query the latency of a bundled instruction.
4759  if (MI.isBundle()) {
4760  unsigned Latency = 0;
4762  MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
4763  while (++I != E && I->isInsideBundle()) {
4764  if (I->getOpcode() != ARM::t2IT)
4765  Latency += getInstrLatency(ItinData, *I, PredCost);
4766  }
4767  return Latency;
4768  }
4769 
4770  const MCInstrDesc &MCID = MI.getDesc();
4771  if (PredCost && (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) &&
4772  !Subtarget.cheapPredicableCPSRDef()))) {
4773  // When predicated, CPSR is an additional source operand for CPSR updating
4774  // instructions, this apparently increases their latencies.
4775  *PredCost = 1;
4776  }
4777  // Be sure to call getStageLatency for an empty itinerary in case it has a
4778  // valid MinLatency property.
4779  if (!ItinData)
4780  return MI.mayLoad() ? 3 : 1;
4781 
4782  unsigned Class = MCID.getSchedClass();
4783 
4784  // For instructions with variable uops, use uops as latency.
4785  if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
4786  return getNumMicroOps(ItinData, MI);
4787 
4788  // For the common case, fall back on the itinerary's latency.
4789  unsigned Latency = ItinData->getStageLatency(Class);
4790 
4791  // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4792  unsigned DefAlign =
4793  MI.hasOneMemOperand() ? (*MI.memoperands_begin())->getAlign().value() : 0;
4794  int Adj = adjustDefLatency(Subtarget, MI, MCID, DefAlign);
4795  if (Adj >= 0 || (int)Latency > -Adj) {
4796  return Latency + Adj;
4797  }
4798  return Latency;
4799 }
4800 
4801 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4802  SDNode *Node) const {
4803  if (!Node->isMachineOpcode())
4804  return 1;
4805 
4806  if (!ItinData || ItinData->isEmpty())
4807  return 1;
4808 
4809  unsigned Opcode = Node->getMachineOpcode();
4810  switch (Opcode) {
4811  default:
4812  return ItinData->getStageLatency(get(Opcode).getSchedClass());
4813  case ARM::VLDMQIA:
4814  case ARM::VSTMQIA:
4815  return 2;
4816  }
4817 }
4818 
4819 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
4820  const MachineRegisterInfo *MRI,
4821  const MachineInstr &DefMI,
4822  unsigned DefIdx,
4823  const MachineInstr &UseMI,
4824  unsigned UseIdx) const {
4825  unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4826  unsigned UDomain = UseMI.getDesc().TSFlags & ARMII::DomainMask;
4827  if (Subtarget.nonpipelinedVFP() &&
4828  (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
4829  return true;
4830 
4831  // Hoist VFP / NEON instructions with 4 or higher latency.
4832  unsigned Latency =
4833  SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);
4834  if (Latency <= 3)
4835  return false;
4836  return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4837  UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4838 }
4839 
4840 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
4841  const MachineInstr &DefMI,
4842  unsigned DefIdx) const {
4843  const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4844  if (!ItinData || ItinData->isEmpty())
4845  return false;
4846 
4847  unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4848  if (DDomain == ARMII::DomainGeneral) {
4849  unsigned DefClass = DefMI.getDesc().getSchedClass();
4850  int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4851  return (DefCycle != -1 && DefCycle <= 2);
4852  }
4853  return false;
4854 }
4855 
4856 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,
4857  StringRef &ErrInfo) const {
4858  if (convertAddSubFlagsOpcode(MI.getOpcode())) {
4859  ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4860  return false;
4861  }
4862  if (MI.getOpcode() == ARM::tMOVr && !Subtarget.hasV6Ops()) {
4863  // Make sure we don't generate a lo-lo mov that isn't supported.
4864  if (!ARM::hGPRRegClass.contains(MI.getOperand(0).getReg()) &&
4865  !ARM::hGPRRegClass.contains(MI.getOperand(1).getReg())) {
4866  ErrInfo = "Non-flag-setting Thumb1 mov is v6-only";
4867  return false;
4868  }
4869  }
4870  if (MI.getOpcode() == ARM::tPUSH ||
4871  MI.getOpcode() == ARM::tPOP ||
4872  MI.getOpcode() == ARM::tPOP_RET) {
4873  for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), 2)) {
4874  if (MO.isImplicit() || !MO.isReg())
4875  continue;
4876  Register Reg = MO.getReg();
4877  if (Reg < ARM::R0 || Reg > ARM::R7) {
4878  if (!(MI.getOpcode() == ARM::tPUSH && Reg == ARM::LR) &&
4879  !(MI.getOpcode() == ARM::tPOP_RET && Reg == ARM::PC)) {
4880  ErrInfo = "Unsupported register in Thumb1 push/pop";
4881  return false;
4882  }
4883  }
4884  }
4885  }
4886  if (MI.getOpcode() == ARM::MVE_VMOV_q_rr) {
4887  assert(MI.getOperand(4).isImm() && MI.getOperand(5).isImm());
4888  if ((MI.getOperand(4).getImm() != 2 && MI.getOperand(4).getImm() != 3) ||
4889  MI.getOperand(4).getImm() != MI.getOperand(5).getImm() + 2) {
4890  ErrInfo = "Incorrect array index for MVE_VMOV_q_rr";
4891  return false;
4892  }
4893  }
4894 
4895  // Check the address model by taking the first Imm operand and checking it is
4896  // legal for that addressing mode.
4898  (ARMII::AddrMode)(MI.getDesc().TSFlags & ARMII::AddrModeMask);
4899  switch (AddrMode) {
4900  default:
4901  break;
4902  case ARMII::AddrModeT2_i7:
4905  case ARMII::AddrModeT2_i8:
4909  case ARMII::AddrModeT2_i12: {
4910  uint32_t Imm = 0;
4911  for (auto Op : MI.operands()) {
4912  if (Op.isImm()) {
4913  Imm = Op.getImm();
4914  break;
4915  }
4916  }
4917  if (!isLegalAddressImm(MI.getOpcode(), Imm, this)) {
4918  ErrInfo = "Incorrect AddrMode Imm for instruction";
4919  return false;
4920  }
4921  break;
4922  }
4923  }
4924  return true;
4925 }
4926 
4928  unsigned LoadImmOpc,
4929  unsigned LoadOpc) const {
4930  assert(!Subtarget.isROPI() && !Subtarget.isRWPI() &&
4931  "ROPI/RWPI not currently supported with stack guard");
4932 
4933  MachineBasicBlock &MBB = *MI->getParent();
4934  DebugLoc DL = MI->getDebugLoc();
4935  Register Reg = MI->getOperand(0).getReg();
4936  MachineInstrBuilder MIB;
4937  unsigned int Offset = 0;
4938 
4939  if (LoadImmOpc == ARM::MRC || LoadImmOpc == ARM::t2MRC) {
4940  assert(Subtarget.isReadTPHard() &&
4941  "TLS stack protector requires hardware TLS register");
4942 
4943  BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4944  .addImm(15)
4945  .addImm(0)
4946  .addImm(13)
4947  .addImm(0)
4948  .addImm(3)
4949  .add(predOps(ARMCC::AL));
4950 
4952  Offset = M.getStackProtectorGuardOffset();
4953  if (Offset & ~0xfffU) {
4954  // The offset won't fit in the LDR's 12-bit immediate field, so emit an
4955  // extra ADD to cover the delta. This gives us a guaranteed 8 additional
4956  // bits, resulting in a range of 0 to +1 MiB for the guard offset.
4957  unsigned AddOpc = (LoadImmOpc == ARM::MRC) ? ARM::ADDri : ARM::t2ADDri;
4958  BuildMI(MBB, MI, DL, get(AddOpc), Reg)
4960  .addImm(Offset & ~0xfffU)
4961  .add(predOps(ARMCC::AL))
4962  .addReg(0);
4963  Offset &= 0xfffU;
4964  }
4965  } else {
4966  const GlobalValue *GV =
4967  cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4968  bool IsIndirect = Subtarget.isGVIndirectSymbol(GV);
4969 
4970  unsigned TargetFlags = ARMII::MO_NO_FLAG;
4971  if (Subtarget.isTargetMachO()) {
4972  TargetFlags |= ARMII::MO_NONLAZY;
4973  } else if (Subtarget.isTargetCOFF()) {
4974  if (GV->hasDLLImportStorageClass())
4975  TargetFlags |= ARMII::MO_DLLIMPORT;
4976  else if (IsIndirect)
4977  TargetFlags |= ARMII::MO_COFFSTUB;
4978  } else if (Subtarget.isGVInGOT(GV)) {
4979  TargetFlags |= ARMII::MO_GOT;
4980  }
4981 
4982  BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4983  .addGlobalAddress(GV, 0, TargetFlags);
4984 
4985  if (IsIndirect) {
4986  MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4987  MIB.addReg(Reg, RegState::Kill).addImm(0);
4988  auto Flags = MachineMemOperand::MOLoad |
4992  MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 4, Align(4));
4993  MIB.addMemOperand(MMO).add(predOps(ARMCC::AL));
4994  }
4995  }
4996 
4997  MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4998  MIB.addReg(Reg, RegState::Kill)
4999  .addImm(Offset)
5000  .cloneMemRefs(*MI)
5001  .add(predOps(ARMCC::AL));
5002 }
5003 
5004 bool
5005 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
5006  unsigned &AddSubOpc,
5007  bool &NegAcc, bool &HasLane) const {
5008  DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
5009  if (I == MLxEntryMap.end())
5010  return false;
5011 
5012  const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
5013  MulOpc = Entry.MulOpc;
5014  AddSubOpc = Entry.AddSubOpc;
5015  NegAcc = Entry.NegAcc;
5016  HasLane = Entry.HasLane;
5017  return true;
5018 }
5019 
5020 //===----------------------------------------------------------------------===//
5021 // Execution domains.
5022 //===----------------------------------------------------------------------===//
5023 //
5024 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
5025 // and some can go down both. The vmov instructions go down the VFP pipeline,
5026 // but they can be changed to vorr equivalents that are executed by the NEON
5027 // pipeline.
5028 //
5029 // We use the following execution domain numbering:
5030 //
5033  ExeVFP = 1,
5035 };
5036 
5037 //
5038 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
5039 //
5040 std::pair<uint16_t, uint16_t>
5042  // If we don't have access to NEON instructions then we won't be able
5043  // to swizzle anything to the NEON domain. Check to make sure.
5044  if (Subtarget.hasNEON()) {
5045  // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
5046  // if they are not predicated.
5047  if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI))
5048  return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
5049 
5050  // CortexA9 is particularly picky about mixing the two and wants these
5051  // converted.
5052  if (Subtarget.useNEONForFPMovs() && !isPredicated(MI) &&
5053  (MI.getOpcode() == ARM::VMOVRS || MI.getOpcode() == ARM::VMOVSR ||
5054  MI.getOpcode() == ARM::VMOVS))
5055  return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
5056  }
5057  // No other instructions can be swizzled, so just determine their domain.
5058  unsigned Domain = MI.getDesc().TSFlags & ARMII::DomainMask;
5059 
5060  if (Domain & ARMII::DomainNEON)
5061  return std::make_pair(ExeNEON, 0);
5062 
5063  // Certain instructions can go either way on Cortex-A8.
5064  // Treat them as NEON instructions.
5065  if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
5066  return std::make_pair(ExeNEON, 0);
5067 
5068  if (Domain & ARMII::DomainVFP)
5069  return std::make_pair(ExeVFP, 0);
5070 
5071  return std::make_pair(ExeGeneric, 0);
5072 }
5073 
5075  unsigned SReg, unsigned &Lane) {
5076  unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
5077  Lane = 0;
5078 
5079  if (DReg != ARM::NoRegister)
5080  return DReg;
5081 
5082  Lane = 1;
5083  DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
5084 
5085  assert(DReg && "S-register with no D super-register?");
5086  return DReg;
5087 }
5088 
5089 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
5090 /// set ImplicitSReg to a register number that must be marked as implicit-use or
5091 /// zero if no register needs to be defined as implicit-use.
5092 ///
5093 /// If the function cannot determine if an SPR should be