LLVM 17.0.0git
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1//===------ llvm/MC/MCInstrDesc.cpp- Instruction Descriptors --------------===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9// This file defines methods on the MCOperandInfo and MCInstrDesc classes, which
10// are used to describe target instructions and their operands.
14#include "llvm/MC/MCInstrDesc.h"
15#include "llvm/MC/MCInst.h"
18using namespace llvm;
21 const MCRegisterInfo &RI) const {
22 if (isBranch() || isCall() || isReturn() || isIndirectBranch())
23 return true;
24 unsigned PC = RI.getProgramCounter();
25 if (PC == 0)
26 return false;
27 if (hasDefOfPhysReg(MI, PC, RI))
28 return true;
29 return false;
33 const MCRegisterInfo *MRI) const {
34 for (MCPhysReg ImpDef : implicit_defs())
35 if (ImpDef == Reg || (MRI && MRI->isSubRegister(Reg, ImpDef)))
36 return true;
37 return false;
40bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
41 const MCRegisterInfo &RI) const {
42 for (int i = 0, e = NumDefs; i != e; ++i)
43 if (MI.getOperand(i).isReg() && MI.getOperand(i).getReg() &&
44 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
45 return true;
47 for (int i = NumOperands - 1, e = MI.getNumOperands(); i != e; ++i)
48 if (MI.getOperand(i).isReg() &&
49 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
50 return true;
51 return hasImplicitDefOfPhysReg(Reg, &RI);
unsigned const MachineRegisterInfo * MRI
IRTranslator LLVM IR MI
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
bool isIndirectBranch() const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MCInstrDesc.h:311
bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, const MCRegisterInfo &RI) const
Return true if this instruction defines the specified physical register, either explicitly or implici...
Definition: MCInstrDesc.cpp:40
unsigned short NumOperands
Definition: MCInstrDesc.h:206
bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const
Return true if this is a branch or an instruction which directly writes to the program counter.
Definition: MCInstrDesc.cpp:20
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:307
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:418
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:580
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
Definition: MCInstrDesc.cpp:32
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:288
bool isReturn() const
Return true if the instruction is a return.
Definition: MCInstrDesc.h:276
unsigned char NumDefs
Definition: MCInstrDesc.h:207
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getProgramCounter() const
Return the register which is the program counter.
bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA or if RegB == RegA.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18