LLVM  13.0.0git
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ARMBaseInstrInfo.cpp File Reference
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMConstantPoolValue.h"
#include "ARMFeatures.h"
#include "ARMHazardRecognizer.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMSubtarget.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "MVETailPredUtils.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Triple.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MultiHazardRecognizer.h"
#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <new>
#include <utility>
#include <vector>
#include "ARMGenInstrInfo.inc"

Go to the source code of this file.

Classes

struct  ARM_MLxEntry
 ARM_MLxEntry - Record information about MLA / MLS instructions. More...
 
struct  AddSubFlagsOpcodePair
 Map pseudo instructions that imply an 'S' bit onto real opcodes. More...
 
struct  OutlinerCosts
 

Namespaces

 llvm
 

Macros

#define DEBUG_TYPE   "arm-instrinfo"
 
#define GET_INSTRINFO_CTOR_DTOR
 

Enumerations

enum  ARMExeDomain { ExeGeneric = 0, ExeVFP = 1, ExeNEON = 2 }
 
enum  MachineOutlinerClass {
  MachineOutlinerDefault, MachineOutlinerTailCall, MachineOutlinerNoLRSave, MachineOutlinerThunk,
  MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, MachineOutlinerNoLRSave,
  MachineOutlinerRegSave, MachineOutlinerDefault, MachineOutlinerDefault, MachineOutlinerTailCall
}
 Constants defining how certain sequences should be outlined. More...
 
enum  MachineOutlinerMBBFlags {
  LRUnavailableSomewhere = 0x2, HasCalls = 0x4, UnsafeRegsDead = 0x8, LRUnavailableSomewhere = 0x2,
  HasCalls = 0x4, UnsafeRegsDead = 0x8
}
 

Functions

static bool isEligibleForITBlock (const MachineInstr *MI)
 
template<>
bool llvm::IsCPSRDead< MachineInstr > (const MachineInstr *MI)
 
static unsigned duplicateCPV (MachineFunction &MF, unsigned &CPI)
 Create a copy of a const pool value. More...
 
static bool isSuitableForMask (MachineInstr *&MI, Register SrcReg, int CmpMask, bool CommonUse)
 isSuitableForMask - Identify a suitable 'and' instruction that operates on the given source register and applies the same mask as a 'tst' instruction. More...
 
static ARMCC::CondCodes getCmpToAddCondition (ARMCC::CondCodes CC)
 getCmpToAddCondition - assume the flags are set by CMP(a,b), return the condition code if we modify the instructions such that flags are set by ADD(a,b,X). More...
 
static bool isRedundantFlagInstr (const MachineInstr *CmpI, Register SrcReg, Register SrcReg2, int ImmValue, const MachineInstr *OI, bool &IsThumb1)
 isRedundantFlagInstr - check whether the first instruction, whose only purpose is to update flags, can be made redundant. More...
 
static bool isOptimizeCompareCandidate (MachineInstr *MI, bool &IsThumb1)
 
static unsigned getNumMicroOpsSwiftLdSt (const InstrItineraryData *ItinData, const MachineInstr &MI)
 
static unsigned getNumMicroOpsSingleIssuePlusExtras (unsigned Opc, unsigned NumRegs)
 
static const MachineInstrgetBundledDefMI (const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist)
 
static const MachineInstrgetBundledUseMI (const TargetRegisterInfo *TRI, const MachineInstr &MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist)
 
static int adjustDefLatency (const ARMSubtarget &Subtarget, const MachineInstr &DefMI, const MCInstrDesc &DefMCID, unsigned DefAlign)
 Return the number of cycles to add to (or subtract from) the static itinerary based on the def opcode and alignment. More...
 
static unsigned getCorrespondingDRegAndLane (const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane)
 
static bool getImplicitSPRUseForDPRUse (const TargetRegisterInfo *TRI, MachineInstr &MI, unsigned DReg, unsigned Lane, unsigned &ImplicitSReg)
 getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, set ImplicitSReg to a register number that must be marked as implicit-use or zero if no register needs to be defined as implicit-use. More...
 
static bool isLRAvailable (const TargetRegisterInfo &TRI, MachineBasicBlock::reverse_iterator I, MachineBasicBlock::reverse_iterator E)
 

Variables

static cl::opt< bool > EnableARM3Addr ("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv"))
 
static const ARM_MLxEntry ARM_MLxTable []
 
static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap []
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "arm-instrinfo"

Definition at line 72 of file ARMBaseInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 74 of file ARMBaseInstrInfo.cpp.

Enumeration Type Documentation

◆ ARMExeDomain

Enumerator
ExeGeneric 
ExeVFP 
ExeNEON 

Definition at line 4915 of file ARMBaseInstrInfo.cpp.

◆ MachineOutlinerClass

Constants defining how certain sequences should be outlined.

This encompasses how an outlined function should be called, and what kind of frame should be emitted for that outlined function.

MachineOutlinerTailCall implies that the function is being created from a sequence of instructions ending in a return.

That is,

I1 OUTLINED_FUNCTION: I2 --> B OUTLINED_FUNCTION I1 BX LR I2 BX LR

+----------------------—+-----—+--—+ | | Thumb2 | ARM | +----------------------—+-----—+--—+ | Call overhead in Bytes | 4 | 4 | | Frame overhead in Bytes | 0 | 0 | | Stack fixup required | No | No | +----------------------—+-----—+--—+

MachineOutlinerThunk implies that the function is being created from a sequence of instructions ending in a call. The outlined function is called with a BL instruction, and the outlined function tail-calls the original call destination.

That is,

I1 OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 BL f I2 B f

+----------------------—+-----—+--—+ | | Thumb2 | ARM | +----------------------—+-----—+--—+ | Call overhead in Bytes | 4 | 4 | | Frame overhead in Bytes | 0 | 0 | | Stack fixup required | No | No | +----------------------—+-----—+--—+

MachineOutlinerNoLRSave implies that the function should be called using a BL instruction, but doesn't require LR to be saved and restored. This happens when LR is known to be dead.

That is,

I1 OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 I3 I2 I3 BX LR

+----------------------—+-----—+--—+ | | Thumb2 | ARM | +----------------------—+-----—+--—+ | Call overhead in Bytes | 4 | 4 | | Frame overhead in Bytes | 4 | 4 | | Stack fixup required | No | No | +----------------------—+-----—+--—+

MachineOutlinerRegSave implies that the function should be called with a save and restore of LR to an available register. This allows us to avoid stack fixups. Note that this outlining variant is compatible with the NoLRSave case.

That is,

I1 Save LR OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 I3 Restore LR I2 I3 BX LR

+----------------------—+-----—+--—+ | | Thumb2 | ARM | +----------------------—+-----—+--—+ | Call overhead in Bytes | 8 | 12 | | Frame overhead in Bytes | 2 | 4 | | Stack fixup required | No | No | +----------------------—+-----—+--—+

MachineOutlinerDefault implies that the function should be called with a save and restore of LR to the stack.

That is,

I1 Save LR OUTLINED_FUNCTION: I2 --> BL OUTLINED_FUNCTION I1 I3 Restore LR I2 I3 BX LR

+----------------------—+-----—+--—+ | | Thumb2 | ARM | +----------------------—+-----—+--—+ | Call overhead in Bytes | 8 | 12 | | Frame overhead in Bytes | 2 | 4 | | Stack fixup required | Yes | Yes | +----------------------—+-----—+--—+

Enumerator
MachineOutlinerDefault 
MachineOutlinerTailCall 

Emit a save, restore, call, and return.

MachineOutlinerNoLRSave 

Only emit a branch.

MachineOutlinerThunk 

Emit a call and return.

MachineOutlinerRegSave 

Emit a call and tail-call.

Same as default, but save to a register.

MachineOutlinerTailCall 
MachineOutlinerThunk 
MachineOutlinerNoLRSave 
MachineOutlinerRegSave 
MachineOutlinerDefault 
MachineOutlinerDefault 
MachineOutlinerTailCall 

Definition at line 5662 of file ARMBaseInstrInfo.cpp.

◆ MachineOutlinerMBBFlags

Enumerator
LRUnavailableSomewhere 
HasCalls 
UnsafeRegsDead 
LRUnavailableSomewhere 
HasCalls 
UnsafeRegsDead 

Definition at line 5670 of file ARMBaseInstrInfo.cpp.

Function Documentation

◆ adjustDefLatency()

static int adjustDefLatency ( const ARMSubtarget Subtarget,
const MachineInstr DefMI,
const MCInstrDesc DefMCID,
unsigned  DefAlign 
)
static

Return the number of cycles to add to (or subtract from) the static itinerary based on the def opcode and alignment.

The caller will ensure that adjusted latency is at least one cycle.

Definition at line 4152 of file ARMBaseInstrInfo.cpp.

References llvm::ARMSubtarget::checkVLDnAccessAlignment(), DefMI, llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::MCInstrDesc::getOpcode(), llvm::ARMSubtarget::isCortexA7(), llvm::ARMSubtarget::isCortexA8(), llvm::ARMSubtarget::isLikeA9(), llvm::ARMSubtarget::isSwift(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, and llvm::ARM_AM::sub.

◆ duplicateCPV()

static unsigned duplicateCPV ( MachineFunction MF,
unsigned &  CPI 
)
static

◆ getBundledDefMI()

static const MachineInstr* getBundledDefMI ( const TargetRegisterInfo TRI,
const MachineInstr MI,
unsigned  Reg,
unsigned &  DefIdx,
unsigned &  Dist 
)
static

Definition at line 4097 of file ARMBaseInstrInfo.cpp.

References assert(), I, MI, Reg, and TRI.

Referenced by llvm::ARMBaseInstrInfo::getOperandLatency().

◆ getBundledUseMI()

static const MachineInstr* getBundledUseMI ( const TargetRegisterInfo TRI,
const MachineInstr MI,
unsigned  Reg,
unsigned &  UseIdx,
unsigned &  Dist 
)
static

Definition at line 4120 of file ARMBaseInstrInfo.cpp.

References assert(), E, MI, Reg, and TRI.

Referenced by llvm::ARMBaseInstrInfo::getOperandLatency().

◆ getCmpToAddCondition()

static ARMCC::CondCodes getCmpToAddCondition ( ARMCC::CondCodes  CC)
inlinestatic

getCmpToAddCondition - assume the flags are set by CMP(a,b), return the condition code if we modify the instructions such that flags are set by ADD(a,b,X).

Definition at line 2827 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, llvm::ARMCC::HS, llvm::ARMCC::LO, llvm::ARMCC::VC, and llvm::ARMCC::VS.

Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr().

◆ getCorrespondingDRegAndLane()

static unsigned getCorrespondingDRegAndLane ( const TargetRegisterInfo TRI,
unsigned  SReg,
unsigned &  Lane 
)
static

◆ getImplicitSPRUseForDPRUse()

static bool getImplicitSPRUseForDPRUse ( const TargetRegisterInfo TRI,
MachineInstr MI,
unsigned  DReg,
unsigned  Lane,
unsigned &  ImplicitSReg 
)
static

getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, set ImplicitSReg to a register number that must be marked as implicit-use or zero if no register needs to be defined as implicit-use.

If the function cannot determine if an SPR should be marked implicit use or not, it returns false.

This function handles cases where an instruction is being modified from taking an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict with an earlier def of an SPR corresponding to DPRLane^1.

If the other SPR is defined, an implicit-use of it should be added. Else, (including the case where the DPR itself is defined), it should not.

Definition at line 4988 of file ARMBaseInstrInfo.cpp.

References llvm::M68kBeads::DReg, llvm::TargetRegisterInfo::getSubReg(), llvm::MachineBasicBlock::LQR_Live, llvm::MachineBasicBlock::LQR_Unknown, MI, and TRI.

Referenced by llvm::ARMBaseInstrInfo::setExecutionDomain().

◆ getNumMicroOpsSingleIssuePlusExtras()

static unsigned getNumMicroOpsSingleIssuePlusExtras ( unsigned  Opc,
unsigned  NumRegs 
)
static

Definition at line 3688 of file ARMBaseInstrInfo.cpp.

Referenced by llvm::ARMBaseInstrInfo::getNumMicroOps().

◆ getNumMicroOpsSwiftLdSt()

static unsigned getNumMicroOpsSwiftLdSt ( const InstrItineraryData ItinData,
const MachineInstr MI 
)
static

◆ isEligibleForITBlock()

static bool isEligibleForITBlock ( const MachineInstr MI)
static

◆ isLRAvailable()

static bool isLRAvailable ( const TargetRegisterInfo TRI,
MachineBasicBlock::reverse_iterator  I,
MachineBasicBlock::reverse_iterator  E 
)
static

◆ isOptimizeCompareCandidate()

static bool isOptimizeCompareCandidate ( MachineInstr MI,
bool &  IsThumb1 
)
static

Definition at line 2904 of file ARMBaseInstrInfo.cpp.

References LLVM_FALLTHROUGH, and MI.

Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr().

◆ isRedundantFlagInstr()

static bool isRedundantFlagInstr ( const MachineInstr CmpI,
Register  SrcReg,
Register  SrcReg2,
int  ImmValue,
const MachineInstr OI,
bool &  IsThumb1 
)
inlinestatic

isRedundantFlagInstr - check whether the first instruction, whose only purpose is to update flags, can be made redundant.

CMPrr can be made redundant by SUBrr if the operands are the same. CMPri can be made redundant by SUBri if the operands are the same. CMPrr(r0, r1) can be made redundant by ADDr[ri](r0, r1, X). This function can be extended later on.

Definition at line 2843 of file ARMBaseInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().

Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr(), and llvm::ARMBaseInstrInfo::shouldSink().

◆ isSuitableForMask()

static bool isSuitableForMask ( MachineInstr *&  MI,
Register  SrcReg,
int  CmpMask,
bool  CommonUse 
)
static

isSuitableForMask - Identify a suitable 'and' instruction that operates on the given source register and applies the same mask as a 'tst' instruction.

Provide a limited look-through for copies. When successful, MI will hold the found instruction.

Definition at line 2809 of file ARMBaseInstrInfo.cpp.

References MI.

Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr().

Variable Documentation

◆ AddSubFlagsOpcodeMap

const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[]
static

Definition at line 2406 of file ARMBaseInstrInfo.cpp.

Referenced by llvm::convertAddSubFlagsOpcode().

◆ ARM_MLxTable

const ARM_MLxEntry ARM_MLxTable[]
static
Initial value:
= {
{ ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
{ ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
{ ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
{ ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
{ ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
{ ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
{ ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
{ ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
{ ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
{ ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
{ ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
{ ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
{ ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
{ ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
{ ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
{ ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
}

Definition at line 90 of file ARMBaseInstrInfo.cpp.

Referenced by llvm::ARMBaseInstrInfo::ARMBaseInstrInfo().

◆ EnableARM3Addr

cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv"))
static