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15 #ifndef LLVM_LIB_TARGET_ARM_MVETAILPREDUTILS_H
16 #define LLVM_LIB_TARGET_ARM_MVETAILPREDUTILS_H
31 return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8;
33 return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16;
35 return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32;
37 return IsDoLoop ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64;
59 switch (
MI->getOpcode()) {
72 return MI.getOpcode() == ARM::t2DoLoopStart ||
73 MI.getOpcode() == ARM::t2DoLoopStartTP ||
74 MI.getOpcode() == ARM::t2WhileLoopStart;
80 unsigned BrOpc = ARM::t2Bcc) {
86 MIB.
add(
MI->getOperand(0));
89 MIB.
addReg(ARM::NoRegister);
93 MIB.
add(
MI->getOperand(1));
97 MI->eraseFromParent();
103 .
add(
MI->getOperand(0))
104 .
add(
MI->getOperand(1))
107 MI->eraseFromParent();
111 bool SetFlags =
false) {
116 MIB.
add(
MI->getOperand(0));
117 MIB.
add(
MI->getOperand(1));
118 MIB.
add(
MI->getOperand(2));
128 MI->eraseFromParent();
133 unsigned BrOpc = ARM::t2Bcc,
bool SkipCmp =
false) {
140 MIB.
add(
MI->getOperand(0));
143 MIB.
addReg(ARM::NoRegister);
149 MIB.
add(
MI->getOperand(1));
152 MI->eraseFromParent();
157 #endif // LLVM_LIB_TARGET_ARM_MVETAILPREDUTILS_H
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This class represents lattice values for constants.
const MachineInstrBuilder & add(const MachineOperand &MO) const
void RevertWhileLoopStart(MachineInstr *MI, const TargetInstrInfo *TII, unsigned BrOpc=ARM::t2Bcc)
static unsigned VCTPOpcodeToLSTP(unsigned Opcode, bool IsDoLoop)
static bool isLoopStart(MachineInstr &MI)
TargetInstrInfo - Interface to description of machine instruction set.
const MachineOperand & getOperand(unsigned i) const
void RevertLoopDec(MachineInstr *MI, const TargetInstrInfo *TII, bool SetFlags=false)
void RevertLoopEnd(MachineInstr *MI, const TargetInstrInfo *TII, unsigned BrOpc=ARM::t2Bcc, bool SkipCmp=false)
const HexagonInstrInfo * TII
Representation of each machine instruction.
void RevertDoLoopStart(MachineInstr *MI, const TargetInstrInfo *TII)
static bool isVCTP(const MachineInstr *MI)
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
static unsigned getTailPredVectorWidth(unsigned Opcode)