LLVM 19.0.0git
Thumb1InstrInfo.cpp
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1//===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "Thumb1InstrInfo.h"
14#include "ARMSubtarget.h"
15#include "llvm/ADT/BitVector.h"
20#include "llvm/IR/Module.h"
21#include "llvm/MC/MCInst.h"
23
24using namespace llvm;
25
27 : ARMBaseInstrInfo(STI) {}
28
29/// Return the noop instruction to use for a noop.
31 return MCInstBuilder(ARM::tMOVr)
32 .addReg(ARM::R8)
33 .addReg(ARM::R8)
35 .addReg(0);
36}
37
38unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
39 return 0;
40}
41
44 const DebugLoc &DL, MCRegister DestReg,
45 MCRegister SrcReg, bool KillSrc) const {
46 // Need to check the arch.
48 const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
49
50 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
51 "Thumb1 can only copy GPR registers");
52
53 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) ||
54 !ARM::tGPRRegClass.contains(DestReg))
55 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
56 .addReg(SrcReg, getKillRegState(KillSrc))
58 else {
59 const TargetRegisterInfo *RegInfo = st.getRegisterInfo();
60 LiveRegUnits UsedRegs(*RegInfo);
61 UsedRegs.addLiveOuts(MBB);
62
63 auto InstUpToI = MBB.end();
64 while (InstUpToI != I)
65 // The pre-decrement is on purpose here.
66 // We want to have the liveness right before I.
67 UsedRegs.stepBackward(*--InstUpToI);
68
69 if (UsedRegs.available(ARM::CPSR)) {
70 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
71 .addReg(SrcReg, getKillRegState(KillSrc))
72 ->addRegisterDead(ARM::CPSR, RegInfo);
73 return;
74 }
75
76 // Use high register to move source to destination
77 // if movs is not an option.
78 BitVector Allocatable = RegInfo->getAllocatableSet(
79 MF, RegInfo->getRegClass(ARM::hGPRRegClassID));
80
81 Register TmpReg = ARM::NoRegister;
82 // Prefer R12 as it is known to not be preserved anyway
83 if (UsedRegs.available(ARM::R12) && Allocatable.test(ARM::R12)) {
84 TmpReg = ARM::R12;
85 } else {
86 for (Register Reg : Allocatable.set_bits()) {
87 if (UsedRegs.available(Reg)) {
88 TmpReg = Reg;
89 break;
90 }
91 }
92 }
93
94 if (TmpReg) {
95 BuildMI(MBB, I, DL, get(ARM::tMOVr), TmpReg)
96 .addReg(SrcReg, getKillRegState(KillSrc))
98 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
99 .addReg(TmpReg, getKillRegState(true))
101 return;
102 }
103
104 // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
105 BuildMI(MBB, I, DL, get(ARM::tPUSH))
107 .addReg(SrcReg, getKillRegState(KillSrc));
108 BuildMI(MBB, I, DL, get(ARM::tPOP))
110 .addReg(DestReg, getDefRegState(true));
111 }
112}
113
116 Register SrcReg, bool isKill, int FI,
117 const TargetRegisterClass *RC,
118 const TargetRegisterInfo *TRI,
119 Register VReg) const {
120 assert((RC == &ARM::tGPRRegClass ||
121 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) &&
122 "Unknown regclass!");
123
124 if (RC == &ARM::tGPRRegClass ||
125 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) {
126 DebugLoc DL;
127 if (I != MBB.end()) DL = I->getDebugLoc();
128
130 MachineFrameInfo &MFI = MF.getFrameInfo();
133 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
134 BuildMI(MBB, I, DL, get(ARM::tSTRspi))
135 .addReg(SrcReg, getKillRegState(isKill))
136 .addFrameIndex(FI)
137 .addImm(0)
138 .addMemOperand(MMO)
140 }
141}
142
145 Register DestReg, int FI,
146 const TargetRegisterClass *RC,
147 const TargetRegisterInfo *TRI,
148 Register VReg) const {
149 assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
150 (DestReg.isPhysical() && isARMLowRegister(DestReg))) &&
151 "Unknown regclass!");
152
153 if (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
154 (DestReg.isPhysical() && isARMLowRegister(DestReg))) {
155 DebugLoc DL;
156 if (I != MBB.end()) DL = I->getDebugLoc();
157
159 MachineFrameInfo &MFI = MF.getFrameInfo();
162 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
163 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
164 .addFrameIndex(FI)
165 .addImm(0)
166 .addMemOperand(MMO)
168 }
169}
170
171void Thumb1InstrInfo::expandLoadStackGuard(
173 MachineFunction &MF = *MI->getParent()->getParent();
174 const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>();
175 const auto *GV = cast<GlobalValue>((*MI->memoperands_begin())->getValue());
176
178 "TLS stack protector not supported for Thumb1 targets");
179
180 unsigned Instr;
181 if (!GV->isDSOLocal())
182 Instr = ARM::tLDRLIT_ga_pcrel;
183 else if (ST.genExecuteOnly() && ST.hasV8MBaselineOps())
184 Instr = ARM::t2MOVi32imm;
185 else if (ST.genExecuteOnly())
186 Instr = ARM::tMOVi32imm;
187 else
188 Instr = ARM::tLDRLIT_ga_abs;
189 expandLoadStackGuardBase(MI, Instr, ARM::tLDRi);
190}
191
193 // In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR
194 // but this is not always possible there, so allow the Scheduler to clone tADCS and tSBCS
195 // even if they have glue.
196 // FIXME. Actually implement the cross-copy where it is possible (post v6)
197 // because these copies entail more spilling.
198 unsigned Opcode = N->getMachineOpcode();
199 if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)
200 return true;
201
202 return false;
203}
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements the BitVector class.
IRTranslator LLVM IR MI
A set of register units.
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
Module.h This file contains the declarations for the Module class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:208
bool test(unsigned Idx) const
Definition: BitVector.h:461
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:140
A debug info location.
Definition: DebugLoc.h:33
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:656
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
Definition: LiveRegUnits.h:116
void stepBackward(const MachineInstr &MI)
Updates liveness when stepping backwards over the instruction MI.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:37
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:43
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
StringRef getStackProtectorGuard() const
Get/set what kind of stack protector guard to use.
Definition: Module.cpp:741
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
Represents one node in the SelectionDAG.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Thumb1InstrInfo(const ARMSubtarget &STI)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
MCInst getNop() const override
Return the noop instruction to use for a noop.
unsigned getUnindexedOpcode(unsigned Opc) const override
bool canCopyGluedNodeDuringSchedule(SDNode *N) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:160
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
unsigned getDefRegState(bool B)
unsigned getKillRegState(bool B)
#define N
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.