LLVM  14.0.0git
Thumb1InstrInfo.cpp
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1 //===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Thumb1InstrInfo.h"
14 #include "ARMSubtarget.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstBuilder.h"
20 
21 using namespace llvm;
22 
24  : ARMBaseInstrInfo(STI), RI() {}
25 
26 /// Return the noop instruction to use for a noop.
28  return MCInstBuilder(ARM::tMOVr)
29  .addReg(ARM::R8)
30  .addReg(ARM::R8)
32  .addReg(0);
33 }
34 
35 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
36  return 0;
37 }
38 
41  const DebugLoc &DL, MCRegister DestReg,
42  MCRegister SrcReg, bool KillSrc) const {
43  // Need to check the arch.
44  MachineFunction &MF = *MBB.getParent();
45  const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
46 
47  assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
48  "Thumb1 can only copy GPR registers");
49 
50  if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
51  || !ARM::tGPRRegClass.contains(DestReg))
52  BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
53  .addReg(SrcReg, getKillRegState(KillSrc))
55  else {
56  // FIXME: Can also use 'mov hi, $src; mov $dst, hi',
57  // with hi as either r10 or r11.
58 
59  const TargetRegisterInfo *RegInfo = st.getRegisterInfo();
60  if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)
62  BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
63  .addReg(SrcReg, getKillRegState(KillSrc))
64  ->addRegisterDead(ARM::CPSR, RegInfo);
65  return;
66  }
67 
68  // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
69  BuildMI(MBB, I, DL, get(ARM::tPUSH))
71  .addReg(SrcReg, getKillRegState(KillSrc));
72  BuildMI(MBB, I, DL, get(ARM::tPOP))
74  .addReg(DestReg, getDefRegState(true));
75  }
76 }
77 
80  Register SrcReg, bool isKill, int FI,
81  const TargetRegisterClass *RC,
82  const TargetRegisterInfo *TRI) const {
83  assert((RC == &ARM::tGPRRegClass ||
84  (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) &&
85  "Unknown regclass!");
86 
87  if (RC == &ARM::tGPRRegClass ||
88  (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) {
89  DebugLoc DL;
90  if (I != MBB.end()) DL = I->getDebugLoc();
91 
92  MachineFunction &MF = *MBB.getParent();
93  MachineFrameInfo &MFI = MF.getFrameInfo();
96  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
97  BuildMI(MBB, I, DL, get(ARM::tSTRspi))
98  .addReg(SrcReg, getKillRegState(isKill))
99  .addFrameIndex(FI)
100  .addImm(0)
101  .addMemOperand(MMO)
102  .add(predOps(ARMCC::AL));
103  }
104 }
105 
108  Register DestReg, int FI,
109  const TargetRegisterClass *RC,
110  const TargetRegisterInfo *TRI) const {
111  assert(
112  (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
113  (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) &&
114  "Unknown regclass!");
115 
116  if (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
117  (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) {
118  DebugLoc DL;
119  if (I != MBB.end()) DL = I->getDebugLoc();
120 
121  MachineFunction &MF = *MBB.getParent();
122  MachineFrameInfo &MFI = MF.getFrameInfo();
125  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
126  BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
127  .addFrameIndex(FI)
128  .addImm(0)
129  .addMemOperand(MMO)
130  .add(predOps(ARMCC::AL));
131  }
132 }
133 
134 void Thumb1InstrInfo::expandLoadStackGuard(
136  MachineFunction &MF = *MI->getParent()->getParent();
137  const TargetMachine &TM = MF.getTarget();
138  if (TM.isPositionIndependent())
139  expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi);
140  else
141  expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi);
142 }
143 
145  // In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR
146  // but this is not always possible there, so allow the Scheduler to clone tADCS and tSBCS
147  // even if they have glue.
148  // FIXME. Actually implement the cross-copy where it is possible (post v6)
149  // because these copies entail more spilling.
150  unsigned Opcode = N->getMachineOpcode();
151  if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)
152  return true;
153 
154  return false;
155 }
ARMSubtarget.h
llvm::MachineInstr::addRegisterDead
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
Definition: MachineInstr.cpp:1957
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::Thumb1InstrInfo::getUnindexedOpcode
unsigned getUnindexedOpcode(unsigned Opc) const override
Definition: Thumb1InstrInfo.cpp:35
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
MCInstBuilder.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
Thumb1InstrInfo.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::ARMBaseInstrInfo::expandLoadStackGuardBase
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
Definition: ARMBaseInstrInfo.cpp:4885
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:502
llvm::Thumb1InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: Thumb1InstrInfo.cpp:107
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
MCInst.h
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:138
llvm::ARMSubtarget::hasV6Ops
bool hasV6Ops() const
Definition: ARMSubtarget.h:611
llvm::Thumb1InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: Thumb1InstrInfo.cpp:39
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:467
llvm::MCInstBuilder
Definition: MCInstBuilder.h:21
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineBasicBlock::LQR_Dead
@ LQR_Dead
Register is known to be fully dead.
Definition: MachineBasicBlock.h:1019
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ARMSubtarget::getRegisterInfo
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:577
llvm::MCInstBuilder::addImm
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:135
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::Thumb1InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: Thumb1InstrInfo.cpp:79
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:622
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
MachineFrameInfo.h
llvm::MachineBasicBlock::computeRegisterLiveness
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, MCRegister Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been defined and not killed as of just before Before.
Definition: MachineBasicBlock.cpp:1485
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1003
llvm::Thumb1InstrInfo::canCopyGluedNodeDuringSchedule
bool canCopyGluedNodeDuringSchedule(SDNode *N) const override
Definition: Thumb1InstrInfo.cpp:144
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::MCInstBuilder::addReg
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
MachineMemOperand.h
llvm::isARMLowRegister
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:160
llvm::Thumb1InstrInfo::getNop
MCInst getNop() const override
Return the noop instruction to use for a noop.
Definition: Thumb1InstrInfo.cpp:27
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::Thumb1InstrInfo::Thumb1InstrInfo
Thumb1InstrInfo(const ARMSubtarget &STI)
Definition: Thumb1InstrInfo.cpp:23
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:541
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23