LLVM  15.0.0git
MachineVerifier.cpp
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1 //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Pass to verify generated machine code. The following is checked:
10 //
11 // Operand counts: All explicit operands must be present.
12 //
13 // Register classes: All physical and virtual register operands must be
14 // compatible with the register class required by the instruction descriptor.
15 //
16 // Register live intervals: Registers must be defined only once, and must be
17 // defined before use.
18 //
19 // The machine code verifier is enabled with the command-line option
20 // -verify-machineinstrs.
21 //===----------------------------------------------------------------------===//
22 
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/DenseMap.h"
25 #include "llvm/ADT/DenseSet.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SetOperations.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/StringRef.h"
33 #include "llvm/ADT/Twine.h"
53 #include "llvm/CodeGen/StackMaps.h"
58 #include "llvm/IR/BasicBlock.h"
59 #include "llvm/IR/Constants.h"
60 #include "llvm/IR/Function.h"
61 #include "llvm/IR/InlineAsm.h"
62 #include "llvm/IR/Instructions.h"
63 #include "llvm/InitializePasses.h"
64 #include "llvm/MC/LaneBitmask.h"
65 #include "llvm/MC/MCAsmInfo.h"
66 #include "llvm/MC/MCInstrDesc.h"
67 #include "llvm/MC/MCRegisterInfo.h"
69 #include "llvm/Pass.h"
70 #include "llvm/Support/Casting.h"
76 #include <algorithm>
77 #include <cassert>
78 #include <cstddef>
79 #include <cstdint>
80 #include <iterator>
81 #include <string>
82 #include <utility>
83 
84 using namespace llvm;
85 
86 namespace {
87 
88  struct MachineVerifier {
89  MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
90 
91  unsigned verify(const MachineFunction &MF);
92 
93  Pass *const PASS;
94  const char *Banner;
95  const MachineFunction *MF;
96  const TargetMachine *TM;
97  const TargetInstrInfo *TII;
98  const TargetRegisterInfo *TRI;
99  const MachineRegisterInfo *MRI;
100  const RegisterBankInfo *RBI;
101 
102  unsigned foundErrors;
103 
104  // Avoid querying the MachineFunctionProperties for each operand.
105  bool isFunctionRegBankSelected;
106  bool isFunctionSelected;
107  bool isFunctionTracksDebugUserValues;
108 
109  using RegVector = SmallVector<Register, 16>;
110  using RegMaskVector = SmallVector<const uint32_t *, 4>;
111  using RegSet = DenseSet<Register>;
114 
115  const MachineInstr *FirstNonPHI;
116  const MachineInstr *FirstTerminator;
117  BlockSet FunctionBlocks;
118 
119  BitVector regsReserved;
120  RegSet regsLive;
121  RegVector regsDefined, regsDead, regsKilled;
122  RegMaskVector regMasks;
123 
124  SlotIndex lastIndex;
125 
126  // Add Reg and any sub-registers to RV
127  void addRegWithSubRegs(RegVector &RV, Register Reg) {
128  RV.push_back(Reg);
129  if (Reg.isPhysical())
130  append_range(RV, TRI->subregs(Reg.asMCReg()));
131  }
132 
133  struct BBInfo {
134  // Is this MBB reachable from the MF entry point?
135  bool reachable = false;
136 
137  // Vregs that must be live in because they are used without being
138  // defined. Map value is the user. vregsLiveIn doesn't include regs
139  // that only are used by PHI nodes.
140  RegMap vregsLiveIn;
141 
142  // Regs killed in MBB. They may be defined again, and will then be in both
143  // regsKilled and regsLiveOut.
144  RegSet regsKilled;
145 
146  // Regs defined in MBB and live out. Note that vregs passing through may
147  // be live out without being mentioned here.
148  RegSet regsLiveOut;
149 
150  // Vregs that pass through MBB untouched. This set is disjoint from
151  // regsKilled and regsLiveOut.
152  RegSet vregsPassed;
153 
154  // Vregs that must pass through MBB because they are needed by a successor
155  // block. This set is disjoint from regsLiveOut.
156  RegSet vregsRequired;
157 
158  // Set versions of block's predecessor and successor lists.
159  BlockSet Preds, Succs;
160 
161  BBInfo() = default;
162 
163  // Add register to vregsRequired if it belongs there. Return true if
164  // anything changed.
165  bool addRequired(Register Reg) {
166  if (!Reg.isVirtual())
167  return false;
168  if (regsLiveOut.count(Reg))
169  return false;
170  return vregsRequired.insert(Reg).second;
171  }
172 
173  // Same for a full set.
174  bool addRequired(const RegSet &RS) {
175  bool Changed = false;
176  for (Register Reg : RS)
177  Changed |= addRequired(Reg);
178  return Changed;
179  }
180 
181  // Same for a full map.
182  bool addRequired(const RegMap &RM) {
183  bool Changed = false;
184  for (const auto &I : RM)
185  Changed |= addRequired(I.first);
186  return Changed;
187  }
188 
189  // Live-out registers are either in regsLiveOut or vregsPassed.
190  bool isLiveOut(Register Reg) const {
191  return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
192  }
193  };
194 
195  // Extra register info per MBB.
197 
198  bool isReserved(Register Reg) {
199  return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id());
200  }
201 
202  bool isAllocatable(Register Reg) const {
203  return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
204  !regsReserved.test(Reg.id());
205  }
206 
207  // Analysis information if available
208  LiveVariables *LiveVars;
209  LiveIntervals *LiveInts;
210  LiveStacks *LiveStks;
211  SlotIndexes *Indexes;
212 
213  void visitMachineFunctionBefore();
214  void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
215  void visitMachineBundleBefore(const MachineInstr *MI);
216 
217  /// Verify that all of \p MI's virtual register operands are scalars.
218  /// \returns True if all virtual register operands are scalar. False
219  /// otherwise.
220  bool verifyAllRegOpsScalar(const MachineInstr &MI,
221  const MachineRegisterInfo &MRI);
222  bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
223  void verifyPreISelGenericInstruction(const MachineInstr *MI);
224  void visitMachineInstrBefore(const MachineInstr *MI);
225  void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
226  void visitMachineBundleAfter(const MachineInstr *MI);
227  void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
228  void visitMachineFunctionAfter();
229 
230  void report(const char *msg, const MachineFunction *MF);
231  void report(const char *msg, const MachineBasicBlock *MBB);
232  void report(const char *msg, const MachineInstr *MI);
233  void report(const char *msg, const MachineOperand *MO, unsigned MONum,
234  LLT MOVRegType = LLT{});
235  void report(const Twine &Msg, const MachineInstr *MI);
236 
237  void report_context(const LiveInterval &LI) const;
238  void report_context(const LiveRange &LR, Register VRegUnit,
239  LaneBitmask LaneMask) const;
240  void report_context(const LiveRange::Segment &S) const;
241  void report_context(const VNInfo &VNI) const;
242  void report_context(SlotIndex Pos) const;
243  void report_context(MCPhysReg PhysReg) const;
244  void report_context_liverange(const LiveRange &LR) const;
245  void report_context_lanemask(LaneBitmask LaneMask) const;
246  void report_context_vreg(Register VReg) const;
247  void report_context_vreg_regunit(Register VRegOrUnit) const;
248 
249  void verifyInlineAsm(const MachineInstr *MI);
250 
251  void checkLiveness(const MachineOperand *MO, unsigned MONum);
252  void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
253  SlotIndex UseIdx, const LiveRange &LR,
254  Register VRegOrUnit,
255  LaneBitmask LaneMask = LaneBitmask::getNone());
256  void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
257  SlotIndex DefIdx, const LiveRange &LR,
258  Register VRegOrUnit, bool SubRangeCheck = false,
259  LaneBitmask LaneMask = LaneBitmask::getNone());
260 
261  void markReachable(const MachineBasicBlock *MBB);
262  void calcRegsPassed();
263  void checkPHIOps(const MachineBasicBlock &MBB);
264 
265  void calcRegsRequired();
266  void verifyLiveVariables();
267  void verifyLiveIntervals();
268  void verifyLiveInterval(const LiveInterval&);
269  void verifyLiveRangeValue(const LiveRange &, const VNInfo *, Register,
270  LaneBitmask);
271  void verifyLiveRangeSegment(const LiveRange &,
273  LaneBitmask);
274  void verifyLiveRange(const LiveRange &, Register,
275  LaneBitmask LaneMask = LaneBitmask::getNone());
276 
277  void verifyStackFrame();
278 
279  void verifySlotIndexes() const;
280  void verifyProperties(const MachineFunction &MF);
281  };
282 
283  struct MachineVerifierPass : public MachineFunctionPass {
284  static char ID; // Pass ID, replacement for typeid
285 
286  const std::string Banner;
287 
288  MachineVerifierPass(std::string banner = std::string())
289  : MachineFunctionPass(ID), Banner(std::move(banner)) {
291  }
292 
293  void getAnalysisUsage(AnalysisUsage &AU) const override {
294  AU.setPreservesAll();
296  }
297 
298  bool runOnMachineFunction(MachineFunction &MF) override {
299  // Skip functions that have known verification problems.
300  // FIXME: Remove this mechanism when all problematic passes have been
301  // fixed.
302  if (MF.getProperties().hasProperty(
304  return false;
305 
306  unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
307  if (FoundErrors)
308  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
309  return false;
310  }
311  };
312 
313 } // end anonymous namespace
314 
315 char MachineVerifierPass::ID = 0;
316 
317 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
318  "Verify generated machine code", false, false)
319 
321  return new MachineVerifierPass(Banner);
322 }
323 
325  const std::string &Banner,
326  const MachineFunction &MF) {
327  // TODO: Use MFAM after porting below analyses.
328  // LiveVariables *LiveVars;
329  // LiveIntervals *LiveInts;
330  // LiveStacks *LiveStks;
331  // SlotIndexes *Indexes;
332  unsigned FoundErrors = MachineVerifier(nullptr, Banner.c_str()).verify(MF);
333  if (FoundErrors)
334  report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
335 }
336 
337 bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
338  const {
339  MachineFunction &MF = const_cast<MachineFunction&>(*this);
340  unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
341  if (AbortOnErrors && FoundErrors)
342  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
343  return FoundErrors == 0;
344 }
345 
346 void MachineVerifier::verifySlotIndexes() const {
347  if (Indexes == nullptr)
348  return;
349 
350  // Ensure the IdxMBB list is sorted by slot indexes.
351  SlotIndex Last;
353  E = Indexes->MBBIndexEnd(); I != E; ++I) {
354  assert(!Last.isValid() || I->first > Last);
355  Last = I->first;
356  }
357 }
358 
359 void MachineVerifier::verifyProperties(const MachineFunction &MF) {
360  // If a pass has introduced virtual registers without clearing the
361  // NoVRegs property (or set it without allocating the vregs)
362  // then report an error.
363  if (MF.getProperties().hasProperty(
365  MRI->getNumVirtRegs())
366  report("Function has NoVRegs property but there are VReg operands", &MF);
367 }
368 
369 unsigned MachineVerifier::verify(const MachineFunction &MF) {
370  foundErrors = 0;
371 
372  this->MF = &MF;
373  TM = &MF.getTarget();
374  TII = MF.getSubtarget().getInstrInfo();
376  RBI = MF.getSubtarget().getRegBankInfo();
377  MRI = &MF.getRegInfo();
378 
379  const bool isFunctionFailedISel = MF.getProperties().hasProperty(
381 
382  // If we're mid-GlobalISel and we already triggered the fallback path then
383  // it's expected that the MIR is somewhat broken but that's ok since we'll
384  // reset it and clear the FailedISel attribute in ResetMachineFunctions.
385  if (isFunctionFailedISel)
386  return foundErrors;
387 
388  isFunctionRegBankSelected = MF.getProperties().hasProperty(
390  isFunctionSelected = MF.getProperties().hasProperty(
392  isFunctionTracksDebugUserValues = MF.getProperties().hasProperty(
394 
395  LiveVars = nullptr;
396  LiveInts = nullptr;
397  LiveStks = nullptr;
398  Indexes = nullptr;
399  if (PASS) {
400  LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
401  // We don't want to verify LiveVariables if LiveIntervals is available.
402  if (!LiveInts)
403  LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
404  LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
405  Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
406  }
407 
408  verifySlotIndexes();
409 
410  verifyProperties(MF);
411 
412  visitMachineFunctionBefore();
413  for (const MachineBasicBlock &MBB : MF) {
414  visitMachineBasicBlockBefore(&MBB);
415  // Keep track of the current bundle header.
416  const MachineInstr *CurBundle = nullptr;
417  // Do we expect the next instruction to be part of the same bundle?
418  bool InBundle = false;
419 
420  for (const MachineInstr &MI : MBB.instrs()) {
421  if (MI.getParent() != &MBB) {
422  report("Bad instruction parent pointer", &MBB);
423  errs() << "Instruction: " << MI;
424  continue;
425  }
426 
427  // Check for consistent bundle flags.
428  if (InBundle && !MI.isBundledWithPred())
429  report("Missing BundledPred flag, "
430  "BundledSucc was set on predecessor",
431  &MI);
432  if (!InBundle && MI.isBundledWithPred())
433  report("BundledPred flag is set, "
434  "but BundledSucc not set on predecessor",
435  &MI);
436 
437  // Is this a bundle header?
438  if (!MI.isInsideBundle()) {
439  if (CurBundle)
440  visitMachineBundleAfter(CurBundle);
441  CurBundle = &MI;
442  visitMachineBundleBefore(CurBundle);
443  } else if (!CurBundle)
444  report("No bundle header", &MI);
445  visitMachineInstrBefore(&MI);
446  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
447  const MachineOperand &Op = MI.getOperand(I);
448  if (Op.getParent() != &MI) {
449  // Make sure to use correct addOperand / removeOperand / ChangeTo
450  // functions when replacing operands of a MachineInstr.
451  report("Instruction has operand with wrong parent set", &MI);
452  }
453 
454  visitMachineOperand(&Op, I);
455  }
456 
457  // Was this the last bundled instruction?
458  InBundle = MI.isBundledWithSucc();
459  }
460  if (CurBundle)
461  visitMachineBundleAfter(CurBundle);
462  if (InBundle)
463  report("BundledSucc flag set on last instruction in block", &MBB.back());
464  visitMachineBasicBlockAfter(&MBB);
465  }
466  visitMachineFunctionAfter();
467 
468  // Clean up.
469  regsLive.clear();
470  regsDefined.clear();
471  regsDead.clear();
472  regsKilled.clear();
473  regMasks.clear();
474  MBBInfoMap.clear();
475 
476  return foundErrors;
477 }
478 
479 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
480  assert(MF);
481  errs() << '\n';
482  if (!foundErrors++) {
483  if (Banner)
484  errs() << "# " << Banner << '\n';
485  if (LiveInts != nullptr)
486  LiveInts->print(errs());
487  else
488  MF->print(errs(), Indexes);
489  }
490  errs() << "*** Bad machine code: " << msg << " ***\n"
491  << "- function: " << MF->getName() << "\n";
492 }
493 
494 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
495  assert(MBB);
496  report(msg, MBB->getParent());
497  errs() << "- basic block: " << printMBBReference(*MBB) << ' '
498  << MBB->getName() << " (" << (const void *)MBB << ')';
499  if (Indexes)
500  errs() << " [" << Indexes->getMBBStartIdx(MBB)
501  << ';' << Indexes->getMBBEndIdx(MBB) << ')';
502  errs() << '\n';
503 }
504 
505 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
506  assert(MI);
507  report(msg, MI->getParent());
508  errs() << "- instruction: ";
509  if (Indexes && Indexes->hasIndex(*MI))
510  errs() << Indexes->getInstructionIndex(*MI) << '\t';
511  MI->print(errs(), /*IsStandalone=*/true);
512 }
513 
514 void MachineVerifier::report(const char *msg, const MachineOperand *MO,
515  unsigned MONum, LLT MOVRegType) {
516  assert(MO);
517  report(msg, MO->getParent());
518  errs() << "- operand " << MONum << ": ";
519  MO->print(errs(), MOVRegType, TRI);
520  errs() << "\n";
521 }
522 
523 void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
524  report(Msg.str().c_str(), MI);
525 }
526 
527 void MachineVerifier::report_context(SlotIndex Pos) const {
528  errs() << "- at: " << Pos << '\n';
529 }
530 
531 void MachineVerifier::report_context(const LiveInterval &LI) const {
532  errs() << "- interval: " << LI << '\n';
533 }
534 
535 void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
536  LaneBitmask LaneMask) const {
537  report_context_liverange(LR);
538  report_context_vreg_regunit(VRegUnit);
539  if (LaneMask.any())
540  report_context_lanemask(LaneMask);
541 }
542 
543 void MachineVerifier::report_context(const LiveRange::Segment &S) const {
544  errs() << "- segment: " << S << '\n';
545 }
546 
547 void MachineVerifier::report_context(const VNInfo &VNI) const {
548  errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
549 }
550 
551 void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
552  errs() << "- liverange: " << LR << '\n';
553 }
554 
555 void MachineVerifier::report_context(MCPhysReg PReg) const {
556  errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
557 }
558 
559 void MachineVerifier::report_context_vreg(Register VReg) const {
560  errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
561 }
562 
563 void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
564  if (Register::isVirtualRegister(VRegOrUnit)) {
565  report_context_vreg(VRegOrUnit);
566  } else {
567  errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
568  }
569 }
570 
571 void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
572  errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
573 }
574 
575 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
576  BBInfo &MInfo = MBBInfoMap[MBB];
577  if (!MInfo.reachable) {
578  MInfo.reachable = true;
579  for (const MachineBasicBlock *Succ : MBB->successors())
580  markReachable(Succ);
581  }
582 }
583 
584 void MachineVerifier::visitMachineFunctionBefore() {
585  lastIndex = SlotIndex();
586  regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
587  : TRI->getReservedRegs(*MF);
588 
589  if (!MF->empty())
590  markReachable(&MF->front());
591 
592  // Build a set of the basic blocks in the function.
593  FunctionBlocks.clear();
594  for (const auto &MBB : *MF) {
595  FunctionBlocks.insert(&MBB);
596  BBInfo &MInfo = MBBInfoMap[&MBB];
597 
598  MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
599  if (MInfo.Preds.size() != MBB.pred_size())
600  report("MBB has duplicate entries in its predecessor list.", &MBB);
601 
602  MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
603  if (MInfo.Succs.size() != MBB.succ_size())
604  report("MBB has duplicate entries in its successor list.", &MBB);
605  }
606 
607  // Check that the register use lists are sane.
608  MRI->verifyUseLists();
609 
610  if (!MF->empty())
611  verifyStackFrame();
612 }
613 
614 void
615 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
616  FirstTerminator = nullptr;
617  FirstNonPHI = nullptr;
618 
619  if (!MF->getProperties().hasProperty(
621  // If this block has allocatable physical registers live-in, check that
622  // it is an entry block or landing pad.
623  for (const auto &LI : MBB->liveins()) {
624  if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
625  MBB->getIterator() != MBB->getParent()->begin()) {
626  report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
627  report_context(LI.PhysReg);
628  }
629  }
630  }
631 
632  // Count the number of landing pad successors.
634  for (const auto *succ : MBB->successors()) {
635  if (succ->isEHPad())
636  LandingPadSuccs.insert(succ);
637  if (!FunctionBlocks.count(succ))
638  report("MBB has successor that isn't part of the function.", MBB);
639  if (!MBBInfoMap[succ].Preds.count(MBB)) {
640  report("Inconsistent CFG", MBB);
641  errs() << "MBB is not in the predecessor list of the successor "
642  << printMBBReference(*succ) << ".\n";
643  }
644  }
645 
646  // Check the predecessor list.
647  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
648  if (!FunctionBlocks.count(Pred))
649  report("MBB has predecessor that isn't part of the function.", MBB);
650  if (!MBBInfoMap[Pred].Succs.count(MBB)) {
651  report("Inconsistent CFG", MBB);
652  errs() << "MBB is not in the successor list of the predecessor "
653  << printMBBReference(*Pred) << ".\n";
654  }
655  }
656 
657  const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
658  const BasicBlock *BB = MBB->getBasicBlock();
659  const Function &F = MF->getFunction();
660  if (LandingPadSuccs.size() > 1 &&
661  !(AsmInfo &&
663  BB && isa<SwitchInst>(BB->getTerminator())) &&
664  !isScopedEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
665  report("MBB has more than one landing pad successor", MBB);
666 
667  // Call analyzeBranch. If it succeeds, there several more conditions to check.
668  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
670  if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
671  Cond)) {
672  // Ok, analyzeBranch thinks it knows what's going on with this block. Let's
673  // check whether its answers match up with reality.
674  if (!TBB && !FBB) {
675  // Block falls through to its successor.
676  if (!MBB->empty() && MBB->back().isBarrier() &&
677  !TII->isPredicated(MBB->back())) {
678  report("MBB exits via unconditional fall-through but ends with a "
679  "barrier instruction!", MBB);
680  }
681  if (!Cond.empty()) {
682  report("MBB exits via unconditional fall-through but has a condition!",
683  MBB);
684  }
685  } else if (TBB && !FBB && Cond.empty()) {
686  // Block unconditionally branches somewhere.
687  if (MBB->empty()) {
688  report("MBB exits via unconditional branch but doesn't contain "
689  "any instructions!", MBB);
690  } else if (!MBB->back().isBarrier()) {
691  report("MBB exits via unconditional branch but doesn't end with a "
692  "barrier instruction!", MBB);
693  } else if (!MBB->back().isTerminator()) {
694  report("MBB exits via unconditional branch but the branch isn't a "
695  "terminator instruction!", MBB);
696  }
697  } else if (TBB && !FBB && !Cond.empty()) {
698  // Block conditionally branches somewhere, otherwise falls through.
699  if (MBB->empty()) {
700  report("MBB exits via conditional branch/fall-through but doesn't "
701  "contain any instructions!", MBB);
702  } else if (MBB->back().isBarrier()) {
703  report("MBB exits via conditional branch/fall-through but ends with a "
704  "barrier instruction!", MBB);
705  } else if (!MBB->back().isTerminator()) {
706  report("MBB exits via conditional branch/fall-through but the branch "
707  "isn't a terminator instruction!", MBB);
708  }
709  } else if (TBB && FBB) {
710  // Block conditionally branches somewhere, otherwise branches
711  // somewhere else.
712  if (MBB->empty()) {
713  report("MBB exits via conditional branch/branch but doesn't "
714  "contain any instructions!", MBB);
715  } else if (!MBB->back().isBarrier()) {
716  report("MBB exits via conditional branch/branch but doesn't end with a "
717  "barrier instruction!", MBB);
718  } else if (!MBB->back().isTerminator()) {
719  report("MBB exits via conditional branch/branch but the branch "
720  "isn't a terminator instruction!", MBB);
721  }
722  if (Cond.empty()) {
723  report("MBB exits via conditional branch/branch but there's no "
724  "condition!", MBB);
725  }
726  } else {
727  report("analyzeBranch returned invalid data!", MBB);
728  }
729 
730  // Now check that the successors match up with the answers reported by
731  // analyzeBranch.
732  if (TBB && !MBB->isSuccessor(TBB))
733  report("MBB exits via jump or conditional branch, but its target isn't a "
734  "CFG successor!",
735  MBB);
736  if (FBB && !MBB->isSuccessor(FBB))
737  report("MBB exits via conditional branch, but its target isn't a CFG "
738  "successor!",
739  MBB);
740 
741  // There might be a fallthrough to the next block if there's either no
742  // unconditional true branch, or if there's a condition, and one of the
743  // branches is missing.
744  bool Fallthrough = !TBB || (!Cond.empty() && !FBB);
745 
746  // A conditional fallthrough must be an actual CFG successor, not
747  // unreachable. (Conversely, an unconditional fallthrough might not really
748  // be a successor, because the block might end in unreachable.)
749  if (!Cond.empty() && !FBB) {
751  if (MBBI == MF->end()) {
752  report("MBB conditionally falls through out of function!", MBB);
753  } else if (!MBB->isSuccessor(&*MBBI))
754  report("MBB exits via conditional branch/fall-through but the CFG "
755  "successors don't match the actual successors!",
756  MBB);
757  }
758 
759  // Verify that there aren't any extra un-accounted-for successors.
760  for (const MachineBasicBlock *SuccMBB : MBB->successors()) {
761  // If this successor is one of the branch targets, it's okay.
762  if (SuccMBB == TBB || SuccMBB == FBB)
763  continue;
764  // If we might have a fallthrough, and the successor is the fallthrough
765  // block, that's also ok.
766  if (Fallthrough && SuccMBB == MBB->getNextNode())
767  continue;
768  // Also accept successors which are for exception-handling or might be
769  // inlineasm_br targets.
770  if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
771  continue;
772  report("MBB has unexpected successors which are not branch targets, "
773  "fallthrough, EHPads, or inlineasm_br targets.",
774  MBB);
775  }
776  }
777 
778  regsLive.clear();
779  if (MRI->tracksLiveness()) {
780  for (const auto &LI : MBB->liveins()) {
781  if (!Register::isPhysicalRegister(LI.PhysReg)) {
782  report("MBB live-in list contains non-physical register", MBB);
783  continue;
784  }
785  for (const MCPhysReg &SubReg : TRI->subregs_inclusive(LI.PhysReg))
786  regsLive.insert(SubReg);
787  }
788  }
789 
790  const MachineFrameInfo &MFI = MF->getFrameInfo();
791  BitVector PR = MFI.getPristineRegs(*MF);
792  for (unsigned I : PR.set_bits()) {
793  for (const MCPhysReg &SubReg : TRI->subregs_inclusive(I))
794  regsLive.insert(SubReg);
795  }
796 
797  regsKilled.clear();
798  regsDefined.clear();
799 
800  if (Indexes)
801  lastIndex = Indexes->getMBBStartIdx(MBB);
802 }
803 
804 // This function gets called for all bundle headers, including normal
805 // stand-alone unbundled instructions.
806 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
807  if (Indexes && Indexes->hasIndex(*MI)) {
808  SlotIndex idx = Indexes->getInstructionIndex(*MI);
809  if (!(idx > lastIndex)) {
810  report("Instruction index out of order", MI);
811  errs() << "Last instruction was at " << lastIndex << '\n';
812  }
813  lastIndex = idx;
814  }
815 
816  // Ensure non-terminators don't follow terminators.
817  if (MI->isTerminator()) {
818  if (!FirstTerminator)
819  FirstTerminator = MI;
820  } else if (FirstTerminator) {
821  report("Non-terminator instruction after the first terminator", MI);
822  errs() << "First terminator was:\t" << *FirstTerminator;
823  }
824 }
825 
826 // The operands on an INLINEASM instruction must follow a template.
827 // Verify that the flag operands make sense.
828 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
829  // The first two operands on INLINEASM are the asm string and global flags.
830  if (MI->getNumOperands() < 2) {
831  report("Too few operands on inline asm", MI);
832  return;
833  }
834  if (!MI->getOperand(0).isSymbol())
835  report("Asm string must be an external symbol", MI);
836  if (!MI->getOperand(1).isImm())
837  report("Asm flags must be an immediate", MI);
838  // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
839  // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
840  // and Extra_IsConvergent = 32.
841  if (!isUInt<6>(MI->getOperand(1).getImm()))
842  report("Unknown asm flags", &MI->getOperand(1), 1);
843 
844  static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
845 
846  unsigned OpNo = InlineAsm::MIOp_FirstOperand;
847  unsigned NumOps;
848  for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
849  const MachineOperand &MO = MI->getOperand(OpNo);
850  // There may be implicit ops after the fixed operands.
851  if (!MO.isImm())
852  break;
853  NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
854  }
855 
856  if (OpNo > MI->getNumOperands())
857  report("Missing operands in last group", MI);
858 
859  // An optional MDNode follows the groups.
860  if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
861  ++OpNo;
862 
863  // All trailing operands must be implicit registers.
864  for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
865  const MachineOperand &MO = MI->getOperand(OpNo);
866  if (!MO.isReg() || !MO.isImplicit())
867  report("Expected implicit register after groups", &MO, OpNo);
868  }
869 }
870 
871 bool MachineVerifier::verifyAllRegOpsScalar(const MachineInstr &MI,
872  const MachineRegisterInfo &MRI) {
873  if (none_of(MI.explicit_operands(), [&MRI](const MachineOperand &Op) {
874  if (!Op.isReg())
875  return false;
876  const auto Reg = Op.getReg();
877  if (Reg.isPhysical())
878  return false;
879  return !MRI.getType(Reg).isScalar();
880  }))
881  return true;
882  report("All register operands must have scalar types", &MI);
883  return false;
884 }
885 
886 /// Check that types are consistent when two operands need to have the same
887 /// number of vector elements.
888 /// \return true if the types are valid.
889 bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
890  const MachineInstr *MI) {
891  if (Ty0.isVector() != Ty1.isVector()) {
892  report("operand types must be all-vector or all-scalar", MI);
893  // Generally we try to report as many issues as possible at once, but in
894  // this case it's not clear what should we be comparing the size of the
895  // scalar with: the size of the whole vector or its lane. Instead of
896  // making an arbitrary choice and emitting not so helpful message, let's
897  // avoid the extra noise and stop here.
898  return false;
899  }
900 
901  if (Ty0.isVector() && Ty0.getNumElements() != Ty1.getNumElements()) {
902  report("operand types must preserve number of vector elements", MI);
903  return false;
904  }
905 
906  return true;
907 }
908 
909 void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
910  if (isFunctionSelected)
911  report("Unexpected generic instruction in a Selected function", MI);
912 
913  const MCInstrDesc &MCID = MI->getDesc();
914  unsigned NumOps = MI->getNumOperands();
915 
916  // Branches must reference a basic block if they are not indirect
917  if (MI->isBranch() && !MI->isIndirectBranch()) {
918  bool HasMBB = false;
919  for (const MachineOperand &Op : MI->operands()) {
920  if (Op.isMBB()) {
921  HasMBB = true;
922  break;
923  }
924  }
925 
926  if (!HasMBB) {
927  report("Branch instruction is missing a basic block operand or "
928  "isIndirectBranch property",
929  MI);
930  }
931  }
932 
933  // Check types.
934  SmallVector<LLT, 4> Types;
935  for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
936  I != E; ++I) {
937  if (!MCID.OpInfo[I].isGenericType())
938  continue;
939  // Generic instructions specify type equality constraints between some of
940  // their operands. Make sure these are consistent.
941  size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
942  Types.resize(std::max(TypeIdx + 1, Types.size()));
943 
944  const MachineOperand *MO = &MI->getOperand(I);
945  if (!MO->isReg()) {
946  report("generic instruction must use register operands", MI);
947  continue;
948  }
949 
950  LLT OpTy = MRI->getType(MO->getReg());
951  // Don't report a type mismatch if there is no actual mismatch, only a
952  // type missing, to reduce noise:
953  if (OpTy.isValid()) {
954  // Only the first valid type for a type index will be printed: don't
955  // overwrite it later so it's always clear which type was expected:
956  if (!Types[TypeIdx].isValid())
957  Types[TypeIdx] = OpTy;
958  else if (Types[TypeIdx] != OpTy)
959  report("Type mismatch in generic instruction", MO, I, OpTy);
960  } else {
961  // Generic instructions must have types attached to their operands.
962  report("Generic instruction is missing a virtual register type", MO, I);
963  }
964  }
965 
966  // Generic opcodes must not have physical register operands.
967  for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
968  const MachineOperand *MO = &MI->getOperand(I);
969  if (MO->isReg() && Register::isPhysicalRegister(MO->getReg()))
970  report("Generic instruction cannot have physical register", MO, I);
971  }
972 
973  // Avoid out of bounds in checks below. This was already reported earlier.
974  if (MI->getNumOperands() < MCID.getNumOperands())
975  return;
976 
978  if (!TII->verifyInstruction(*MI, ErrorInfo))
979  report(ErrorInfo.data(), MI);
980 
981  // Verify properties of various specific instruction types
982  unsigned Opc = MI->getOpcode();
983  switch (Opc) {
984  case TargetOpcode::G_ASSERT_SEXT:
985  case TargetOpcode::G_ASSERT_ZEXT: {
986  std::string OpcName =
987  Opc == TargetOpcode::G_ASSERT_ZEXT ? "G_ASSERT_ZEXT" : "G_ASSERT_SEXT";
988  if (!MI->getOperand(2).isImm()) {
989  report(Twine(OpcName, " expects an immediate operand #2"), MI);
990  break;
991  }
992 
993  Register Dst = MI->getOperand(0).getReg();
994  Register Src = MI->getOperand(1).getReg();
995  LLT SrcTy = MRI->getType(Src);
996  int64_t Imm = MI->getOperand(2).getImm();
997  if (Imm <= 0) {
998  report(Twine(OpcName, " size must be >= 1"), MI);
999  break;
1000  }
1001 
1002  if (Imm >= SrcTy.getScalarSizeInBits()) {
1003  report(Twine(OpcName, " size must be less than source bit width"), MI);
1004  break;
1005  }
1006 
1007  const RegisterBank *SrcRB = RBI->getRegBank(Src, *MRI, *TRI);
1008  const RegisterBank *DstRB = RBI->getRegBank(Dst, *MRI, *TRI);
1009 
1010  // Allow only the source bank to be set.
1011  if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1012  report(Twine(OpcName, " cannot change register bank"), MI);
1013  break;
1014  }
1015 
1016  // Don't allow a class change. Do allow member class->regbank.
1017  const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(Dst);
1018  if (DstRC && DstRC != MRI->getRegClassOrNull(Src)) {
1019  report(
1020  Twine(OpcName, " source and destination register classes must match"),
1021  MI);
1022  break;
1023  }
1024 
1025  break;
1026  }
1027 
1028  case TargetOpcode::G_CONSTANT:
1029  case TargetOpcode::G_FCONSTANT: {
1030  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1031  if (DstTy.isVector())
1032  report("Instruction cannot use a vector result type", MI);
1033 
1034  if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1035  if (!MI->getOperand(1).isCImm()) {
1036  report("G_CONSTANT operand must be cimm", MI);
1037  break;
1038  }
1039 
1040  const ConstantInt *CI = MI->getOperand(1).getCImm();
1041  if (CI->getBitWidth() != DstTy.getSizeInBits())
1042  report("inconsistent constant size", MI);
1043  } else {
1044  if (!MI->getOperand(1).isFPImm()) {
1045  report("G_FCONSTANT operand must be fpimm", MI);
1046  break;
1047  }
1048  const ConstantFP *CF = MI->getOperand(1).getFPImm();
1049 
1051  DstTy.getSizeInBits()) {
1052  report("inconsistent constant size", MI);
1053  }
1054  }
1055 
1056  break;
1057  }
1058  case TargetOpcode::G_LOAD:
1059  case TargetOpcode::G_STORE:
1060  case TargetOpcode::G_ZEXTLOAD:
1061  case TargetOpcode::G_SEXTLOAD: {
1062  LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1063  LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1064  if (!PtrTy.isPointer())
1065  report("Generic memory instruction must access a pointer", MI);
1066 
1067  // Generic loads and stores must have a single MachineMemOperand
1068  // describing that access.
1069  if (!MI->hasOneMemOperand()) {
1070  report("Generic instruction accessing memory must have one mem operand",
1071  MI);
1072  } else {
1073  const MachineMemOperand &MMO = **MI->memoperands_begin();
1074  if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1075  MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1076  if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
1077  report("Generic extload must have a narrower memory type", MI);
1078  } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
1079  if (MMO.getSize() > ValTy.getSizeInBytes())
1080  report("load memory size cannot exceed result size", MI);
1081  } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
1082  if (ValTy.getSizeInBytes() < MMO.getSize())
1083  report("store memory size cannot exceed value size", MI);
1084  }
1085 
1086  const AtomicOrdering Order = MMO.getSuccessOrdering();
1087  if (Opc == TargetOpcode::G_STORE) {
1088  if (Order == AtomicOrdering::Acquire ||
1090  report("atomic store cannot use acquire ordering", MI);
1091 
1092  } else {
1093  if (Order == AtomicOrdering::Release ||
1095  report("atomic load cannot use release ordering", MI);
1096  }
1097  }
1098 
1099  break;
1100  }
1101  case TargetOpcode::G_PHI: {
1102  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1103  if (!DstTy.isValid() || !all_of(drop_begin(MI->operands()),
1104  [this, &DstTy](const MachineOperand &MO) {
1105  if (!MO.isReg())
1106  return true;
1107  LLT Ty = MRI->getType(MO.getReg());
1108  if (!Ty.isValid() || (Ty != DstTy))
1109  return false;
1110  return true;
1111  }))
1112  report("Generic Instruction G_PHI has operands with incompatible/missing "
1113  "types",
1114  MI);
1115  break;
1116  }
1117  case TargetOpcode::G_BITCAST: {
1118  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1119  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1120  if (!DstTy.isValid() || !SrcTy.isValid())
1121  break;
1122 
1123  if (SrcTy.isPointer() != DstTy.isPointer())
1124  report("bitcast cannot convert between pointers and other types", MI);
1125 
1126  if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1127  report("bitcast sizes must match", MI);
1128 
1129  if (SrcTy == DstTy)
1130  report("bitcast must change the type", MI);
1131 
1132  break;
1133  }
1134  case TargetOpcode::G_INTTOPTR:
1135  case TargetOpcode::G_PTRTOINT:
1136  case TargetOpcode::G_ADDRSPACE_CAST: {
1137  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1138  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1139  if (!DstTy.isValid() || !SrcTy.isValid())
1140  break;
1141 
1142  verifyVectorElementMatch(DstTy, SrcTy, MI);
1143 
1144  DstTy = DstTy.getScalarType();
1145  SrcTy = SrcTy.getScalarType();
1146 
1147  if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1148  if (!DstTy.isPointer())
1149  report("inttoptr result type must be a pointer", MI);
1150  if (SrcTy.isPointer())
1151  report("inttoptr source type must not be a pointer", MI);
1152  } else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1153  if (!SrcTy.isPointer())
1154  report("ptrtoint source type must be a pointer", MI);
1155  if (DstTy.isPointer())
1156  report("ptrtoint result type must not be a pointer", MI);
1157  } else {
1158  assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1159  if (!SrcTy.isPointer() || !DstTy.isPointer())
1160  report("addrspacecast types must be pointers", MI);
1161  else {
1162  if (SrcTy.getAddressSpace() == DstTy.getAddressSpace())
1163  report("addrspacecast must convert different address spaces", MI);
1164  }
1165  }
1166 
1167  break;
1168  }
1169  case TargetOpcode::G_PTR_ADD: {
1170  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1171  LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1172  LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1173  if (!DstTy.isValid() || !PtrTy.isValid() || !OffsetTy.isValid())
1174  break;
1175 
1176  if (!PtrTy.getScalarType().isPointer())
1177  report("gep first operand must be a pointer", MI);
1178 
1179  if (OffsetTy.getScalarType().isPointer())
1180  report("gep offset operand must not be a pointer", MI);
1181 
1182  // TODO: Is the offset allowed to be a scalar with a vector?
1183  break;
1184  }
1185  case TargetOpcode::G_PTRMASK: {
1186  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1187  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1188  LLT MaskTy = MRI->getType(MI->getOperand(2).getReg());
1189  if (!DstTy.isValid() || !SrcTy.isValid() || !MaskTy.isValid())
1190  break;
1191 
1192  if (!DstTy.getScalarType().isPointer())
1193  report("ptrmask result type must be a pointer", MI);
1194 
1195  if (!MaskTy.getScalarType().isScalar())
1196  report("ptrmask mask type must be an integer", MI);
1197 
1198  verifyVectorElementMatch(DstTy, MaskTy, MI);
1199  break;
1200  }
1201  case TargetOpcode::G_SEXT:
1202  case TargetOpcode::G_ZEXT:
1203  case TargetOpcode::G_ANYEXT:
1204  case TargetOpcode::G_TRUNC:
1205  case TargetOpcode::G_FPEXT:
1206  case TargetOpcode::G_FPTRUNC: {
1207  // Number of operands and presense of types is already checked (and
1208  // reported in case of any issues), so no need to report them again. As
1209  // we're trying to report as many issues as possible at once, however, the
1210  // instructions aren't guaranteed to have the right number of operands or
1211  // types attached to them at this point
1212  assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
1213  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1214  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1215  if (!DstTy.isValid() || !SrcTy.isValid())
1216  break;
1217 
1218  LLT DstElTy = DstTy.getScalarType();
1219  LLT SrcElTy = SrcTy.getScalarType();
1220  if (DstElTy.isPointer() || SrcElTy.isPointer())
1221  report("Generic extend/truncate can not operate on pointers", MI);
1222 
1223  verifyVectorElementMatch(DstTy, SrcTy, MI);
1224 
1225  unsigned DstSize = DstElTy.getSizeInBits();
1226  unsigned SrcSize = SrcElTy.getSizeInBits();
1227  switch (MI->getOpcode()) {
1228  default:
1229  if (DstSize <= SrcSize)
1230  report("Generic extend has destination type no larger than source", MI);
1231  break;
1232  case TargetOpcode::G_TRUNC:
1233  case TargetOpcode::G_FPTRUNC:
1234  if (DstSize >= SrcSize)
1235  report("Generic truncate has destination type no smaller than source",
1236  MI);
1237  break;
1238  }
1239  break;
1240  }
1241  case TargetOpcode::G_SELECT: {
1242  LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1243  LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1244  if (!SelTy.isValid() || !CondTy.isValid())
1245  break;
1246 
1247  // Scalar condition select on a vector is valid.
1248  if (CondTy.isVector())
1249  verifyVectorElementMatch(SelTy, CondTy, MI);
1250  break;
1251  }
1252  case TargetOpcode::G_MERGE_VALUES: {
1253  // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1254  // e.g. s2N = MERGE sN, sN
1255  // Merging multiple scalars into a vector is not allowed, should use
1256  // G_BUILD_VECTOR for that.
1257  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1258  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1259  if (DstTy.isVector() || SrcTy.isVector())
1260  report("G_MERGE_VALUES cannot operate on vectors", MI);
1261 
1262  const unsigned NumOps = MI->getNumOperands();
1263  if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
1264  report("G_MERGE_VALUES result size is inconsistent", MI);
1265 
1266  for (unsigned I = 2; I != NumOps; ++I) {
1267  if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1268  report("G_MERGE_VALUES source types do not match", MI);
1269  }
1270 
1271  break;
1272  }
1273  case TargetOpcode::G_UNMERGE_VALUES: {
1274  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1275  LLT SrcTy = MRI->getType(MI->getOperand(MI->getNumOperands()-1).getReg());
1276  // For now G_UNMERGE can split vectors.
1277  for (unsigned i = 0; i < MI->getNumOperands()-1; ++i) {
1278  if (MRI->getType(MI->getOperand(i).getReg()) != DstTy)
1279  report("G_UNMERGE_VALUES destination types do not match", MI);
1280  }
1281  if (SrcTy.getSizeInBits() !=
1282  (DstTy.getSizeInBits() * (MI->getNumOperands() - 1))) {
1283  report("G_UNMERGE_VALUES source operand does not cover dest operands",
1284  MI);
1285  }
1286  break;
1287  }
1288  case TargetOpcode::G_BUILD_VECTOR: {
1289  // Source types must be scalars, dest type a vector. Total size of scalars
1290  // must match the dest vector size.
1291  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1292  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1293  if (!DstTy.isVector() || SrcEltTy.isVector()) {
1294  report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
1295  break;
1296  }
1297 
1298  if (DstTy.getElementType() != SrcEltTy)
1299  report("G_BUILD_VECTOR result element type must match source type", MI);
1300 
1301  if (DstTy.getNumElements() != MI->getNumOperands() - 1)
1302  report("G_BUILD_VECTOR must have an operand for each elemement", MI);
1303 
1304  for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1305  if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1306  report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
1307 
1308  break;
1309  }
1310  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1311  // Source types must be scalars, dest type a vector. Scalar types must be
1312  // larger than the dest vector elt type, as this is a truncating operation.
1313  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1314  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1315  if (!DstTy.isVector() || SrcEltTy.isVector())
1316  report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1317  MI);
1318  for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1319  if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1320  report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1321  MI);
1322  if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
1323  report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1324  "dest elt type",
1325  MI);
1326  break;
1327  }
1328  case TargetOpcode::G_CONCAT_VECTORS: {
1329  // Source types should be vectors, and total size should match the dest
1330  // vector size.
1331  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1332  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1333  if (!DstTy.isVector() || !SrcTy.isVector())
1334  report("G_CONCAT_VECTOR requires vector source and destination operands",
1335  MI);
1336 
1337  if (MI->getNumOperands() < 3)
1338  report("G_CONCAT_VECTOR requires at least 2 source operands", MI);
1339 
1340  for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1341  if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1342  report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
1343  if (DstTy.getNumElements() !=
1344  SrcTy.getNumElements() * (MI->getNumOperands() - 1))
1345  report("G_CONCAT_VECTOR num dest and source elements should match", MI);
1346  break;
1347  }
1348  case TargetOpcode::G_ICMP:
1349  case TargetOpcode::G_FCMP: {
1350  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1351  LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1352 
1353  if ((DstTy.isVector() != SrcTy.isVector()) ||
1354  (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements()))
1355  report("Generic vector icmp/fcmp must preserve number of lanes", MI);
1356 
1357  break;
1358  }
1359  case TargetOpcode::G_EXTRACT: {
1360  const MachineOperand &SrcOp = MI->getOperand(1);
1361  if (!SrcOp.isReg()) {
1362  report("extract source must be a register", MI);
1363  break;
1364  }
1365 
1366  const MachineOperand &OffsetOp = MI->getOperand(2);
1367  if (!OffsetOp.isImm()) {
1368  report("extract offset must be a constant", MI);
1369  break;
1370  }
1371 
1372  unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1373  unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1374  if (SrcSize == DstSize)
1375  report("extract source must be larger than result", MI);
1376 
1377  if (DstSize + OffsetOp.getImm() > SrcSize)
1378  report("extract reads past end of register", MI);
1379  break;
1380  }
1381  case TargetOpcode::G_INSERT: {
1382  const MachineOperand &SrcOp = MI->getOperand(2);
1383  if (!SrcOp.isReg()) {
1384  report("insert source must be a register", MI);
1385  break;
1386  }
1387 
1388  const MachineOperand &OffsetOp = MI->getOperand(3);
1389  if (!OffsetOp.isImm()) {
1390  report("insert offset must be a constant", MI);
1391  break;
1392  }
1393 
1394  unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1395  unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1396 
1397  if (DstSize <= SrcSize)
1398  report("inserted size must be smaller than total register", MI);
1399 
1400  if (SrcSize + OffsetOp.getImm() > DstSize)
1401  report("insert writes past end of register", MI);
1402 
1403  break;
1404  }
1405  case TargetOpcode::G_JUMP_TABLE: {
1406  if (!MI->getOperand(1).isJTI())
1407  report("G_JUMP_TABLE source operand must be a jump table index", MI);
1408  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1409  if (!DstTy.isPointer())
1410  report("G_JUMP_TABLE dest operand must have a pointer type", MI);
1411  break;
1412  }
1413  case TargetOpcode::G_BRJT: {
1414  if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1415  report("G_BRJT src operand 0 must be a pointer type", MI);
1416 
1417  if (!MI->getOperand(1).isJTI())
1418  report("G_BRJT src operand 1 must be a jump table index", MI);
1419 
1420  const auto &IdxOp = MI->getOperand(2);
1421  if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1422  report("G_BRJT src operand 2 must be a scalar reg type", MI);
1423  break;
1424  }
1425  case TargetOpcode::G_INTRINSIC:
1426  case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1427  // TODO: Should verify number of def and use operands, but the current
1428  // interface requires passing in IR types for mangling.
1429  const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1430  if (!IntrIDOp.isIntrinsicID()) {
1431  report("G_INTRINSIC first src operand must be an intrinsic ID", MI);
1432  break;
1433  }
1434 
1435  bool NoSideEffects = MI->getOpcode() == TargetOpcode::G_INTRINSIC;
1436  unsigned IntrID = IntrIDOp.getIntrinsicID();
1437  if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1439  = Intrinsic::getAttributes(MF->getFunction().getContext(),
1440  static_cast<Intrinsic::ID>(IntrID));
1441  bool DeclHasSideEffects = !Attrs.hasFnAttr(Attribute::ReadNone);
1442  if (NoSideEffects && DeclHasSideEffects) {
1443  report("G_INTRINSIC used with intrinsic that accesses memory", MI);
1444  break;
1445  }
1446  if (!NoSideEffects && !DeclHasSideEffects) {
1447  report("G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic", MI);
1448  break;
1449  }
1450  }
1451 
1452  break;
1453  }
1454  case TargetOpcode::G_SEXT_INREG: {
1455  if (!MI->getOperand(2).isImm()) {
1456  report("G_SEXT_INREG expects an immediate operand #2", MI);
1457  break;
1458  }
1459 
1460  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1461  int64_t Imm = MI->getOperand(2).getImm();
1462  if (Imm <= 0)
1463  report("G_SEXT_INREG size must be >= 1", MI);
1464  if (Imm >= SrcTy.getScalarSizeInBits())
1465  report("G_SEXT_INREG size must be less than source bit width", MI);
1466  break;
1467  }
1468  case TargetOpcode::G_SHUFFLE_VECTOR: {
1469  const MachineOperand &MaskOp = MI->getOperand(3);
1470  if (!MaskOp.isShuffleMask()) {
1471  report("Incorrect mask operand type for G_SHUFFLE_VECTOR", MI);
1472  break;
1473  }
1474 
1475  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1476  LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
1477  LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
1478 
1479  if (Src0Ty != Src1Ty)
1480  report("Source operands must be the same type", MI);
1481 
1482  if (Src0Ty.getScalarType() != DstTy.getScalarType())
1483  report("G_SHUFFLE_VECTOR cannot change element type", MI);
1484 
1485  // Don't check that all operands are vector because scalars are used in
1486  // place of 1 element vectors.
1487  int SrcNumElts = Src0Ty.isVector() ? Src0Ty.getNumElements() : 1;
1488  int DstNumElts = DstTy.isVector() ? DstTy.getNumElements() : 1;
1489 
1490  ArrayRef<int> MaskIdxes = MaskOp.getShuffleMask();
1491 
1492  if (static_cast<int>(MaskIdxes.size()) != DstNumElts)
1493  report("Wrong result type for shufflemask", MI);
1494 
1495  for (int Idx : MaskIdxes) {
1496  if (Idx < 0)
1497  continue;
1498 
1499  if (Idx >= 2 * SrcNumElts)
1500  report("Out of bounds shuffle index", MI);
1501  }
1502 
1503  break;
1504  }
1505  case TargetOpcode::G_DYN_STACKALLOC: {
1506  const MachineOperand &DstOp = MI->getOperand(0);
1507  const MachineOperand &AllocOp = MI->getOperand(1);
1508  const MachineOperand &AlignOp = MI->getOperand(2);
1509 
1510  if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
1511  report("dst operand 0 must be a pointer type", MI);
1512  break;
1513  }
1514 
1515  if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) {
1516  report("src operand 1 must be a scalar reg type", MI);
1517  break;
1518  }
1519 
1520  if (!AlignOp.isImm()) {
1521  report("src operand 2 must be an immediate type", MI);
1522  break;
1523  }
1524  break;
1525  }
1526  case TargetOpcode::G_MEMCPY_INLINE:
1527  case TargetOpcode::G_MEMCPY:
1528  case TargetOpcode::G_MEMMOVE: {
1529  ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1530  if (MMOs.size() != 2) {
1531  report("memcpy/memmove must have 2 memory operands", MI);
1532  break;
1533  }
1534 
1535  if ((!MMOs[0]->isStore() || MMOs[0]->isLoad()) ||
1536  (MMOs[1]->isStore() || !MMOs[1]->isLoad())) {
1537  report("wrong memory operand types", MI);
1538  break;
1539  }
1540 
1541  if (MMOs[0]->getSize() != MMOs[1]->getSize())
1542  report("inconsistent memory operand sizes", MI);
1543 
1544  LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1545  LLT SrcPtrTy = MRI->getType(MI->getOperand(1).getReg());
1546 
1547  if (!DstPtrTy.isPointer() || !SrcPtrTy.isPointer()) {
1548  report("memory instruction operand must be a pointer", MI);
1549  break;
1550  }
1551 
1552  if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1553  report("inconsistent store address space", MI);
1554  if (SrcPtrTy.getAddressSpace() != MMOs[1]->getAddrSpace())
1555  report("inconsistent load address space", MI);
1556 
1557  if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1558  if (!MI->getOperand(3).isImm() || (MI->getOperand(3).getImm() & ~1LL))
1559  report("'tail' flag (operand 3) must be an immediate 0 or 1", MI);
1560 
1561  break;
1562  }
1563  case TargetOpcode::G_BZERO:
1564  case TargetOpcode::G_MEMSET: {
1565  ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1566  std::string Name = Opc == TargetOpcode::G_MEMSET ? "memset" : "bzero";
1567  if (MMOs.size() != 1) {
1568  report(Twine(Name, " must have 1 memory operand"), MI);
1569  break;
1570  }
1571 
1572  if ((!MMOs[0]->isStore() || MMOs[0]->isLoad())) {
1573  report(Twine(Name, " memory operand must be a store"), MI);
1574  break;
1575  }
1576 
1577  LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1578  if (!DstPtrTy.isPointer()) {
1579  report(Twine(Name, " operand must be a pointer"), MI);
1580  break;
1581  }
1582 
1583  if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1584  report("inconsistent " + Twine(Name, " address space"), MI);
1585 
1586  if (!MI->getOperand(MI->getNumOperands() - 1).isImm() ||
1587  (MI->getOperand(MI->getNumOperands() - 1).getImm() & ~1LL))
1588  report("'tail' flag (last operand) must be an immediate 0 or 1", MI);
1589 
1590  break;
1591  }
1592  case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1593  case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1594  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1595  LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1596  LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1597  if (!DstTy.isScalar())
1598  report("Vector reduction requires a scalar destination type", MI);
1599  if (!Src1Ty.isScalar())
1600  report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI);
1601  if (!Src2Ty.isVector())
1602  report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI);
1603  break;
1604  }
1605  case TargetOpcode::G_VECREDUCE_FADD:
1606  case TargetOpcode::G_VECREDUCE_FMUL:
1607  case TargetOpcode::G_VECREDUCE_FMAX:
1608  case TargetOpcode::G_VECREDUCE_FMIN:
1609  case TargetOpcode::G_VECREDUCE_ADD:
1610  case TargetOpcode::G_VECREDUCE_MUL:
1611  case TargetOpcode::G_VECREDUCE_AND:
1612  case TargetOpcode::G_VECREDUCE_OR:
1613  case TargetOpcode::G_VECREDUCE_XOR:
1614  case TargetOpcode::G_VECREDUCE_SMAX:
1615  case TargetOpcode::G_VECREDUCE_SMIN:
1616  case TargetOpcode::G_VECREDUCE_UMAX:
1617  case TargetOpcode::G_VECREDUCE_UMIN: {
1618  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1619  if (!DstTy.isScalar())
1620  report("Vector reduction requires a scalar destination type", MI);
1621  break;
1622  }
1623 
1624  case TargetOpcode::G_SBFX:
1625  case TargetOpcode::G_UBFX: {
1626  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1627  if (DstTy.isVector()) {
1628  report("Bitfield extraction is not supported on vectors", MI);
1629  break;
1630  }
1631  break;
1632  }
1633  case TargetOpcode::G_SHL:
1634  case TargetOpcode::G_LSHR:
1635  case TargetOpcode::G_ASHR:
1636  case TargetOpcode::G_ROTR:
1637  case TargetOpcode::G_ROTL: {
1638  LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1639  LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1640  if (Src1Ty.isVector() != Src2Ty.isVector()) {
1641  report("Shifts and rotates require operands to be either all scalars or "
1642  "all vectors",
1643  MI);
1644  break;
1645  }
1646  break;
1647  }
1648  case TargetOpcode::G_LLROUND:
1649  case TargetOpcode::G_LROUND: {
1650  verifyAllRegOpsScalar(*MI, *MRI);
1651  break;
1652  }
1653  default:
1654  break;
1655  }
1656 }
1657 
1658 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
1659  const MCInstrDesc &MCID = MI->getDesc();
1660  if (MI->getNumOperands() < MCID.getNumOperands()) {
1661  report("Too few operands", MI);
1662  errs() << MCID.getNumOperands() << " operands expected, but "
1663  << MI->getNumOperands() << " given.\n";
1664  }
1665 
1666  if (MI->isPHI()) {
1667  if (MF->getProperties().hasProperty(
1669  report("Found PHI instruction with NoPHIs property set", MI);
1670 
1671  if (FirstNonPHI)
1672  report("Found PHI instruction after non-PHI", MI);
1673  } else if (FirstNonPHI == nullptr)
1674  FirstNonPHI = MI;
1675 
1676  // Check the tied operands.
1677  if (MI->isInlineAsm())
1678  verifyInlineAsm(MI);
1679 
1680  // Check that unspillable terminators define a reg and have at most one use.
1681  if (TII->isUnspillableTerminator(MI)) {
1682  if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
1683  report("Unspillable Terminator does not define a reg", MI);
1684  Register Def = MI->getOperand(0).getReg();
1685  if (Def.isVirtual() &&
1686  !MF->getProperties().hasProperty(
1688  std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1)
1689  report("Unspillable Terminator expected to have at most one use!", MI);
1690  }
1691 
1692  // A fully-formed DBG_VALUE must have a location. Ignore partially formed
1693  // DBG_VALUEs: these are convenient to use in tests, but should never get
1694  // generated.
1695  if (MI->isDebugValue() && MI->getNumOperands() == 4)
1696  if (!MI->getDebugLoc())
1697  report("Missing DebugLoc for debug instruction", MI);
1698 
1699  // Meta instructions should never be the subject of debug value tracking,
1700  // they don't create a value in the output program at all.
1701  if (MI->isMetaInstruction() && MI->peekDebugInstrNum())
1702  report("Metadata instruction should not have a value tracking number", MI);
1703 
1704  // Check the MachineMemOperands for basic consistency.
1705  for (MachineMemOperand *Op : MI->memoperands()) {
1706  if (Op->isLoad() && !MI->mayLoad())
1707  report("Missing mayLoad flag", MI);
1708  if (Op->isStore() && !MI->mayStore())
1709  report("Missing mayStore flag", MI);
1710  }
1711 
1712  // Debug values must not have a slot index.
1713  // Other instructions must have one, unless they are inside a bundle.
1714  if (LiveInts) {
1715  bool mapped = !LiveInts->isNotInMIMap(*MI);
1716  if (MI->isDebugOrPseudoInstr()) {
1717  if (mapped)
1718  report("Debug instruction has a slot index", MI);
1719  } else if (MI->isInsideBundle()) {
1720  if (mapped)
1721  report("Instruction inside bundle has a slot index", MI);
1722  } else {
1723  if (!mapped)
1724  report("Missing slot index", MI);
1725  }
1726  }
1727 
1728  unsigned Opc = MCID.getOpcode();
1730  verifyPreISelGenericInstruction(MI);
1731  return;
1732  }
1733 
1735  if (!TII->verifyInstruction(*MI, ErrorInfo))
1736  report(ErrorInfo.data(), MI);
1737 
1738  // Verify properties of various specific instruction types
1739  switch (MI->getOpcode()) {
1740  case TargetOpcode::COPY: {
1741  const MachineOperand &DstOp = MI->getOperand(0);
1742  const MachineOperand &SrcOp = MI->getOperand(1);
1743  const Register SrcReg = SrcOp.getReg();
1744  const Register DstReg = DstOp.getReg();
1745 
1746  LLT DstTy = MRI->getType(DstReg);
1747  LLT SrcTy = MRI->getType(SrcReg);
1748  if (SrcTy.isValid() && DstTy.isValid()) {
1749  // If both types are valid, check that the types are the same.
1750  if (SrcTy != DstTy) {
1751  report("Copy Instruction is illegal with mismatching types", MI);
1752  errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
1753  }
1754 
1755  break;
1756  }
1757 
1758  if (!SrcTy.isValid() && !DstTy.isValid())
1759  break;
1760 
1761  // If we have only one valid type, this is likely a copy between a virtual
1762  // and physical register.
1763  unsigned SrcSize = 0;
1764  unsigned DstSize = 0;
1765  if (SrcReg.isPhysical() && DstTy.isValid()) {
1766  const TargetRegisterClass *SrcRC =
1767  TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
1768  if (SrcRC)
1769  SrcSize = TRI->getRegSizeInBits(*SrcRC);
1770  }
1771 
1772  if (SrcSize == 0)
1773  SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
1774 
1775  if (DstReg.isPhysical() && SrcTy.isValid()) {
1776  const TargetRegisterClass *DstRC =
1777  TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
1778  if (DstRC)
1779  DstSize = TRI->getRegSizeInBits(*DstRC);
1780  }
1781 
1782  if (DstSize == 0)
1783  DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
1784 
1785  if (SrcSize != 0 && DstSize != 0 && SrcSize != DstSize) {
1786  if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
1787  report("Copy Instruction is illegal with mismatching sizes", MI);
1788  errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
1789  << "\n";
1790  }
1791  }
1792  break;
1793  }
1794  case TargetOpcode::STATEPOINT: {
1795  StatepointOpers SO(MI);
1796  if (!MI->getOperand(SO.getIDPos()).isImm() ||
1797  !MI->getOperand(SO.getNBytesPos()).isImm() ||
1798  !MI->getOperand(SO.getNCallArgsPos()).isImm()) {
1799  report("meta operands to STATEPOINT not constant!", MI);
1800  break;
1801  }
1802 
1803  auto VerifyStackMapConstant = [&](unsigned Offset) {
1804  if (Offset >= MI->getNumOperands()) {
1805  report("stack map constant to STATEPOINT is out of range!", MI);
1806  return;
1807  }
1808  if (!MI->getOperand(Offset - 1).isImm() ||
1809  MI->getOperand(Offset - 1).getImm() != StackMaps::ConstantOp ||
1810  !MI->getOperand(Offset).isImm())
1811  report("stack map constant to STATEPOINT not well formed!", MI);
1812  };
1813  VerifyStackMapConstant(SO.getCCIdx());
1814  VerifyStackMapConstant(SO.getFlagsIdx());
1815  VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
1816  VerifyStackMapConstant(SO.getNumGCPtrIdx());
1817  VerifyStackMapConstant(SO.getNumAllocaIdx());
1818  VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
1819 
1820  // Verify that all explicit statepoint defs are tied to gc operands as
1821  // they are expected to be a relocation of gc operands.
1822  unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
1823  unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
1824  for (unsigned Idx = 0; Idx < MI->getNumDefs(); Idx++) {
1825  unsigned UseOpIdx;
1826  if (!MI->isRegTiedToUseOperand(Idx, &UseOpIdx)) {
1827  report("STATEPOINT defs expected to be tied", MI);
1828  break;
1829  }
1830  if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
1831  report("STATEPOINT def tied to non-gc operand", MI);
1832  break;
1833  }
1834  }
1835 
1836  // TODO: verify we have properly encoded deopt arguments
1837  } break;
1838  case TargetOpcode::INSERT_SUBREG: {
1839  unsigned InsertedSize;
1840  if (unsigned SubIdx = MI->getOperand(2).getSubReg())
1841  InsertedSize = TRI->getSubRegIdxSize(SubIdx);
1842  else
1843  InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
1844  unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
1845  if (SubRegSize < InsertedSize) {
1846  report("INSERT_SUBREG expected inserted value to have equal or lesser "
1847  "size than the subreg it was inserted into", MI);
1848  break;
1849  }
1850  } break;
1851  }
1852 }
1853 
1854 void
1855 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
1856  const MachineInstr *MI = MO->getParent();
1857  const MCInstrDesc &MCID = MI->getDesc();
1858  unsigned NumDefs = MCID.getNumDefs();
1859  if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
1860  NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
1861 
1862  // The first MCID.NumDefs operands must be explicit register defines
1863  if (MONum < NumDefs) {
1864  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1865  if (!MO->isReg())
1866  report("Explicit definition must be a register", MO, MONum);
1867  else if (!MO->isDef() && !MCOI.isOptionalDef())
1868  report("Explicit definition marked as use", MO, MONum);
1869  else if (MO->isImplicit())
1870  report("Explicit definition marked as implicit", MO, MONum);
1871  } else if (MONum < MCID.getNumOperands()) {
1872  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1873  // Don't check if it's the last operand in a variadic instruction. See,
1874  // e.g., LDM_RET in the arm back end. Check non-variadic operands only.
1875  bool IsOptional = MI->isVariadic() && MONum == MCID.getNumOperands() - 1;
1876  if (!IsOptional) {
1877  if (MO->isReg()) {
1878  if (MO->isDef() && !MCOI.isOptionalDef() && !MCID.variadicOpsAreDefs())
1879  report("Explicit operand marked as def", MO, MONum);
1880  if (MO->isImplicit())
1881  report("Explicit operand marked as implicit", MO, MONum);
1882  }
1883 
1884  // Check that an instruction has register operands only as expected.
1885  if (MCOI.OperandType == MCOI::OPERAND_REGISTER &&
1886  !MO->isReg() && !MO->isFI())
1887  report("Expected a register operand.", MO, MONum);
1888  if (MO->isReg()) {
1889  if (MCOI.OperandType == MCOI::OPERAND_IMMEDIATE ||
1890  (MCOI.OperandType == MCOI::OPERAND_PCREL &&
1891  !TII->isPCRelRegisterOperandLegal(*MO)))
1892  report("Expected a non-register operand.", MO, MONum);
1893  }
1894  }
1895 
1896  int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
1897  if (TiedTo != -1) {
1898  if (!MO->isReg())
1899  report("Tied use must be a register", MO, MONum);
1900  else if (!MO->isTied())
1901  report("Operand should be tied", MO, MONum);
1902  else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
1903  report("Tied def doesn't match MCInstrDesc", MO, MONum);
1904  else if (Register::isPhysicalRegister(MO->getReg())) {
1905  const MachineOperand &MOTied = MI->getOperand(TiedTo);
1906  if (!MOTied.isReg())
1907  report("Tied counterpart must be a register", &MOTied, TiedTo);
1908  else if (Register::isPhysicalRegister(MOTied.getReg()) &&
1909  MO->getReg() != MOTied.getReg())
1910  report("Tied physical registers must match.", &MOTied, TiedTo);
1911  }
1912  } else if (MO->isReg() && MO->isTied())
1913  report("Explicit operand should not be tied", MO, MONum);
1914  } else {
1915  // ARM adds %reg0 operands to indicate predicates. We'll allow that.
1916  if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
1917  report("Extra explicit operand on non-variadic instruction", MO, MONum);
1918  }
1919 
1920  switch (MO->getType()) {
1922  // Verify debug flag on debug instructions. Check this first because reg0
1923  // indicates an undefined debug value.
1924  if (MI->isDebugInstr() && MO->isUse()) {
1925  if (!MO->isDebug())
1926  report("Register operand must be marked debug", MO, MONum);
1927  } else if (MO->isDebug()) {
1928  report("Register operand must not be marked debug", MO, MONum);
1929  }
1930 
1931  const Register Reg = MO->getReg();
1932  if (!Reg)
1933  return;
1934  if (MRI->tracksLiveness() && !MI->isDebugInstr())
1935  checkLiveness(MO, MONum);
1936 
1937  if (MO->isDef() && MO->isUndef() && !MO->getSubReg() &&
1938  MO->getReg().isVirtual()) // TODO: Apply to physregs too
1939  report("Undef virtual register def operands require a subregister", MO, MONum);
1940 
1941  // Verify the consistency of tied operands.
1942  if (MO->isTied()) {
1943  unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
1944  const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
1945  if (!OtherMO.isReg())
1946  report("Must be tied to a register", MO, MONum);
1947  if (!OtherMO.isTied())
1948  report("Missing tie flags on tied operand", MO, MONum);
1949  if (MI->findTiedOperandIdx(OtherIdx) != MONum)
1950  report("Inconsistent tie links", MO, MONum);
1951  if (MONum < MCID.getNumDefs()) {
1952  if (OtherIdx < MCID.getNumOperands()) {
1953  if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
1954  report("Explicit def tied to explicit use without tie constraint",
1955  MO, MONum);
1956  } else {
1957  if (!OtherMO.isImplicit())
1958  report("Explicit def should be tied to implicit use", MO, MONum);
1959  }
1960  }
1961  }
1962 
1963  // Verify two-address constraints after the twoaddressinstruction pass.
1964  // Both twoaddressinstruction pass and phi-node-elimination pass call
1965  // MRI->leaveSSA() to set MF as NoSSA, we should do the verification after
1966  // twoaddressinstruction pass not after phi-node-elimination pass. So we
1967  // shouldn't use the NoSSA as the condition, we should based on
1968  // TiedOpsRewritten property to verify two-address constraints, this
1969  // property will be set in twoaddressinstruction pass.
1970  unsigned DefIdx;
1971  if (MF->getProperties().hasProperty(
1973  MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
1974  Reg != MI->getOperand(DefIdx).getReg())
1975  report("Two-address instruction operands must be identical", MO, MONum);
1976 
1977  // Check register classes.
1978  unsigned SubIdx = MO->getSubReg();
1979 
1981  if (SubIdx) {
1982  report("Illegal subregister index for physical register", MO, MONum);
1983  return;
1984  }
1985  if (MONum < MCID.getNumOperands()) {
1986  if (const TargetRegisterClass *DRC =
1987  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1988  if (!DRC->contains(Reg)) {
1989  report("Illegal physical register for instruction", MO, MONum);
1990  errs() << printReg(Reg, TRI) << " is not a "
1991  << TRI->getRegClassName(DRC) << " register.\n";
1992  }
1993  }
1994  }
1995  if (MO->isRenamable()) {
1996  if (MRI->isReserved(Reg)) {
1997  report("isRenamable set on reserved register", MO, MONum);
1998  return;
1999  }
2000  }
2001  } else {
2002  // Virtual register.
2004  if (!RC) {
2005  // This is a generic virtual register.
2006 
2007  // Do not allow undef uses for generic virtual registers. This ensures
2008  // getVRegDef can never fail and return null on a generic register.
2009  //
2010  // FIXME: This restriction should probably be broadened to all SSA
2011  // MIR. However, DetectDeadLanes/ProcessImplicitDefs technically still
2012  // run on the SSA function just before phi elimination.
2013  if (MO->isUndef())
2014  report("Generic virtual register use cannot be undef", MO, MONum);
2015 
2016  // Debug value instruction is permitted to use undefined vregs.
2017  // This is a performance measure to skip the overhead of immediately
2018  // pruning unused debug operands. The final undef substitution occurs
2019  // when debug values are allocated in LDVImpl::handleDebugValue, so
2020  // these verifications always apply after this pass.
2021  if (isFunctionTracksDebugUserValues || !MO->isUse() ||
2022  !MI->isDebugValue() || !MRI->def_empty(Reg)) {
2023  // If we're post-Select, we can't have gvregs anymore.
2024  if (isFunctionSelected) {
2025  report("Generic virtual register invalid in a Selected function",
2026  MO, MONum);
2027  return;
2028  }
2029 
2030  // The gvreg must have a type and it must not have a SubIdx.
2031  LLT Ty = MRI->getType(Reg);
2032  if (!Ty.isValid()) {
2033  report("Generic virtual register must have a valid type", MO,
2034  MONum);
2035  return;
2036  }
2037 
2038  const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
2039 
2040  // If we're post-RegBankSelect, the gvreg must have a bank.
2041  if (!RegBank && isFunctionRegBankSelected) {
2042  report("Generic virtual register must have a bank in a "
2043  "RegBankSelected function",
2044  MO, MONum);
2045  return;
2046  }
2047 
2048  // Make sure the register fits into its register bank if any.
2049  if (RegBank && Ty.isValid() &&
2050  RegBank->getSize() < Ty.getSizeInBits()) {
2051  report("Register bank is too small for virtual register", MO,
2052  MONum);
2053  errs() << "Register bank " << RegBank->getName() << " too small("
2054  << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
2055  << "-bits\n";
2056  return;
2057  }
2058  }
2059 
2060  if (SubIdx) {
2061  report("Generic virtual register does not allow subregister index", MO,
2062  MONum);
2063  return;
2064  }
2065 
2066  // If this is a target specific instruction and this operand
2067  // has register class constraint, the virtual register must
2068  // comply to it.
2069  if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
2070  MONum < MCID.getNumOperands() &&
2071  TII->getRegClass(MCID, MONum, TRI, *MF)) {
2072  report("Virtual register does not match instruction constraint", MO,
2073  MONum);
2074  errs() << "Expect register class "
2075  << TRI->getRegClassName(
2076  TII->getRegClass(MCID, MONum, TRI, *MF))
2077  << " but got nothing\n";
2078  return;
2079  }
2080 
2081  break;
2082  }
2083  if (SubIdx) {
2084  const TargetRegisterClass *SRC =
2085  TRI->getSubClassWithSubReg(RC, SubIdx);
2086  if (!SRC) {
2087  report("Invalid subregister index for virtual register", MO, MONum);
2088  errs() << "Register class " << TRI->getRegClassName(RC)
2089  << " does not support subreg index " << SubIdx << "\n";
2090  return;
2091  }
2092  if (RC != SRC) {
2093  report("Invalid register class for subregister index", MO, MONum);
2094  errs() << "Register class " << TRI->getRegClassName(RC)
2095  << " does not fully support subreg index " << SubIdx << "\n";
2096  return;
2097  }
2098  }
2099  if (MONum < MCID.getNumOperands()) {
2100  if (const TargetRegisterClass *DRC =
2101  TII->getRegClass(MCID, MONum, TRI, *MF)) {
2102  if (SubIdx) {
2103  const TargetRegisterClass *SuperRC =
2104  TRI->getLargestLegalSuperClass(RC, *MF);
2105  if (!SuperRC) {
2106  report("No largest legal super class exists.", MO, MONum);
2107  return;
2108  }
2109  DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2110  if (!DRC) {
2111  report("No matching super-reg register class.", MO, MONum);
2112  return;
2113  }
2114  }
2115  if (!RC->hasSuperClassEq(DRC)) {
2116  report("Illegal virtual register for instruction", MO, MONum);
2117  errs() << "Expected a " << TRI->getRegClassName(DRC)
2118  << " register, but got a " << TRI->getRegClassName(RC)
2119  << " register\n";
2120  }
2121  }
2122  }
2123  }
2124  break;
2125  }
2126 
2128  regMasks.push_back(MO->getRegMask());
2129  break;
2130 
2132  if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
2133  report("PHI operand is not in the CFG", MO, MONum);
2134  break;
2135 
2137  if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
2138  LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2139  int FI = MO->getIndex();
2140  LiveInterval &LI = LiveStks->getInterval(FI);
2141  SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
2142 
2143  bool stores = MI->mayStore();
2144  bool loads = MI->mayLoad();
2145  // For a memory-to-memory move, we need to check if the frame
2146  // index is used for storing or loading, by inspecting the
2147  // memory operands.
2148  if (stores && loads) {
2149  for (auto *MMO : MI->memoperands()) {
2150  const PseudoSourceValue *PSV = MMO->getPseudoValue();
2151  if (PSV == nullptr) continue;
2153  dyn_cast<FixedStackPseudoSourceValue>(PSV);
2154  if (Value == nullptr) continue;
2155  if (Value->getFrameIndex() != FI) continue;
2156 
2157  if (MMO->isStore())
2158  loads = false;
2159  else
2160  stores = false;
2161  break;
2162  }
2163  if (loads == stores)
2164  report("Missing fixed stack memoperand.", MI);
2165  }
2166  if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
2167  report("Instruction loads from dead spill slot", MO, MONum);
2168  errs() << "Live stack: " << LI << '\n';
2169  }
2170  if (stores && !LI.liveAt(Idx.getRegSlot())) {
2171  report("Instruction stores to dead spill slot", MO, MONum);
2172  errs() << "Live stack: " << LI << '\n';
2173  }
2174  }
2175  break;
2176 
2177  default:
2178  break;
2179  }
2180 }
2181 
2182 void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
2183  unsigned MONum, SlotIndex UseIdx,
2184  const LiveRange &LR,
2185  Register VRegOrUnit,
2186  LaneBitmask LaneMask) {
2187  LiveQueryResult LRQ = LR.Query(UseIdx);
2188  // Check if we have a segment at the use, note however that we only need one
2189  // live subregister range, the others may be dead.
2190  if (!LRQ.valueIn() && LaneMask.none()) {
2191  report("No live segment at use", MO, MONum);
2192  report_context_liverange(LR);
2193  report_context_vreg_regunit(VRegOrUnit);
2194  report_context(UseIdx);
2195  }
2196  if (MO->isKill() && !LRQ.isKill()) {
2197  report("Live range continues after kill flag", MO, MONum);
2198  report_context_liverange(LR);
2199  report_context_vreg_regunit(VRegOrUnit);
2200  if (LaneMask.any())
2201  report_context_lanemask(LaneMask);
2202  report_context(UseIdx);
2203  }
2204 }
2205 
2206 void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
2207  unsigned MONum, SlotIndex DefIdx,
2208  const LiveRange &LR,
2209  Register VRegOrUnit,
2210  bool SubRangeCheck,
2211  LaneBitmask LaneMask) {
2212  if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
2213  assert(VNI && "NULL valno is not allowed");
2214  if (VNI->def != DefIdx) {
2215  report("Inconsistent valno->def", MO, MONum);
2216  report_context_liverange(LR);
2217  report_context_vreg_regunit(VRegOrUnit);
2218  if (LaneMask.any())
2219  report_context_lanemask(LaneMask);
2220  report_context(*VNI);
2221  report_context(DefIdx);
2222  }
2223  } else {
2224  report("No live segment at def", MO, MONum);
2225  report_context_liverange(LR);
2226  report_context_vreg_regunit(VRegOrUnit);
2227  if (LaneMask.any())
2228  report_context_lanemask(LaneMask);
2229  report_context(DefIdx);
2230  }
2231  // Check that, if the dead def flag is present, LiveInts agree.
2232  if (MO->isDead()) {
2233  LiveQueryResult LRQ = LR.Query(DefIdx);
2234  if (!LRQ.isDeadDef()) {
2235  assert(Register::isVirtualRegister(VRegOrUnit) &&
2236  "Expecting a virtual register.");
2237  // A dead subreg def only tells us that the specific subreg is dead. There
2238  // could be other non-dead defs of other subregs, or we could have other
2239  // parts of the register being live through the instruction. So unless we
2240  // are checking liveness for a subrange it is ok for the live range to
2241  // continue, given that we have a dead def of a subregister.
2242  if (SubRangeCheck || MO->getSubReg() == 0) {
2243  report("Live range continues after dead def flag", MO, MONum);
2244  report_context_liverange(LR);
2245  report_context_vreg_regunit(VRegOrUnit);
2246  if (LaneMask.any())
2247  report_context_lanemask(LaneMask);
2248  }
2249  }
2250  }
2251 }
2252 
2253 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
2254  const MachineInstr *MI = MO->getParent();
2255  const Register Reg = MO->getReg();
2256  const unsigned SubRegIdx = MO->getSubReg();
2257 
2258  const LiveInterval *LI = nullptr;
2259  if (LiveInts && Reg.isVirtual()) {
2260  if (LiveInts->hasInterval(Reg)) {
2261  LI = &LiveInts->getInterval(Reg);
2262  if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() &&
2264  report("Live interval for subreg operand has no subranges", MO, MONum);
2265  } else {
2266  report("Virtual register has no live interval", MO, MONum);
2267  }
2268  }
2269 
2270  // Both use and def operands can read a register.
2271  if (MO->readsReg()) {
2272  if (MO->isKill())
2273  addRegWithSubRegs(regsKilled, Reg);
2274 
2275  // Check that LiveVars knows this kill (unless we are inside a bundle, in
2276  // which case we have already checked that LiveVars knows any kills on the
2277  // bundle header instead).
2278  if (LiveVars && Reg.isVirtual() && MO->isKill() &&
2279  !MI->isBundledWithPred()) {
2280  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2281  if (!is_contained(VI.Kills, MI))
2282  report("Kill missing from LiveVariables", MO, MONum);
2283  }
2284 
2285  // Check LiveInts liveness and kill.
2286  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2287  SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
2288  // Check the cached regunit intervals.
2289  if (Reg.isPhysical() && !isReserved(Reg)) {
2290  for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
2291  ++Units) {
2292  if (MRI->isReservedRegUnit(*Units))
2293  continue;
2294  if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
2295  checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
2296  }
2297  }
2298 
2299  if (Reg.isVirtual()) {
2300  // This is a virtual register interval.
2301  checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2302 
2303  if (LI->hasSubRanges() && !MO->isDef()) {
2304  LaneBitmask MOMask = SubRegIdx != 0
2305  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2307  LaneBitmask LiveInMask;
2308  for (const LiveInterval::SubRange &SR : LI->subranges()) {
2309  if ((MOMask & SR.LaneMask).none())
2310  continue;
2311  checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2312  LiveQueryResult LRQ = SR.Query(UseIdx);
2313  if (LRQ.valueIn())
2314  LiveInMask |= SR.LaneMask;
2315  }
2316  // At least parts of the register has to be live at the use.
2317  if ((LiveInMask & MOMask).none()) {
2318  report("No live subrange at use", MO, MONum);
2319  report_context(*LI);
2320  report_context(UseIdx);
2321  }
2322  }
2323  }
2324  }
2325 
2326  // Use of a dead register.
2327  if (!regsLive.count(Reg)) {
2328  if (Reg.isPhysical()) {
2329  // Reserved registers may be used even when 'dead'.
2330  bool Bad = !isReserved(Reg);
2331  // We are fine if just any subregister has a defined value.
2332  if (Bad) {
2333 
2334  for (const MCPhysReg &SubReg : TRI->subregs(Reg)) {
2335  if (regsLive.count(SubReg)) {
2336  Bad = false;
2337  break;
2338  }
2339  }
2340  }
2341  // If there is an additional implicit-use of a super register we stop
2342  // here. By definition we are fine if the super register is not
2343  // (completely) dead, if the complete super register is dead we will
2344  // get a report for its operand.
2345  if (Bad) {
2346  for (const MachineOperand &MOP : MI->uses()) {
2347  if (!MOP.isReg() || !MOP.isImplicit())
2348  continue;
2349 
2350  if (!MOP.getReg().isPhysical())
2351  continue;
2352 
2353  if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg))
2354  Bad = false;
2355  }
2356  }
2357  if (Bad)
2358  report("Using an undefined physical register", MO, MONum);
2359  } else if (MRI->def_empty(Reg)) {
2360  report("Reading virtual register without a def", MO, MONum);
2361  } else {
2362  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2363  // We don't know which virtual registers are live in, so only complain
2364  // if vreg was killed in this MBB. Otherwise keep track of vregs that
2365  // must be live in. PHI instructions are handled separately.
2366  if (MInfo.regsKilled.count(Reg))
2367  report("Using a killed virtual register", MO, MONum);
2368  else if (!MI->isPHI())
2369  MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
2370  }
2371  }
2372  }
2373 
2374  if (MO->isDef()) {
2375  // Register defined.
2376  // TODO: verify that earlyclobber ops are not used.
2377  if (MO->isDead())
2378  addRegWithSubRegs(regsDead, Reg);
2379  else
2380  addRegWithSubRegs(regsDefined, Reg);
2381 
2382  // Verify SSA form.
2383  if (MRI->isSSA() && Reg.isVirtual() &&
2384  std::next(MRI->def_begin(Reg)) != MRI->def_end())
2385  report("Multiple virtual register defs in SSA form", MO, MONum);
2386 
2387  // Check LiveInts for a live segment, but only for virtual registers.
2388  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2389  SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
2390  DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
2391 
2392  if (Reg.isVirtual()) {
2393  checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
2394 
2395  if (LI->hasSubRanges()) {
2396  LaneBitmask MOMask = SubRegIdx != 0
2397  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2399  for (const LiveInterval::SubRange &SR : LI->subranges()) {
2400  if ((SR.LaneMask & MOMask).none())
2401  continue;
2402  checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
2403  }
2404  }
2405  }
2406  }
2407  }
2408 }
2409 
2410 // This function gets called after visiting all instructions in a bundle. The
2411 // argument points to the bundle header.
2412 // Normal stand-alone instructions are also considered 'bundles', and this
2413 // function is called for all of them.
2414 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
2415  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2416  set_union(MInfo.regsKilled, regsKilled);
2417  set_subtract(regsLive, regsKilled); regsKilled.clear();
2418  // Kill any masked registers.
2419  while (!regMasks.empty()) {
2420  const uint32_t *Mask = regMasks.pop_back_val();
2421  for (Register Reg : regsLive)
2422  if (Reg.isPhysical() &&
2424  regsDead.push_back(Reg);
2425  }
2426  set_subtract(regsLive, regsDead); regsDead.clear();
2427  set_union(regsLive, regsDefined); regsDefined.clear();
2428 }
2429 
2430 void
2431 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
2432  MBBInfoMap[MBB].regsLiveOut = regsLive;
2433  regsLive.clear();
2434 
2435  if (Indexes) {
2436  SlotIndex stop = Indexes->getMBBEndIdx(MBB);
2437  if (!(stop > lastIndex)) {
2438  report("Block ends before last instruction index", MBB);
2439  errs() << "Block ends at " << stop
2440  << " last instruction was at " << lastIndex << '\n';
2441  }
2442  lastIndex = stop;
2443  }
2444 }
2445 
2446 namespace {
2447 // This implements a set of registers that serves as a filter: can filter other
2448 // sets by passing through elements not in the filter and blocking those that
2449 // are. Any filter implicitly includes the full set of physical registers upon
2450 // creation, thus filtering them all out. The filter itself as a set only grows,
2451 // and needs to be as efficient as possible.
2452 struct VRegFilter {
2453  // Add elements to the filter itself. \pre Input set \p FromRegSet must have
2454  // no duplicates. Both virtual and physical registers are fine.
2455  template <typename RegSetT> void add(const RegSetT &FromRegSet) {
2456  SmallVector<Register, 0> VRegsBuffer;
2457  filterAndAdd(FromRegSet, VRegsBuffer);
2458  }
2459  // Filter \p FromRegSet through the filter and append passed elements into \p
2460  // ToVRegs. All elements appended are then added to the filter itself.
2461  // \returns true if anything changed.
2462  template <typename RegSetT>
2463  bool filterAndAdd(const RegSetT &FromRegSet,
2464  SmallVectorImpl<Register> &ToVRegs) {
2465  unsigned SparseUniverse = Sparse.size();
2466  unsigned NewSparseUniverse = SparseUniverse;
2467  unsigned NewDenseSize = Dense.size();
2468  size_t Begin = ToVRegs.size();
2469  for (Register Reg : FromRegSet) {
2470  if (!Reg.isVirtual())
2471  continue;
2472  unsigned Index = Register::virtReg2Index(Reg);
2473  if (Index < SparseUniverseMax) {
2474  if (Index < SparseUniverse && Sparse.test(Index))
2475  continue;
2476  NewSparseUniverse = std::max(NewSparseUniverse, Index + 1);
2477  } else {
2478  if (Dense.count(Reg))
2479  continue;
2480  ++NewDenseSize;
2481  }
2482  ToVRegs.push_back(Reg);
2483  }
2484  size_t End = ToVRegs.size();
2485  if (Begin == End)
2486  return false;
2487  // Reserving space in sets once performs better than doing so continuously
2488  // and pays easily for double look-ups (even in Dense with SparseUniverseMax
2489  // tuned all the way down) and double iteration (the second one is over a
2490  // SmallVector, which is a lot cheaper compared to DenseSet or BitVector).
2491  Sparse.resize(NewSparseUniverse);
2492  Dense.reserve(NewDenseSize);
2493  for (unsigned I = Begin; I < End; ++I) {
2494  Register Reg = ToVRegs[I];
2495  unsigned Index = Register::virtReg2Index(Reg);
2496  if (Index < SparseUniverseMax)
2497  Sparse.set(Index);
2498  else
2499  Dense.insert(Reg);
2500  }
2501  return true;
2502  }
2503 
2504 private:
2505  static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2506  // VRegs indexed within SparseUniverseMax are tracked by Sparse, those beyound
2507  // are tracked by Dense. The only purpose of the threashold and the Dense set
2508  // is to have a reasonably growing memory usage in pathological cases (large
2509  // number of very sparse VRegFilter instances live at the same time). In
2510  // practice even in the worst-by-execution time cases having all elements
2511  // tracked by Sparse (very large SparseUniverseMax scenario) tends to be more
2512  // space efficient than if tracked by Dense. The threashold is set to keep the
2513  // worst-case memory usage within 2x of figures determined empirically for
2514  // "all Dense" scenario in such worst-by-execution-time cases.
2515  BitVector Sparse;
2517 };
2518 
2519 // Implements both a transfer function and a (binary, in-place) join operator
2520 // for a dataflow over register sets with set union join and filtering transfer
2521 // (out_b = in_b \ filter_b). filter_b is expected to be set-up ahead of time.
2522 // Maintains out_b as its state, allowing for O(n) iteration over it at any
2523 // time, where n is the size of the set (as opposed to O(U) where U is the
2524 // universe). filter_b implicitly contains all physical registers at all times.
2525 class FilteringVRegSet {
2526  VRegFilter Filter;
2528 
2529 public:
2530  // Set-up the filter_b. \pre Input register set \p RS must have no duplicates.
2531  // Both virtual and physical registers are fine.
2532  template <typename RegSetT> void addToFilter(const RegSetT &RS) {
2533  Filter.add(RS);
2534  }
2535  // Passes \p RS through the filter_b (transfer function) and adds what's left
2536  // to itself (out_b).
2537  template <typename RegSetT> bool add(const RegSetT &RS) {
2538  // Double-duty the Filter: to maintain VRegs a set (and the join operation
2539  // a set union) just add everything being added here to the Filter as well.
2540  return Filter.filterAndAdd(RS, VRegs);
2541  }
2542  using const_iterator = decltype(VRegs)::const_iterator;
2543  const_iterator begin() const { return VRegs.begin(); }
2544  const_iterator end() const { return VRegs.end(); }
2545  size_t size() const { return VRegs.size(); }
2546 };
2547 } // namespace
2548 
2549 // Calculate the largest possible vregsPassed sets. These are the registers that
2550 // can pass through an MBB live, but may not be live every time. It is assumed
2551 // that all vregsPassed sets are empty before the call.
2552 void MachineVerifier::calcRegsPassed() {
2553  if (MF->empty())
2554  // ReversePostOrderTraversal doesn't handle empty functions.
2555  return;
2556 
2557  for (const MachineBasicBlock *MB :
2559  FilteringVRegSet VRegs;
2560  BBInfo &Info = MBBInfoMap[MB];
2561  assert(Info.reachable);
2562 
2563  VRegs.addToFilter(Info.regsKilled);
2564  VRegs.addToFilter(Info.regsLiveOut);
2565  for (const MachineBasicBlock *Pred : MB->predecessors()) {
2566  const BBInfo &PredInfo = MBBInfoMap[Pred];
2567  if (!PredInfo.reachable)
2568  continue;
2569 
2570  VRegs.add(PredInfo.regsLiveOut);
2571  VRegs.add(PredInfo.vregsPassed);
2572  }
2573  Info.vregsPassed.reserve(VRegs.size());
2574  Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2575  }
2576 }
2577 
2578 // Calculate the set of virtual registers that must be passed through each basic
2579 // block in order to satisfy the requirements of successor blocks. This is very
2580 // similar to calcRegsPassed, only backwards.
2581 void MachineVerifier::calcRegsRequired() {
2582  // First push live-in regs to predecessors' vregsRequired.
2584  for (const auto &MBB : *MF) {
2585  BBInfo &MInfo = MBBInfoMap[&MBB];
2586  for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2587  BBInfo &PInfo = MBBInfoMap[Pred];
2588  if (PInfo.addRequired(MInfo.vregsLiveIn))
2589  todo.insert(Pred);
2590  }
2591 
2592  // Handle the PHI node.
2593  for (const MachineInstr &MI : MBB.phis()) {
2594  for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
2595  // Skip those Operands which are undef regs or not regs.
2596  if (!MI.getOperand(i).isReg() || !MI.getOperand(i).readsReg())
2597  continue;
2598 
2599  // Get register and predecessor for one PHI edge.
2600  Register Reg = MI.getOperand(i).getReg();
2601  const MachineBasicBlock *Pred = MI.getOperand(i + 1).getMBB();
2602 
2603  BBInfo &PInfo = MBBInfoMap[Pred];
2604  if (PInfo.addRequired(Reg))
2605  todo.insert(Pred);
2606  }
2607  }
2608  }
2609 
2610  // Iteratively push vregsRequired to predecessors. This will converge to the
2611  // same final state regardless of DenseSet iteration order.
2612  while (!todo.empty()) {
2613  const MachineBasicBlock *MBB = *todo.begin();
2614  todo.erase(MBB);
2615  BBInfo &MInfo = MBBInfoMap[MBB];
2616  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
2617  if (Pred == MBB)
2618  continue;
2619  BBInfo &SInfo = MBBInfoMap[Pred];
2620  if (SInfo.addRequired(MInfo.vregsRequired))
2621  todo.insert(Pred);
2622  }
2623  }
2624 }
2625 
2626 // Check PHI instructions at the beginning of MBB. It is assumed that
2627 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
2628 void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
2629  BBInfo &MInfo = MBBInfoMap[&MBB];
2630 
2632  for (const MachineInstr &Phi : MBB) {
2633  if (!Phi.isPHI())
2634  break;
2635  seen.clear();
2636 
2637  const MachineOperand &MODef = Phi.getOperand(0);
2638  if (!MODef.isReg() || !MODef.isDef()) {
2639  report("Expected first PHI operand to be a register def", &MODef, 0);
2640  continue;
2641  }
2642  if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
2643  MODef.isEarlyClobber() || MODef.isDebug())
2644  report("Unexpected flag on PHI operand", &MODef, 0);
2645  Register DefReg = MODef.getReg();
2646  if (!Register::isVirtualRegister(DefReg))
2647  report("Expected first PHI operand to be a virtual register", &MODef, 0);
2648 
2649  for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
2650  const MachineOperand &MO0 = Phi.getOperand(I);
2651  if (!MO0.isReg()) {
2652  report("Expected PHI operand to be a register", &MO0, I);
2653  continue;
2654  }
2655  if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
2656  MO0.isDebug() || MO0.isTied())
2657  report("Unexpected flag on PHI operand", &MO0, I);
2658 
2659  const MachineOperand &MO1 = Phi.getOperand(I + 1);
2660  if (!MO1.isMBB()) {
2661  report("Expected PHI operand to be a basic block", &MO1, I + 1);
2662  continue;
2663  }
2664 
2665  const MachineBasicBlock &Pre = *MO1.getMBB();
2666  if (!Pre.isSuccessor(&MBB)) {
2667  report("PHI input is not a predecessor block", &MO1, I + 1);
2668  continue;
2669  }
2670 
2671  if (MInfo.reachable) {
2672  seen.insert(&Pre);
2673  BBInfo &PrInfo = MBBInfoMap[&Pre];
2674  if (!MO0.isUndef() && PrInfo.reachable &&
2675  !PrInfo.isLiveOut(MO0.getReg()))
2676  report("PHI operand is not live-out from predecessor", &MO0, I);
2677  }
2678  }
2679 
2680  // Did we see all predecessors?
2681  if (MInfo.reachable) {
2682  for (MachineBasicBlock *Pred : MBB.predecessors()) {
2683  if (!seen.count(Pred)) {
2684  report("Missing PHI operand", &Phi);
2685  errs() << printMBBReference(*Pred)
2686  << " is a predecessor according to the CFG.\n";
2687  }
2688  }
2689  }
2690  }
2691 }
2692 
2693 void MachineVerifier::visitMachineFunctionAfter() {
2694  calcRegsPassed();
2695 
2696  for (const MachineBasicBlock &MBB : *MF)
2697  checkPHIOps(MBB);
2698 
2699  // Now check liveness info if available
2700  calcRegsRequired();
2701 
2702  // Check for killed virtual registers that should be live out.
2703  for (const auto &MBB : *MF) {
2704  BBInfo &MInfo = MBBInfoMap[&MBB];
2705  for (Register VReg : MInfo.vregsRequired)
2706  if (MInfo.regsKilled.count(VReg)) {
2707  report("Virtual register killed in block, but needed live out.", &MBB);
2708  errs() << "Virtual register " << printReg(VReg)
2709  << " is used after the block.\n";
2710  }
2711  }
2712 
2713  if (!MF->empty()) {
2714  BBInfo &MInfo = MBBInfoMap[&MF->front()];
2715  for (Register VReg : MInfo.vregsRequired) {
2716  report("Virtual register defs don't dominate all uses.", MF);
2717  report_context_vreg(VReg);
2718  }
2719  }
2720 
2721  if (LiveVars)
2722  verifyLiveVariables();
2723  if (LiveInts)
2724  verifyLiveIntervals();
2725 
2726  // Check live-in list of each MBB. If a register is live into MBB, check
2727  // that the register is in regsLiveOut of each predecessor block. Since
2728  // this must come from a definition in the predecesssor or its live-in
2729  // list, this will catch a live-through case where the predecessor does not
2730  // have the register in its live-in list. This currently only checks
2731  // registers that have no aliases, are not allocatable and are not
2732  // reserved, which could mean a condition code register for instance.
2733  if (MRI->tracksLiveness())
2734  for (const auto &MBB : *MF)
2736  MCPhysReg LiveInReg = P.PhysReg;
2737  bool hasAliases = MCRegAliasIterator(LiveInReg, TRI, false).isValid();
2738  if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
2739  continue;
2740  for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2741  BBInfo &PInfo = MBBInfoMap[Pred];
2742  if (!PInfo.regsLiveOut.count(LiveInReg)) {
2743  report("Live in register not found to be live out from predecessor.",
2744  &MBB);
2745  errs() << TRI->getName(LiveInReg)
2746  << " not found to be live out from "
2747  << printMBBReference(*Pred) << "\n";
2748  }
2749  }
2750  }
2751 
2752  for (auto CSInfo : MF->getCallSitesInfo())
2753  if (!CSInfo.first->isCall())
2754  report("Call site info referencing instruction that is not call", MF);
2755 
2756  // If there's debug-info, check that we don't have any duplicate value
2757  // tracking numbers.
2758  if (MF->getFunction().getSubprogram()) {
2759  DenseSet<unsigned> SeenNumbers;
2760  for (auto &MBB : *MF) {
2761  for (auto &MI : MBB) {
2762  if (auto Num = MI.peekDebugInstrNum()) {
2763  auto Result = SeenNumbers.insert((unsigned)Num);
2764  if (!Result.second)
2765  report("Instruction has a duplicated value tracking number", &MI);
2766  }
2767  }
2768  }
2769  }
2770 }
2771 
2772 void MachineVerifier::verifyLiveVariables() {
2773  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
2774  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2776  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2777  for (const auto &MBB : *MF) {
2778  BBInfo &MInfo = MBBInfoMap[&MBB];
2779 
2780  // Our vregsRequired should be identical to LiveVariables' AliveBlocks
2781  if (MInfo.vregsRequired.count(Reg)) {
2782  if (!VI.AliveBlocks.test(MBB.getNumber())) {
2783  report("LiveVariables: Block missing from AliveBlocks", &MBB);
2784  errs() << "Virtual register " << printReg(Reg)
2785  << " must be live through the block.\n";
2786  }
2787  } else {
2788  if (VI.AliveBlocks.test(MBB.getNumber())) {
2789  report("LiveVariables: Block should not be in AliveBlocks", &MBB);
2790  errs() << "Virtual register " << printReg(Reg)
2791  << " is not needed live through the block.\n";
2792  }
2793  }
2794  }
2795  }
2796 }
2797 
2798 void MachineVerifier::verifyLiveIntervals() {
2799  assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
2800  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2802 
2803  // Spilling and splitting may leave unused registers around. Skip them.
2804  if (MRI->reg_nodbg_empty(Reg))
2805  continue;
2806 
2807  if (!LiveInts->hasInterval(Reg)) {
2808  report("Missing live interval for virtual register", MF);
2809  errs() << printReg(Reg, TRI) << " still has defs or uses\n";
2810  continue;
2811  }
2812 
2813  const LiveInterval &LI = LiveInts->getInterval(Reg);
2814  assert(Reg == LI.reg() && "Invalid reg to interval mapping");
2815  verifyLiveInterval(LI);
2816  }
2817 
2818  // Verify all the cached regunit intervals.
2819  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
2820  if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
2821  verifyLiveRange(*LR, i);
2822 }
2823 
2824 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
2825  const VNInfo *VNI, Register Reg,
2826  LaneBitmask LaneMask) {
2827  if (VNI->isUnused())
2828  return;
2829 
2830  const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
2831 
2832  if (!DefVNI) {
2833  report("Value not live at VNInfo def and not marked unused", MF);
2834  report_context(LR, Reg, LaneMask);
2835  report_context(*VNI);
2836  return;
2837  }
2838 
2839  if (DefVNI != VNI) {
2840  report("Live segment at def has different VNInfo", MF);
2841  report_context(LR, Reg, LaneMask);
2842  report_context(*VNI);
2843  return;
2844  }
2845 
2846  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
2847  if (!MBB) {
2848  report("Invalid VNInfo definition index", MF);
2849  report_context(LR, Reg, LaneMask);
2850  report_context(*VNI);
2851  return;
2852  }
2853 
2854  if (VNI->isPHIDef()) {
2855  if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
2856  report("PHIDef VNInfo is not defined at MBB start", MBB);
2857  report_context(LR, Reg, LaneMask);
2858  report_context(*VNI);
2859  }
2860  return;
2861  }
2862 
2863  // Non-PHI def.
2864  const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
2865  if (!MI) {
2866  report("No instruction at VNInfo def index", MBB);
2867  report_context(LR, Reg, LaneMask);
2868  report_context(*VNI);
2869  return;
2870  }
2871 
2872  if (Reg != 0) {
2873  bool hasDef = false;
2874  bool isEarlyClobber = false;
2875  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2876  if (!MOI->isReg() || !MOI->isDef())
2877  continue;
2879  if (MOI->getReg() != Reg)
2880  continue;
2881  } else {
2882  if (!Register::isPhysicalRegister(MOI->getReg()) ||
2883  !TRI->hasRegUnit(MOI->getReg(), Reg))
2884  continue;
2885  }
2886  if (LaneMask.any() &&
2887  (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
2888  continue;
2889  hasDef = true;
2890  if (MOI->isEarlyClobber())
2891  isEarlyClobber = true;
2892  }
2893 
2894  if (!hasDef) {
2895  report("Defining instruction does not modify register", MI);
2896  report_context(LR, Reg, LaneMask);
2897  report_context(*VNI);
2898  }
2899 
2900  // Early clobber defs begin at USE slots, but other defs must begin at
2901  // DEF slots.
2902  if (isEarlyClobber) {
2903  if (!VNI->def.isEarlyClobber()) {
2904  report("Early clobber def must be at an early-clobber slot", MBB);
2905  report_context(LR, Reg, LaneMask);
2906  report_context(*VNI);
2907  }
2908  } else if (!VNI->def.isRegister()) {
2909  report("Non-PHI, non-early clobber def must be at a register slot", MBB);
2910  report_context(LR, Reg, LaneMask);
2911  report_context(*VNI);
2912  }
2913  }
2914 }
2915 
2916 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
2918  Register Reg,
2919  LaneBitmask LaneMask) {
2920  const LiveRange::Segment &S = *I;
2921  const VNInfo *VNI = S.valno;
2922  assert(VNI && "Live segment has no valno");
2923 
2924  if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
2925  report("Foreign valno in live segment", MF);
2926  report_context(LR, Reg, LaneMask);
2927  report_context(S);
2928  report_context(*VNI);
2929  }
2930 
2931  if (VNI->isUnused()) {
2932  report("Live segment valno is marked unused", MF);
2933  report_context(LR, Reg, LaneMask);
2934  report_context(S);
2935  }
2936 
2937  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
2938  if (!MBB) {
2939  report("Bad start of live segment, no basic block", MF);
2940  report_context(LR, Reg, LaneMask);
2941  report_context(S);
2942  return;
2943  }
2944  SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
2945  if (S.start != MBBStartIdx && S.start != VNI->def) {
2946  report("Live segment must begin at MBB entry or valno def", MBB);
2947  report_context(LR, Reg, LaneMask);
2948  report_context(S);
2949  }
2950 
2951  const MachineBasicBlock *EndMBB =
2952  LiveInts->getMBBFromIndex(S.end.getPrevSlot());
2953  if (!EndMBB) {
2954  report("Bad end of live segment, no basic block", MF);
2955  report_context(LR, Reg, LaneMask);
2956  report_context(S);
2957  return;
2958  }
2959 
2960  // No more checks for live-out segments.
2961  if (S.end == LiveInts->getMBBEndIdx(EndMBB))
2962  return;
2963 
2964  // RegUnit intervals are allowed dead phis.
2965  if (!Register::isVirtualRegister(Reg) && VNI->isPHIDef() &&
2966  S.start == VNI->def && S.end == VNI->def.getDeadSlot())
2967  return;
2968 
2969  // The live segment is ending inside EndMBB
2970  const MachineInstr *MI =
2971  LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
2972  if (!MI) {
2973  report("Live segment doesn't end at a valid instruction", EndMBB);
2974  report_context(LR, Reg, LaneMask);
2975  report_context(S);
2976  return;
2977  }
2978 
2979  // The block slot must refer to a basic block boundary.
2980  if (S.end.isBlock()) {
2981  report("Live segment ends at B slot of an instruction", EndMBB);
2982  report_context(LR, Reg, LaneMask);
2983  report_context(S);
2984  }
2985 
2986  if (S.end.isDead()) {
2987  // Segment ends on the dead slot.
2988  // That means there must be a dead def.
2989  if (!SlotIndex::isSameInstr(S.start, S.end)) {
2990  report("Live segment ending at dead slot spans instructions", EndMBB);
2991  report_context(LR, Reg, LaneMask);
2992  report_context(S);
2993  }
2994  }
2995 
2996  // After tied operands are rewritten, a live segment can only end at an
2997  // early-clobber slot if it is being redefined by an early-clobber def.
2998  // TODO: Before tied operands are rewritten, a live segment can only end at an
2999  // early-clobber slot if the last use is tied to an early-clobber def.
3000  if (MF->getProperties().hasProperty(
3002  S.end.isEarlyClobber()) {
3003  if (I+1 == LR.end() || (I+1)->start != S.end) {
3004  report("Live segment ending at early clobber slot must be "
3005  "redefined by an EC def in the same instruction", EndMBB);
3006  report_context(LR, Reg, LaneMask);
3007  report_context(S);
3008  }
3009  }
3010 
3011  // The following checks only apply to virtual registers. Physreg liveness
3012  // is too weird to check.
3014  // A live segment can end with either a redefinition, a kill flag on a
3015  // use, or a dead flag on a def.
3016  bool hasRead = false;
3017  bool hasSubRegDef = false;
3018  bool hasDeadDef = false;
3019  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
3020  if (!MOI->isReg() || MOI->getReg() != Reg)
3021  continue;
3022  unsigned Sub = MOI->getSubReg();
3023  LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
3024  : LaneBitmask::getAll();
3025  if (MOI->isDef()) {
3026  if (Sub != 0) {
3027  hasSubRegDef = true;
3028  // An operand %0:sub0 reads %0:sub1..n. Invert the lane
3029  // mask for subregister defs. Read-undef defs will be handled by
3030  // readsReg below.
3031  SLM = ~SLM;
3032  }
3033  if (MOI->isDead())
3034  hasDeadDef = true;
3035  }
3036  if (LaneMask.any() && (LaneMask & SLM).none())
3037  continue;
3038  if (MOI->readsReg())
3039  hasRead = true;
3040  }
3041  if (S.end.isDead()) {
3042  // Make sure that the corresponding machine operand for a "dead" live
3043  // range has the dead flag. We cannot perform this check for subregister
3044  // liveranges as partially dead values are allowed.
3045  if (LaneMask.none() && !hasDeadDef) {
3046  report("Instruction ending live segment on dead slot has no dead flag",
3047  MI);
3048  report_context(LR, Reg, LaneMask);
3049  report_context(S);
3050  }
3051  } else {
3052  if (!hasRead) {
3053  // When tracking subregister liveness, the main range must start new
3054  // values on partial register writes, even if there is no read.
3055  if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
3056  !hasSubRegDef) {
3057  report("Instruction ending live segment doesn't read the register",
3058  MI);
3059  report_context(LR, Reg, LaneMask);
3060  report_context(S);
3061  }
3062  }
3063  }
3064  }
3065 
3066  // Now check all the basic blocks in this live segment.
3068  // Is this live segment the beginning of a non-PHIDef VN?
3069  if (S.start == VNI->def && !VNI->isPHIDef()) {
3070  // Not live-in to any blocks.
3071  if (MBB == EndMBB)
3072  return;
3073  // Skip this block.
3074  ++MFI;
3075  }
3076 
3078  if (LaneMask.any()) {
3079  LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
3080  OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
3081  }
3082 
3083  while (true) {
3084  assert(LiveInts->isLiveInToMBB(LR, &*MFI));
3085  // We don't know how to track physregs into a landing pad.
3086  if (!Register::isVirtualRegister(Reg) && MFI->isEHPad()) {
3087  if (&*MFI == EndMBB)
3088  break;
3089  ++MFI;
3090  continue;
3091  }
3092 
3093  // Is VNI a PHI-def in the current block?
3094  bool IsPHI = VNI->isPHIDef() &&
3095  VNI->def == LiveInts->getMBBStartIdx(&*MFI);
3096 
3097  // Check that VNI is live-out of all predecessors.
3098  for (const MachineBasicBlock *Pred : MFI->predecessors()) {
3099  SlotIndex PEnd = LiveInts->getMBBEndIdx(Pred);
3100  // Predecessor of landing pad live-out on last call.
3101  if (MFI->isEHPad()) {
3102  for (const MachineInstr &MI : llvm::reverse(*Pred)) {
3103  if (MI.isCall()) {
3104  PEnd = Indexes->getInstructionIndex(MI).getBoundaryIndex();
3105  break;
3106  }
3107  }
3108  }
3109  const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
3110 
3111  // All predecessors must have a live-out value. However for a phi
3112  // instruction with subregister intervals
3113  // only one of the subregisters (not necessarily the current one) needs to
3114  // be defined.
3115  if (!PVNI && (LaneMask.none() || !IsPHI)) {
3116  if (LiveRangeCalc::isJointlyDominated(Pred, Undefs, *Indexes))
3117  continue;
3118  report("Register not marked live out of predecessor", Pred);
3119  report_context(LR, Reg, LaneMask);
3120  report_context(*VNI);
3121  errs() << " live into " << printMBBReference(*MFI) << '@'
3122  << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
3123  << PEnd << '\n';
3124  continue;
3125  }
3126 
3127  // Only PHI-defs can take different predecessor values.
3128  if (!IsPHI && PVNI != VNI) {
3129  report("Different value live out of predecessor", Pred);
3130  report_context(LR, Reg, LaneMask);
3131  errs() << "Valno #" << PVNI->id << " live out of "
3132  << printMBBReference(*Pred) << '@' << PEnd << "\nValno #"
3133  << VNI->id << " live into " << printMBBReference(*MFI) << '@'
3134  << LiveInts->getMBBStartIdx(&*MFI) << '\n';
3135  }
3136  }
3137  if (&*MFI == EndMBB)
3138  break;
3139  ++MFI;
3140  }
3141 }
3142 
3143 void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg,
3144  LaneBitmask LaneMask) {
3145  for (const VNInfo *VNI : LR.valnos)
3146  verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3147 
3148  for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
3149  verifyLiveRangeSegment(LR, I, Reg, LaneMask);
3150 }
3151 
3152 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
3153  Register Reg = LI.reg();
3155  verifyLiveRange(LI, Reg);
3156 
3157  LaneBitmask Mask;
3159  for (const LiveInterval::SubRange &SR : LI.subranges()) {
3160  if ((Mask & SR.LaneMask).any()) {
3161  report("Lane masks of sub ranges overlap in live interval", MF);
3162  report_context(LI);
3163  }
3164  if ((SR.LaneMask & ~MaxMask).any()) {
3165  report("Subrange lanemask is invalid", MF);
3166  report_context(LI);
3167  }
3168  if (SR.empty()) {
3169  report("Subrange must not be empty", MF);
3170  report_context(SR, LI.reg(), SR.LaneMask);
3171  }
3172  Mask |= SR.LaneMask;
3173  verifyLiveRange(SR, LI.reg(), SR.LaneMask);
3174  if (!LI.covers(SR)) {
3175  report("A Subrange is not covered by the main range", MF);
3176  report_context(LI);
3177  }
3178  }
3179 
3180  // Check the LI only has one connected component.
3181  ConnectedVNInfoEqClasses ConEQ(*LiveInts);
3182  unsigned NumComp = ConEQ.Classify(LI);
3183  if (NumComp > 1) {
3184  report("Multiple connected components in live interval", MF);
3185  report_context(LI);
3186  for (unsigned comp = 0; comp != NumComp; ++comp) {
3187  errs() << comp << ": valnos";
3188  for (const VNInfo *I : LI.valnos)
3189  if (comp == ConEQ.getEqClass(I))
3190  errs() << ' ' << I->id;
3191  errs() << '\n';
3192  }
3193  }
3194 }
3195 
3196 namespace {
3197 
3198  // FrameSetup and FrameDestroy can have zero adjustment, so using a single
3199  // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
3200  // value is zero.
3201  // We use a bool plus an integer to capture the stack state.
3202  struct StackStateOfBB {
3203  StackStateOfBB() = default;
3204  StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
3205  EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3206  ExitIsSetup(ExitSetup) {}
3207 
3208  // Can be negative, which means we are setting up a frame.
3209  int EntryValue = 0;
3210  int ExitValue = 0;
3211  bool EntryIsSetup = false;
3212  bool ExitIsSetup = false;
3213  };
3214 
3215 } // end anonymous namespace
3216 
3217 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
3218 /// by a FrameDestroy <n>, stack adjustments are identical on all
3219 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
3220 void MachineVerifier::verifyStackFrame() {
3221  unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
3222  unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
3223  if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3224  return;
3225 
3227  SPState.resize(MF->getNumBlockIDs());
3229 
3230  // Visit the MBBs in DFS order.
3231  for (df_ext_iterator<const MachineFunction *,
3233  DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
3234  DFI != DFE; ++DFI) {
3235  const MachineBasicBlock *MBB = *DFI;
3236 
3237  StackStateOfBB BBState;
3238  // Check the exit state of the DFS stack predecessor.
3239  if (DFI.getPathLength() >= 2) {
3240  const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
3241  assert(Reachable.count(StackPred) &&
3242  "DFS stack predecessor is already visited.\n");
3243  BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
3244  BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
3245  BBState.ExitValue = BBState.EntryValue;
3246  BBState.ExitIsSetup = BBState.EntryIsSetup;
3247  }
3248 
3249  // Update stack state by checking contents of MBB.
3250  for (const auto &I : *MBB) {
3251  if (I.getOpcode() == FrameSetupOpcode) {
3252  if (BBState.ExitIsSetup)
3253  report("FrameSetup is after another FrameSetup", &I);
3254  BBState.ExitValue -= TII->getFrameTotalSize(I);
3255  BBState.ExitIsSetup = true;
3256  }
3257 
3258  if (I.getOpcode() == FrameDestroyOpcode) {
3259  int Size = TII->getFrameTotalSize(I);
3260  if (!BBState.ExitIsSetup)
3261  report("FrameDestroy is not after a FrameSetup", &I);
3262  int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3263  BBState.ExitValue;
3264  if (BBState.ExitIsSetup && AbsSPAdj != Size) {
3265  report("FrameDestroy <n> is after FrameSetup <m>", &I);
3266  errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
3267  << AbsSPAdj << ">.\n";
3268  }
3269  BBState.ExitValue += Size;
3270  BBState.ExitIsSetup = false;
3271  }
3272  }
3273  SPState[MBB->getNumber()] = BBState;
3274 
3275  // Make sure the exit state of any predecessor is consistent with the entry
3276  // state.
3277  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
3278  if (Reachable.count(Pred) &&
3279  (SPState[Pred->getNumber()].ExitValue != BBState.EntryValue ||
3280  SPState[Pred->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3281  report("The exit stack state of a predecessor is inconsistent.", MBB);
3282  errs() << "Predecessor " << printMBBReference(*Pred)
3283  << " has exit state (" << SPState[Pred->getNumber()].ExitValue
3284  << ", " << SPState[Pred->getNumber()].ExitIsSetup << "), while "
3285  << printMBBReference(*MBB) << " has entry state ("
3286  << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
3287  }
3288  }
3289 
3290  // Make sure the entry state of any successor is consistent with the exit
3291  // state.
3292  for (const MachineBasicBlock *Succ : MBB->successors()) {
3293  if (Reachable.count(Succ) &&
3294  (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3295  SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3296  report("The entry stack state of a successor is inconsistent.", MBB);
3297  errs() << "Successor " << printMBBReference(*Succ)
3298  << " has entry state (" << SPState[Succ->getNumber()].EntryValue
3299  << ", " << SPState[Succ->getNumber()].EntryIsSetup << "), while "
3300  << printMBBReference(*MBB) << " has exit state ("
3301  << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
3302  }
3303  }
3304 
3305  // Make sure a basic block with return ends with zero stack adjustment.
3306  if (!MBB->empty() && MBB->back().isReturn()) {
3307  if (BBState.ExitIsSetup)
3308  report("A return block ends with a FrameSetup.", MBB);
3309  if (BBState.ExitValue)
3310  report("A return block ends with a nonzero stack adjustment.", MBB);
3311  }
3312  }
3313 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:76
llvm::LaneBitmask
Definition: LaneBitmask.h:40
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:624
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:788
llvm::MachineBasicBlock::succ_size
unsigned succ_size() const
Definition: MachineBasicBlock.h:353
llvm::MachineMemOperand::isStore
bool isStore() const
Definition: MachineMemOperand.h:287
llvm::AtomicOrdering::AcquireRelease
@ AcquireRelease
Attrs
Function Attrs
Definition: README_ALTIVEC.txt:215
llvm::LiveInterval::computeSubRangeUndefs
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
Definition: LiveInterval.cpp:977
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:223
llvm::MachineFunctionProperties::hasProperty
bool hasProperty(Property P) const
Definition: MachineFunction.h:176
llvm::MachineBasicBlock::pred_begin
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Definition: MachineBasicBlock.h:325
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
MathExtras.h
llvm::MachineRegisterInfo::def_begin
def_iterator def_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:392
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::LiveStacks::getInterval
LiveInterval & getInterval(int Slot)
Definition: LiveStacks.h:68
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
llvm::LiveRange::empty
bool empty() const
Definition: LiveInterval.h:382
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1621
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:280
llvm::MachineRegisterInfo::shouldTrackSubRegLiveness
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level.
Definition: MachineRegisterInfo.h:212
llvm::SmallPtrSetImpl::erase
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
Definition: SmallPtrSet.h:379
LiveRangeCalc.h
MCTargetOptions.h
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:205
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:224
llvm::LiveIntervals::isLiveInToMBB
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
Definition: LiveIntervals.h:245
llvm::ConstantInt::getBitWidth
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:136
MCInstrDesc.h
SetOperations.h
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::isPreISelGenericOptimizationHint
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
llvm::MCOI::OPERAND_IMMEDIATE
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:59
llvm::Function
Definition: Function.h:60
StringRef.h
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
Pass.h
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::HexagonInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition: HexagonInstrInfo.cpp:432
llvm::BitVector::clear
void clear()
clear - Removes all bits from the bitvector.
Definition: BitVector.h:328
llvm::MachineBasicBlock::instrs
instr_range instrs()
Definition: MachineBasicBlock.h:272
llvm::SlotIndex::getBoundaryIndex
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
Definition: SlotIndexes.h:247
llvm::set_union
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
Definition: SetOperations.h:23
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::LiveIntervals::isNotInMIMap
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
Definition: LiveIntervals.h:221
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:592
llvm::ilist_node_with_parent::getNextNode
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:289
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:729
llvm::TargetRegisterInfo::getMinimalPhysRegClassLLT
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:230
InlineAsm.h
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::TargetRegisterInfo::isInAllocatableClass
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
Definition: TargetRegisterInfo.h:362
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:116
llvm::LiveIntervals::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:231
llvm::RegisterBankInfo::getRegBank
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
Definition: RegisterBankInfo.h:431
ErrorHandling.h
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:440
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::LiveQueryResult::isDeadDef
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:117
llvm::LiveRange::Segment
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
llvm::BitVector::set_bits
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:133
RegisterBankInfo.h
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
MachineBasicBlock.h
INITIALIZE_PASS
INITIALIZE_PASS(MachineVerifierPass, "machineverifier", "Verify generated machine code", false, false) FunctionPass *llvm
Definition: MachineVerifier.cpp:317
stores
hexagon widen stores
Definition: HexagonStoreWidening.cpp:118
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:239
llvm::VNInfo::def
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::LLT::getScalarType
LLT getScalarType() const
Definition: LowLevelTypeImpl.h:167
DenseMap.h
llvm::MachineBasicBlock::liveins
iterator_range< livein_iterator > liveins() const
Definition: MachineBasicBlock.h:421
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:380
llvm::AttributeList
Definition: Attributes.h:408
TargetInstrInfo.h
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
llvm::HexagonInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
Definition: HexagonInstrInfo.cpp:1658
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
EHPersonalities.h
llvm::ConstantFP::getValueAPF
const APFloat & getValueAPF() const
Definition: Constants.h:297
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:765
llvm::SmallPtrSet< const MachineBasicBlock *, 8 >
llvm::SlotIndex::isEarlyClobber
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
Definition: SlotIndexes.h:228
llvm::Intrinsic::getAttributes
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
llvm::SlotIndexes::getMBBEndIdx
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:475
llvm::Packing::Dense
@ Dense
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
STLExtras.h
llvm::MachineBasicBlock::back
MachineInstr & back()
Definition: MachineBasicBlock.h:257
llvm::MCRegisterInfo::getNumRegUnits
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
Definition: MCRegisterInfo.h:505
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:330
llvm::LiveQueryResult
Result of a LiveRange query.
Definition: LiveInterval.h:90
llvm::detail::DenseSetImpl::insert
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
llvm::APFloat::getSemantics
const fltSemantics & getSemantics() const
Definition: APFloat.h:1222
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1620
p
the resulting code requires compare and branches when and if * p
Definition: README.txt:396
llvm::LiveIntervals::getMBBFromIndex
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Definition: LiveIntervals.h:255
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:103
DepthFirstIterator.h
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:51
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:226
llvm::MachineRegisterInfo::use_nodbg_begin
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:526
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::MCRegisterInfo::subregs
iterator_range< mc_subreg_iterator > subregs(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, excluding Reg.
Definition: MCRegisterInfo.h:309
llvm::MachineRegisterInfo::tracksLiveness
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
Definition: MachineRegisterInfo.h:195
llvm::LiveIntervals::print
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Definition: LiveIntervals.cpp:153
isLiveOut
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
Definition: SIOptimizeExecMasking.cpp:287
llvm::classifyEHPersonality
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
Definition: EHPersonalities.cpp:21
llvm::verifyMachineFunction
void verifyMachineFunction(MachineFunctionAnalysisManager *, const std::string &Banner, const MachineFunction &MF)
Definition: MachineVerifier.cpp:324
llvm::df_ext_begin
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
Definition: DepthFirstIterator.h:242
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:84
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::MachineBasicBlock::pred_size
unsigned pred_size() const
Definition: MachineBasicBlock.h:337
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:116
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::APFloatBase::getSizeInBits
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:226
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1607
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:834
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::SlotIndexes::hasIndex
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:379
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::LiveStacks::hasInterval
bool hasInterval(int Slot) const
Definition: LiveStacks.h:82
llvm::LiveRange::liveAt
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:401
llvm::MachineFunctionProperties::Property::Selected
@ Selected
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::LiveVariables::VarInfo
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:80
Constants.h
llvm::LiveRange::begin
iterator begin()
Definition: LiveInterval.h:215
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:378
llvm::MCRegisterInfo::subregs_inclusive
iterator_range< mc_subreg_iterator > subregs_inclusive(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, including Reg.
Definition: MCRegisterInfo.h:316
llvm::LiveIntervals::getMBBStartIdx
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
Definition: LiveIntervals.h:236
llvm::LiveIntervals::getCachedRegUnit
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
Definition: LiveIntervals.h:406
llvm::LiveRange::covers
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
Definition: LiveInterval.cpp:494
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::set_subtract
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Definition: SetOperations.h:63
llvm::MachineBasicBlock::succ_end
succ_iterator succ_end()
Definition: MachineBasicBlock.h:343
llvm::Pass::getAnalysisIfAvailable
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Definition: PassAnalysisSupport.h:211
llvm::DstOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:106
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:925
Twine.h
llvm::BitVector::size
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:152
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::MachineOperand::getRegMask
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Definition: MachineOperand.h:639
llvm::MachineBasicBlock::isSuccessor
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
Definition: MachineBasicBlock.cpp:909
llvm::LiveRange::const_iterator
Segments::const_iterator const_iterator
Definition: LiveInterval.h:213
llvm::MachineOperand::MO_FrameIndex
@ MO_FrameIndex
Abstract Stack Frame Index.
Definition: MachineOperand.h:56
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::LaneBitmask::getNone
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:83
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::TargetRegisterInfo::hasRegUnit
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
Definition: TargetRegisterInfo.h:428
b
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
Definition: README.txt:418
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:731
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:328
LiveVariables.h
DenseSet.h
TargetOpcodes.h
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
pass
modulo schedule Modulo Schedule test pass
Definition: ModuloSchedule.cpp:2103
llvm::LiveRange::valnos
VNInfoList valnos
Definition: LiveInterval.h:204
llvm::MachineBasicBlock::RegisterMaskPair
Pair of physical register and lane mask.
Definition: MachineBasicBlock.h:100
MachineInstrBundle.h
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:139
llvm::AtomicOrdering::Acquire
@ Acquire
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::SlotIndexes::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:384
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::PrintLaneMask
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:94
llvm::SmallVectorImpl::resize
void resize(size_type N)
Definition: SmallVector.h:619
llvm::SlotIndex::getDeadSlot
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:258
BitVector.h
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:822
llvm::MachineRegisterInfo::use_nodbg_end
static use_nodbg_iterator use_nodbg_end()
Definition: MachineRegisterInfo.h:529
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:313
llvm::SlotIndex::isRegister
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
Definition: SlotIndexes.h:232
SmallPtrSet.h
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:303
llvm::BitVector
Definition: BitVector.h:75
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:62
llvm::MachineFunction::verify
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
Definition: MachineVerifier.cpp:337
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
llvm::MachineRegisterInfo::reservedRegsFrozen
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
Definition: MachineRegisterInfo.h:900
llvm::LiveQueryResult::valueIn
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:105
llvm::MachineFunctionAnalysisManager
An AnalysisManager<MachineFunction> that also exposes IR analysis results.
Definition: MachinePassManager.h:41
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:82
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
LowLevelTypeImpl.h
llvm::initializeMachineVerifierPassPass
void initializeMachineVerifierPassPass(PassRegistry &)
llvm::printRegUnit
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
Definition: TargetRegisterInfo.cpp:142
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:434
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:129
llvm::SlotIndexes::MBBIndexEnd
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
Definition: SlotIndexes.h:508
llvm::InlineAsm::MIOp_FirstOperand
@ MIOp_FirstOperand
Definition: InlineAsm.h:225
llvm::MachineRegisterInfo::isSSA
bool isSSA() const
Definition: MachineRegisterInfo.h:183
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:112
llvm::MachineFunctionProperties::Property::FailsVerification
@ FailsVerification
llvm::LLT::getAddressSpace
unsigned getAddressSpace() const
Definition: LowLevelTypeImpl.h:238
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::DenseSet
Implements a dense probed hash-table based set.
Definition: DenseSet.h:268
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
BasicBlock.h
llvm::ClrHandlerType::Filter
@ Filter
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:626
VI
@ VI
Definition: SIInstrInfo.cpp:7831
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:394
llvm::LiveRange::getVNInfoBefore
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
Definition: LiveInterval.h:429
llvm::SlotIndexes::getMBBStartIdx
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:465
llvm::MachineBasicBlock::pred_end
pred_iterator pred_end()
Definition: MachineBasicBlock.h:327
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:409
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::clear
void clear()
Definition: DenseMap.h:112
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
LiveIntervals.h
llvm::LiveRange
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
llvm::LiveIntervals::getMBBEndIdx
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
Definition: LiveIntervals.h:241
llvm::VNInfo::id
unsigned id
The ID number of this value.
Definition: LiveInterval.h:58
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:756
llvm::ARM_AM::add
@ add
Definition: ARMAddressingModes.h:39
llvm::MCOperandInfo::isGenericType
bool isGenericType() const
Definition: MCInstrDesc.h:117
llvm::SlotIndexes::MBBIndexBegin
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
Definition: SlotIndexes.h:503
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap
Definition: DenseMap.h:716
llvm::LiveRange::getNumValNums
unsigned getNumValNums() const
Definition: LiveInterval.h:313
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:384
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineFunctionProperties::Property::TracksDebugUserValues
@ TracksDebugUserValues
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::LaneBitmask::any
constexpr bool any() const
Definition: LaneBitmask.h:53
llvm::isScopedEHPersonality
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
Definition: EHPersonalities.h:79
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:60
MCRegisterInfo.h
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:122
llvm::SmallPtrSetImpl::begin
iterator begin() const
Definition: SmallPtrSet.h:403
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:126
llvm::createMachineVerifierPass
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
llvm::SlotIndex::isSameInstr
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:196
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1672
llvm::LiveRange::Query
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:541
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:218
MachineFunctionPass.h
llvm::MachineFunctionProperties::Property::RegBankSelected
@ RegBankSelected
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MIBundleOperandIteratorBase::isValid
bool isValid() const
isValid - Returns true until all the operands have been visited.
Definition: MachineInstrBundle.h:136
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:659
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:567
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:120
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1665
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:341
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:435
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::MachineMemOperand::getSuccessOrdering
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
Definition: MachineMemOperand.h:269
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition: MachineOperand.h:602
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineBasicBlock::predecessors
iterator_range< pred_iterator > predecessors()
Definition: MachineBasicBlock.h:358
llvm::ErrorInfo
Base class for user error types.
Definition: Error.h:347
llvm::MachineRegisterInfo::def_end
static def_iterator def_end()
Definition: MachineRegisterInfo.h:395
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:821
isStore
static bool isStore(int Opcode)
Definition: ARCInstrInfo.cpp:58
llvm::LLT::isScalar
bool isScalar() const
Definition: LowLevelTypeImpl.h:118
llvm::SlotIndex::getRegSlot
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:253
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::SmallPtrSetImpl::count
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:383
llvm::TargetSubtargetInfo::getRegBankInfo
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
Definition: TargetSubtargetInfo.h:129
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::df_iterator_default_set
Definition: DepthFirstIterator.h:70
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1588
llvm::MachineOperand::isShuffleMask
bool isShuffleMask() const
Definition: MachineOperand.h:353
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:481
llvm::SmallPtrSetImplBase::clear
void clear()
Definition: SmallPtrSet.h:95
llvm::MachineBasicBlock::phis
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
Definition: MachineBasicBlock.h:305
llvm::ArrayRef< int >
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:1078
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:178
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:178
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:364
llvm::MachineBasicBlock::isEHPad
bool isEHPad() const
Returns true if the block is a landing pad.
Definition: MachineBasicBlock.h:548
isLoad
static bool isLoad(int Opcode)
Definition: ARCInstrInfo.cpp:53
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::LaneBitmask::none
constexpr bool none() const
Definition: LaneBitmask.h:52
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineOperand::isIntrinsicID
bool isIntrinsicID() const
Definition: MachineOperand.h:351
uint32_t
llvm::append_range
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
Definition: STLExtras.h:1813
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:55
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
TargetSubtargetInfo.h
llvm::MachineFrameInfo::getPristineRegs
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
Definition: MachineFrameInfo.cpp:115
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:855
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MachineFunctionProperties::Property::TiedOpsRewritten
@ TiedOpsRewritten
llvm::MCInstrDesc::variadicOpsAreDefs
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:415
llvm::df_ext_end
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Definition: DepthFirstIterator.h:247
llvm::LiveInterval::SubRange
A live range for subregisters.
Definition: LiveInterval.h:693
llvm::MachineRegisterInfo::getReservedRegs
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
Definition: MachineRegisterInfo.h:914
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SmallPtrSetImplBase::size
size_type size() const
Definition: SmallPtrSet.h:93
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
llvm::AtomicOrdering::Release
@ Release
llvm::VNInfo::isPHIDef
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:78
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LiveRangeCalc::isJointlyDominated
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
Definition: LiveRangeCalc.cpp:432
llvm::MCOperandInfo::getGenericTypeIndex
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:122
llvm::MachineFunctionProperties::Property::FailedISel
@ FailedISel
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:489
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
std
Definition: BitVector.h:851
llvm::MachineFunctionProperties::Property::NoPHIs
@ NoPHIs
llvm::MachineOperand::readsReg
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Definition: MachineOperand.h:457
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:277
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:636
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:341
llvm::ConstMIBundleOperands
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
Definition: MachineInstrBundle.h:185
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::RegisterBank::getName
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:51
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:234
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:566
llvm::LLT::getSizeInBytes
TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelTypeImpl.h:162
llvm::RegisterBank::getSize
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:54
Casting.h
llvm::FixedStackPseudoSourceValue
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
Definition: PseudoSourceValue.h:94
Function.h
llvm::MachineFunction::print
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
Definition: MachineFunction.cpp:571
llvm::SlotIndexes::MBBIndexIterator
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
Definition: SlotIndexes.h:486
llvm::MachineRegisterInfo::getRegBankOrNull
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
Definition: MachineRegisterInfo.h:668
verify
ppc ctr loops verify
Definition: PPCCTRLoopsVerify.cpp:76
StackMaps.h
llvm::LiveRange::getValNumInfo
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
Definition: LiveInterval.h:317
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveRange::getVNInfoAt
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:421
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::ReversePostOrderTraversal
Definition: PostOrderIterator.h:291
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:445
LiveInterval.h
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:777
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:680
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:187
Instructions.h
PostOrderIterator.h
SmallVector.h
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:355
LiveStacks.h
RegisterBank.h
llvm::SmallPtrSetImplBase::empty
LLVM_NODISCARD bool empty() const
Definition: SmallPtrSet.h:92
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::DstOp
Definition: MachineIRBuilder.h:65
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:717
llvm::LiveInterval::hasSubRanges
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:803
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::df_ext_iterator
Definition: DepthFirstIterator.h:236
llvm::LiveVariables::getVarInfo
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
Definition: LiveVariables.cpp:84
LaneBitmask.h
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:249
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:430
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MachineOperand.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::LiveVariables
Definition: LiveVariables.h:47
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
llvm::VNInfo::isUnused
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:81
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:125
llvm::MachineRegisterInfo::isReservedRegUnit
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
Definition: MachineRegisterInfo.cpp:636
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:63
SlotIndexes.h
llvm::LLT::getElementType
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelTypeImpl.h:248
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:385
raw_ostream.h
llvm::MachineFunction::empty
bool empty() const
Definition: MachineFunction.h:833
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:212
llvm::MachineInstr::isBarrier
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:846
llvm::ConnectedVNInfoEqClasses
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
Definition: LiveInterval.h:998
InitializePasses.h
llvm::LiveStacks
Definition: LiveStacks.h:35
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
TargetRegisterInfo.h
llvm::MachineBasicBlock::getName
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
Definition: MachineBasicBlock.cpp:310
llvm::LiveQueryResult::isKill
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:112
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
llvm::LaneBitmask::getAll
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:84
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SrcOp
Definition: MachineIRBuilder.h:126
llvm::LiveRange::end
iterator end()
Definition: LiveInterval.h:216
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
llvm::MachineRegisterInfo::verifyUseLists
void verifyUseLists() const
Verify the use list of all registers.
Definition: MachineRegisterInfo.cpp:253
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:211
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::MCRegisterInfo::getSubRegIdxSize
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
Definition: MCRegisterInfo.cpp:56
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::LiveInterval::subranges
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:775