91 struct MachineVerifier {
92 MachineVerifier(
Pass *
pass,
const char *b) : PASS(
pass), Banner(
b) {}
105 unsigned foundErrors = 0;
108 bool isFunctionRegBankSelected =
false;
109 bool isFunctionSelected =
false;
110 bool isFunctionTracksDebugUserValues =
false;
120 BlockSet FunctionBlocks;
124 RegVector regsDefined, regsDead, regsKilled;
125 RegMaskVector regMasks;
130 void addRegWithSubRegs(RegVector &RV,
Register Reg) {
132 if (
Reg.isPhysical())
138 bool reachable =
false;
159 RegSet vregsRequired;
162 BlockSet Preds, Succs;
169 if (!
Reg.isVirtual())
171 if (regsLiveOut.count(Reg))
173 return vregsRequired.insert(Reg).second;
177 bool addRequired(
const RegSet &RS) {
178 bool Changed =
false;
180 Changed |= addRequired(Reg);
185 bool addRequired(
const RegMap &RM) {
186 bool Changed =
false;
187 for (
const auto &
I : RM)
188 Changed |= addRequired(
I.first);
194 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
202 return Reg.id() < regsReserved.
size() && regsReserved.
test(
Reg.id());
205 bool isAllocatable(
Register Reg)
const {
206 return Reg.id() <
TRI->getNumRegs() &&
TRI->isInAllocatableClass(Reg) &&
216 void visitMachineFunctionBefore();
228 void visitMachineOperand(
const MachineOperand *MO,
unsigned MONum);
231 void visitMachineFunctionAfter();
236 void report(
const char *msg,
const MachineOperand *MO,
unsigned MONum,
244 void report_context(
const VNInfo &VNI)
const;
245 void report_context(
SlotIndex Pos)
const;
246 void report_context(
MCPhysReg PhysReg)
const;
247 void report_context_liverange(
const LiveRange &LR)
const;
248 void report_context_lanemask(
LaneBitmask LaneMask)
const;
249 void report_context_vreg(
Register VReg)
const;
250 void report_context_vreg_regunit(
Register VRegOrUnit)
const;
261 Register VRegOrUnit,
bool SubRangeCheck =
false,
265 void calcRegsPassed();
268 void calcRegsRequired();
269 void verifyLiveVariables();
270 void verifyLiveIntervals();
274 void verifyLiveRangeSegment(
const LiveRange &,
280 void verifyStackFrame();
282 void verifySlotIndexes()
const;
289 const std::string Banner;
291 MachineVerifierPass(std::string banner = std::string())
310 MachineFunctionProperties::Property::FailsVerification))
313 unsigned FoundErrors = MachineVerifier(
this, Banner.c_str()).verify(MF);
322char MachineVerifierPass::ID = 0;
325 "Verify generated machine code",
false,
false)
328 return new MachineVerifierPass(Banner);
332 const std::string &Banner,
339 unsigned FoundErrors = MachineVerifier(
nullptr, Banner.c_str()).verify(MF);
347 unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
348 if (AbortOnErrors && FoundErrors)
350 return FoundErrors == 0;
353void MachineVerifier::verifySlotIndexes()
const {
354 if (Indexes ==
nullptr)
372 MRI->getNumVirtRegs())
373 report(
"Function has NoVRegs property but there are VReg operands", &MF);
392 if (isFunctionFailedISel)
417 verifyProperties(MF);
419 visitMachineFunctionBefore();
421 visitMachineBasicBlockBefore(&
MBB);
425 bool InBundle =
false;
428 if (
MI.getParent() != &
MBB) {
429 report(
"Bad instruction parent pointer", &
MBB);
430 errs() <<
"Instruction: " <<
MI;
435 if (InBundle && !
MI.isBundledWithPred())
436 report(
"Missing BundledPred flag, "
437 "BundledSucc was set on predecessor",
439 if (!InBundle &&
MI.isBundledWithPred())
440 report(
"BundledPred flag is set, "
441 "but BundledSucc not set on predecessor",
445 if (!
MI.isInsideBundle()) {
447 visitMachineBundleAfter(CurBundle);
449 visitMachineBundleBefore(CurBundle);
450 }
else if (!CurBundle)
451 report(
"No bundle header", &
MI);
452 visitMachineInstrBefore(&
MI);
453 for (
unsigned I = 0,
E =
MI.getNumOperands();
I !=
E; ++
I) {
455 if (
Op.getParent() != &
MI) {
458 report(
"Instruction has operand with wrong parent set", &
MI);
461 visitMachineOperand(&Op,
I);
465 InBundle =
MI.isBundledWithSucc();
468 visitMachineBundleAfter(CurBundle);
470 report(
"BundledSucc flag set on last instruction in block", &
MBB.
back());
471 visitMachineBasicBlockAfter(&
MBB);
473 visitMachineFunctionAfter();
486void MachineVerifier::report(
const char *msg,
const MachineFunction *MF) {
489 if (!foundErrors++) {
491 errs() <<
"# " << Banner <<
'\n';
492 if (LiveInts !=
nullptr)
497 errs() <<
"*** Bad machine code: " << msg <<
" ***\n"
498 <<
"- function: " << MF->
getName() <<
"\n";
512void MachineVerifier::report(
const char *msg,
const MachineInstr *
MI) {
514 report(msg,
MI->getParent());
515 errs() <<
"- instruction: ";
521void MachineVerifier::report(
const char *msg,
const MachineOperand *MO,
522 unsigned MONum,
LLT MOVRegType) {
525 errs() <<
"- operand " << MONum <<
": ";
531 report(
Msg.str().c_str(),
MI);
534void MachineVerifier::report_context(
SlotIndex Pos)
const {
535 errs() <<
"- at: " << Pos <<
'\n';
538void MachineVerifier::report_context(
const LiveInterval &LI)
const {
539 errs() <<
"- interval: " << LI <<
'\n';
544 report_context_liverange(LR);
545 report_context_vreg_regunit(VRegUnit);
547 report_context_lanemask(LaneMask);
551 errs() <<
"- segment: " << S <<
'\n';
554void MachineVerifier::report_context(
const VNInfo &VNI)
const {
555 errs() <<
"- ValNo: " << VNI.
id <<
" (def " << VNI.
def <<
")\n";
558void MachineVerifier::report_context_liverange(
const LiveRange &LR)
const {
559 errs() <<
"- liverange: " << LR <<
'\n';
562void MachineVerifier::report_context(
MCPhysReg PReg)
const {
566void MachineVerifier::report_context_vreg(
Register VReg)
const {
570void MachineVerifier::report_context_vreg_regunit(
Register VRegOrUnit)
const {
572 report_context_vreg(VRegOrUnit);
578void MachineVerifier::report_context_lanemask(
LaneBitmask LaneMask)
const {
583 BBInfo &MInfo = MBBInfoMap[
MBB];
584 if (!MInfo.reachable) {
585 MInfo.reachable =
true;
591void MachineVerifier::visitMachineFunctionBefore() {
593 regsReserved =
MRI->reservedRegsFrozen() ?
MRI->getReservedRegs()
594 :
TRI->getReservedRegs(*MF);
597 markReachable(&MF->
front());
600 FunctionBlocks.clear();
601 for (
const auto &
MBB : *MF) {
602 FunctionBlocks.insert(&
MBB);
603 BBInfo &MInfo = MBBInfoMap[&
MBB];
607 report(
"MBB has duplicate entries in its predecessor list.", &
MBB);
611 report(
"MBB has duplicate entries in its successor list.", &
MBB);
615 MRI->verifyUseLists();
623 FirstTerminator =
nullptr;
624 FirstNonPHI =
nullptr;
626 if (!MF->getProperties().hasProperty(
631 if (isAllocatable(LI.PhysReg) && !
MBB->
isEHPad() &&
634 report(
"MBB has allocatable live-in, but isn't entry, landing-pad, or "
635 "inlineasm-br-indirect-target.",
637 report_context(LI.PhysReg);
644 report(
"ir-block-address-taken is associated with basic block not used by "
653 LandingPadSuccs.
insert(succ);
654 if (!FunctionBlocks.count(succ))
655 report(
"MBB has successor that isn't part of the function.",
MBB);
656 if (!MBBInfoMap[succ].Preds.count(
MBB)) {
657 report(
"Inconsistent CFG",
MBB);
658 errs() <<
"MBB is not in the predecessor list of the successor "
665 if (!FunctionBlocks.count(Pred))
666 report(
"MBB has predecessor that isn't part of the function.",
MBB);
667 if (!MBBInfoMap[Pred].Succs.count(
MBB)) {
668 report(
"Inconsistent CFG",
MBB);
669 errs() <<
"MBB is not in the successor list of the predecessor "
677 if (LandingPadSuccs.
size() > 1 &&
682 report(
"MBB has more than one landing pad successor",
MBB);
695 report(
"MBB exits via unconditional fall-through but ends with a "
696 "barrier instruction!",
MBB);
699 report(
"MBB exits via unconditional fall-through but has a condition!",
702 }
else if (
TBB && !FBB &&
Cond.empty()) {
705 report(
"MBB exits via unconditional branch but doesn't contain "
706 "any instructions!",
MBB);
708 report(
"MBB exits via unconditional branch but doesn't end with a "
709 "barrier instruction!",
MBB);
711 report(
"MBB exits via unconditional branch but the branch isn't a "
712 "terminator instruction!",
MBB);
714 }
else if (
TBB && !FBB && !
Cond.empty()) {
717 report(
"MBB exits via conditional branch/fall-through but doesn't "
718 "contain any instructions!",
MBB);
720 report(
"MBB exits via conditional branch/fall-through but ends with a "
721 "barrier instruction!",
MBB);
723 report(
"MBB exits via conditional branch/fall-through but the branch "
724 "isn't a terminator instruction!",
MBB);
726 }
else if (
TBB && FBB) {
730 report(
"MBB exits via conditional branch/branch but doesn't "
731 "contain any instructions!",
MBB);
733 report(
"MBB exits via conditional branch/branch but doesn't end with a "
734 "barrier instruction!",
MBB);
736 report(
"MBB exits via conditional branch/branch but the branch "
737 "isn't a terminator instruction!",
MBB);
740 report(
"MBB exits via conditional branch/branch but there's no "
744 report(
"analyzeBranch returned invalid data!",
MBB);
750 report(
"MBB exits via jump or conditional branch, but its target isn't a "
754 report(
"MBB exits via conditional branch, but its target isn't a CFG "
761 bool Fallthrough = !
TBB || (!
Cond.empty() && !FBB);
766 if (!
Cond.empty() && !FBB) {
769 report(
"MBB conditionally falls through out of function!",
MBB);
771 report(
"MBB exits via conditional branch/fall-through but the CFG "
772 "successors don't match the actual successors!",
779 if (SuccMBB ==
TBB || SuccMBB == FBB)
787 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
789 report(
"MBB has unexpected successors which are not branch targets, "
790 "fallthrough, EHPads, or inlineasm_br targets.",
796 if (
MRI->tracksLiveness()) {
799 report(
"MBB live-in list contains non-physical register",
MBB);
823void MachineVerifier::visitMachineBundleBefore(
const MachineInstr *
MI) {
826 if (!(idx > lastIndex)) {
827 report(
"Instruction index out of order",
MI);
828 errs() <<
"Last instruction was at " << lastIndex <<
'\n';
834 if (
MI->isTerminator()) {
835 if (!FirstTerminator)
836 FirstTerminator =
MI;
837 }
else if (FirstTerminator) {
840 if (FirstTerminator->
getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
841 report(
"Non-terminator instruction after the first terminator",
MI);
842 errs() <<
"First terminator was:\t" << *FirstTerminator;
851 if (
MI->getNumOperands() < 2) {
852 report(
"Too few operands on inline asm",
MI);
855 if (!
MI->getOperand(0).isSymbol())
856 report(
"Asm string must be an external symbol",
MI);
857 if (!
MI->getOperand(1).isImm())
858 report(
"Asm flags must be an immediate",
MI);
862 if (!isUInt<6>(
MI->getOperand(1).getImm()))
863 report(
"Unknown asm flags", &
MI->getOperand(1), 1);
869 for (
unsigned e =
MI->getNumOperands(); OpNo <
e; OpNo += NumOps) {
877 if (OpNo >
MI->getNumOperands())
878 report(
"Missing operands in last group",
MI);
881 if (OpNo < MI->getNumOperands() &&
MI->getOperand(OpNo).isMetadata())
885 for (
unsigned e =
MI->getNumOperands(); OpNo < e; ++OpNo) {
888 report(
"Expected implicit register after groups", &MO, OpNo);
891 if (
MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
904 if (!IndirectTargetMBB) {
905 report(
"INLINEASM_BR indirect target does not exist", &MO, i);
910 report(
"INLINEASM_BR indirect target missing from successor list", &MO,
914 report(
"INLINEASM_BR indirect target predecessor list missing parent",
920bool MachineVerifier::verifyAllRegOpsScalar(
const MachineInstr &
MI,
925 const auto Reg = Op.getReg();
926 if (Reg.isPhysical())
928 return !MRI.getType(Reg).isScalar();
931 report(
"All register operands must have scalar types", &
MI);
938bool MachineVerifier::verifyVectorElementMatch(
LLT Ty0,
LLT Ty1,
941 report(
"operand types must be all-vector or all-scalar",
MI);
951 report(
"operand types must preserve number of vector elements",
MI);
958void MachineVerifier::verifyPreISelGenericInstruction(
const MachineInstr *
MI) {
959 if (isFunctionSelected)
960 report(
"Unexpected generic instruction in a Selected function",
MI);
963 unsigned NumOps =
MI->getNumOperands();
966 if (
MI->isBranch() && !
MI->isIndirectBranch()) {
976 report(
"Branch instruction is missing a basic block operand or "
977 "isIndirectBranch property",
990 size_t TypeIdx = MCID.
operands()[
I].getGenericTypeIndex();
991 Types.resize(std::max(TypeIdx + 1,
Types.size()));
995 report(
"generic instruction must use register operands",
MI);
1005 if (!Types[TypeIdx].
isValid())
1006 Types[TypeIdx] = OpTy;
1007 else if (Types[TypeIdx] != OpTy)
1008 report(
"Type mismatch in generic instruction", MO,
I, OpTy);
1011 report(
"Generic instruction is missing a virtual register type", MO,
I);
1016 for (
unsigned I = 0;
I <
MI->getNumOperands(); ++
I) {
1019 report(
"Generic instruction cannot have physical register", MO,
I);
1031 unsigned Opc =
MI->getOpcode();
1033 case TargetOpcode::G_ASSERT_SEXT:
1034 case TargetOpcode::G_ASSERT_ZEXT: {
1035 std::string OpcName =
1036 Opc == TargetOpcode::G_ASSERT_ZEXT ?
"G_ASSERT_ZEXT" :
"G_ASSERT_SEXT";
1037 if (!
MI->getOperand(2).isImm()) {
1038 report(
Twine(OpcName,
" expects an immediate operand #2"),
MI);
1044 LLT SrcTy =
MRI->getType(Src);
1045 int64_t
Imm =
MI->getOperand(2).getImm();
1047 report(
Twine(OpcName,
" size must be >= 1"),
MI);
1052 report(
Twine(OpcName,
" size must be less than source bit width"),
MI);
1060 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1061 report(
Twine(OpcName,
" cannot change register bank"),
MI);
1067 if (DstRC && DstRC !=
MRI->getRegClassOrNull(Src)) {
1069 Twine(OpcName,
" source and destination register classes must match"),
1077 case TargetOpcode::G_CONSTANT:
1078 case TargetOpcode::G_FCONSTANT: {
1079 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1081 report(
"Instruction cannot use a vector result type",
MI);
1083 if (
MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1084 if (!
MI->getOperand(1).isCImm()) {
1085 report(
"G_CONSTANT operand must be cimm",
MI);
1091 report(
"inconsistent constant size",
MI);
1093 if (!
MI->getOperand(1).isFPImm()) {
1094 report(
"G_FCONSTANT operand must be fpimm",
MI);
1101 report(
"inconsistent constant size",
MI);
1107 case TargetOpcode::G_LOAD:
1108 case TargetOpcode::G_STORE:
1109 case TargetOpcode::G_ZEXTLOAD:
1110 case TargetOpcode::G_SEXTLOAD: {
1111 LLT ValTy =
MRI->getType(
MI->getOperand(0).getReg());
1112 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1114 report(
"Generic memory instruction must access a pointer",
MI);
1118 if (!
MI->hasOneMemOperand()) {
1119 report(
"Generic instruction accessing memory must have one mem operand",
1123 if (
MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1124 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1126 report(
"Generic extload must have a narrower memory type",
MI);
1127 }
else if (
MI->getOpcode() == TargetOpcode::G_LOAD) {
1129 report(
"load memory size cannot exceed result size",
MI);
1130 }
else if (
MI->getOpcode() == TargetOpcode::G_STORE) {
1132 report(
"store memory size cannot exceed value size",
MI);
1136 if (Opc == TargetOpcode::G_STORE) {
1139 report(
"atomic store cannot use acquire ordering",
MI);
1144 report(
"atomic load cannot use release ordering",
MI);
1150 case TargetOpcode::G_PHI: {
1151 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1156 LLT Ty = MRI->getType(MO.getReg());
1157 if (!Ty.isValid() || (Ty != DstTy))
1161 report(
"Generic Instruction G_PHI has operands with incompatible/missing "
1166 case TargetOpcode::G_BITCAST: {
1167 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1168 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1173 report(
"bitcast cannot convert between pointers and other types",
MI);
1176 report(
"bitcast sizes must match",
MI);
1179 report(
"bitcast must change the type",
MI);
1183 case TargetOpcode::G_INTTOPTR:
1184 case TargetOpcode::G_PTRTOINT:
1185 case TargetOpcode::G_ADDRSPACE_CAST: {
1186 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1187 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1191 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1196 if (
MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1198 report(
"inttoptr result type must be a pointer",
MI);
1200 report(
"inttoptr source type must not be a pointer",
MI);
1201 }
else if (
MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1203 report(
"ptrtoint source type must be a pointer",
MI);
1205 report(
"ptrtoint result type must not be a pointer",
MI);
1207 assert(
MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1209 report(
"addrspacecast types must be pointers",
MI);
1212 report(
"addrspacecast must convert different address spaces",
MI);
1218 case TargetOpcode::G_PTR_ADD: {
1219 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1220 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1221 LLT OffsetTy =
MRI->getType(
MI->getOperand(2).getReg());
1226 report(
"gep first operand must be a pointer",
MI);
1229 report(
"gep offset operand must not be a pointer",
MI);
1234 case TargetOpcode::G_PTRMASK: {
1235 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1236 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1237 LLT MaskTy =
MRI->getType(
MI->getOperand(2).getReg());
1242 report(
"ptrmask result type must be a pointer",
MI);
1245 report(
"ptrmask mask type must be an integer",
MI);
1247 verifyVectorElementMatch(DstTy, MaskTy,
MI);
1250 case TargetOpcode::G_SEXT:
1251 case TargetOpcode::G_ZEXT:
1252 case TargetOpcode::G_ANYEXT:
1253 case TargetOpcode::G_TRUNC:
1254 case TargetOpcode::G_FPEXT:
1255 case TargetOpcode::G_FPTRUNC: {
1262 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1263 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1270 report(
"Generic extend/truncate can not operate on pointers",
MI);
1272 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1276 switch (
MI->getOpcode()) {
1278 if (DstSize <= SrcSize)
1279 report(
"Generic extend has destination type no larger than source",
MI);
1281 case TargetOpcode::G_TRUNC:
1282 case TargetOpcode::G_FPTRUNC:
1283 if (DstSize >= SrcSize)
1284 report(
"Generic truncate has destination type no smaller than source",
1290 case TargetOpcode::G_SELECT: {
1291 LLT SelTy =
MRI->getType(
MI->getOperand(0).getReg());
1292 LLT CondTy =
MRI->getType(
MI->getOperand(1).getReg());
1298 verifyVectorElementMatch(SelTy, CondTy,
MI);
1301 case TargetOpcode::G_MERGE_VALUES: {
1306 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1307 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1309 report(
"G_MERGE_VALUES cannot operate on vectors",
MI);
1311 const unsigned NumOps =
MI->getNumOperands();
1313 report(
"G_MERGE_VALUES result size is inconsistent",
MI);
1315 for (
unsigned I = 2;
I != NumOps; ++
I) {
1316 if (
MRI->getType(
MI->getOperand(
I).getReg()) != SrcTy)
1317 report(
"G_MERGE_VALUES source types do not match",
MI);
1322 case TargetOpcode::G_UNMERGE_VALUES: {
1323 unsigned NumDsts =
MI->getNumOperands() - 1;
1324 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1325 for (
unsigned i = 1; i < NumDsts; ++i) {
1326 if (
MRI->getType(
MI->getOperand(i).getReg()) != DstTy) {
1327 report(
"G_UNMERGE_VALUES destination types do not match",
MI);
1332 LLT SrcTy =
MRI->getType(
MI->getOperand(NumDsts).getReg());
1337 report(
"G_UNMERGE_VALUES source operand does not match vector "
1338 "destination operands",
1345 report(
"G_UNMERGE_VALUES vector source operand does not match scalar "
1346 "destination operands",
1351 report(
"G_UNMERGE_VALUES scalar source operand does not match scalar "
1352 "destination operands",
1358 case TargetOpcode::G_BUILD_VECTOR: {
1361 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1362 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1364 report(
"G_BUILD_VECTOR must produce a vector from scalar operands",
MI);
1369 report(
"G_BUILD_VECTOR result element type must match source type",
MI);
1372 report(
"G_BUILD_VECTOR must have an operand for each elemement",
MI);
1375 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1376 report(
"G_BUILD_VECTOR source operand types are not homogeneous",
MI);
1380 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1383 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1384 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1386 report(
"G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1389 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1390 report(
"G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1393 report(
"G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1398 case TargetOpcode::G_CONCAT_VECTORS: {
1401 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1402 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1404 report(
"G_CONCAT_VECTOR requires vector source and destination operands",
1407 if (
MI->getNumOperands() < 3)
1408 report(
"G_CONCAT_VECTOR requires at least 2 source operands",
MI);
1411 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1412 report(
"G_CONCAT_VECTOR source operand types are not homogeneous",
MI);
1415 report(
"G_CONCAT_VECTOR num dest and source elements should match",
MI);
1418 case TargetOpcode::G_ICMP:
1419 case TargetOpcode::G_FCMP: {
1420 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1421 LLT SrcTy =
MRI->getType(
MI->getOperand(2).getReg());
1425 report(
"Generic vector icmp/fcmp must preserve number of lanes",
MI);
1429 case TargetOpcode::G_EXTRACT: {
1431 if (!
SrcOp.isReg()) {
1432 report(
"extract source must be a register",
MI);
1437 if (!OffsetOp.
isImm()) {
1438 report(
"extract offset must be a constant",
MI);
1442 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1444 if (SrcSize == DstSize)
1445 report(
"extract source must be larger than result",
MI);
1447 if (DstSize + OffsetOp.
getImm() > SrcSize)
1448 report(
"extract reads past end of register",
MI);
1451 case TargetOpcode::G_INSERT: {
1453 if (!
SrcOp.isReg()) {
1454 report(
"insert source must be a register",
MI);
1459 if (!OffsetOp.
isImm()) {
1460 report(
"insert offset must be a constant",
MI);
1464 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1467 if (DstSize <= SrcSize)
1468 report(
"inserted size must be smaller than total register",
MI);
1470 if (SrcSize + OffsetOp.
getImm() > DstSize)
1471 report(
"insert writes past end of register",
MI);
1475 case TargetOpcode::G_JUMP_TABLE: {
1476 if (!
MI->getOperand(1).isJTI())
1477 report(
"G_JUMP_TABLE source operand must be a jump table index",
MI);
1478 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1480 report(
"G_JUMP_TABLE dest operand must have a pointer type",
MI);
1483 case TargetOpcode::G_BRJT: {
1484 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
1485 report(
"G_BRJT src operand 0 must be a pointer type",
MI);
1487 if (!
MI->getOperand(1).isJTI())
1488 report(
"G_BRJT src operand 1 must be a jump table index",
MI);
1490 const auto &IdxOp =
MI->getOperand(2);
1491 if (!IdxOp.isReg() ||
MRI->getType(IdxOp.getReg()).isPointer())
1492 report(
"G_BRJT src operand 2 must be a scalar reg type",
MI);
1495 case TargetOpcode::G_INTRINSIC:
1496 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1501 report(
"G_INTRINSIC first src operand must be an intrinsic ID",
MI);
1505 bool NoSideEffects =
MI->getOpcode() == TargetOpcode::G_INTRINSIC;
1507 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1509 MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
1510 bool DeclHasSideEffects = !
Attrs.getMemoryEffects().doesNotAccessMemory();
1511 if (NoSideEffects && DeclHasSideEffects) {
1512 report(
"G_INTRINSIC used with intrinsic that accesses memory",
MI);
1515 if (!NoSideEffects && !DeclHasSideEffects) {
1516 report(
"G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic",
MI);
1523 case TargetOpcode::G_SEXT_INREG: {
1524 if (!
MI->getOperand(2).isImm()) {
1525 report(
"G_SEXT_INREG expects an immediate operand #2",
MI);
1529 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1530 int64_t
Imm =
MI->getOperand(2).getImm();
1532 report(
"G_SEXT_INREG size must be >= 1",
MI);
1534 report(
"G_SEXT_INREG size must be less than source bit width",
MI);
1537 case TargetOpcode::G_SHUFFLE_VECTOR: {
1540 report(
"Incorrect mask operand type for G_SHUFFLE_VECTOR",
MI);
1544 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1545 LLT Src0Ty =
MRI->getType(
MI->getOperand(1).getReg());
1546 LLT Src1Ty =
MRI->getType(
MI->getOperand(2).getReg());
1548 if (Src0Ty != Src1Ty)
1549 report(
"Source operands must be the same type",
MI);
1552 report(
"G_SHUFFLE_VECTOR cannot change element type",
MI);
1561 if (
static_cast<int>(MaskIdxes.
size()) != DstNumElts)
1562 report(
"Wrong result type for shufflemask",
MI);
1564 for (
int Idx : MaskIdxes) {
1568 if (
Idx >= 2 * SrcNumElts)
1569 report(
"Out of bounds shuffle index",
MI);
1574 case TargetOpcode::G_DYN_STACKALLOC: {
1580 report(
"dst operand 0 must be a pointer type",
MI);
1584 if (!AllocOp.
isReg() || !
MRI->getType(AllocOp.
getReg()).isScalar()) {
1585 report(
"src operand 1 must be a scalar reg type",
MI);
1589 if (!AlignOp.
isImm()) {
1590 report(
"src operand 2 must be an immediate type",
MI);
1595 case TargetOpcode::G_MEMCPY_INLINE:
1596 case TargetOpcode::G_MEMCPY:
1597 case TargetOpcode::G_MEMMOVE: {
1599 if (MMOs.
size() != 2) {
1600 report(
"memcpy/memmove must have 2 memory operands",
MI);
1606 report(
"wrong memory operand types",
MI);
1611 report(
"inconsistent memory operand sizes",
MI);
1613 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1614 LLT SrcPtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1617 report(
"memory instruction operand must be a pointer",
MI);
1622 report(
"inconsistent store address space",
MI);
1624 report(
"inconsistent load address space",
MI);
1626 if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1627 if (!
MI->getOperand(3).isImm() || (
MI->getOperand(3).getImm() & ~1LL))
1628 report(
"'tail' flag (operand 3) must be an immediate 0 or 1",
MI);
1632 case TargetOpcode::G_BZERO:
1633 case TargetOpcode::G_MEMSET: {
1635 std::string
Name = Opc == TargetOpcode::G_MEMSET ?
"memset" :
"bzero";
1636 if (MMOs.
size() != 1) {
1637 report(
Twine(
Name,
" must have 1 memory operand"),
MI);
1642 report(
Twine(
Name,
" memory operand must be a store"),
MI);
1646 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1648 report(
Twine(
Name,
" operand must be a pointer"),
MI);
1653 report(
"inconsistent " +
Twine(
Name,
" address space"),
MI);
1655 if (!
MI->getOperand(
MI->getNumOperands() - 1).isImm() ||
1656 (
MI->getOperand(
MI->getNumOperands() - 1).getImm() & ~1LL))
1657 report(
"'tail' flag (last operand) must be an immediate 0 or 1",
MI);
1661 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1662 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1663 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1664 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1665 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1667 report(
"Vector reduction requires a scalar destination type",
MI);
1669 report(
"Sequential FADD/FMUL vector reduction requires a scalar 1st operand",
MI);
1671 report(
"Sequential FADD/FMUL vector reduction must have a vector 2nd operand",
MI);
1674 case TargetOpcode::G_VECREDUCE_FADD:
1675 case TargetOpcode::G_VECREDUCE_FMUL:
1676 case TargetOpcode::G_VECREDUCE_FMAX:
1677 case TargetOpcode::G_VECREDUCE_FMIN:
1678 case TargetOpcode::G_VECREDUCE_ADD:
1679 case TargetOpcode::G_VECREDUCE_MUL:
1680 case TargetOpcode::G_VECREDUCE_AND:
1681 case TargetOpcode::G_VECREDUCE_OR:
1682 case TargetOpcode::G_VECREDUCE_XOR:
1683 case TargetOpcode::G_VECREDUCE_SMAX:
1684 case TargetOpcode::G_VECREDUCE_SMIN:
1685 case TargetOpcode::G_VECREDUCE_UMAX:
1686 case TargetOpcode::G_VECREDUCE_UMIN: {
1687 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1689 report(
"Vector reduction requires a scalar destination type",
MI);
1693 case TargetOpcode::G_SBFX:
1694 case TargetOpcode::G_UBFX: {
1695 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1697 report(
"Bitfield extraction is not supported on vectors",
MI);
1702 case TargetOpcode::G_SHL:
1703 case TargetOpcode::G_LSHR:
1704 case TargetOpcode::G_ASHR:
1705 case TargetOpcode::G_ROTR:
1706 case TargetOpcode::G_ROTL: {
1707 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1708 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1710 report(
"Shifts and rotates require operands to be either all scalars or "
1717 case TargetOpcode::G_LLROUND:
1718 case TargetOpcode::G_LROUND: {
1719 verifyAllRegOpsScalar(*
MI, *
MRI);
1722 case TargetOpcode::G_IS_FPCLASS: {
1723 LLT DestTy =
MRI->getType(
MI->getOperand(0).getReg());
1726 report(
"Destination must be a scalar or vector of scalars",
MI);
1729 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1732 report(
"Source must be a scalar or vector of scalars",
MI);
1735 if (!verifyVectorElementMatch(DestTy, SrcTy,
MI))
1738 if (!TestMO.
isImm()) {
1739 report(
"floating-point class set (operand 2) must be an immediate",
MI);
1744 report(
"Incorrect floating-point class set (operand 2)",
MI);
1749 case TargetOpcode::G_ASSERT_ALIGN: {
1750 if (
MI->getOperand(2).getImm() < 1)
1751 report(
"alignment immediate must be >= 1",
MI);
1754 case TargetOpcode::G_CONSTANT_POOL: {
1755 if (!
MI->getOperand(1).isCPI())
1756 report(
"Src operand 1 must be a constant pool index",
MI);
1757 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
1758 report(
"Dst operand 0 must be a pointer",
MI);
1766void MachineVerifier::visitMachineInstrBefore(
const MachineInstr *
MI) {
1769 report(
"Too few operands",
MI);
1771 <<
MI->getNumOperands() <<
" given.\n";
1775 if (MF->getProperties().hasProperty(
1777 report(
"Found PHI instruction with NoPHIs property set",
MI);
1780 report(
"Found PHI instruction after non-PHI",
MI);
1781 }
else if (FirstNonPHI ==
nullptr)
1785 if (
MI->isInlineAsm())
1786 verifyInlineAsm(
MI);
1789 if (
TII->isUnspillableTerminator(
MI)) {
1790 if (!
MI->getOperand(0).isReg() || !
MI->getOperand(0).isDef())
1791 report(
"Unspillable Terminator does not define a reg",
MI);
1793 if (
Def.isVirtual() &&
1794 !MF->getProperties().hasProperty(
1796 std::distance(
MRI->use_nodbg_begin(Def),
MRI->use_nodbg_end()) > 1)
1797 report(
"Unspillable Terminator expected to have at most one use!",
MI);
1803 if (
MI->isDebugValue() &&
MI->getNumOperands() == 4)
1804 if (!
MI->getDebugLoc())
1805 report(
"Missing DebugLoc for debug instruction",
MI);
1809 if (
MI->isMetaInstruction() &&
MI->peekDebugInstrNum())
1810 report(
"Metadata instruction should not have a value tracking number",
MI);
1814 if (
Op->isLoad() && !
MI->mayLoad())
1815 report(
"Missing mayLoad flag",
MI);
1816 if (
Op->isStore() && !
MI->mayStore())
1817 report(
"Missing mayStore flag",
MI);
1824 if (
MI->isDebugOrPseudoInstr()) {
1826 report(
"Debug instruction has a slot index",
MI);
1827 }
else if (
MI->isInsideBundle()) {
1829 report(
"Instruction inside bundle has a slot index",
MI);
1832 report(
"Missing slot index",
MI);
1838 verifyPreISelGenericInstruction(
MI);
1847 switch (
MI->getOpcode()) {
1848 case TargetOpcode::COPY: {
1854 LLT DstTy =
MRI->getType(DstReg);
1855 LLT SrcTy =
MRI->getType(SrcReg);
1858 if (SrcTy != DstTy) {
1859 report(
"Copy Instruction is illegal with mismatching types",
MI);
1860 errs() <<
"Def = " << DstTy <<
", Src = " << SrcTy <<
"\n";
1871 unsigned SrcSize = 0;
1872 unsigned DstSize = 0;
1875 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
1877 SrcSize =
TRI->getRegSizeInBits(*SrcRC);
1881 SrcSize =
TRI->getRegSizeInBits(SrcReg, *
MRI);
1885 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
1887 DstSize =
TRI->getRegSizeInBits(*DstRC);
1891 DstSize =
TRI->getRegSizeInBits(DstReg, *
MRI);
1893 if (SrcSize != 0 && DstSize != 0 && SrcSize != DstSize) {
1894 if (!
DstOp.getSubReg() && !
SrcOp.getSubReg()) {
1895 report(
"Copy Instruction is illegal with mismatching sizes",
MI);
1896 errs() <<
"Def Size = " << DstSize <<
", Src Size = " << SrcSize
1902 case TargetOpcode::STATEPOINT: {
1904 if (!
MI->getOperand(SO.getIDPos()).isImm() ||
1905 !
MI->getOperand(SO.getNBytesPos()).isImm() ||
1906 !
MI->getOperand(SO.getNCallArgsPos()).isImm()) {
1907 report(
"meta operands to STATEPOINT not constant!",
MI);
1911 auto VerifyStackMapConstant = [&](
unsigned Offset) {
1912 if (
Offset >=
MI->getNumOperands()) {
1913 report(
"stack map constant to STATEPOINT is out of range!",
MI);
1916 if (!
MI->getOperand(
Offset - 1).isImm() ||
1917 MI->getOperand(
Offset - 1).getImm() != StackMaps::ConstantOp ||
1919 report(
"stack map constant to STATEPOINT not well formed!",
MI);
1921 VerifyStackMapConstant(SO.getCCIdx());
1922 VerifyStackMapConstant(SO.getFlagsIdx());
1923 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
1924 VerifyStackMapConstant(SO.getNumGCPtrIdx());
1925 VerifyStackMapConstant(SO.getNumAllocaIdx());
1926 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
1930 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
1931 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
1932 for (
unsigned Idx = 0;
Idx <
MI->getNumDefs();
Idx++) {
1935 report(
"STATEPOINT defs expected to be tied",
MI);
1938 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
1939 report(
"STATEPOINT def tied to non-gc operand",
MI);
1946 case TargetOpcode::INSERT_SUBREG: {
1947 unsigned InsertedSize;
1948 if (
unsigned SubIdx =
MI->getOperand(2).getSubReg())
1949 InsertedSize =
TRI->getSubRegIdxSize(SubIdx);
1951 InsertedSize =
TRI->getRegSizeInBits(
MI->getOperand(2).getReg(), *
MRI);
1952 unsigned SubRegSize =
TRI->getSubRegIdxSize(
MI->getOperand(3).getImm());
1953 if (SubRegSize < InsertedSize) {
1954 report(
"INSERT_SUBREG expected inserted value to have equal or lesser "
1955 "size than the subreg it was inserted into",
MI);
1959 case TargetOpcode::REG_SEQUENCE: {
1960 unsigned NumOps =
MI->getNumOperands();
1961 if (!(NumOps & 1)) {
1962 report(
"Invalid number of operands for REG_SEQUENCE",
MI);
1966 for (
unsigned I = 1;
I != NumOps;
I += 2) {
1971 report(
"Invalid register operand for REG_SEQUENCE", &RegOp,
I);
1973 if (!SubRegOp.
isImm() || SubRegOp.
getImm() == 0 ||
1974 SubRegOp.
getImm() >=
TRI->getNumSubRegIndices()) {
1975 report(
"Invalid subregister index operand for REG_SEQUENCE",
1980 Register DstReg =
MI->getOperand(0).getReg();
1982 report(
"REG_SEQUENCE does not support physical register results",
MI);
1984 if (
MI->getOperand(0).getSubReg())
1985 report(
"Invalid subreg result for REG_SEQUENCE",
MI);
1993MachineVerifier::visitMachineOperand(
const MachineOperand *MO,
unsigned MONum) {
1997 if (MCID.
getOpcode() == TargetOpcode::PATCHPOINT)
1998 NumDefs = (MONum == 0 && MO->
isReg()) ? NumDefs : 0;
2001 if (MONum < NumDefs) {
2004 report(
"Explicit definition must be a register", MO, MONum);
2006 report(
"Explicit definition marked as use", MO, MONum);
2008 report(
"Explicit definition marked as implicit", MO, MONum);
2017 report(
"Explicit operand marked as def", MO, MONum);
2019 report(
"Explicit operand marked as implicit", MO, MONum);
2025 report(
"Expected a register operand.", MO, MONum);
2029 !
TII->isPCRelRegisterOperandLegal(*MO)))
2030 report(
"Expected a non-register operand.", MO, MONum);
2037 report(
"Tied use must be a register", MO, MONum);
2039 report(
"Operand should be tied", MO, MONum);
2040 else if (
unsigned(TiedTo) !=
MI->findTiedOperandIdx(MONum))
2041 report(
"Tied def doesn't match MCInstrDesc", MO, MONum);
2044 if (!MOTied.
isReg())
2045 report(
"Tied counterpart must be a register", &MOTied, TiedTo);
2048 report(
"Tied physical registers must match.", &MOTied, TiedTo);
2051 report(
"Explicit operand should not be tied", MO, MONum);
2055 report(
"Extra explicit operand on non-variadic instruction", MO, MONum);
2062 if (
MI->isDebugInstr() && MO->
isUse()) {
2064 report(
"Register operand must be marked debug", MO, MONum);
2066 report(
"Register operand must not be marked debug", MO, MONum);
2072 if (
MRI->tracksLiveness() && !
MI->isDebugInstr())
2073 checkLiveness(MO, MONum);
2077 report(
"Undef virtual register def operands require a subregister", MO, MONum);
2081 unsigned OtherIdx =
MI->findTiedOperandIdx(MONum);
2083 if (!OtherMO.
isReg())
2084 report(
"Must be tied to a register", MO, MONum);
2086 report(
"Missing tie flags on tied operand", MO, MONum);
2087 if (
MI->findTiedOperandIdx(OtherIdx) != MONum)
2088 report(
"Inconsistent tie links", MO, MONum);
2092 report(
"Explicit def tied to explicit use without tie constraint",
2096 report(
"Explicit def should be tied to implicit use", MO, MONum);
2109 if (MF->getProperties().hasProperty(
2111 MO->
isUse() &&
MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2112 Reg !=
MI->getOperand(DefIdx).getReg())
2113 report(
"Two-address instruction operands must be identical", MO, MONum);
2118 if (
Reg.isPhysical()) {
2120 report(
"Illegal subregister index for physical register", MO, MONum);
2125 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2126 if (!DRC->contains(Reg)) {
2127 report(
"Illegal physical register for instruction", MO, MONum);
2129 <<
TRI->getRegClassName(DRC) <<
" register.\n";
2134 if (
MRI->isReserved(Reg)) {
2135 report(
"isRenamable set on reserved register", MO, MONum);
2152 report(
"Generic virtual register use cannot be undef", MO, MONum);
2159 if (isFunctionTracksDebugUserValues || !MO->
isUse() ||
2160 !
MI->isDebugValue() || !
MRI->def_empty(Reg)) {
2162 if (isFunctionSelected) {
2163 report(
"Generic virtual register invalid in a Selected function",
2169 LLT Ty =
MRI->getType(Reg);
2171 report(
"Generic virtual register must have a valid type", MO,
2180 if (!RegBank && isFunctionRegBankSelected) {
2181 report(
"Generic virtual register must have a bank in a "
2182 "RegBankSelected function",
2188 if (RegBank && Ty.
isValid() &&
2190 report(
"Register bank is too small for virtual register", MO,
2192 errs() <<
"Register bank " << RegBank->
getName() <<
" too small("
2200 report(
"Generic virtual register does not allow subregister index", MO,
2210 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2211 report(
"Virtual register does not match instruction constraint", MO,
2213 errs() <<
"Expect register class "
2214 <<
TRI->getRegClassName(
2215 TII->getRegClass(MCID, MONum,
TRI, *MF))
2216 <<
" but got nothing\n";
2224 TRI->getSubClassWithSubReg(RC, SubIdx);
2226 report(
"Invalid subregister index for virtual register", MO, MONum);
2227 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2228 <<
" does not support subreg index " << SubIdx <<
"\n";
2232 report(
"Invalid register class for subregister index", MO, MONum);
2233 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2234 <<
" does not fully support subreg index " << SubIdx <<
"\n";
2240 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2243 TRI->getLargestLegalSuperClass(RC, *MF);
2245 report(
"No largest legal super class exists.", MO, MONum);
2248 DRC =
TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2250 report(
"No matching super-reg register class.", MO, MONum);
2255 report(
"Illegal virtual register for instruction", MO, MONum);
2256 errs() <<
"Expected a " <<
TRI->getRegClassName(DRC)
2257 <<
" register, but got a " <<
TRI->getRegClassName(RC)
2272 report(
"PHI operand is not in the CFG", MO, MONum);
2283 bool loads =
MI->mayLoad();
2288 for (
auto *MMO :
MI->memoperands()) {
2290 if (PSV ==
nullptr)
continue;
2292 dyn_cast<FixedStackPseudoSourceValue>(PSV);
2293 if (
Value ==
nullptr)
continue;
2294 if (
Value->getFrameIndex() != FI)
continue;
2303 report(
"Missing fixed stack memoperand.",
MI);
2305 if (loads && !LI.
liveAt(
Idx.getRegSlot(
true))) {
2306 report(
"Instruction loads from dead spill slot", MO, MONum);
2307 errs() <<
"Live stack: " << LI <<
'\n';
2310 report(
"Instruction stores to dead spill slot", MO, MONum);
2311 errs() <<
"Live stack: " << LI <<
'\n';
2317 if (MO->
getCFIIndex() >= MF->getFrameInstructions().size())
2318 report(
"CFI instruction has invalid index", MO, MONum);
2326void MachineVerifier::checkLivenessAtUse(
const MachineOperand *MO,
2335 report(
"No live segment at use", MO, MONum);
2336 report_context_liverange(LR);
2337 report_context_vreg_regunit(VRegOrUnit);
2338 report_context(UseIdx);
2341 report(
"Live range continues after kill flag", MO, MONum);
2342 report_context_liverange(LR);
2343 report_context_vreg_regunit(VRegOrUnit);
2345 report_context_lanemask(LaneMask);
2346 report_context(UseIdx);
2350void MachineVerifier::checkLivenessAtDef(
const MachineOperand *MO,
2365 if (((SubRangeCheck || MO->
getSubReg() == 0) && VNI->def != DefIdx) ||
2367 (VNI->def != DefIdx &&
2368 (!VNI->def.isEarlyClobber() || !DefIdx.
isRegister()))) {
2369 report(
"Inconsistent valno->def", MO, MONum);
2370 report_context_liverange(LR);
2371 report_context_vreg_regunit(VRegOrUnit);
2373 report_context_lanemask(LaneMask);
2374 report_context(*VNI);
2375 report_context(DefIdx);
2378 report(
"No live segment at def", MO, MONum);
2379 report_context_liverange(LR);
2380 report_context_vreg_regunit(VRegOrUnit);
2382 report_context_lanemask(LaneMask);
2383 report_context(DefIdx);
2395 if (SubRangeCheck || MO->
getSubReg() == 0) {
2396 report(
"Live range continues after dead def flag", MO, MONum);
2397 report_context_liverange(LR);
2398 report_context_vreg_regunit(VRegOrUnit);
2400 report_context_lanemask(LaneMask);
2406void MachineVerifier::checkLiveness(
const MachineOperand *MO,
unsigned MONum) {
2409 const unsigned SubRegIdx = MO->
getSubReg();
2412 if (LiveInts &&
Reg.isVirtual()) {
2417 report(
"Live interval for subreg operand has no subranges", MO, MONum);
2419 report(
"Virtual register has no live interval", MO, MONum);
2426 addRegWithSubRegs(regsKilled, Reg);
2431 if (LiveVars &&
Reg.isVirtual() && MO->
isKill() &&
2432 !
MI->isBundledWithPred()) {
2435 report(
"Kill missing from LiveVariables", MO, MONum);
2442 if (
Reg.isPhysical() && !isReserved(Reg)) {
2445 if (
MRI->isReservedRegUnit(*Units))
2448 checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
2452 if (
Reg.isVirtual()) {
2454 checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2458 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2459 :
MRI->getMaxLaneMaskForVReg(Reg);
2462 if ((MOMask & SR.LaneMask).none())
2464 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2467 LiveInMask |= SR.LaneMask;
2470 if ((LiveInMask & MOMask).
none()) {
2471 report(
"No live subrange at use", MO, MONum);
2472 report_context(*LI);
2473 report_context(UseIdx);
2480 if (!regsLive.count(Reg)) {
2481 if (
Reg.isPhysical()) {
2483 bool Bad = !isReserved(Reg);
2488 if (regsLive.count(
SubReg)) {
2500 if (!MOP.isReg() || !MOP.isImplicit())
2503 if (!MOP.getReg().isPhysical())
2511 report(
"Using an undefined physical register", MO, MONum);
2512 }
else if (
MRI->def_empty(Reg)) {
2513 report(
"Reading virtual register without a def", MO, MONum);
2515 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2519 if (MInfo.regsKilled.count(Reg))
2520 report(
"Using a killed virtual register", MO, MONum);
2521 else if (!
MI->isPHI())
2522 MInfo.vregsLiveIn.insert(std::make_pair(Reg,
MI));
2531 addRegWithSubRegs(regsDead, Reg);
2533 addRegWithSubRegs(regsDefined, Reg);
2536 if (
MRI->isSSA() &&
Reg.isVirtual() &&
2537 std::next(
MRI->def_begin(Reg)) !=
MRI->def_end())
2538 report(
"Multiple virtual register defs in SSA form", MO, MONum);
2545 if (
Reg.isVirtual()) {
2546 checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
2550 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2551 :
MRI->getMaxLaneMaskForVReg(Reg);
2553 if ((SR.LaneMask & MOMask).none())
2555 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg,
true, SR.LaneMask);
2567void MachineVerifier::visitMachineBundleAfter(
const MachineInstr *
MI) {
2568 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2569 set_union(MInfo.regsKilled, regsKilled);
2570 set_subtract(regsLive, regsKilled); regsKilled.clear();
2572 while (!regMasks.empty()) {
2575 if (
Reg.isPhysical() &&
2577 regsDead.push_back(Reg);
2580 set_union(regsLive, regsDefined); regsDefined.clear();
2585 MBBInfoMap[
MBB].regsLiveOut = regsLive;
2590 if (!(stop > lastIndex)) {
2591 report(
"Block ends before last instruction index",
MBB);
2592 errs() <<
"Block ends at " << stop
2593 <<
" last instruction was at " << lastIndex <<
'\n';
2608 template <
typename RegSetT>
void add(
const RegSetT &FromRegSet) {
2610 filterAndAdd(FromRegSet, VRegsBuffer);
2615 template <
typename RegSetT>
2616 bool filterAndAdd(
const RegSetT &FromRegSet,
2618 unsigned SparseUniverse = Sparse.size();
2619 unsigned NewSparseUniverse = SparseUniverse;
2620 unsigned NewDenseSize =
Dense.size();
2621 size_t Begin = ToVRegs.
size();
2623 if (!
Reg.isVirtual())
2626 if (
Index < SparseUniverseMax) {
2627 if (
Index < SparseUniverse && Sparse.test(
Index))
2629 NewSparseUniverse = std::max(NewSparseUniverse,
Index + 1);
2644 Sparse.resize(NewSparseUniverse);
2645 Dense.reserve(NewDenseSize);
2646 for (
unsigned I = Begin;
I <
End; ++
I) {
2649 if (
Index < SparseUniverseMax)
2658 static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2678class FilteringVRegSet {
2685 template <
typename RegSetT>
void addToFilter(
const RegSetT &RS) {
2690 template <
typename RegSetT>
bool add(
const RegSetT &RS) {
2693 return Filter.filterAndAdd(RS, VRegs);
2698 size_t size()
const {
return VRegs.
size(); }
2705void MachineVerifier::calcRegsPassed() {
2712 FilteringVRegSet VRegs;
2713 BBInfo &
Info = MBBInfoMap[MB];
2716 VRegs.addToFilter(
Info.regsKilled);
2717 VRegs.addToFilter(
Info.regsLiveOut);
2719 const BBInfo &PredInfo = MBBInfoMap[Pred];
2720 if (!PredInfo.reachable)
2723 VRegs.add(PredInfo.regsLiveOut);
2724 VRegs.add(PredInfo.vregsPassed);
2726 Info.vregsPassed.reserve(VRegs.size());
2727 Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2734void MachineVerifier::calcRegsRequired() {
2737 for (
const auto &
MBB : *MF) {
2738 BBInfo &MInfo = MBBInfoMap[&
MBB];
2740 BBInfo &PInfo = MBBInfoMap[Pred];
2741 if (PInfo.addRequired(MInfo.vregsLiveIn))
2747 for (
unsigned i = 1, e =
MI.getNumOperands(); i != e; i += 2) {
2749 if (!
MI.getOperand(i).isReg() || !
MI.getOperand(i).readsReg())
2756 BBInfo &PInfo = MBBInfoMap[Pred];
2757 if (PInfo.addRequired(Reg))
2765 while (!todo.
empty()) {
2768 BBInfo &MInfo = MBBInfoMap[
MBB];
2772 BBInfo &SInfo = MBBInfoMap[Pred];
2773 if (SInfo.addRequired(MInfo.vregsRequired))
2782 BBInfo &MInfo = MBBInfoMap[&
MBB];
2792 report(
"Expected first PHI operand to be a register def", &MODef, 0);
2797 report(
"Unexpected flag on PHI operand", &MODef, 0);
2800 report(
"Expected first PHI operand to be a virtual register", &MODef, 0);
2802 for (
unsigned I = 1,
E = Phi.getNumOperands();
I !=
E;
I += 2) {
2805 report(
"Expected PHI operand to be a register", &MO0,
I);
2810 report(
"Unexpected flag on PHI operand", &MO0,
I);
2814 report(
"Expected PHI operand to be a basic block", &MO1,
I + 1);
2820 report(
"PHI input is not a predecessor block", &MO1,
I + 1);
2824 if (MInfo.reachable) {
2826 BBInfo &PrInfo = MBBInfoMap[&Pre];
2827 if (!MO0.
isUndef() && PrInfo.reachable &&
2828 !PrInfo.isLiveOut(MO0.
getReg()))
2829 report(
"PHI operand is not live-out from predecessor", &MO0,
I);
2834 if (MInfo.reachable) {
2836 if (!seen.
count(Pred)) {
2837 report(
"Missing PHI operand", &Phi);
2839 <<
" is a predecessor according to the CFG.\n";
2846void MachineVerifier::visitMachineFunctionAfter() {
2856 for (
const auto &
MBB : *MF) {
2857 BBInfo &MInfo = MBBInfoMap[&
MBB];
2858 for (
Register VReg : MInfo.vregsRequired)
2859 if (MInfo.regsKilled.count(VReg)) {
2860 report(
"Virtual register killed in block, but needed live out.", &
MBB);
2862 <<
" is used after the block.\n";
2867 BBInfo &MInfo = MBBInfoMap[&MF->front()];
2868 for (
Register VReg : MInfo.vregsRequired) {
2869 report(
"Virtual register defs don't dominate all uses.", MF);
2870 report_context_vreg(VReg);
2875 verifyLiveVariables();
2877 verifyLiveIntervals();
2886 if (
MRI->tracksLiveness())
2887 for (
const auto &
MBB : *MF)
2891 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
2894 BBInfo &PInfo = MBBInfoMap[Pred];
2895 if (!PInfo.regsLiveOut.count(LiveInReg)) {
2896 report(
"Live in register not found to be live out from predecessor.",
2898 errs() <<
TRI->getName(LiveInReg)
2899 <<
" not found to be live out from "
2905 for (
auto CSInfo : MF->getCallSitesInfo())
2906 if (!CSInfo.first->isCall())
2907 report(
"Call site info referencing instruction that is not call", MF);
2911 if (MF->getFunction().getSubprogram()) {
2913 for (
const auto &
MBB : *MF) {
2914 for (
const auto &
MI :
MBB) {
2915 if (
auto Num =
MI.peekDebugInstrNum()) {
2918 report(
"Instruction has a duplicated value tracking number", &
MI);
2925void MachineVerifier::verifyLiveVariables() {
2926 assert(LiveVars &&
"Don't call verifyLiveVariables without LiveVars");
2927 for (
unsigned I = 0,
E =
MRI->getNumVirtRegs();
I !=
E; ++
I) {
2930 for (
const auto &
MBB : *MF) {
2931 BBInfo &MInfo = MBBInfoMap[&
MBB];
2934 if (MInfo.vregsRequired.count(Reg)) {
2936 report(
"LiveVariables: Block missing from AliveBlocks", &
MBB);
2938 <<
" must be live through the block.\n";
2942 report(
"LiveVariables: Block should not be in AliveBlocks", &
MBB);
2944 <<
" is not needed live through the block.\n";
2951void MachineVerifier::verifyLiveIntervals() {
2952 assert(LiveInts &&
"Don't call verifyLiveIntervals without LiveInts");
2953 for (
unsigned I = 0,
E =
MRI->getNumVirtRegs();
I !=
E; ++
I) {
2957 if (
MRI->reg_nodbg_empty(Reg))
2961 report(
"Missing live interval for virtual register", MF);
2967 assert(Reg == LI.
reg() &&
"Invalid reg to interval mapping");
2968 verifyLiveInterval(LI);
2972 for (
unsigned i = 0, e =
TRI->getNumRegUnits(); i != e; ++i)
2974 verifyLiveRange(*LR, i);
2977void MachineVerifier::verifyLiveRangeValue(
const LiveRange &LR,
2986 report(
"Value not live at VNInfo def and not marked unused", MF);
2987 report_context(LR, Reg, LaneMask);
2988 report_context(*VNI);
2992 if (DefVNI != VNI) {
2993 report(
"Live segment at def has different VNInfo", MF);
2994 report_context(LR, Reg, LaneMask);
2995 report_context(*VNI);
3001 report(
"Invalid VNInfo definition index", MF);
3002 report_context(LR, Reg, LaneMask);
3003 report_context(*VNI);
3009 report(
"PHIDef VNInfo is not defined at MBB start",
MBB);
3010 report_context(LR, Reg, LaneMask);
3011 report_context(*VNI);
3019 report(
"No instruction at VNInfo def index",
MBB);
3020 report_context(LR, Reg, LaneMask);
3021 report_context(*VNI);
3026 bool hasDef =
false;
3027 bool isEarlyClobber =
false;
3029 if (!MOI->isReg() || !MOI->isDef())
3031 if (
Reg.isVirtual()) {
3032 if (MOI->getReg() != Reg)
3035 if (!MOI->getReg().isPhysical() || !
TRI->hasRegUnit(MOI->getReg(), Reg))
3038 if (LaneMask.
any() &&
3039 (
TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3042 if (MOI->isEarlyClobber())
3043 isEarlyClobber =
true;
3047 report(
"Defining instruction does not modify register",
MI);
3048 report_context(LR, Reg, LaneMask);
3049 report_context(*VNI);
3054 if (isEarlyClobber) {
3056 report(
"Early clobber def must be at an early-clobber slot",
MBB);
3057 report_context(LR, Reg, LaneMask);
3058 report_context(*VNI);
3061 report(
"Non-PHI, non-early clobber def must be at a register slot",
MBB);
3062 report_context(LR, Reg, LaneMask);
3063 report_context(*VNI);
3068void MachineVerifier::verifyLiveRangeSegment(
const LiveRange &LR,
3074 assert(VNI &&
"Live segment has no valno");
3077 report(
"Foreign valno in live segment", MF);
3078 report_context(LR, Reg, LaneMask);
3080 report_context(*VNI);
3084 report(
"Live segment valno is marked unused", MF);
3085 report_context(LR, Reg, LaneMask);
3091 report(
"Bad start of live segment, no basic block", MF);
3092 report_context(LR, Reg, LaneMask);
3098 report(
"Live segment must begin at MBB entry or valno def",
MBB);
3099 report_context(LR, Reg, LaneMask);
3106 report(
"Bad end of live segment, no basic block", MF);
3107 report_context(LR, Reg, LaneMask);
3123 report(
"Live segment doesn't end at a valid instruction", EndMBB);
3124 report_context(LR, Reg, LaneMask);
3131 report(
"Live segment ends at B slot of an instruction", EndMBB);
3132 report_context(LR, Reg, LaneMask);
3140 report(
"Live segment ending at dead slot spans instructions", EndMBB);
3141 report_context(LR, Reg, LaneMask);
3150 if (MF->getProperties().hasProperty(
3153 if (
I + 1 == LR.
end() || (
I + 1)->start != S.
end) {
3154 report(
"Live segment ending at early clobber slot must be "
3155 "redefined by an EC def in the same instruction",
3157 report_context(LR, Reg, LaneMask);
3164 if (
Reg.isVirtual()) {
3167 bool hasRead =
false;
3168 bool hasSubRegDef =
false;
3169 bool hasDeadDef =
false;
3171 if (!MOI->isReg() || MOI->getReg() != Reg)
3173 unsigned Sub = MOI->getSubReg();
3178 hasSubRegDef =
true;
3187 if (LaneMask.
any() && (LaneMask & SLM).none())
3189 if (MOI->readsReg())
3196 if (LaneMask.
none() && !hasDeadDef) {
3198 "Instruction ending live segment on dead slot has no dead flag",
3200 report_context(LR, Reg, LaneMask);
3207 if (!
MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.
any() ||
3209 report(
"Instruction ending live segment doesn't read the register",
3211 report_context(LR, Reg, LaneMask);
3231 if (LaneMask.
any()) {
3239 if (!
Reg.isVirtual() && MFI->isEHPad()) {
3240 if (&*MFI == EndMBB)
3254 if (MFI->isEHPad()) {
3268 if (!PVNI && (LaneMask.
none() || !IsPHI)) {
3271 report(
"Register not marked live out of predecessor", Pred);
3272 report_context(LR, Reg, LaneMask);
3273 report_context(*VNI);
3281 if (!IsPHI && PVNI != VNI) {
3282 report(
"Different value live out of predecessor", Pred);
3283 report_context(LR, Reg, LaneMask);
3284 errs() <<
"Valno #" << PVNI->
id <<
" live out of "
3290 if (&*MFI == EndMBB)
3299 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3302 verifyLiveRangeSegment(LR,
I, Reg, LaneMask);
3305void MachineVerifier::verifyLiveInterval(
const LiveInterval &LI) {
3308 verifyLiveRange(LI, Reg);
3313 if ((Mask & SR.LaneMask).any()) {
3314 report(
"Lane masks of sub ranges overlap in live interval", MF);
3317 if ((SR.LaneMask & ~MaxMask).any()) {
3318 report(
"Subrange lanemask is invalid", MF);
3322 report(
"Subrange must not be empty", MF);
3323 report_context(SR, LI.
reg(), SR.LaneMask);
3325 Mask |= SR.LaneMask;
3326 verifyLiveRange(SR, LI.
reg(), SR.LaneMask);
3328 report(
"A Subrange is not covered by the main range", MF);
3335 unsigned NumComp = ConEQ.Classify(LI);
3337 report(
"Multiple connected components in live interval", MF);
3339 for (
unsigned comp = 0; comp != NumComp; ++comp) {
3340 errs() << comp <<
": valnos";
3342 if (comp == ConEQ.getEqClass(
I))
3343 errs() <<
' ' <<
I->id;
3355 struct StackStateOfBB {
3356 StackStateOfBB() =
default;
3357 StackStateOfBB(
int EntryVal,
int ExitVal,
bool EntrySetup,
bool ExitSetup) :
3358 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3359 ExitIsSetup(ExitSetup) {}
3364 bool EntryIsSetup =
false;
3365 bool ExitIsSetup =
false;
3373void MachineVerifier::verifyStackFrame() {
3374 unsigned FrameSetupOpcode =
TII->getCallFrameSetupOpcode();
3375 unsigned FrameDestroyOpcode =
TII->getCallFrameDestroyOpcode();
3376 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3380 SPState.
resize(MF->getNumBlockIDs());
3387 DFI != DFE; ++DFI) {
3390 StackStateOfBB BBState;
3392 if (DFI.getPathLength() >= 2) {
3395 "DFS stack predecessor is already visited.\n");
3396 BBState.EntryValue = SPState[StackPred->
getNumber()].ExitValue;
3397 BBState.EntryIsSetup = SPState[StackPred->
getNumber()].ExitIsSetup;
3398 BBState.ExitValue = BBState.EntryValue;
3399 BBState.ExitIsSetup = BBState.EntryIsSetup;
3403 for (
const auto &
I : *
MBB) {
3404 if (
I.getOpcode() == FrameSetupOpcode) {
3405 if (BBState.ExitIsSetup)
3406 report(
"FrameSetup is after another FrameSetup", &
I);
3407 BBState.ExitValue -=
TII->getFrameTotalSize(
I);
3408 BBState.ExitIsSetup =
true;
3411 if (
I.getOpcode() == FrameDestroyOpcode) {
3412 int Size =
TII->getFrameTotalSize(
I);
3413 if (!BBState.ExitIsSetup)
3414 report(
"FrameDestroy is not after a FrameSetup", &
I);
3415 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3417 if (BBState.ExitIsSetup && AbsSPAdj !=
Size) {
3418 report(
"FrameDestroy <n> is after FrameSetup <m>", &
I);
3419 errs() <<
"FrameDestroy <" <<
Size <<
"> is after FrameSetup <"
3420 << AbsSPAdj <<
">.\n";
3422 BBState.ExitValue +=
Size;
3423 BBState.ExitIsSetup =
false;
3431 if (Reachable.
count(Pred) &&
3432 (SPState[Pred->
getNumber()].ExitValue != BBState.EntryValue ||
3433 SPState[Pred->
getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3434 report(
"The exit stack state of a predecessor is inconsistent.",
MBB);
3436 <<
" has exit state (" << SPState[Pred->
getNumber()].ExitValue
3437 <<
", " << SPState[Pred->
getNumber()].ExitIsSetup <<
"), while "
3439 << BBState.EntryValue <<
", " << BBState.EntryIsSetup <<
").\n";
3446 if (Reachable.
count(Succ) &&
3447 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3448 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3449 report(
"The entry stack state of a successor is inconsistent.",
MBB);
3451 <<
" has entry state (" << SPState[Succ->getNumber()].EntryValue
3452 <<
", " << SPState[Succ->getNumber()].EntryIsSetup <<
"), while "
3454 << BBState.ExitValue <<
", " << BBState.ExitIsSetup <<
").\n";
3460 if (BBState.ExitIsSetup)
3461 report(
"A return block ends with a FrameSetup.",
MBB);
3462 if (BBState.ExitValue)
3463 report(
"A return block ends with a nonzero stack adjustment.",
MBB);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator MBBI
static bool isLoad(int Opcode)
static bool isStore(int Opcode)
SmallVector< MachineOperand, 4 > Cond
This file implements the BitVector class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
This file defines the DenseSet and SmallDenseSet classes.
This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.
const HexagonInstrInfo * TII
A common definition of LaneBitmask for use in TableGen and CodeGen.
Implement a low-level type suitable for MachineInstr level instruction selection.
unsigned const TargetRegisterInfo * TRI
modulo schedule Modulo Schedule test pass
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
This file defines generic set operations that may be used on set's of different types,...
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
static unsigned getSize(unsigned Kind)
const fltSemantics & getSemantics() const
Represent the analysis usage information of a pass.
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
void setPreservesAll()
Set by analyses that do not transform their input at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches,...
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
bool test(unsigned Idx) const
void clear()
clear - Removes all bits from the bitvector.
iterator_range< const_set_bits_iterator > set_bits() const
size_type size() const
size - Returns the number of bits in this bitvector.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Implements a dense probed hash-table based set.
Base class for user error types.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
FunctionPass class - This class is used to implement most global optimizations.
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr unsigned getAddressSpace() const
constexpr LLT getScalarType() const
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
bool hasInterval(Register Reg) const
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Result of a LiveRange query.
bool isDeadDef() const
Return true if this instruction has a dead def.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
bool isKill() const
Return true if the live-in value is killed by this instruction.
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
This class represents the liveness of a register, stack slot, etc.
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
bool liveAt(SlotIndex index) const
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
unsigned getNumValNums() const
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
LiveInterval & getInterval(int Slot)
bool hasInterval(int Slot) const
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
This class is intended to be used as a base class for asm properties and features specific to the tar...
ExceptionHandling getExceptionHandlingType() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getOpcode() const
Return the opcode number for this descriptor.
This holds information about one operand of a machine instruction, indicating the register class for ...
bool isOptionalDef() const
Set if this operand is a optional def.
uint8_t OperandType
Information about the type of the operand.
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool isValid() const
isValid - Returns true until all the operands have been visited.
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
iterator_range< livein_iterator > liveins() const
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
succ_iterator succ_begin()
bool isIRBlockAddressTaken() const
Test whether this block is the target of an IR BlockAddress.
unsigned succ_size() const
BasicBlock * getAddressTakenIRBlock() const
Retrieves the BasicBlock which corresponds to this MachineBasicBlock.
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
pred_iterator pred_begin()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< succ_iterator > successors()
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
An AnalysisManager<MachineFunction> that also exposes IR analysis results.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isReturn(QueryType Type=AnyInBundle) const
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
A description of a memory reference used in the backend.
const PseudoSourceValue * getPseudoValue() const
uint64_t getSize() const
Return the size in bytes of the memory reference.
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isIntrinsicID() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isShuffleMask() const
unsigned getCFIIndex() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
Intrinsic::ID getIntrinsicID() const
bool isInternalRead() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
This class implements the register bank concept.
const char * getName() const
Get a user friendly name of this register bank.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SlotIndex - An opaque wrapper around machine indexes.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
VNInfo - Value Number Information.
bool isUnused() const
Returns true if this value is unused.
unsigned id
The ID number of this value.
SlotIndex def
The index of the defining instruction.
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
Iterator for intrusive lists based on ilist_node.
self_iterator getIterator()
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
const CustomOperand< const MCSubtargetInfo & > Msg[]
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
Reg
All possible values of the reg field in the ModR/M byte.
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
const_iterator end(StringRef path)
Get end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
@ SjLj
setjmp/longjmp based exceptions
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
void initializeMachineVerifierPassPass(PassRegistry &)
auto reverse(ContainerTy &&C)
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
void verifyMachineFunction(MachineFunctionAnalysisManager *, const std::string &Banner, const MachineFunction &MF)
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
static constexpr LaneBitmask getAll()
constexpr bool none() const
constexpr bool any() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
Pair of physical register and lane mask.