LLVM  14.0.0git
MachineVerifier.cpp
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1 //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Pass to verify generated machine code. The following is checked:
10 //
11 // Operand counts: All explicit operands must be present.
12 //
13 // Register classes: All physical and virtual register operands must be
14 // compatible with the register class required by the instruction descriptor.
15 //
16 // Register live intervals: Registers must be defined only once, and must be
17 // defined before use.
18 //
19 // The machine code verifier is enabled with the command-line option
20 // -verify-machineinstrs.
21 //===----------------------------------------------------------------------===//
22 
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/DenseMap.h"
25 #include "llvm/ADT/DenseSet.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SetOperations.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/StringRef.h"
33 #include "llvm/ADT/Twine.h"
52 #include "llvm/CodeGen/StackMaps.h"
57 #include "llvm/IR/BasicBlock.h"
58 #include "llvm/IR/Function.h"
59 #include "llvm/IR/InlineAsm.h"
60 #include "llvm/IR/Instructions.h"
61 #include "llvm/InitializePasses.h"
62 #include "llvm/MC/LaneBitmask.h"
63 #include "llvm/MC/MCAsmInfo.h"
64 #include "llvm/MC/MCInstrDesc.h"
65 #include "llvm/MC/MCRegisterInfo.h"
67 #include "llvm/Pass.h"
68 #include "llvm/Support/Casting.h"
74 #include <algorithm>
75 #include <cassert>
76 #include <cstddef>
77 #include <cstdint>
78 #include <iterator>
79 #include <string>
80 #include <utility>
81 
82 using namespace llvm;
83 
84 namespace {
85 
86  struct MachineVerifier {
87  MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
88 
89  unsigned verify(const MachineFunction &MF);
90 
91  Pass *const PASS;
92  const char *Banner;
93  const MachineFunction *MF;
94  const TargetMachine *TM;
95  const TargetInstrInfo *TII;
96  const TargetRegisterInfo *TRI;
97  const MachineRegisterInfo *MRI;
98 
99  unsigned foundErrors;
100 
101  // Avoid querying the MachineFunctionProperties for each operand.
102  bool isFunctionRegBankSelected;
103  bool isFunctionSelected;
104 
105  using RegVector = SmallVector<Register, 16>;
106  using RegMaskVector = SmallVector<const uint32_t *, 4>;
107  using RegSet = DenseSet<Register>;
110 
111  const MachineInstr *FirstNonPHI;
112  const MachineInstr *FirstTerminator;
113  BlockSet FunctionBlocks;
114 
115  BitVector regsReserved;
116  RegSet regsLive;
117  RegVector regsDefined, regsDead, regsKilled;
118  RegMaskVector regMasks;
119 
120  SlotIndex lastIndex;
121 
122  // Add Reg and any sub-registers to RV
123  void addRegWithSubRegs(RegVector &RV, Register Reg) {
124  RV.push_back(Reg);
125  if (Reg.isPhysical())
126  append_range(RV, TRI->subregs(Reg.asMCReg()));
127  }
128 
129  struct BBInfo {
130  // Is this MBB reachable from the MF entry point?
131  bool reachable = false;
132 
133  // Vregs that must be live in because they are used without being
134  // defined. Map value is the user. vregsLiveIn doesn't include regs
135  // that only are used by PHI nodes.
136  RegMap vregsLiveIn;
137 
138  // Regs killed in MBB. They may be defined again, and will then be in both
139  // regsKilled and regsLiveOut.
140  RegSet regsKilled;
141 
142  // Regs defined in MBB and live out. Note that vregs passing through may
143  // be live out without being mentioned here.
144  RegSet regsLiveOut;
145 
146  // Vregs that pass through MBB untouched. This set is disjoint from
147  // regsKilled and regsLiveOut.
148  RegSet vregsPassed;
149 
150  // Vregs that must pass through MBB because they are needed by a successor
151  // block. This set is disjoint from regsLiveOut.
152  RegSet vregsRequired;
153 
154  // Set versions of block's predecessor and successor lists.
155  BlockSet Preds, Succs;
156 
157  BBInfo() = default;
158 
159  // Add register to vregsRequired if it belongs there. Return true if
160  // anything changed.
161  bool addRequired(Register Reg) {
162  if (!Reg.isVirtual())
163  return false;
164  if (regsLiveOut.count(Reg))
165  return false;
166  return vregsRequired.insert(Reg).second;
167  }
168 
169  // Same for a full set.
170  bool addRequired(const RegSet &RS) {
171  bool Changed = false;
172  for (Register Reg : RS)
173  Changed |= addRequired(Reg);
174  return Changed;
175  }
176 
177  // Same for a full map.
178  bool addRequired(const RegMap &RM) {
179  bool Changed = false;
180  for (const auto &I : RM)
181  Changed |= addRequired(I.first);
182  return Changed;
183  }
184 
185  // Live-out registers are either in regsLiveOut or vregsPassed.
186  bool isLiveOut(Register Reg) const {
187  return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
188  }
189  };
190 
191  // Extra register info per MBB.
193 
194  bool isReserved(Register Reg) {
195  return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id());
196  }
197 
198  bool isAllocatable(Register Reg) const {
199  return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
200  !regsReserved.test(Reg.id());
201  }
202 
203  // Analysis information if available
204  LiveVariables *LiveVars;
205  LiveIntervals *LiveInts;
206  LiveStacks *LiveStks;
207  SlotIndexes *Indexes;
208 
209  void visitMachineFunctionBefore();
210  void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
211  void visitMachineBundleBefore(const MachineInstr *MI);
212 
213  /// Verify that all of \p MI's virtual register operands are scalars.
214  /// \returns True if all virtual register operands are scalar. False
215  /// otherwise.
216  bool verifyAllRegOpsScalar(const MachineInstr &MI,
217  const MachineRegisterInfo &MRI);
218  bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
219  void verifyPreISelGenericInstruction(const MachineInstr *MI);
220  void visitMachineInstrBefore(const MachineInstr *MI);
221  void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
222  void visitMachineBundleAfter(const MachineInstr *MI);
223  void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
224  void visitMachineFunctionAfter();
225 
226  void report(const char *msg, const MachineFunction *MF);
227  void report(const char *msg, const MachineBasicBlock *MBB);
228  void report(const char *msg, const MachineInstr *MI);
229  void report(const char *msg, const MachineOperand *MO, unsigned MONum,
230  LLT MOVRegType = LLT{});
231  void report(const Twine &Msg, const MachineInstr *MI);
232 
233  void report_context(const LiveInterval &LI) const;
234  void report_context(const LiveRange &LR, Register VRegUnit,
235  LaneBitmask LaneMask) const;
236  void report_context(const LiveRange::Segment &S) const;
237  void report_context(const VNInfo &VNI) const;
238  void report_context(SlotIndex Pos) const;
239  void report_context(MCPhysReg PhysReg) const;
240  void report_context_liverange(const LiveRange &LR) const;
241  void report_context_lanemask(LaneBitmask LaneMask) const;
242  void report_context_vreg(Register VReg) const;
243  void report_context_vreg_regunit(Register VRegOrUnit) const;
244 
245  void verifyInlineAsm(const MachineInstr *MI);
246 
247  void checkLiveness(const MachineOperand *MO, unsigned MONum);
248  void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
249  SlotIndex UseIdx, const LiveRange &LR,
250  Register VRegOrUnit,
251  LaneBitmask LaneMask = LaneBitmask::getNone());
252  void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
253  SlotIndex DefIdx, const LiveRange &LR,
254  Register VRegOrUnit, bool SubRangeCheck = false,
255  LaneBitmask LaneMask = LaneBitmask::getNone());
256 
257  void markReachable(const MachineBasicBlock *MBB);
258  void calcRegsPassed();
259  void checkPHIOps(const MachineBasicBlock &MBB);
260 
261  void calcRegsRequired();
262  void verifyLiveVariables();
263  void verifyLiveIntervals();
264  void verifyLiveInterval(const LiveInterval&);
265  void verifyLiveRangeValue(const LiveRange &, const VNInfo *, Register,
266  LaneBitmask);
267  void verifyLiveRangeSegment(const LiveRange &,
269  LaneBitmask);
270  void verifyLiveRange(const LiveRange &, Register,
271  LaneBitmask LaneMask = LaneBitmask::getNone());
272 
273  void verifyStackFrame();
274 
275  void verifySlotIndexes() const;
276  void verifyProperties(const MachineFunction &MF);
277  };
278 
279  struct MachineVerifierPass : public MachineFunctionPass {
280  static char ID; // Pass ID, replacement for typeid
281 
282  const std::string Banner;
283 
284  MachineVerifierPass(std::string banner = std::string())
285  : MachineFunctionPass(ID), Banner(std::move(banner)) {
287  }
288 
289  void getAnalysisUsage(AnalysisUsage &AU) const override {
290  AU.setPreservesAll();
292  }
293 
294  bool runOnMachineFunction(MachineFunction &MF) override {
295  // Skip functions that have known verification problems.
296  // FIXME: Remove this mechanism when all problematic passes have been
297  // fixed.
298  if (MF.getProperties().hasProperty(
300  return false;
301 
302  unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
303  if (FoundErrors)
304  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
305  return false;
306  }
307  };
308 
309 } // end anonymous namespace
310 
311 char MachineVerifierPass::ID = 0;
312 
313 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
314  "Verify generated machine code", false, false)
315 
317  return new MachineVerifierPass(Banner);
318 }
319 
321  const std::string &Banner,
322  const MachineFunction &MF) {
323  // TODO: Use MFAM after porting below analyses.
324  // LiveVariables *LiveVars;
325  // LiveIntervals *LiveInts;
326  // LiveStacks *LiveStks;
327  // SlotIndexes *Indexes;
328  unsigned FoundErrors = MachineVerifier(nullptr, Banner.c_str()).verify(MF);
329  if (FoundErrors)
330  report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
331 }
332 
333 bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
334  const {
335  MachineFunction &MF = const_cast<MachineFunction&>(*this);
336  unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
337  if (AbortOnErrors && FoundErrors)
338  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
339  return FoundErrors == 0;
340 }
341 
342 void MachineVerifier::verifySlotIndexes() const {
343  if (Indexes == nullptr)
344  return;
345 
346  // Ensure the IdxMBB list is sorted by slot indexes.
347  SlotIndex Last;
349  E = Indexes->MBBIndexEnd(); I != E; ++I) {
350  assert(!Last.isValid() || I->first > Last);
351  Last = I->first;
352  }
353 }
354 
355 void MachineVerifier::verifyProperties(const MachineFunction &MF) {
356  // If a pass has introduced virtual registers without clearing the
357  // NoVRegs property (or set it without allocating the vregs)
358  // then report an error.
359  if (MF.getProperties().hasProperty(
361  MRI->getNumVirtRegs())
362  report("Function has NoVRegs property but there are VReg operands", &MF);
363 }
364 
365 unsigned MachineVerifier::verify(const MachineFunction &MF) {
366  foundErrors = 0;
367 
368  this->MF = &MF;
369  TM = &MF.getTarget();
370  TII = MF.getSubtarget().getInstrInfo();
372  MRI = &MF.getRegInfo();
373 
374  const bool isFunctionFailedISel = MF.getProperties().hasProperty(
376 
377  // If we're mid-GlobalISel and we already triggered the fallback path then
378  // it's expected that the MIR is somewhat broken but that's ok since we'll
379  // reset it and clear the FailedISel attribute in ResetMachineFunctions.
380  if (isFunctionFailedISel)
381  return foundErrors;
382 
383  isFunctionRegBankSelected = MF.getProperties().hasProperty(
385  isFunctionSelected = MF.getProperties().hasProperty(
387 
388  LiveVars = nullptr;
389  LiveInts = nullptr;
390  LiveStks = nullptr;
391  Indexes = nullptr;
392  if (PASS) {
393  LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
394  // We don't want to verify LiveVariables if LiveIntervals is available.
395  if (!LiveInts)
396  LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
397  LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
398  Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
399  }
400 
401  verifySlotIndexes();
402 
403  verifyProperties(MF);
404 
405  visitMachineFunctionBefore();
406  for (const MachineBasicBlock &MBB : MF) {
407  visitMachineBasicBlockBefore(&MBB);
408  // Keep track of the current bundle header.
409  const MachineInstr *CurBundle = nullptr;
410  // Do we expect the next instruction to be part of the same bundle?
411  bool InBundle = false;
412 
413  for (const MachineInstr &MI : MBB.instrs()) {
414  if (MI.getParent() != &MBB) {
415  report("Bad instruction parent pointer", &MBB);
416  errs() << "Instruction: " << MI;
417  continue;
418  }
419 
420  // Check for consistent bundle flags.
421  if (InBundle && !MI.isBundledWithPred())
422  report("Missing BundledPred flag, "
423  "BundledSucc was set on predecessor",
424  &MI);
425  if (!InBundle && MI.isBundledWithPred())
426  report("BundledPred flag is set, "
427  "but BundledSucc not set on predecessor",
428  &MI);
429 
430  // Is this a bundle header?
431  if (!MI.isInsideBundle()) {
432  if (CurBundle)
433  visitMachineBundleAfter(CurBundle);
434  CurBundle = &MI;
435  visitMachineBundleBefore(CurBundle);
436  } else if (!CurBundle)
437  report("No bundle header", &MI);
438  visitMachineInstrBefore(&MI);
439  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
440  const MachineOperand &Op = MI.getOperand(I);
441  if (Op.getParent() != &MI) {
442  // Make sure to use correct addOperand / RemoveOperand / ChangeTo
443  // functions when replacing operands of a MachineInstr.
444  report("Instruction has operand with wrong parent set", &MI);
445  }
446 
447  visitMachineOperand(&Op, I);
448  }
449 
450  // Was this the last bundled instruction?
451  InBundle = MI.isBundledWithSucc();
452  }
453  if (CurBundle)
454  visitMachineBundleAfter(CurBundle);
455  if (InBundle)
456  report("BundledSucc flag set on last instruction in block", &MBB.back());
457  visitMachineBasicBlockAfter(&MBB);
458  }
459  visitMachineFunctionAfter();
460 
461  // Clean up.
462  regsLive.clear();
463  regsDefined.clear();
464  regsDead.clear();
465  regsKilled.clear();
466  regMasks.clear();
467  MBBInfoMap.clear();
468 
469  return foundErrors;
470 }
471 
472 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
473  assert(MF);
474  errs() << '\n';
475  if (!foundErrors++) {
476  if (Banner)
477  errs() << "# " << Banner << '\n';
478  if (LiveInts != nullptr)
479  LiveInts->print(errs());
480  else
481  MF->print(errs(), Indexes);
482  }
483  errs() << "*** Bad machine code: " << msg << " ***\n"
484  << "- function: " << MF->getName() << "\n";
485 }
486 
487 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
488  assert(MBB);
489  report(msg, MBB->getParent());
490  errs() << "- basic block: " << printMBBReference(*MBB) << ' '
491  << MBB->getName() << " (" << (const void *)MBB << ')';
492  if (Indexes)
493  errs() << " [" << Indexes->getMBBStartIdx(MBB)
494  << ';' << Indexes->getMBBEndIdx(MBB) << ')';
495  errs() << '\n';
496 }
497 
498 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
499  assert(MI);
500  report(msg, MI->getParent());
501  errs() << "- instruction: ";
502  if (Indexes && Indexes->hasIndex(*MI))
503  errs() << Indexes->getInstructionIndex(*MI) << '\t';
504  MI->print(errs(), /*IsStandalone=*/true);
505 }
506 
507 void MachineVerifier::report(const char *msg, const MachineOperand *MO,
508  unsigned MONum, LLT MOVRegType) {
509  assert(MO);
510  report(msg, MO->getParent());
511  errs() << "- operand " << MONum << ": ";
512  MO->print(errs(), MOVRegType, TRI);
513  errs() << "\n";
514 }
515 
516 void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
517  report(Msg.str().c_str(), MI);
518 }
519 
520 void MachineVerifier::report_context(SlotIndex Pos) const {
521  errs() << "- at: " << Pos << '\n';
522 }
523 
524 void MachineVerifier::report_context(const LiveInterval &LI) const {
525  errs() << "- interval: " << LI << '\n';
526 }
527 
528 void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
529  LaneBitmask LaneMask) const {
530  report_context_liverange(LR);
531  report_context_vreg_regunit(VRegUnit);
532  if (LaneMask.any())
533  report_context_lanemask(LaneMask);
534 }
535 
536 void MachineVerifier::report_context(const LiveRange::Segment &S) const {
537  errs() << "- segment: " << S << '\n';
538 }
539 
540 void MachineVerifier::report_context(const VNInfo &VNI) const {
541  errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
542 }
543 
544 void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
545  errs() << "- liverange: " << LR << '\n';
546 }
547 
548 void MachineVerifier::report_context(MCPhysReg PReg) const {
549  errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
550 }
551 
552 void MachineVerifier::report_context_vreg(Register VReg) const {
553  errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
554 }
555 
556 void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
557  if (Register::isVirtualRegister(VRegOrUnit)) {
558  report_context_vreg(VRegOrUnit);
559  } else {
560  errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
561  }
562 }
563 
564 void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
565  errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
566 }
567 
568 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
569  BBInfo &MInfo = MBBInfoMap[MBB];
570  if (!MInfo.reachable) {
571  MInfo.reachable = true;
572  for (const MachineBasicBlock *Succ : MBB->successors())
573  markReachable(Succ);
574  }
575 }
576 
577 void MachineVerifier::visitMachineFunctionBefore() {
578  lastIndex = SlotIndex();
579  regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
580  : TRI->getReservedRegs(*MF);
581 
582  if (!MF->empty())
583  markReachable(&MF->front());
584 
585  // Build a set of the basic blocks in the function.
586  FunctionBlocks.clear();
587  for (const auto &MBB : *MF) {
588  FunctionBlocks.insert(&MBB);
589  BBInfo &MInfo = MBBInfoMap[&MBB];
590 
591  MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
592  if (MInfo.Preds.size() != MBB.pred_size())
593  report("MBB has duplicate entries in its predecessor list.", &MBB);
594 
595  MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
596  if (MInfo.Succs.size() != MBB.succ_size())
597  report("MBB has duplicate entries in its successor list.", &MBB);
598  }
599 
600  // Check that the register use lists are sane.
601  MRI->verifyUseLists();
602 
603  if (!MF->empty())
604  verifyStackFrame();
605 }
606 
607 void
608 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
609  FirstTerminator = nullptr;
610  FirstNonPHI = nullptr;
611 
612  if (!MF->getProperties().hasProperty(
614  // If this block has allocatable physical registers live-in, check that
615  // it is an entry block or landing pad.
616  for (const auto &LI : MBB->liveins()) {
617  if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
618  MBB->getIterator() != MBB->getParent()->begin()) {
619  report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
620  report_context(LI.PhysReg);
621  }
622  }
623  }
624 
625  // Count the number of landing pad successors.
627  for (const auto *succ : MBB->successors()) {
628  if (succ->isEHPad())
629  LandingPadSuccs.insert(succ);
630  if (!FunctionBlocks.count(succ))
631  report("MBB has successor that isn't part of the function.", MBB);
632  if (!MBBInfoMap[succ].Preds.count(MBB)) {
633  report("Inconsistent CFG", MBB);
634  errs() << "MBB is not in the predecessor list of the successor "
635  << printMBBReference(*succ) << ".\n";
636  }
637  }
638 
639  // Check the predecessor list.
640  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
641  if (!FunctionBlocks.count(Pred))
642  report("MBB has predecessor that isn't part of the function.", MBB);
643  if (!MBBInfoMap[Pred].Succs.count(MBB)) {
644  report("Inconsistent CFG", MBB);
645  errs() << "MBB is not in the successor list of the predecessor "
646  << printMBBReference(*Pred) << ".\n";
647  }
648  }
649 
650  const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
651  const BasicBlock *BB = MBB->getBasicBlock();
652  const Function &F = MF->getFunction();
653  if (LandingPadSuccs.size() > 1 &&
654  !(AsmInfo &&
656  BB && isa<SwitchInst>(BB->getTerminator())) &&
657  !isScopedEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
658  report("MBB has more than one landing pad successor", MBB);
659 
660  // Call analyzeBranch. If it succeeds, there several more conditions to check.
661  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
663  if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
664  Cond)) {
665  // Ok, analyzeBranch thinks it knows what's going on with this block. Let's
666  // check whether its answers match up with reality.
667  if (!TBB && !FBB) {
668  // Block falls through to its successor.
669  if (!MBB->empty() && MBB->back().isBarrier() &&
670  !TII->isPredicated(MBB->back())) {
671  report("MBB exits via unconditional fall-through but ends with a "
672  "barrier instruction!", MBB);
673  }
674  if (!Cond.empty()) {
675  report("MBB exits via unconditional fall-through but has a condition!",
676  MBB);
677  }
678  } else if (TBB && !FBB && Cond.empty()) {
679  // Block unconditionally branches somewhere.
680  if (MBB->empty()) {
681  report("MBB exits via unconditional branch but doesn't contain "
682  "any instructions!", MBB);
683  } else if (!MBB->back().isBarrier()) {
684  report("MBB exits via unconditional branch but doesn't end with a "
685  "barrier instruction!", MBB);
686  } else if (!MBB->back().isTerminator()) {
687  report("MBB exits via unconditional branch but the branch isn't a "
688  "terminator instruction!", MBB);
689  }
690  } else if (TBB && !FBB && !Cond.empty()) {
691  // Block conditionally branches somewhere, otherwise falls through.
692  if (MBB->empty()) {
693  report("MBB exits via conditional branch/fall-through but doesn't "
694  "contain any instructions!", MBB);
695  } else if (MBB->back().isBarrier()) {
696  report("MBB exits via conditional branch/fall-through but ends with a "
697  "barrier instruction!", MBB);
698  } else if (!MBB->back().isTerminator()) {
699  report("MBB exits via conditional branch/fall-through but the branch "
700  "isn't a terminator instruction!", MBB);
701  }
702  } else if (TBB && FBB) {
703  // Block conditionally branches somewhere, otherwise branches
704  // somewhere else.
705  if (MBB->empty()) {
706  report("MBB exits via conditional branch/branch but doesn't "
707  "contain any instructions!", MBB);
708  } else if (!MBB->back().isBarrier()) {
709  report("MBB exits via conditional branch/branch but doesn't end with a "
710  "barrier instruction!", MBB);
711  } else if (!MBB->back().isTerminator()) {
712  report("MBB exits via conditional branch/branch but the branch "
713  "isn't a terminator instruction!", MBB);
714  }
715  if (Cond.empty()) {
716  report("MBB exits via conditional branch/branch but there's no "
717  "condition!", MBB);
718  }
719  } else {
720  report("analyzeBranch returned invalid data!", MBB);
721  }
722 
723  // Now check that the successors match up with the answers reported by
724  // analyzeBranch.
725  if (TBB && !MBB->isSuccessor(TBB))
726  report("MBB exits via jump or conditional branch, but its target isn't a "
727  "CFG successor!",
728  MBB);
729  if (FBB && !MBB->isSuccessor(FBB))
730  report("MBB exits via conditional branch, but its target isn't a CFG "
731  "successor!",
732  MBB);
733 
734  // There might be a fallthrough to the next block if there's either no
735  // unconditional true branch, or if there's a condition, and one of the
736  // branches is missing.
737  bool Fallthrough = !TBB || (!Cond.empty() && !FBB);
738 
739  // A conditional fallthrough must be an actual CFG successor, not
740  // unreachable. (Conversely, an unconditional fallthrough might not really
741  // be a successor, because the block might end in unreachable.)
742  if (!Cond.empty() && !FBB) {
744  if (MBBI == MF->end()) {
745  report("MBB conditionally falls through out of function!", MBB);
746  } else if (!MBB->isSuccessor(&*MBBI))
747  report("MBB exits via conditional branch/fall-through but the CFG "
748  "successors don't match the actual successors!",
749  MBB);
750  }
751 
752  // Verify that there aren't any extra un-accounted-for successors.
753  for (const MachineBasicBlock *SuccMBB : MBB->successors()) {
754  // If this successor is one of the branch targets, it's okay.
755  if (SuccMBB == TBB || SuccMBB == FBB)
756  continue;
757  // If we might have a fallthrough, and the successor is the fallthrough
758  // block, that's also ok.
759  if (Fallthrough && SuccMBB == MBB->getNextNode())
760  continue;
761  // Also accept successors which are for exception-handling or might be
762  // inlineasm_br targets.
763  if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
764  continue;
765  report("MBB has unexpected successors which are not branch targets, "
766  "fallthrough, EHPads, or inlineasm_br targets.",
767  MBB);
768  }
769  }
770 
771  regsLive.clear();
772  if (MRI->tracksLiveness()) {
773  for (const auto &LI : MBB->liveins()) {
774  if (!Register::isPhysicalRegister(LI.PhysReg)) {
775  report("MBB live-in list contains non-physical register", MBB);
776  continue;
777  }
778  for (const MCPhysReg &SubReg : TRI->subregs_inclusive(LI.PhysReg))
779  regsLive.insert(SubReg);
780  }
781  }
782 
783  const MachineFrameInfo &MFI = MF->getFrameInfo();
784  BitVector PR = MFI.getPristineRegs(*MF);
785  for (unsigned I : PR.set_bits()) {
786  for (const MCPhysReg &SubReg : TRI->subregs_inclusive(I))
787  regsLive.insert(SubReg);
788  }
789 
790  regsKilled.clear();
791  regsDefined.clear();
792 
793  if (Indexes)
794  lastIndex = Indexes->getMBBStartIdx(MBB);
795 }
796 
797 // This function gets called for all bundle headers, including normal
798 // stand-alone unbundled instructions.
799 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
800  if (Indexes && Indexes->hasIndex(*MI)) {
801  SlotIndex idx = Indexes->getInstructionIndex(*MI);
802  if (!(idx > lastIndex)) {
803  report("Instruction index out of order", MI);
804  errs() << "Last instruction was at " << lastIndex << '\n';
805  }
806  lastIndex = idx;
807  }
808 
809  // Ensure non-terminators don't follow terminators.
810  if (MI->isTerminator()) {
811  if (!FirstTerminator)
812  FirstTerminator = MI;
813  } else if (FirstTerminator) {
814  report("Non-terminator instruction after the first terminator", MI);
815  errs() << "First terminator was:\t" << *FirstTerminator;
816  }
817 }
818 
819 // The operands on an INLINEASM instruction must follow a template.
820 // Verify that the flag operands make sense.
821 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
822  // The first two operands on INLINEASM are the asm string and global flags.
823  if (MI->getNumOperands() < 2) {
824  report("Too few operands on inline asm", MI);
825  return;
826  }
827  if (!MI->getOperand(0).isSymbol())
828  report("Asm string must be an external symbol", MI);
829  if (!MI->getOperand(1).isImm())
830  report("Asm flags must be an immediate", MI);
831  // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
832  // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
833  // and Extra_IsConvergent = 32.
834  if (!isUInt<6>(MI->getOperand(1).getImm()))
835  report("Unknown asm flags", &MI->getOperand(1), 1);
836 
837  static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
838 
839  unsigned OpNo = InlineAsm::MIOp_FirstOperand;
840  unsigned NumOps;
841  for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
842  const MachineOperand &MO = MI->getOperand(OpNo);
843  // There may be implicit ops after the fixed operands.
844  if (!MO.isImm())
845  break;
846  NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
847  }
848 
849  if (OpNo > MI->getNumOperands())
850  report("Missing operands in last group", MI);
851 
852  // An optional MDNode follows the groups.
853  if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
854  ++OpNo;
855 
856  // All trailing operands must be implicit registers.
857  for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
858  const MachineOperand &MO = MI->getOperand(OpNo);
859  if (!MO.isReg() || !MO.isImplicit())
860  report("Expected implicit register after groups", &MO, OpNo);
861  }
862 }
863 
864 bool MachineVerifier::verifyAllRegOpsScalar(const MachineInstr &MI,
865  const MachineRegisterInfo &MRI) {
866  if (none_of(MI.explicit_operands(), [&MRI](const MachineOperand &Op) {
867  if (!Op.isReg())
868  return false;
869  const auto Reg = Op.getReg();
870  if (Reg.isPhysical())
871  return false;
872  return !MRI.getType(Reg).isScalar();
873  }))
874  return true;
875  report("All register operands must have scalar types", &MI);
876  return false;
877 }
878 
879 /// Check that types are consistent when two operands need to have the same
880 /// number of vector elements.
881 /// \return true if the types are valid.
882 bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
883  const MachineInstr *MI) {
884  if (Ty0.isVector() != Ty1.isVector()) {
885  report("operand types must be all-vector or all-scalar", MI);
886  // Generally we try to report as many issues as possible at once, but in
887  // this case it's not clear what should we be comparing the size of the
888  // scalar with: the size of the whole vector or its lane. Instead of
889  // making an arbitrary choice and emitting not so helpful message, let's
890  // avoid the extra noise and stop here.
891  return false;
892  }
893 
894  if (Ty0.isVector() && Ty0.getNumElements() != Ty1.getNumElements()) {
895  report("operand types must preserve number of vector elements", MI);
896  return false;
897  }
898 
899  return true;
900 }
901 
902 void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
903  if (isFunctionSelected)
904  report("Unexpected generic instruction in a Selected function", MI);
905 
906  const MCInstrDesc &MCID = MI->getDesc();
907  unsigned NumOps = MI->getNumOperands();
908 
909  // Branches must reference a basic block if they are not indirect
910  if (MI->isBranch() && !MI->isIndirectBranch()) {
911  bool HasMBB = false;
912  for (const MachineOperand &Op : MI->operands()) {
913  if (Op.isMBB()) {
914  HasMBB = true;
915  break;
916  }
917  }
918 
919  if (!HasMBB) {
920  report("Branch instruction is missing a basic block operand or "
921  "isIndirectBranch property",
922  MI);
923  }
924  }
925 
926  // Check types.
927  SmallVector<LLT, 4> Types;
928  for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
929  I != E; ++I) {
930  if (!MCID.OpInfo[I].isGenericType())
931  continue;
932  // Generic instructions specify type equality constraints between some of
933  // their operands. Make sure these are consistent.
934  size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
935  Types.resize(std::max(TypeIdx + 1, Types.size()));
936 
937  const MachineOperand *MO = &MI->getOperand(I);
938  if (!MO->isReg()) {
939  report("generic instruction must use register operands", MI);
940  continue;
941  }
942 
943  LLT OpTy = MRI->getType(MO->getReg());
944  // Don't report a type mismatch if there is no actual mismatch, only a
945  // type missing, to reduce noise:
946  if (OpTy.isValid()) {
947  // Only the first valid type for a type index will be printed: don't
948  // overwrite it later so it's always clear which type was expected:
949  if (!Types[TypeIdx].isValid())
950  Types[TypeIdx] = OpTy;
951  else if (Types[TypeIdx] != OpTy)
952  report("Type mismatch in generic instruction", MO, I, OpTy);
953  } else {
954  // Generic instructions must have types attached to their operands.
955  report("Generic instruction is missing a virtual register type", MO, I);
956  }
957  }
958 
959  // Generic opcodes must not have physical register operands.
960  for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
961  const MachineOperand *MO = &MI->getOperand(I);
962  if (MO->isReg() && Register::isPhysicalRegister(MO->getReg()))
963  report("Generic instruction cannot have physical register", MO, I);
964  }
965 
966  // Avoid out of bounds in checks below. This was already reported earlier.
967  if (MI->getNumOperands() < MCID.getNumOperands())
968  return;
969 
971  if (!TII->verifyInstruction(*MI, ErrorInfo))
972  report(ErrorInfo.data(), MI);
973 
974  // Verify properties of various specific instruction types
975  unsigned Opc = MI->getOpcode();
976  switch (Opc) {
977  case TargetOpcode::G_ASSERT_SEXT:
978  case TargetOpcode::G_ASSERT_ZEXT: {
979  std::string OpcName =
980  Opc == TargetOpcode::G_ASSERT_ZEXT ? "G_ASSERT_ZEXT" : "G_ASSERT_SEXT";
981  if (!MI->getOperand(2).isImm()) {
982  report(Twine(OpcName, " expects an immediate operand #2"), MI);
983  break;
984  }
985 
986  Register Dst = MI->getOperand(0).getReg();
987  Register Src = MI->getOperand(1).getReg();
988  LLT SrcTy = MRI->getType(Src);
989  int64_t Imm = MI->getOperand(2).getImm();
990  if (Imm <= 0) {
991  report(Twine(OpcName, " size must be >= 1"), MI);
992  break;
993  }
994 
995  if (Imm >= SrcTy.getScalarSizeInBits()) {
996  report(Twine(OpcName, " size must be less than source bit width"), MI);
997  break;
998  }
999 
1000  if (MRI->getRegBankOrNull(Src) != MRI->getRegBankOrNull(Dst)) {
1001  report(
1002  Twine(OpcName, " source and destination register banks must match"),
1003  MI);
1004  break;
1005  }
1006 
1007  if (MRI->getRegClassOrNull(Src) != MRI->getRegClassOrNull(Dst))
1008  report(
1009  Twine(OpcName, " source and destination register classes must match"),
1010  MI);
1011 
1012  break;
1013  }
1014 
1015  case TargetOpcode::G_CONSTANT:
1016  case TargetOpcode::G_FCONSTANT: {
1017  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1018  if (DstTy.isVector())
1019  report("Instruction cannot use a vector result type", MI);
1020 
1021  if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1022  if (!MI->getOperand(1).isCImm()) {
1023  report("G_CONSTANT operand must be cimm", MI);
1024  break;
1025  }
1026 
1027  const ConstantInt *CI = MI->getOperand(1).getCImm();
1028  if (CI->getBitWidth() != DstTy.getSizeInBits())
1029  report("inconsistent constant size", MI);
1030  } else {
1031  if (!MI->getOperand(1).isFPImm()) {
1032  report("G_FCONSTANT operand must be fpimm", MI);
1033  break;
1034  }
1035  const ConstantFP *CF = MI->getOperand(1).getFPImm();
1036 
1038  DstTy.getSizeInBits()) {
1039  report("inconsistent constant size", MI);
1040  }
1041  }
1042 
1043  break;
1044  }
1045  case TargetOpcode::G_LOAD:
1046  case TargetOpcode::G_STORE:
1047  case TargetOpcode::G_ZEXTLOAD:
1048  case TargetOpcode::G_SEXTLOAD: {
1049  LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1050  LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1051  if (!PtrTy.isPointer())
1052  report("Generic memory instruction must access a pointer", MI);
1053 
1054  // Generic loads and stores must have a single MachineMemOperand
1055  // describing that access.
1056  if (!MI->hasOneMemOperand()) {
1057  report("Generic instruction accessing memory must have one mem operand",
1058  MI);
1059  } else {
1060  const MachineMemOperand &MMO = **MI->memoperands_begin();
1061  if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1062  MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1063  if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
1064  report("Generic extload must have a narrower memory type", MI);
1065  } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
1066  if (MMO.getSize() > ValTy.getSizeInBytes())
1067  report("load memory size cannot exceed result size", MI);
1068  } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
1069  if (ValTy.getSizeInBytes() < MMO.getSize())
1070  report("store memory size cannot exceed value size", MI);
1071  }
1072  }
1073 
1074  break;
1075  }
1076  case TargetOpcode::G_PHI: {
1077  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1078  if (!DstTy.isValid() || !all_of(drop_begin(MI->operands()),
1079  [this, &DstTy](const MachineOperand &MO) {
1080  if (!MO.isReg())
1081  return true;
1082  LLT Ty = MRI->getType(MO.getReg());
1083  if (!Ty.isValid() || (Ty != DstTy))
1084  return false;
1085  return true;
1086  }))
1087  report("Generic Instruction G_PHI has operands with incompatible/missing "
1088  "types",
1089  MI);
1090  break;
1091  }
1092  case TargetOpcode::G_BITCAST: {
1093  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1094  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1095  if (!DstTy.isValid() || !SrcTy.isValid())
1096  break;
1097 
1098  if (SrcTy.isPointer() != DstTy.isPointer())
1099  report("bitcast cannot convert between pointers and other types", MI);
1100 
1101  if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1102  report("bitcast sizes must match", MI);
1103 
1104  if (SrcTy == DstTy)
1105  report("bitcast must change the type", MI);
1106 
1107  break;
1108  }
1109  case TargetOpcode::G_INTTOPTR:
1110  case TargetOpcode::G_PTRTOINT:
1111  case TargetOpcode::G_ADDRSPACE_CAST: {
1112  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1113  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1114  if (!DstTy.isValid() || !SrcTy.isValid())
1115  break;
1116 
1117  verifyVectorElementMatch(DstTy, SrcTy, MI);
1118 
1119  DstTy = DstTy.getScalarType();
1120  SrcTy = SrcTy.getScalarType();
1121 
1122  if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1123  if (!DstTy.isPointer())
1124  report("inttoptr result type must be a pointer", MI);
1125  if (SrcTy.isPointer())
1126  report("inttoptr source type must not be a pointer", MI);
1127  } else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1128  if (!SrcTy.isPointer())
1129  report("ptrtoint source type must be a pointer", MI);
1130  if (DstTy.isPointer())
1131  report("ptrtoint result type must not be a pointer", MI);
1132  } else {
1133  assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1134  if (!SrcTy.isPointer() || !DstTy.isPointer())
1135  report("addrspacecast types must be pointers", MI);
1136  else {
1137  if (SrcTy.getAddressSpace() == DstTy.getAddressSpace())
1138  report("addrspacecast must convert different address spaces", MI);
1139  }
1140  }
1141 
1142  break;
1143  }
1144  case TargetOpcode::G_PTR_ADD: {
1145  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1146  LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1147  LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1148  if (!DstTy.isValid() || !PtrTy.isValid() || !OffsetTy.isValid())
1149  break;
1150 
1151  if (!PtrTy.getScalarType().isPointer())
1152  report("gep first operand must be a pointer", MI);
1153 
1154  if (OffsetTy.getScalarType().isPointer())
1155  report("gep offset operand must not be a pointer", MI);
1156 
1157  // TODO: Is the offset allowed to be a scalar with a vector?
1158  break;
1159  }
1160  case TargetOpcode::G_PTRMASK: {
1161  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1162  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1163  LLT MaskTy = MRI->getType(MI->getOperand(2).getReg());
1164  if (!DstTy.isValid() || !SrcTy.isValid() || !MaskTy.isValid())
1165  break;
1166 
1167  if (!DstTy.getScalarType().isPointer())
1168  report("ptrmask result type must be a pointer", MI);
1169 
1170  if (!MaskTy.getScalarType().isScalar())
1171  report("ptrmask mask type must be an integer", MI);
1172 
1173  verifyVectorElementMatch(DstTy, MaskTy, MI);
1174  break;
1175  }
1176  case TargetOpcode::G_SEXT:
1177  case TargetOpcode::G_ZEXT:
1178  case TargetOpcode::G_ANYEXT:
1179  case TargetOpcode::G_TRUNC:
1180  case TargetOpcode::G_FPEXT:
1181  case TargetOpcode::G_FPTRUNC: {
1182  // Number of operands and presense of types is already checked (and
1183  // reported in case of any issues), so no need to report them again. As
1184  // we're trying to report as many issues as possible at once, however, the
1185  // instructions aren't guaranteed to have the right number of operands or
1186  // types attached to them at this point
1187  assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
1188  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1189  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1190  if (!DstTy.isValid() || !SrcTy.isValid())
1191  break;
1192 
1193  LLT DstElTy = DstTy.getScalarType();
1194  LLT SrcElTy = SrcTy.getScalarType();
1195  if (DstElTy.isPointer() || SrcElTy.isPointer())
1196  report("Generic extend/truncate can not operate on pointers", MI);
1197 
1198  verifyVectorElementMatch(DstTy, SrcTy, MI);
1199 
1200  unsigned DstSize = DstElTy.getSizeInBits();
1201  unsigned SrcSize = SrcElTy.getSizeInBits();
1202  switch (MI->getOpcode()) {
1203  default:
1204  if (DstSize <= SrcSize)
1205  report("Generic extend has destination type no larger than source", MI);
1206  break;
1207  case TargetOpcode::G_TRUNC:
1208  case TargetOpcode::G_FPTRUNC:
1209  if (DstSize >= SrcSize)
1210  report("Generic truncate has destination type no smaller than source",
1211  MI);
1212  break;
1213  }
1214  break;
1215  }
1216  case TargetOpcode::G_SELECT: {
1217  LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1218  LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1219  if (!SelTy.isValid() || !CondTy.isValid())
1220  break;
1221 
1222  // Scalar condition select on a vector is valid.
1223  if (CondTy.isVector())
1224  verifyVectorElementMatch(SelTy, CondTy, MI);
1225  break;
1226  }
1227  case TargetOpcode::G_MERGE_VALUES: {
1228  // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1229  // e.g. s2N = MERGE sN, sN
1230  // Merging multiple scalars into a vector is not allowed, should use
1231  // G_BUILD_VECTOR for that.
1232  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1233  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1234  if (DstTy.isVector() || SrcTy.isVector())
1235  report("G_MERGE_VALUES cannot operate on vectors", MI);
1236 
1237  const unsigned NumOps = MI->getNumOperands();
1238  if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
1239  report("G_MERGE_VALUES result size is inconsistent", MI);
1240 
1241  for (unsigned I = 2; I != NumOps; ++I) {
1242  if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1243  report("G_MERGE_VALUES source types do not match", MI);
1244  }
1245 
1246  break;
1247  }
1248  case TargetOpcode::G_UNMERGE_VALUES: {
1249  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1250  LLT SrcTy = MRI->getType(MI->getOperand(MI->getNumOperands()-1).getReg());
1251  // For now G_UNMERGE can split vectors.
1252  for (unsigned i = 0; i < MI->getNumOperands()-1; ++i) {
1253  if (MRI->getType(MI->getOperand(i).getReg()) != DstTy)
1254  report("G_UNMERGE_VALUES destination types do not match", MI);
1255  }
1256  if (SrcTy.getSizeInBits() !=
1257  (DstTy.getSizeInBits() * (MI->getNumOperands() - 1))) {
1258  report("G_UNMERGE_VALUES source operand does not cover dest operands",
1259  MI);
1260  }
1261  break;
1262  }
1263  case TargetOpcode::G_BUILD_VECTOR: {
1264  // Source types must be scalars, dest type a vector. Total size of scalars
1265  // must match the dest vector size.
1266  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1267  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1268  if (!DstTy.isVector() || SrcEltTy.isVector()) {
1269  report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
1270  break;
1271  }
1272 
1273  if (DstTy.getElementType() != SrcEltTy)
1274  report("G_BUILD_VECTOR result element type must match source type", MI);
1275 
1276  if (DstTy.getNumElements() != MI->getNumOperands() - 1)
1277  report("G_BUILD_VECTOR must have an operand for each elemement", MI);
1278 
1279  for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1280  if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1281  report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
1282 
1283  break;
1284  }
1285  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1286  // Source types must be scalars, dest type a vector. Scalar types must be
1287  // larger than the dest vector elt type, as this is a truncating operation.
1288  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1289  LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1290  if (!DstTy.isVector() || SrcEltTy.isVector())
1291  report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1292  MI);
1293  for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1294  if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1295  report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1296  MI);
1297  if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
1298  report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1299  "dest elt type",
1300  MI);
1301  break;
1302  }
1303  case TargetOpcode::G_CONCAT_VECTORS: {
1304  // Source types should be vectors, and total size should match the dest
1305  // vector size.
1306  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1307  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1308  if (!DstTy.isVector() || !SrcTy.isVector())
1309  report("G_CONCAT_VECTOR requires vector source and destination operands",
1310  MI);
1311 
1312  if (MI->getNumOperands() < 3)
1313  report("G_CONCAT_VECTOR requires at least 2 source operands", MI);
1314 
1315  for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1316  if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1317  report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
1318  if (DstTy.getNumElements() !=
1319  SrcTy.getNumElements() * (MI->getNumOperands() - 1))
1320  report("G_CONCAT_VECTOR num dest and source elements should match", MI);
1321  break;
1322  }
1323  case TargetOpcode::G_ICMP:
1324  case TargetOpcode::G_FCMP: {
1325  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1326  LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1327 
1328  if ((DstTy.isVector() != SrcTy.isVector()) ||
1329  (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements()))
1330  report("Generic vector icmp/fcmp must preserve number of lanes", MI);
1331 
1332  break;
1333  }
1334  case TargetOpcode::G_EXTRACT: {
1335  const MachineOperand &SrcOp = MI->getOperand(1);
1336  if (!SrcOp.isReg()) {
1337  report("extract source must be a register", MI);
1338  break;
1339  }
1340 
1341  const MachineOperand &OffsetOp = MI->getOperand(2);
1342  if (!OffsetOp.isImm()) {
1343  report("extract offset must be a constant", MI);
1344  break;
1345  }
1346 
1347  unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1348  unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1349  if (SrcSize == DstSize)
1350  report("extract source must be larger than result", MI);
1351 
1352  if (DstSize + OffsetOp.getImm() > SrcSize)
1353  report("extract reads past end of register", MI);
1354  break;
1355  }
1356  case TargetOpcode::G_INSERT: {
1357  const MachineOperand &SrcOp = MI->getOperand(2);
1358  if (!SrcOp.isReg()) {
1359  report("insert source must be a register", MI);
1360  break;
1361  }
1362 
1363  const MachineOperand &OffsetOp = MI->getOperand(3);
1364  if (!OffsetOp.isImm()) {
1365  report("insert offset must be a constant", MI);
1366  break;
1367  }
1368 
1369  unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1370  unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1371 
1372  if (DstSize <= SrcSize)
1373  report("inserted size must be smaller than total register", MI);
1374 
1375  if (SrcSize + OffsetOp.getImm() > DstSize)
1376  report("insert writes past end of register", MI);
1377 
1378  break;
1379  }
1380  case TargetOpcode::G_JUMP_TABLE: {
1381  if (!MI->getOperand(1).isJTI())
1382  report("G_JUMP_TABLE source operand must be a jump table index", MI);
1383  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1384  if (!DstTy.isPointer())
1385  report("G_JUMP_TABLE dest operand must have a pointer type", MI);
1386  break;
1387  }
1388  case TargetOpcode::G_BRJT: {
1389  if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1390  report("G_BRJT src operand 0 must be a pointer type", MI);
1391 
1392  if (!MI->getOperand(1).isJTI())
1393  report("G_BRJT src operand 1 must be a jump table index", MI);
1394 
1395  const auto &IdxOp = MI->getOperand(2);
1396  if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1397  report("G_BRJT src operand 2 must be a scalar reg type", MI);
1398  break;
1399  }
1400  case TargetOpcode::G_INTRINSIC:
1401  case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1402  // TODO: Should verify number of def and use operands, but the current
1403  // interface requires passing in IR types for mangling.
1404  const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1405  if (!IntrIDOp.isIntrinsicID()) {
1406  report("G_INTRINSIC first src operand must be an intrinsic ID", MI);
1407  break;
1408  }
1409 
1410  bool NoSideEffects = MI->getOpcode() == TargetOpcode::G_INTRINSIC;
1411  unsigned IntrID = IntrIDOp.getIntrinsicID();
1412  if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1414  = Intrinsic::getAttributes(MF->getFunction().getContext(),
1415  static_cast<Intrinsic::ID>(IntrID));
1416  bool DeclHasSideEffects = !Attrs.hasFnAttr(Attribute::ReadNone);
1417  if (NoSideEffects && DeclHasSideEffects) {
1418  report("G_INTRINSIC used with intrinsic that accesses memory", MI);
1419  break;
1420  }
1421  if (!NoSideEffects && !DeclHasSideEffects) {
1422  report("G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic", MI);
1423  break;
1424  }
1425  }
1426 
1427  break;
1428  }
1429  case TargetOpcode::G_SEXT_INREG: {
1430  if (!MI->getOperand(2).isImm()) {
1431  report("G_SEXT_INREG expects an immediate operand #2", MI);
1432  break;
1433  }
1434 
1435  LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1436  int64_t Imm = MI->getOperand(2).getImm();
1437  if (Imm <= 0)
1438  report("G_SEXT_INREG size must be >= 1", MI);
1439  if (Imm >= SrcTy.getScalarSizeInBits())
1440  report("G_SEXT_INREG size must be less than source bit width", MI);
1441  break;
1442  }
1443  case TargetOpcode::G_SHUFFLE_VECTOR: {
1444  const MachineOperand &MaskOp = MI->getOperand(3);
1445  if (!MaskOp.isShuffleMask()) {
1446  report("Incorrect mask operand type for G_SHUFFLE_VECTOR", MI);
1447  break;
1448  }
1449 
1450  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1451  LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
1452  LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
1453 
1454  if (Src0Ty != Src1Ty)
1455  report("Source operands must be the same type", MI);
1456 
1457  if (Src0Ty.getScalarType() != DstTy.getScalarType())
1458  report("G_SHUFFLE_VECTOR cannot change element type", MI);
1459 
1460  // Don't check that all operands are vector because scalars are used in
1461  // place of 1 element vectors.
1462  int SrcNumElts = Src0Ty.isVector() ? Src0Ty.getNumElements() : 1;
1463  int DstNumElts = DstTy.isVector() ? DstTy.getNumElements() : 1;
1464 
1465  ArrayRef<int> MaskIdxes = MaskOp.getShuffleMask();
1466 
1467  if (static_cast<int>(MaskIdxes.size()) != DstNumElts)
1468  report("Wrong result type for shufflemask", MI);
1469 
1470  for (int Idx : MaskIdxes) {
1471  if (Idx < 0)
1472  continue;
1473 
1474  if (Idx >= 2 * SrcNumElts)
1475  report("Out of bounds shuffle index", MI);
1476  }
1477 
1478  break;
1479  }
1480  case TargetOpcode::G_DYN_STACKALLOC: {
1481  const MachineOperand &DstOp = MI->getOperand(0);
1482  const MachineOperand &AllocOp = MI->getOperand(1);
1483  const MachineOperand &AlignOp = MI->getOperand(2);
1484 
1485  if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
1486  report("dst operand 0 must be a pointer type", MI);
1487  break;
1488  }
1489 
1490  if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) {
1491  report("src operand 1 must be a scalar reg type", MI);
1492  break;
1493  }
1494 
1495  if (!AlignOp.isImm()) {
1496  report("src operand 2 must be an immediate type", MI);
1497  break;
1498  }
1499  break;
1500  }
1501  case TargetOpcode::G_MEMCPY_INLINE:
1502  case TargetOpcode::G_MEMCPY:
1503  case TargetOpcode::G_MEMMOVE: {
1504  ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1505  if (MMOs.size() != 2) {
1506  report("memcpy/memmove must have 2 memory operands", MI);
1507  break;
1508  }
1509 
1510  if ((!MMOs[0]->isStore() || MMOs[0]->isLoad()) ||
1511  (MMOs[1]->isStore() || !MMOs[1]->isLoad())) {
1512  report("wrong memory operand types", MI);
1513  break;
1514  }
1515 
1516  if (MMOs[0]->getSize() != MMOs[1]->getSize())
1517  report("inconsistent memory operand sizes", MI);
1518 
1519  LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1520  LLT SrcPtrTy = MRI->getType(MI->getOperand(1).getReg());
1521 
1522  if (!DstPtrTy.isPointer() || !SrcPtrTy.isPointer()) {
1523  report("memory instruction operand must be a pointer", MI);
1524  break;
1525  }
1526 
1527  if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1528  report("inconsistent store address space", MI);
1529  if (SrcPtrTy.getAddressSpace() != MMOs[1]->getAddrSpace())
1530  report("inconsistent load address space", MI);
1531 
1532  if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1533  if (!MI->getOperand(3).isImm() || (MI->getOperand(3).getImm() & ~1LL))
1534  report("'tail' flag (operand 3) must be an immediate 0 or 1", MI);
1535 
1536  break;
1537  }
1538  case TargetOpcode::G_BZERO:
1539  case TargetOpcode::G_MEMSET: {
1540  ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1541  std::string Name = Opc == TargetOpcode::G_MEMSET ? "memset" : "bzero";
1542  if (MMOs.size() != 1) {
1543  report(Twine(Name, " must have 1 memory operand"), MI);
1544  break;
1545  }
1546 
1547  if ((!MMOs[0]->isStore() || MMOs[0]->isLoad())) {
1548  report(Twine(Name, " memory operand must be a store"), MI);
1549  break;
1550  }
1551 
1552  LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1553  if (!DstPtrTy.isPointer()) {
1554  report(Twine(Name, " operand must be a pointer"), MI);
1555  break;
1556  }
1557 
1558  if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1559  report("inconsistent " + Twine(Name, " address space"), MI);
1560 
1561  if (!MI->getOperand(MI->getNumOperands() - 1).isImm() ||
1562  (MI->getOperand(MI->getNumOperands() - 1).getImm() & ~1LL))
1563  report("'tail' flag (last operand) must be an immediate 0 or 1", MI);
1564 
1565  break;
1566  }
1567  case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1568  case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1569  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1570  LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1571  LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1572  if (!DstTy.isScalar())
1573  report("Vector reduction requires a scalar destination type", MI);
1574  if (!Src1Ty.isScalar())
1575  report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI);
1576  if (!Src2Ty.isVector())
1577  report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI);
1578  break;
1579  }
1580  case TargetOpcode::G_VECREDUCE_FADD:
1581  case TargetOpcode::G_VECREDUCE_FMUL:
1582  case TargetOpcode::G_VECREDUCE_FMAX:
1583  case TargetOpcode::G_VECREDUCE_FMIN:
1584  case TargetOpcode::G_VECREDUCE_ADD:
1585  case TargetOpcode::G_VECREDUCE_MUL:
1586  case TargetOpcode::G_VECREDUCE_AND:
1587  case TargetOpcode::G_VECREDUCE_OR:
1588  case TargetOpcode::G_VECREDUCE_XOR:
1589  case TargetOpcode::G_VECREDUCE_SMAX:
1590  case TargetOpcode::G_VECREDUCE_SMIN:
1591  case TargetOpcode::G_VECREDUCE_UMAX:
1592  case TargetOpcode::G_VECREDUCE_UMIN: {
1593  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1594  if (!DstTy.isScalar())
1595  report("Vector reduction requires a scalar destination type", MI);
1596  break;
1597  }
1598 
1599  case TargetOpcode::G_SBFX:
1600  case TargetOpcode::G_UBFX: {
1601  LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1602  if (DstTy.isVector()) {
1603  report("Bitfield extraction is not supported on vectors", MI);
1604  break;
1605  }
1606  break;
1607  }
1608  case TargetOpcode::G_ROTR:
1609  case TargetOpcode::G_ROTL: {
1610  LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1611  LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1612  if (Src1Ty.isVector() != Src2Ty.isVector()) {
1613  report("Rotate requires operands to be either all scalars or all vectors",
1614  MI);
1615  break;
1616  }
1617  break;
1618  }
1619  case TargetOpcode::G_LLROUND:
1620  case TargetOpcode::G_LROUND: {
1621  verifyAllRegOpsScalar(*MI, *MRI);
1622  break;
1623  }
1624  default:
1625  break;
1626  }
1627 }
1628 
1629 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
1630  const MCInstrDesc &MCID = MI->getDesc();
1631  if (MI->getNumOperands() < MCID.getNumOperands()) {
1632  report("Too few operands", MI);
1633  errs() << MCID.getNumOperands() << " operands expected, but "
1634  << MI->getNumOperands() << " given.\n";
1635  }
1636 
1637  if (MI->isPHI()) {
1638  if (MF->getProperties().hasProperty(
1640  report("Found PHI instruction with NoPHIs property set", MI);
1641 
1642  if (FirstNonPHI)
1643  report("Found PHI instruction after non-PHI", MI);
1644  } else if (FirstNonPHI == nullptr)
1645  FirstNonPHI = MI;
1646 
1647  // Check the tied operands.
1648  if (MI->isInlineAsm())
1649  verifyInlineAsm(MI);
1650 
1651  // Check that unspillable terminators define a reg and have at most one use.
1652  if (TII->isUnspillableTerminator(MI)) {
1653  if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
1654  report("Unspillable Terminator does not define a reg", MI);
1655  Register Def = MI->getOperand(0).getReg();
1656  if (Def.isVirtual() &&
1657  !MF->getProperties().hasProperty(
1659  std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1)
1660  report("Unspillable Terminator expected to have at most one use!", MI);
1661  }
1662 
1663  // A fully-formed DBG_VALUE must have a location. Ignore partially formed
1664  // DBG_VALUEs: these are convenient to use in tests, but should never get
1665  // generated.
1666  if (MI->isDebugValue() && MI->getNumOperands() == 4)
1667  if (!MI->getDebugLoc())
1668  report("Missing DebugLoc for debug instruction", MI);
1669 
1670  // Meta instructions should never be the subject of debug value tracking,
1671  // they don't create a value in the output program at all.
1672  if (MI->isMetaInstruction() && MI->peekDebugInstrNum())
1673  report("Metadata instruction should not have a value tracking number", MI);
1674 
1675  // Check the MachineMemOperands for basic consistency.
1676  for (MachineMemOperand *Op : MI->memoperands()) {
1677  if (Op->isLoad() && !MI->mayLoad())
1678  report("Missing mayLoad flag", MI);
1679  if (Op->isStore() && !MI->mayStore())
1680  report("Missing mayStore flag", MI);
1681  }
1682 
1683  // Debug values must not have a slot index.
1684  // Other instructions must have one, unless they are inside a bundle.
1685  if (LiveInts) {
1686  bool mapped = !LiveInts->isNotInMIMap(*MI);
1687  if (MI->isDebugOrPseudoInstr()) {
1688  if (mapped)
1689  report("Debug instruction has a slot index", MI);
1690  } else if (MI->isInsideBundle()) {
1691  if (mapped)
1692  report("Instruction inside bundle has a slot index", MI);
1693  } else {
1694  if (!mapped)
1695  report("Missing slot index", MI);
1696  }
1697  }
1698 
1699  unsigned Opc = MCID.getOpcode();
1701  verifyPreISelGenericInstruction(MI);
1702  return;
1703  }
1704 
1706  if (!TII->verifyInstruction(*MI, ErrorInfo))
1707  report(ErrorInfo.data(), MI);
1708 
1709  // Verify properties of various specific instruction types
1710  switch (MI->getOpcode()) {
1711  case TargetOpcode::COPY: {
1712  const MachineOperand &DstOp = MI->getOperand(0);
1713  const MachineOperand &SrcOp = MI->getOperand(1);
1714  const Register SrcReg = SrcOp.getReg();
1715  const Register DstReg = DstOp.getReg();
1716 
1717  LLT DstTy = MRI->getType(DstReg);
1718  LLT SrcTy = MRI->getType(SrcReg);
1719  if (SrcTy.isValid() && DstTy.isValid()) {
1720  // If both types are valid, check that the types are the same.
1721  if (SrcTy != DstTy) {
1722  report("Copy Instruction is illegal with mismatching types", MI);
1723  errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
1724  }
1725 
1726  break;
1727  }
1728 
1729  if (!SrcTy.isValid() && !DstTy.isValid())
1730  break;
1731 
1732  // If we have only one valid type, this is likely a copy between a virtual
1733  // and physical register.
1734  unsigned SrcSize = 0;
1735  unsigned DstSize = 0;
1736  if (SrcReg.isPhysical() && DstTy.isValid()) {
1737  const TargetRegisterClass *SrcRC =
1738  TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
1739  if (SrcRC)
1740  SrcSize = TRI->getRegSizeInBits(*SrcRC);
1741  }
1742 
1743  if (SrcSize == 0)
1744  SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
1745 
1746  if (DstReg.isPhysical() && SrcTy.isValid()) {
1747  const TargetRegisterClass *DstRC =
1748  TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
1749  if (DstRC)
1750  DstSize = TRI->getRegSizeInBits(*DstRC);
1751  }
1752 
1753  if (DstSize == 0)
1754  DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
1755 
1756  if (SrcSize != 0 && DstSize != 0 && SrcSize != DstSize) {
1757  if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
1758  report("Copy Instruction is illegal with mismatching sizes", MI);
1759  errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
1760  << "\n";
1761  }
1762  }
1763  break;
1764  }
1765  case TargetOpcode::STATEPOINT: {
1766  StatepointOpers SO(MI);
1767  if (!MI->getOperand(SO.getIDPos()).isImm() ||
1768  !MI->getOperand(SO.getNBytesPos()).isImm() ||
1769  !MI->getOperand(SO.getNCallArgsPos()).isImm()) {
1770  report("meta operands to STATEPOINT not constant!", MI);
1771  break;
1772  }
1773 
1774  auto VerifyStackMapConstant = [&](unsigned Offset) {
1775  if (Offset >= MI->getNumOperands()) {
1776  report("stack map constant to STATEPOINT is out of range!", MI);
1777  return;
1778  }
1779  if (!MI->getOperand(Offset - 1).isImm() ||
1780  MI->getOperand(Offset - 1).getImm() != StackMaps::ConstantOp ||
1781  !MI->getOperand(Offset).isImm())
1782  report("stack map constant to STATEPOINT not well formed!", MI);
1783  };
1784  VerifyStackMapConstant(SO.getCCIdx());
1785  VerifyStackMapConstant(SO.getFlagsIdx());
1786  VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
1787  VerifyStackMapConstant(SO.getNumGCPtrIdx());
1788  VerifyStackMapConstant(SO.getNumAllocaIdx());
1789  VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
1790 
1791  // Verify that all explicit statepoint defs are tied to gc operands as
1792  // they are expected to be a relocation of gc operands.
1793  unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
1794  unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
1795  for (unsigned Idx = 0; Idx < MI->getNumDefs(); Idx++) {
1796  unsigned UseOpIdx;
1797  if (!MI->isRegTiedToUseOperand(Idx, &UseOpIdx)) {
1798  report("STATEPOINT defs expected to be tied", MI);
1799  break;
1800  }
1801  if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
1802  report("STATEPOINT def tied to non-gc operand", MI);
1803  break;
1804  }
1805  }
1806 
1807  // TODO: verify we have properly encoded deopt arguments
1808  } break;
1809  case TargetOpcode::INSERT_SUBREG: {
1810  unsigned InsertedSize;
1811  if (unsigned SubIdx = MI->getOperand(2).getSubReg())
1812  InsertedSize = TRI->getSubRegIdxSize(SubIdx);
1813  else
1814  InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
1815  unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
1816  if (SubRegSize < InsertedSize) {
1817  report("INSERT_SUBREG expected inserted value to have equal or lesser "
1818  "size than the subreg it was inserted into", MI);
1819  break;
1820  }
1821  } break;
1822  }
1823 }
1824 
1825 void
1826 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
1827  const MachineInstr *MI = MO->getParent();
1828  const MCInstrDesc &MCID = MI->getDesc();
1829  unsigned NumDefs = MCID.getNumDefs();
1830  if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
1831  NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
1832 
1833  // The first MCID.NumDefs operands must be explicit register defines
1834  if (MONum < NumDefs) {
1835  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1836  if (!MO->isReg())
1837  report("Explicit definition must be a register", MO, MONum);
1838  else if (!MO->isDef() && !MCOI.isOptionalDef())
1839  report("Explicit definition marked as use", MO, MONum);
1840  else if (MO->isImplicit())
1841  report("Explicit definition marked as implicit", MO, MONum);
1842  } else if (MONum < MCID.getNumOperands()) {
1843  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1844  // Don't check if it's the last operand in a variadic instruction. See,
1845  // e.g., LDM_RET in the arm back end. Check non-variadic operands only.
1846  bool IsOptional = MI->isVariadic() && MONum == MCID.getNumOperands() - 1;
1847  if (!IsOptional) {
1848  if (MO->isReg()) {
1849  if (MO->isDef() && !MCOI.isOptionalDef() && !MCID.variadicOpsAreDefs())
1850  report("Explicit operand marked as def", MO, MONum);
1851  if (MO->isImplicit())
1852  report("Explicit operand marked as implicit", MO, MONum);
1853  }
1854 
1855  // Check that an instruction has register operands only as expected.
1856  if (MCOI.OperandType == MCOI::OPERAND_REGISTER &&
1857  !MO->isReg() && !MO->isFI())
1858  report("Expected a register operand.", MO, MONum);
1859  if (MO->isReg()) {
1860  if (MCOI.OperandType == MCOI::OPERAND_IMMEDIATE ||
1861  (MCOI.OperandType == MCOI::OPERAND_PCREL &&
1862  !TII->isPCRelRegisterOperandLegal(*MO)))
1863  report("Expected a non-register operand.", MO, MONum);
1864  }
1865  }
1866 
1867  int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
1868  if (TiedTo != -1) {
1869  if (!MO->isReg())
1870  report("Tied use must be a register", MO, MONum);
1871  else if (!MO->isTied())
1872  report("Operand should be tied", MO, MONum);
1873  else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
1874  report("Tied def doesn't match MCInstrDesc", MO, MONum);
1875  else if (Register::isPhysicalRegister(MO->getReg())) {
1876  const MachineOperand &MOTied = MI->getOperand(TiedTo);
1877  if (!MOTied.isReg())
1878  report("Tied counterpart must be a register", &MOTied, TiedTo);
1879  else if (Register::isPhysicalRegister(MOTied.getReg()) &&
1880  MO->getReg() != MOTied.getReg())
1881  report("Tied physical registers must match.", &MOTied, TiedTo);
1882  }
1883  } else if (MO->isReg() && MO->isTied())
1884  report("Explicit operand should not be tied", MO, MONum);
1885  } else {
1886  // ARM adds %reg0 operands to indicate predicates. We'll allow that.
1887  if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
1888  report("Extra explicit operand on non-variadic instruction", MO, MONum);
1889  }
1890 
1891  switch (MO->getType()) {
1893  // Verify debug flag on debug instructions. Check this first because reg0
1894  // indicates an undefined debug value.
1895  if (MI->isDebugInstr() && MO->isUse()) {
1896  if (!MO->isDebug())
1897  report("Register operand must be marked debug", MO, MONum);
1898  } else if (MO->isDebug()) {
1899  report("Register operand must not be marked debug", MO, MONum);
1900  }
1901 
1902  const Register Reg = MO->getReg();
1903  if (!Reg)
1904  return;
1905  if (MRI->tracksLiveness() && !MI->isDebugValue())
1906  checkLiveness(MO, MONum);
1907 
1908  // Verify the consistency of tied operands.
1909  if (MO->isTied()) {
1910  unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
1911  const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
1912  if (!OtherMO.isReg())
1913  report("Must be tied to a register", MO, MONum);
1914  if (!OtherMO.isTied())
1915  report("Missing tie flags on tied operand", MO, MONum);
1916  if (MI->findTiedOperandIdx(OtherIdx) != MONum)
1917  report("Inconsistent tie links", MO, MONum);
1918  if (MONum < MCID.getNumDefs()) {
1919  if (OtherIdx < MCID.getNumOperands()) {
1920  if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
1921  report("Explicit def tied to explicit use without tie constraint",
1922  MO, MONum);
1923  } else {
1924  if (!OtherMO.isImplicit())
1925  report("Explicit def should be tied to implicit use", MO, MONum);
1926  }
1927  }
1928  }
1929 
1930  // Verify two-address constraints after the twoaddressinstruction pass.
1931  // Both twoaddressinstruction pass and phi-node-elimination pass call
1932  // MRI->leaveSSA() to set MF as NoSSA, we should do the verification after
1933  // twoaddressinstruction pass not after phi-node-elimination pass. So we
1934  // shouldn't use the NoSSA as the condition, we should based on
1935  // TiedOpsRewritten property to verify two-address constraints, this
1936  // property will be set in twoaddressinstruction pass.
1937  unsigned DefIdx;
1938  if (MF->getProperties().hasProperty(
1940  MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
1941  Reg != MI->getOperand(DefIdx).getReg())
1942  report("Two-address instruction operands must be identical", MO, MONum);
1943 
1944  // Check register classes.
1945  unsigned SubIdx = MO->getSubReg();
1946 
1948  if (SubIdx) {
1949  report("Illegal subregister index for physical register", MO, MONum);
1950  return;
1951  }
1952  if (MONum < MCID.getNumOperands()) {
1953  if (const TargetRegisterClass *DRC =
1954  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1955  if (!DRC->contains(Reg)) {
1956  report("Illegal physical register for instruction", MO, MONum);
1957  errs() << printReg(Reg, TRI) << " is not a "
1958  << TRI->getRegClassName(DRC) << " register.\n";
1959  }
1960  }
1961  }
1962  if (MO->isRenamable()) {
1963  if (MRI->isReserved(Reg)) {
1964  report("isRenamable set on reserved register", MO, MONum);
1965  return;
1966  }
1967  }
1968  } else {
1969  // Virtual register.
1971  if (!RC) {
1972  // This is a generic virtual register.
1973 
1974  // Do not allow undef uses for generic virtual registers. This ensures
1975  // getVRegDef can never fail and return null on a generic register.
1976  //
1977  // FIXME: This restriction should probably be broadened to all SSA
1978  // MIR. However, DetectDeadLanes/ProcessImplicitDefs technically still
1979  // run on the SSA function just before phi elimination.
1980  if (MO->isUndef())
1981  report("Generic virtual register use cannot be undef", MO, MONum);
1982 
1983  // If we're post-Select, we can't have gvregs anymore.
1984  if (isFunctionSelected) {
1985  report("Generic virtual register invalid in a Selected function",
1986  MO, MONum);
1987  return;
1988  }
1989 
1990  // The gvreg must have a type and it must not have a SubIdx.
1991  LLT Ty = MRI->getType(Reg);
1992  if (!Ty.isValid()) {
1993  report("Generic virtual register must have a valid type", MO,
1994  MONum);
1995  return;
1996  }
1997 
1998  const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
1999 
2000  // If we're post-RegBankSelect, the gvreg must have a bank.
2001  if (!RegBank && isFunctionRegBankSelected) {
2002  report("Generic virtual register must have a bank in a "
2003  "RegBankSelected function",
2004  MO, MONum);
2005  return;
2006  }
2007 
2008  // Make sure the register fits into its register bank if any.
2009  if (RegBank && Ty.isValid() &&
2010  RegBank->getSize() < Ty.getSizeInBits()) {
2011  report("Register bank is too small for virtual register", MO,
2012  MONum);
2013  errs() << "Register bank " << RegBank->getName() << " too small("
2014  << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
2015  << "-bits\n";
2016  return;
2017  }
2018  if (SubIdx) {
2019  report("Generic virtual register does not allow subregister index", MO,
2020  MONum);
2021  return;
2022  }
2023 
2024  // If this is a target specific instruction and this operand
2025  // has register class constraint, the virtual register must
2026  // comply to it.
2027  if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
2028  MONum < MCID.getNumOperands() &&
2029  TII->getRegClass(MCID, MONum, TRI, *MF)) {
2030  report("Virtual register does not match instruction constraint", MO,
2031  MONum);
2032  errs() << "Expect register class "
2033  << TRI->getRegClassName(
2034  TII->getRegClass(MCID, MONum, TRI, *MF))
2035  << " but got nothing\n";
2036  return;
2037  }
2038 
2039  break;
2040  }
2041  if (SubIdx) {
2042  const TargetRegisterClass *SRC =
2043  TRI->getSubClassWithSubReg(RC, SubIdx);
2044  if (!SRC) {
2045  report("Invalid subregister index for virtual register", MO, MONum);
2046  errs() << "Register class " << TRI->getRegClassName(RC)
2047  << " does not support subreg index " << SubIdx << "\n";
2048  return;
2049  }
2050  if (RC != SRC) {
2051  report("Invalid register class for subregister index", MO, MONum);
2052  errs() << "Register class " << TRI->getRegClassName(RC)
2053  << " does not fully support subreg index " << SubIdx << "\n";
2054  return;
2055  }
2056  }
2057  if (MONum < MCID.getNumOperands()) {
2058  if (const TargetRegisterClass *DRC =
2059  TII->getRegClass(MCID, MONum, TRI, *MF)) {
2060  if (SubIdx) {
2061  const TargetRegisterClass *SuperRC =
2062  TRI->getLargestLegalSuperClass(RC, *MF);
2063  if (!SuperRC) {
2064  report("No largest legal super class exists.", MO, MONum);
2065  return;
2066  }
2067  DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2068  if (!DRC) {
2069  report("No matching super-reg register class.", MO, MONum);
2070  return;
2071  }
2072  }
2073  if (!RC->hasSuperClassEq(DRC)) {
2074  report("Illegal virtual register for instruction", MO, MONum);
2075  errs() << "Expected a " << TRI->getRegClassName(DRC)
2076  << " register, but got a " << TRI->getRegClassName(RC)
2077  << " register\n";
2078  }
2079  }
2080  }
2081  }
2082  break;
2083  }
2084 
2086  regMasks.push_back(MO->getRegMask());
2087  break;
2088 
2090  if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
2091  report("PHI operand is not in the CFG", MO, MONum);
2092  break;
2093 
2095  if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
2096  LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2097  int FI = MO->getIndex();
2098  LiveInterval &LI = LiveStks->getInterval(FI);
2099  SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
2100 
2101  bool stores = MI->mayStore();
2102  bool loads = MI->mayLoad();
2103  // For a memory-to-memory move, we need to check if the frame
2104  // index is used for storing or loading, by inspecting the
2105  // memory operands.
2106  if (stores && loads) {
2107  for (auto *MMO : MI->memoperands()) {
2108  const PseudoSourceValue *PSV = MMO->getPseudoValue();
2109  if (PSV == nullptr) continue;
2111  dyn_cast<FixedStackPseudoSourceValue>(PSV);
2112  if (Value == nullptr) continue;
2113  if (Value->getFrameIndex() != FI) continue;
2114 
2115  if (MMO->isStore())
2116  loads = false;
2117  else
2118  stores = false;
2119  break;
2120  }
2121  if (loads == stores)
2122  report("Missing fixed stack memoperand.", MI);
2123  }
2124  if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
2125  report("Instruction loads from dead spill slot", MO, MONum);
2126  errs() << "Live stack: " << LI << '\n';
2127  }
2128  if (stores && !LI.liveAt(Idx.getRegSlot())) {
2129  report("Instruction stores to dead spill slot", MO, MONum);
2130  errs() << "Live stack: " << LI << '\n';
2131  }
2132  }
2133  break;
2134 
2135  default:
2136  break;
2137  }
2138 }
2139 
2140 void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
2141  unsigned MONum, SlotIndex UseIdx,
2142  const LiveRange &LR,
2143  Register VRegOrUnit,
2144  LaneBitmask LaneMask) {
2145  LiveQueryResult LRQ = LR.Query(UseIdx);
2146  // Check if we have a segment at the use, note however that we only need one
2147  // live subregister range, the others may be dead.
2148  if (!LRQ.valueIn() && LaneMask.none()) {
2149  report("No live segment at use", MO, MONum);
2150  report_context_liverange(LR);
2151  report_context_vreg_regunit(VRegOrUnit);
2152  report_context(UseIdx);
2153  }
2154  if (MO->isKill() && !LRQ.isKill()) {
2155  report("Live range continues after kill flag", MO, MONum);
2156  report_context_liverange(LR);
2157  report_context_vreg_regunit(VRegOrUnit);
2158  if (LaneMask.any())
2159  report_context_lanemask(LaneMask);
2160  report_context(UseIdx);
2161  }
2162 }
2163 
2164 void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
2165  unsigned MONum, SlotIndex DefIdx,
2166  const LiveRange &LR,
2167  Register VRegOrUnit,
2168  bool SubRangeCheck,
2169  LaneBitmask LaneMask) {
2170  if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
2171  assert(VNI && "NULL valno is not allowed");
2172  if (VNI->def != DefIdx) {
2173  report("Inconsistent valno->def", MO, MONum);
2174  report_context_liverange(LR);
2175  report_context_vreg_regunit(VRegOrUnit);
2176  if (LaneMask.any())
2177  report_context_lanemask(LaneMask);
2178  report_context(*VNI);
2179  report_context(DefIdx);
2180  }
2181  } else {
2182  report("No live segment at def", MO, MONum);
2183  report_context_liverange(LR);
2184  report_context_vreg_regunit(VRegOrUnit);
2185  if (LaneMask.any())
2186  report_context_lanemask(LaneMask);
2187  report_context(DefIdx);
2188  }
2189  // Check that, if the dead def flag is present, LiveInts agree.
2190  if (MO->isDead()) {
2191  LiveQueryResult LRQ = LR.Query(DefIdx);
2192  if (!LRQ.isDeadDef()) {
2193  assert(Register::isVirtualRegister(VRegOrUnit) &&
2194  "Expecting a virtual register.");
2195  // A dead subreg def only tells us that the specific subreg is dead. There
2196  // could be other non-dead defs of other subregs, or we could have other
2197  // parts of the register being live through the instruction. So unless we
2198  // are checking liveness for a subrange it is ok for the live range to
2199  // continue, given that we have a dead def of a subregister.
2200  if (SubRangeCheck || MO->getSubReg() == 0) {
2201  report("Live range continues after dead def flag", MO, MONum);
2202  report_context_liverange(LR);
2203  report_context_vreg_regunit(VRegOrUnit);
2204  if (LaneMask.any())
2205  report_context_lanemask(LaneMask);
2206  }
2207  }
2208  }
2209 }
2210 
2211 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
2212  const MachineInstr *MI = MO->getParent();
2213  const Register Reg = MO->getReg();
2214  const unsigned SubRegIdx = MO->getSubReg();
2215 
2216  const LiveInterval *LI = nullptr;
2217  if (LiveInts && Reg.isVirtual()) {
2218  if (LiveInts->hasInterval(Reg)) {
2219  LI = &LiveInts->getInterval(Reg);
2220  if (SubRegIdx != 0 && !LI->empty() && !LI->hasSubRanges() &&
2222  report("Live interval for subreg operand has no subranges", MO, MONum);
2223  } else {
2224  report("Virtual register has no live interval", MO, MONum);
2225  }
2226  }
2227 
2228  // Both use and def operands can read a register.
2229  if (MO->readsReg()) {
2230  if (MO->isKill())
2231  addRegWithSubRegs(regsKilled, Reg);
2232 
2233  // Check that LiveVars knows this kill (unless we are inside a bundle, in
2234  // which case we have already checked that LiveVars knows any kills on the
2235  // bundle header instead).
2236  if (LiveVars && Reg.isVirtual() && MO->isKill() &&
2237  !MI->isBundledWithPred()) {
2238  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2239  if (!is_contained(VI.Kills, MI))
2240  report("Kill missing from LiveVariables", MO, MONum);
2241  }
2242 
2243  // Check LiveInts liveness and kill.
2244  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2245  SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
2246  // Check the cached regunit intervals.
2247  if (Reg.isPhysical() && !isReserved(Reg)) {
2248  for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
2249  ++Units) {
2250  if (MRI->isReservedRegUnit(*Units))
2251  continue;
2252  if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
2253  checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
2254  }
2255  }
2256 
2257  if (Reg.isVirtual()) {
2258  // This is a virtual register interval.
2259  checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2260 
2261  if (LI->hasSubRanges() && !MO->isDef()) {
2262  LaneBitmask MOMask = SubRegIdx != 0
2263  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2265  LaneBitmask LiveInMask;
2266  for (const LiveInterval::SubRange &SR : LI->subranges()) {
2267  if ((MOMask & SR.LaneMask).none())
2268  continue;
2269  checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2270  LiveQueryResult LRQ = SR.Query(UseIdx);
2271  if (LRQ.valueIn())
2272  LiveInMask |= SR.LaneMask;
2273  }
2274  // At least parts of the register has to be live at the use.
2275  if ((LiveInMask & MOMask).none()) {
2276  report("No live subrange at use", MO, MONum);
2277  report_context(*LI);
2278  report_context(UseIdx);
2279  }
2280  }
2281  }
2282  }
2283 
2284  // Use of a dead register.
2285  if (!regsLive.count(Reg)) {
2286  if (Reg.isPhysical()) {
2287  // Reserved registers may be used even when 'dead'.
2288  bool Bad = !isReserved(Reg);
2289  // We are fine if just any subregister has a defined value.
2290  if (Bad) {
2291 
2292  for (const MCPhysReg &SubReg : TRI->subregs(Reg)) {
2293  if (regsLive.count(SubReg)) {
2294  Bad = false;
2295  break;
2296  }
2297  }
2298  }
2299  // If there is an additional implicit-use of a super register we stop
2300  // here. By definition we are fine if the super register is not
2301  // (completely) dead, if the complete super register is dead we will
2302  // get a report for its operand.
2303  if (Bad) {
2304  for (const MachineOperand &MOP : MI->uses()) {
2305  if (!MOP.isReg() || !MOP.isImplicit())
2306  continue;
2307 
2308  if (!MOP.getReg().isPhysical())
2309  continue;
2310 
2311  if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg))
2312  Bad = false;
2313  }
2314  }
2315  if (Bad)
2316  report("Using an undefined physical register", MO, MONum);
2317  } else if (MRI->def_empty(Reg)) {
2318  report("Reading virtual register without a def", MO, MONum);
2319  } else {
2320  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2321  // We don't know which virtual registers are live in, so only complain
2322  // if vreg was killed in this MBB. Otherwise keep track of vregs that
2323  // must be live in. PHI instructions are handled separately.
2324  if (MInfo.regsKilled.count(Reg))
2325  report("Using a killed virtual register", MO, MONum);
2326  else if (!MI->isPHI())
2327  MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
2328  }
2329  }
2330  }
2331 
2332  if (MO->isDef()) {
2333  // Register defined.
2334  // TODO: verify that earlyclobber ops are not used.
2335  if (MO->isDead())
2336  addRegWithSubRegs(regsDead, Reg);
2337  else
2338  addRegWithSubRegs(regsDefined, Reg);
2339 
2340  // Verify SSA form.
2341  if (MRI->isSSA() && Reg.isVirtual() &&
2342  std::next(MRI->def_begin(Reg)) != MRI->def_end())
2343  report("Multiple virtual register defs in SSA form", MO, MONum);
2344 
2345  // Check LiveInts for a live segment, but only for virtual registers.
2346  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2347  SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
2348  DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
2349 
2350  if (Reg.isVirtual()) {
2351  checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
2352 
2353  if (LI->hasSubRanges()) {
2354  LaneBitmask MOMask = SubRegIdx != 0
2355  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2357  for (const LiveInterval::SubRange &SR : LI->subranges()) {
2358  if ((SR.LaneMask & MOMask).none())
2359  continue;
2360  checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
2361  }
2362  }
2363  }
2364  }
2365  }
2366 }
2367 
2368 // This function gets called after visiting all instructions in a bundle. The
2369 // argument points to the bundle header.
2370 // Normal stand-alone instructions are also considered 'bundles', and this
2371 // function is called for all of them.
2372 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
2373  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2374  set_union(MInfo.regsKilled, regsKilled);
2375  set_subtract(regsLive, regsKilled); regsKilled.clear();
2376  // Kill any masked registers.
2377  while (!regMasks.empty()) {
2378  const uint32_t *Mask = regMasks.pop_back_val();
2379  for (Register Reg : regsLive)
2380  if (Reg.isPhysical() &&
2382  regsDead.push_back(Reg);
2383  }
2384  set_subtract(regsLive, regsDead); regsDead.clear();
2385  set_union(regsLive, regsDefined); regsDefined.clear();
2386 }
2387 
2388 void
2389 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
2390  MBBInfoMap[MBB].regsLiveOut = regsLive;
2391  regsLive.clear();
2392 
2393  if (Indexes) {
2394  SlotIndex stop = Indexes->getMBBEndIdx(MBB);
2395  if (!(stop > lastIndex)) {
2396  report("Block ends before last instruction index", MBB);
2397  errs() << "Block ends at " << stop
2398  << " last instruction was at " << lastIndex << '\n';
2399  }
2400  lastIndex = stop;
2401  }
2402 }
2403 
2404 namespace {
2405 // This implements a set of registers that serves as a filter: can filter other
2406 // sets by passing through elements not in the filter and blocking those that
2407 // are. Any filter implicitly includes the full set of physical registers upon
2408 // creation, thus filtering them all out. The filter itself as a set only grows,
2409 // and needs to be as efficient as possible.
2410 struct VRegFilter {
2411  // Add elements to the filter itself. \pre Input set \p FromRegSet must have
2412  // no duplicates. Both virtual and physical registers are fine.
2413  template <typename RegSetT> void add(const RegSetT &FromRegSet) {
2414  SmallVector<Register, 0> VRegsBuffer;
2415  filterAndAdd(FromRegSet, VRegsBuffer);
2416  }
2417  // Filter \p FromRegSet through the filter and append passed elements into \p
2418  // ToVRegs. All elements appended are then added to the filter itself.
2419  // \returns true if anything changed.
2420  template <typename RegSetT>
2421  bool filterAndAdd(const RegSetT &FromRegSet,
2422  SmallVectorImpl<Register> &ToVRegs) {
2423  unsigned SparseUniverse = Sparse.size();
2424  unsigned NewSparseUniverse = SparseUniverse;
2425  unsigned NewDenseSize = Dense.size();
2426  size_t Begin = ToVRegs.size();
2427  for (Register Reg : FromRegSet) {
2428  if (!Reg.isVirtual())
2429  continue;
2430  unsigned Index = Register::virtReg2Index(Reg);
2431  if (Index < SparseUniverseMax) {
2432  if (Index < SparseUniverse && Sparse.test(Index))
2433  continue;
2434  NewSparseUniverse = std::max(NewSparseUniverse, Index + 1);
2435  } else {
2436  if (Dense.count(Reg))
2437  continue;
2438  ++NewDenseSize;
2439  }
2440  ToVRegs.push_back(Reg);
2441  }
2442  size_t End = ToVRegs.size();
2443  if (Begin == End)
2444  return false;
2445  // Reserving space in sets once performs better than doing so continuously
2446  // and pays easily for double look-ups (even in Dense with SparseUniverseMax
2447  // tuned all the way down) and double iteration (the second one is over a
2448  // SmallVector, which is a lot cheaper compared to DenseSet or BitVector).
2449  Sparse.resize(NewSparseUniverse);
2450  Dense.reserve(NewDenseSize);
2451  for (unsigned I = Begin; I < End; ++I) {
2452  Register Reg = ToVRegs[I];
2453  unsigned Index = Register::virtReg2Index(Reg);
2454  if (Index < SparseUniverseMax)
2455  Sparse.set(Index);
2456  else
2457  Dense.insert(Reg);
2458  }
2459  return true;
2460  }
2461 
2462 private:
2463  static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2464  // VRegs indexed within SparseUniverseMax are tracked by Sparse, those beyound
2465  // are tracked by Dense. The only purpose of the threashold and the Dense set
2466  // is to have a reasonably growing memory usage in pathological cases (large
2467  // number of very sparse VRegFilter instances live at the same time). In
2468  // practice even in the worst-by-execution time cases having all elements
2469  // tracked by Sparse (very large SparseUniverseMax scenario) tends to be more
2470  // space efficient than if tracked by Dense. The threashold is set to keep the
2471  // worst-case memory usage within 2x of figures determined empirically for
2472  // "all Dense" scenario in such worst-by-execution-time cases.
2473  BitVector Sparse;
2474  DenseSet<unsigned> Dense;
2475 };
2476 
2477 // Implements both a transfer function and a (binary, in-place) join operator
2478 // for a dataflow over register sets with set union join and filtering transfer
2479 // (out_b = in_b \ filter_b). filter_b is expected to be set-up ahead of time.
2480 // Maintains out_b as its state, allowing for O(n) iteration over it at any
2481 // time, where n is the size of the set (as opposed to O(U) where U is the
2482 // universe). filter_b implicitly contains all physical registers at all times.
2483 class FilteringVRegSet {
2484  VRegFilter Filter;
2486 
2487 public:
2488  // Set-up the filter_b. \pre Input register set \p RS must have no duplicates.
2489  // Both virtual and physical registers are fine.
2490  template <typename RegSetT> void addToFilter(const RegSetT &RS) {
2491  Filter.add(RS);
2492  }
2493  // Passes \p RS through the filter_b (transfer function) and adds what's left
2494  // to itself (out_b).
2495  template <typename RegSetT> bool add(const RegSetT &RS) {
2496  // Double-duty the Filter: to maintain VRegs a set (and the join operation
2497  // a set union) just add everything being added here to the Filter as well.
2498  return Filter.filterAndAdd(RS, VRegs);
2499  }
2500  using const_iterator = decltype(VRegs)::const_iterator;
2501  const_iterator begin() const { return VRegs.begin(); }
2502  const_iterator end() const { return VRegs.end(); }
2503  size_t size() const { return VRegs.size(); }
2504 };
2505 } // namespace
2506 
2507 // Calculate the largest possible vregsPassed sets. These are the registers that
2508 // can pass through an MBB live, but may not be live every time. It is assumed
2509 // that all vregsPassed sets are empty before the call.
2510 void MachineVerifier::calcRegsPassed() {
2511  if (MF->empty())
2512  // ReversePostOrderTraversal doesn't handle empty functions.
2513  return;
2514 
2515  for (const MachineBasicBlock *MB :
2517  FilteringVRegSet VRegs;
2518  BBInfo &Info = MBBInfoMap[MB];
2519  assert(Info.reachable);
2520 
2521  VRegs.addToFilter(Info.regsKilled);
2522  VRegs.addToFilter(Info.regsLiveOut);
2523  for (const MachineBasicBlock *Pred : MB->predecessors()) {
2524  const BBInfo &PredInfo = MBBInfoMap[Pred];
2525  if (!PredInfo.reachable)
2526  continue;
2527 
2528  VRegs.add(PredInfo.regsLiveOut);
2529  VRegs.add(PredInfo.vregsPassed);
2530  }
2531  Info.vregsPassed.reserve(VRegs.size());
2532  Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2533  }
2534 }
2535 
2536 // Calculate the set of virtual registers that must be passed through each basic
2537 // block in order to satisfy the requirements of successor blocks. This is very
2538 // similar to calcRegsPassed, only backwards.
2539 void MachineVerifier::calcRegsRequired() {
2540  // First push live-in regs to predecessors' vregsRequired.
2542  for (const auto &MBB : *MF) {
2543  BBInfo &MInfo = MBBInfoMap[&MBB];
2544  for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2545  BBInfo &PInfo = MBBInfoMap[Pred];
2546  if (PInfo.addRequired(MInfo.vregsLiveIn))
2547  todo.insert(Pred);
2548  }
2549 
2550  // Handle the PHI node.
2551  for (const MachineInstr &MI : MBB.phis()) {
2552  for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
2553  // Skip those Operands which are undef regs or not regs.
2554  if (!MI.getOperand(i).isReg() || !MI.getOperand(i).readsReg())
2555  continue;
2556 
2557  // Get register and predecessor for one PHI edge.
2558  Register Reg = MI.getOperand(i).getReg();
2559  const MachineBasicBlock *Pred = MI.getOperand(i + 1).getMBB();
2560 
2561  BBInfo &PInfo = MBBInfoMap[Pred];
2562  if (PInfo.addRequired(Reg))
2563  todo.insert(Pred);
2564  }
2565  }
2566  }
2567 
2568  // Iteratively push vregsRequired to predecessors. This will converge to the
2569  // same final state regardless of DenseSet iteration order.
2570  while (!todo.empty()) {
2571  const MachineBasicBlock *MBB = *todo.begin();
2572  todo.erase(MBB);
2573  BBInfo &MInfo = MBBInfoMap[MBB];
2574  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
2575  if (Pred == MBB)
2576  continue;
2577  BBInfo &SInfo = MBBInfoMap[Pred];
2578  if (SInfo.addRequired(MInfo.vregsRequired))
2579  todo.insert(Pred);
2580  }
2581  }
2582 }
2583 
2584 // Check PHI instructions at the beginning of MBB. It is assumed that
2585 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
2586 void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
2587  BBInfo &MInfo = MBBInfoMap[&MBB];
2588 
2590  for (const MachineInstr &Phi : MBB) {
2591  if (!Phi.isPHI())
2592  break;
2593  seen.clear();
2594 
2595  const MachineOperand &MODef = Phi.getOperand(0);
2596  if (!MODef.isReg() || !MODef.isDef()) {
2597  report("Expected first PHI operand to be a register def", &MODef, 0);
2598  continue;
2599  }
2600  if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
2601  MODef.isEarlyClobber() || MODef.isDebug())
2602  report("Unexpected flag on PHI operand", &MODef, 0);
2603  Register DefReg = MODef.getReg();
2604  if (!Register::isVirtualRegister(DefReg))
2605  report("Expected first PHI operand to be a virtual register", &MODef, 0);
2606 
2607  for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
2608  const MachineOperand &MO0 = Phi.getOperand(I);
2609  if (!MO0.isReg()) {
2610  report("Expected PHI operand to be a register", &MO0, I);
2611  continue;
2612  }
2613  if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
2614  MO0.isDebug() || MO0.isTied())
2615  report("Unexpected flag on PHI operand", &MO0, I);
2616 
2617  const MachineOperand &MO1 = Phi.getOperand(I + 1);
2618  if (!MO1.isMBB()) {
2619  report("Expected PHI operand to be a basic block", &MO1, I + 1);
2620  continue;
2621  }
2622 
2623  const MachineBasicBlock &Pre = *MO1.getMBB();
2624  if (!Pre.isSuccessor(&MBB)) {
2625  report("PHI input is not a predecessor block", &MO1, I + 1);
2626  continue;
2627  }
2628 
2629  if (MInfo.reachable) {
2630  seen.insert(&Pre);
2631  BBInfo &PrInfo = MBBInfoMap[&Pre];
2632  if (!MO0.isUndef() && PrInfo.reachable &&
2633  !PrInfo.isLiveOut(MO0.getReg()))
2634  report("PHI operand is not live-out from predecessor", &MO0, I);
2635  }
2636  }
2637 
2638  // Did we see all predecessors?
2639  if (MInfo.reachable) {
2640  for (MachineBasicBlock *Pred : MBB.predecessors()) {
2641  if (!seen.count(Pred)) {
2642  report("Missing PHI operand", &Phi);
2643  errs() << printMBBReference(*Pred)
2644  << " is a predecessor according to the CFG.\n";
2645  }
2646  }
2647  }
2648  }
2649 }
2650 
2651 void MachineVerifier::visitMachineFunctionAfter() {
2652  calcRegsPassed();
2653 
2654  for (const MachineBasicBlock &MBB : *MF)
2655  checkPHIOps(MBB);
2656 
2657  // Now check liveness info if available
2658  calcRegsRequired();
2659 
2660  // Check for killed virtual registers that should be live out.
2661  for (const auto &MBB : *MF) {
2662  BBInfo &MInfo = MBBInfoMap[&MBB];
2663  for (Register VReg : MInfo.vregsRequired)
2664  if (MInfo.regsKilled.count(VReg)) {
2665  report("Virtual register killed in block, but needed live out.", &MBB);
2666  errs() << "Virtual register " << printReg(VReg)
2667  << " is used after the block.\n";
2668  }
2669  }
2670 
2671  if (!MF->empty()) {
2672  BBInfo &MInfo = MBBInfoMap[&MF->front()];
2673  for (Register VReg : MInfo.vregsRequired) {
2674  report("Virtual register defs don't dominate all uses.", MF);
2675  report_context_vreg(VReg);
2676  }
2677  }
2678 
2679  if (LiveVars)
2680  verifyLiveVariables();
2681  if (LiveInts)
2682  verifyLiveIntervals();
2683 
2684  // Check live-in list of each MBB. If a register is live into MBB, check
2685  // that the register is in regsLiveOut of each predecessor block. Since
2686  // this must come from a definition in the predecesssor or its live-in
2687  // list, this will catch a live-through case where the predecessor does not
2688  // have the register in its live-in list. This currently only checks
2689  // registers that have no aliases, are not allocatable and are not
2690  // reserved, which could mean a condition code register for instance.
2691  if (MRI->tracksLiveness())
2692  for (const auto &MBB : *MF)
2694  MCPhysReg LiveInReg = P.PhysReg;
2695  bool hasAliases = MCRegAliasIterator(LiveInReg, TRI, false).isValid();
2696  if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
2697  continue;
2698  for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2699  BBInfo &PInfo = MBBInfoMap[Pred];
2700  if (!PInfo.regsLiveOut.count(LiveInReg)) {
2701  report("Live in register not found to be live out from predecessor.",
2702  &MBB);
2703  errs() << TRI->getName(LiveInReg)
2704  << " not found to be live out from "
2705  << printMBBReference(*Pred) << "\n";
2706  }
2707  }
2708  }
2709 
2710  for (auto CSInfo : MF->getCallSitesInfo())
2711  if (!CSInfo.first->isCall())
2712  report("Call site info referencing instruction that is not call", MF);
2713 
2714  // If there's debug-info, check that we don't have any duplicate value
2715  // tracking numbers.
2716  if (MF->getFunction().getSubprogram()) {
2717  DenseSet<unsigned> SeenNumbers;
2718  for (auto &MBB : *MF) {
2719  for (auto &MI : MBB) {
2720  if (auto Num = MI.peekDebugInstrNum()) {
2721  auto Result = SeenNumbers.insert((unsigned)Num);
2722  if (!Result.second)
2723  report("Instruction has a duplicated value tracking number", &MI);
2724  }
2725  }
2726  }
2727  }
2728 }
2729 
2730 void MachineVerifier::verifyLiveVariables() {
2731  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
2732  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2734  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2735  for (const auto &MBB : *MF) {
2736  BBInfo &MInfo = MBBInfoMap[&MBB];
2737 
2738  // Our vregsRequired should be identical to LiveVariables' AliveBlocks
2739  if (MInfo.vregsRequired.count(Reg)) {
2740  if (!VI.AliveBlocks.test(MBB.getNumber())) {
2741  report("LiveVariables: Block missing from AliveBlocks", &MBB);
2742  errs() << "Virtual register " << printReg(Reg)
2743  << " must be live through the block.\n";
2744  }
2745  } else {
2746  if (VI.AliveBlocks.test(MBB.getNumber())) {
2747  report("LiveVariables: Block should not be in AliveBlocks", &MBB);
2748  errs() << "Virtual register " << printReg(Reg)
2749  << " is not needed live through the block.\n";
2750  }
2751  }
2752  }
2753  }
2754 }
2755 
2756 void MachineVerifier::verifyLiveIntervals() {
2757  assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
2758  for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2760 
2761  // Spilling and splitting may leave unused registers around. Skip them.
2762  if (MRI->reg_nodbg_empty(Reg))
2763  continue;
2764 
2765  if (!LiveInts->hasInterval(Reg)) {
2766  report("Missing live interval for virtual register", MF);
2767  errs() << printReg(Reg, TRI) << " still has defs or uses\n";
2768  continue;
2769  }
2770 
2771  const LiveInterval &LI = LiveInts->getInterval(Reg);
2772  assert(Reg == LI.reg() && "Invalid reg to interval mapping");
2773  verifyLiveInterval(LI);
2774  }
2775 
2776  // Verify all the cached regunit intervals.
2777  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
2778  if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
2779  verifyLiveRange(*LR, i);
2780 }
2781 
2782 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
2783  const VNInfo *VNI, Register Reg,
2784  LaneBitmask LaneMask) {
2785  if (VNI->isUnused())
2786  return;
2787 
2788  const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
2789 
2790  if (!DefVNI) {
2791  report("Value not live at VNInfo def and not marked unused", MF);
2792  report_context(LR, Reg, LaneMask);
2793  report_context(*VNI);
2794  return;
2795  }
2796 
2797  if (DefVNI != VNI) {
2798  report("Live segment at def has different VNInfo", MF);
2799  report_context(LR, Reg, LaneMask);
2800  report_context(*VNI);
2801  return;
2802  }
2803 
2804  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
2805  if (!MBB) {
2806  report("Invalid VNInfo definition index", MF);
2807  report_context(LR, Reg, LaneMask);
2808  report_context(*VNI);
2809  return;
2810  }
2811 
2812  if (VNI->isPHIDef()) {
2813  if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
2814  report("PHIDef VNInfo is not defined at MBB start", MBB);
2815  report_context(LR, Reg, LaneMask);
2816  report_context(*VNI);
2817  }
2818  return;
2819  }
2820 
2821  // Non-PHI def.
2822  const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
2823  if (!MI) {
2824  report("No instruction at VNInfo def index", MBB);
2825  report_context(LR, Reg, LaneMask);
2826  report_context(*VNI);
2827  return;
2828  }
2829 
2830  if (Reg != 0) {
2831  bool hasDef = false;
2832  bool isEarlyClobber = false;
2833  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2834  if (!MOI->isReg() || !MOI->isDef())
2835  continue;
2837  if (MOI->getReg() != Reg)
2838  continue;
2839  } else {
2840  if (!Register::isPhysicalRegister(MOI->getReg()) ||
2841  !TRI->hasRegUnit(MOI->getReg(), Reg))
2842  continue;
2843  }
2844  if (LaneMask.any() &&
2845  (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
2846  continue;
2847  hasDef = true;
2848  if (MOI->isEarlyClobber())
2849  isEarlyClobber = true;
2850  }
2851 
2852  if (!hasDef) {
2853  report("Defining instruction does not modify register", MI);
2854  report_context(LR, Reg, LaneMask);
2855  report_context(*VNI);
2856  }
2857 
2858  // Early clobber defs begin at USE slots, but other defs must begin at
2859  // DEF slots.
2860  if (isEarlyClobber) {
2861  if (!VNI->def.isEarlyClobber()) {
2862  report("Early clobber def must be at an early-clobber slot", MBB);
2863  report_context(LR, Reg, LaneMask);
2864  report_context(*VNI);
2865  }
2866  } else if (!VNI->def.isRegister()) {
2867  report("Non-PHI, non-early clobber def must be at a register slot", MBB);
2868  report_context(LR, Reg, LaneMask);
2869  report_context(*VNI);
2870  }
2871  }
2872 }
2873 
2874 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
2876  Register Reg,
2877  LaneBitmask LaneMask) {
2878  const LiveRange::Segment &S = *I;
2879  const VNInfo *VNI = S.valno;
2880  assert(VNI && "Live segment has no valno");
2881 
2882  if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
2883  report("Foreign valno in live segment", MF);
2884  report_context(LR, Reg, LaneMask);
2885  report_context(S);
2886  report_context(*VNI);
2887  }
2888 
2889  if (VNI->isUnused()) {
2890  report("Live segment valno is marked unused", MF);
2891  report_context(LR, Reg, LaneMask);
2892  report_context(S);
2893  }
2894 
2895  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
2896  if (!MBB) {
2897  report("Bad start of live segment, no basic block", MF);
2898  report_context(LR, Reg, LaneMask);
2899  report_context(S);
2900  return;
2901  }
2902  SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
2903  if (S.start != MBBStartIdx && S.start != VNI->def) {
2904  report("Live segment must begin at MBB entry or valno def", MBB);
2905  report_context(LR, Reg, LaneMask);
2906  report_context(S);
2907  }
2908 
2909  const MachineBasicBlock *EndMBB =
2910  LiveInts->getMBBFromIndex(S.end.getPrevSlot());
2911  if (!EndMBB) {
2912  report("Bad end of live segment, no basic block", MF);
2913  report_context(LR, Reg, LaneMask);
2914  report_context(S);
2915  return;
2916  }
2917 
2918  // No more checks for live-out segments.
2919  if (S.end == LiveInts->getMBBEndIdx(EndMBB))
2920  return;
2921 
2922  // RegUnit intervals are allowed dead phis.
2923  if (!Register::isVirtualRegister(Reg) && VNI->isPHIDef() &&
2924  S.start == VNI->def && S.end == VNI->def.getDeadSlot())
2925  return;
2926 
2927  // The live segment is ending inside EndMBB
2928  const MachineInstr *MI =
2929  LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
2930  if (!MI) {
2931  report("Live segment doesn't end at a valid instruction", EndMBB);
2932  report_context(LR, Reg, LaneMask);
2933  report_context(S);
2934  return;
2935  }
2936 
2937  // The block slot must refer to a basic block boundary.
2938  if (S.end.isBlock()) {
2939  report("Live segment ends at B slot of an instruction", EndMBB);
2940  report_context(LR, Reg, LaneMask);
2941  report_context(S);
2942  }
2943 
2944  if (S.end.isDead()) {
2945  // Segment ends on the dead slot.
2946  // That means there must be a dead def.
2947  if (!SlotIndex::isSameInstr(S.start, S.end)) {
2948  report("Live segment ending at dead slot spans instructions", EndMBB);
2949  report_context(LR, Reg, LaneMask);
2950  report_context(S);
2951  }
2952  }
2953 
2954  // After tied operands are rewritten, a live segment can only end at an
2955  // early-clobber slot if it is being redefined by an early-clobber def.
2956  // TODO: Before tied operands are rewritten, a live segment can only end at an
2957  // early-clobber slot if the last use is tied to an early-clobber def.
2958  if (MF->getProperties().hasProperty(
2960  S.end.isEarlyClobber()) {
2961  if (I+1 == LR.end() || (I+1)->start != S.end) {
2962  report("Live segment ending at early clobber slot must be "
2963  "redefined by an EC def in the same instruction", EndMBB);
2964  report_context(LR, Reg, LaneMask);
2965  report_context(S);
2966  }
2967  }
2968 
2969  // The following checks only apply to virtual registers. Physreg liveness
2970  // is too weird to check.
2972  // A live segment can end with either a redefinition, a kill flag on a
2973  // use, or a dead flag on a def.
2974  bool hasRead = false;
2975  bool hasSubRegDef = false;
2976  bool hasDeadDef = false;
2977  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2978  if (!MOI->isReg() || MOI->getReg() != Reg)
2979  continue;
2980  unsigned Sub = MOI->getSubReg();
2981  LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
2982  : LaneBitmask::getAll();
2983  if (MOI->isDef()) {
2984  if (Sub != 0) {
2985  hasSubRegDef = true;
2986  // An operand %0:sub0 reads %0:sub1..n. Invert the lane
2987  // mask for subregister defs. Read-undef defs will be handled by
2988  // readsReg below.
2989  SLM = ~SLM;
2990  }
2991  if (MOI->isDead())
2992  hasDeadDef = true;
2993  }
2994  if (LaneMask.any() && (LaneMask & SLM).none())
2995  continue;
2996  if (MOI->readsReg())
2997  hasRead = true;
2998  }
2999  if (S.end.isDead()) {
3000  // Make sure that the corresponding machine operand for a "dead" live
3001  // range has the dead flag. We cannot perform this check for subregister
3002  // liveranges as partially dead values are allowed.
3003  if (LaneMask.none() && !hasDeadDef) {
3004  report("Instruction ending live segment on dead slot has no dead flag",
3005  MI);
3006  report_context(LR, Reg, LaneMask);
3007  report_context(S);
3008  }
3009  } else {
3010  if (!hasRead) {
3011  // When tracking subregister liveness, the main range must start new
3012  // values on partial register writes, even if there is no read.
3013  if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
3014  !hasSubRegDef) {
3015  report("Instruction ending live segment doesn't read the register",
3016  MI);
3017  report_context(LR, Reg, LaneMask);
3018  report_context(S);
3019  }
3020  }
3021  }
3022  }
3023 
3024  // Now check all the basic blocks in this live segment.
3026  // Is this live segment the beginning of a non-PHIDef VN?
3027  if (S.start == VNI->def && !VNI->isPHIDef()) {
3028  // Not live-in to any blocks.
3029  if (MBB == EndMBB)
3030  return;
3031  // Skip this block.
3032  ++MFI;
3033  }
3034 
3036  if (LaneMask.any()) {
3037  LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
3038  OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
3039  }
3040 
3041  while (true) {
3042  assert(LiveInts->isLiveInToMBB(LR, &*MFI));
3043  // We don't know how to track physregs into a landing pad.
3044  if (!Register::isVirtualRegister(Reg) && MFI->isEHPad()) {
3045  if (&*MFI == EndMBB)
3046  break;
3047  ++MFI;
3048  continue;
3049  }
3050 
3051  // Is VNI a PHI-def in the current block?
3052  bool IsPHI = VNI->isPHIDef() &&
3053  VNI->def == LiveInts->getMBBStartIdx(&*MFI);
3054 
3055  // Check that VNI is live-out of all predecessors.
3056  for (const MachineBasicBlock *Pred : MFI->predecessors()) {
3057  SlotIndex PEnd = LiveInts->getMBBEndIdx(Pred);
3058  // Predecessor of landing pad live-out on last call.
3059  if (MFI->isEHPad()) {
3060  for (auto I = Pred->rbegin(), E = Pred->rend(); I != E; ++I) {
3061  if (I->isCall()) {
3062  PEnd = Indexes->getInstructionIndex(*I).getBoundaryIndex();
3063  break;
3064  }
3065  }
3066  }
3067  const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
3068 
3069  // All predecessors must have a live-out value. However for a phi
3070  // instruction with subregister intervals
3071  // only one of the subregisters (not necessarily the current one) needs to
3072  // be defined.
3073  if (!PVNI && (LaneMask.none() || !IsPHI)) {
3074  if (LiveRangeCalc::isJointlyDominated(Pred, Undefs, *Indexes))
3075  continue;
3076  report("Register not marked live out of predecessor", Pred);
3077  report_context(LR, Reg, LaneMask);
3078  report_context(*VNI);
3079  errs() << " live into " << printMBBReference(*MFI) << '@'
3080  << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
3081  << PEnd << '\n';
3082  continue;
3083  }
3084 
3085  // Only PHI-defs can take different predecessor values.
3086  if (!IsPHI && PVNI != VNI) {
3087  report("Different value live out of predecessor", Pred);
3088  report_context(LR, Reg, LaneMask);
3089  errs() << "Valno #" << PVNI->id << " live out of "
3090  << printMBBReference(*Pred) << '@' << PEnd << "\nValno #"
3091  << VNI->id << " live into " << printMBBReference(*MFI) << '@'
3092  << LiveInts->getMBBStartIdx(&*MFI) << '\n';
3093  }
3094  }
3095  if (&*MFI == EndMBB)
3096  break;
3097  ++MFI;
3098  }
3099 }
3100 
3101 void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg,
3102  LaneBitmask LaneMask) {
3103  for (const VNInfo *VNI : LR.valnos)
3104  verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3105 
3106  for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
3107  verifyLiveRangeSegment(LR, I, Reg, LaneMask);
3108 }
3109 
3110 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
3111  Register Reg = LI.reg();
3113  verifyLiveRange(LI, Reg);
3114 
3115  LaneBitmask Mask;
3117  for (const LiveInterval::SubRange &SR : LI.subranges()) {
3118  if ((Mask & SR.LaneMask).any()) {
3119  report("Lane masks of sub ranges overlap in live interval", MF);
3120  report_context(LI);
3121  }
3122  if ((SR.LaneMask & ~MaxMask).any()) {
3123  report("Subrange lanemask is invalid", MF);
3124  report_context(LI);
3125  }
3126  if (SR.empty()) {
3127  report("Subrange must not be empty", MF);
3128  report_context(SR, LI.reg(), SR.LaneMask);
3129  }
3130  Mask |= SR.LaneMask;
3131  verifyLiveRange(SR, LI.reg(), SR.LaneMask);
3132  if (!LI.covers(SR)) {
3133  report("A Subrange is not covered by the main range", MF);
3134  report_context(LI);
3135  }
3136  }
3137 
3138  // Check the LI only has one connected component.
3139  ConnectedVNInfoEqClasses ConEQ(*LiveInts);
3140  unsigned NumComp = ConEQ.Classify(LI);
3141  if (NumComp > 1) {
3142  report("Multiple connected components in live interval", MF);
3143  report_context(LI);
3144  for (unsigned comp = 0; comp != NumComp; ++comp) {
3145  errs() << comp << ": valnos";
3146  for (const VNInfo *I : LI.valnos)
3147  if (comp == ConEQ.getEqClass(I))
3148  errs() << ' ' << I->id;
3149  errs() << '\n';
3150  }
3151  }
3152 }
3153 
3154 namespace {
3155 
3156  // FrameSetup and FrameDestroy can have zero adjustment, so using a single
3157  // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
3158  // value is zero.
3159  // We use a bool plus an integer to capture the stack state.
3160  struct StackStateOfBB {
3161  StackStateOfBB() = default;
3162  StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
3163  EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3164  ExitIsSetup(ExitSetup) {}
3165 
3166  // Can be negative, which means we are setting up a frame.
3167  int EntryValue = 0;
3168  int ExitValue = 0;
3169  bool EntryIsSetup = false;
3170  bool ExitIsSetup = false;
3171  };
3172 
3173 } // end anonymous namespace
3174 
3175 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
3176 /// by a FrameDestroy <n>, stack adjustments are identical on all
3177 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
3178 void MachineVerifier::verifyStackFrame() {
3179  unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
3180  unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
3181  if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3182  return;
3183 
3185  SPState.resize(MF->getNumBlockIDs());
3187 
3188  // Visit the MBBs in DFS order.
3189  for (df_ext_iterator<const MachineFunction *,
3191  DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
3192  DFI != DFE; ++DFI) {
3193  const MachineBasicBlock *MBB = *DFI;
3194 
3195  StackStateOfBB BBState;
3196  // Check the exit state of the DFS stack predecessor.
3197  if (DFI.getPathLength() >= 2) {
3198  const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
3199  assert(Reachable.count(StackPred) &&
3200  "DFS stack predecessor is already visited.\n");
3201  BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
3202  BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
3203  BBState.ExitValue = BBState.EntryValue;
3204  BBState.ExitIsSetup = BBState.EntryIsSetup;
3205  }
3206 
3207  // Update stack state by checking contents of MBB.
3208  for (const auto &I : *MBB) {
3209  if (I.getOpcode() == FrameSetupOpcode) {
3210  if (BBState.ExitIsSetup)
3211  report("FrameSetup is after another FrameSetup", &I);
3212  BBState.ExitValue -= TII->getFrameTotalSize(I);
3213  BBState.ExitIsSetup = true;
3214  }
3215 
3216  if (I.getOpcode() == FrameDestroyOpcode) {
3217  int Size = TII->getFrameTotalSize(I);
3218  if (!BBState.ExitIsSetup)
3219  report("FrameDestroy is not after a FrameSetup", &I);
3220  int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3221  BBState.ExitValue;
3222  if (BBState.ExitIsSetup && AbsSPAdj != Size) {
3223  report("FrameDestroy <n> is after FrameSetup <m>", &I);
3224  errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
3225  << AbsSPAdj << ">.\n";
3226  }
3227  BBState.ExitValue += Size;
3228  BBState.ExitIsSetup = false;
3229  }
3230  }
3231  SPState[MBB->getNumber()] = BBState;
3232 
3233  // Make sure the exit state of any predecessor is consistent with the entry
3234  // state.
3235  for (const MachineBasicBlock *Pred : MBB->predecessors()) {
3236  if (Reachable.count(Pred) &&
3237  (SPState[Pred->getNumber()].ExitValue != BBState.EntryValue ||
3238  SPState[Pred->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3239  report("The exit stack state of a predecessor is inconsistent.", MBB);
3240  errs() << "Predecessor " << printMBBReference(*Pred)
3241  << " has exit state (" << SPState[Pred->getNumber()].ExitValue
3242  << ", " << SPState[Pred->getNumber()].ExitIsSetup << "), while "
3243  << printMBBReference(*MBB) << " has entry state ("
3244  << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
3245  }
3246  }
3247 
3248  // Make sure the entry state of any successor is consistent with the exit
3249  // state.
3250  for (const MachineBasicBlock *Succ : MBB->successors()) {
3251  if (Reachable.count(Succ) &&
3252  (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3253  SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3254  report("The entry stack state of a successor is inconsistent.", MBB);
3255  errs() << "Successor " << printMBBReference(*Succ)
3256  << " has entry state (" << SPState[Succ->getNumber()].EntryValue
3257  << ", " << SPState[Succ->getNumber()].EntryIsSetup << "), while "
3258  << printMBBReference(*MBB) << " has exit state ("
3259  << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
3260  }
3261  }
3262 
3263  // Make sure a basic block with return ends with zero stack adjustment.
3264  if (!MBB->empty() && MBB->back().isReturn()) {
3265  if (BBState.ExitIsSetup)
3266  report("A return block ends with a FrameSetup.", MBB);
3267  if (BBState.ExitValue)
3268  report("A return block ends with a nonzero stack adjustment.", MBB);
3269  }
3270  }
3271 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::LaneBitmask
Definition: LaneBitmask.h:40
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:613
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:243
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:777
llvm::MachineBasicBlock::succ_size
unsigned succ_size() const
Definition: MachineBasicBlock.h:344
llvm::MachineMemOperand::isStore
bool isStore() const
Definition: MachineMemOperand.h:289
Attrs
Function Attrs
Definition: README_ALTIVEC.txt:215
llvm::LiveInterval::computeSubRangeUndefs
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
Definition: LiveInterval.cpp:977
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:221
llvm::MachineFunctionProperties::hasProperty
bool hasProperty(Property P) const
Definition: MachineFunction.h:169
llvm::InlineAsm::MIOp_FirstOperand
@ MIOp_FirstOperand
Definition: InlineAsm.h:220
llvm::MachineBasicBlock::pred_begin
pred_iterator pred_begin()
Definition: MachineBasicBlock.h:316
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
MathExtras.h
llvm::MachineRegisterInfo::def_begin
def_iterator def_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:384
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::LiveStacks::getInterval
LiveInterval & getInterval(int Slot)
Definition: LiveStacks.h:64
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
llvm::LiveRange::empty
bool empty() const
Definition: LiveInterval.h:374
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1595
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:266
llvm::MachineRegisterInfo::shouldTrackSubRegLiveness
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level.
Definition: MachineRegisterInfo.h:214
llvm::SmallPtrSetImpl::erase
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
Definition: SmallPtrSet.h:378
MCTargetOptions.h
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:202
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:213
llvm::LiveIntervals::isLiveInToMBB
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
Definition: LiveIntervals.h:245
llvm::ConstantInt::getBitWidth
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:136
MCInstrDesc.h
SetOperations.h
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::isPreISelGenericOptimizationHint
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
llvm::MCOI::OPERAND_IMMEDIATE
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:58
llvm::Function
Definition: Function.h:62
StringRef.h
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
Pass.h
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::HexagonInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition: HexagonInstrInfo.cpp:389
llvm::BitVector::clear
void clear()
clear - Removes all bits from the bitvector.
Definition: BitVector.h:327
llvm::MachineBasicBlock::instrs
instr_range instrs()
Definition: MachineBasicBlock.h:263
llvm::SlotIndex::getBoundaryIndex
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
Definition: SlotIndexes.h:248
llvm::set_union
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
Definition: SetOperations.h:22
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::LiveIntervals::isNotInMIMap
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
Definition: LiveIntervals.h:221
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:583
llvm::ilist_node_with_parent::getNextNode
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:288
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:731
llvm::TargetRegisterInfo::getMinimalPhysRegClassLLT
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:229
InlineAsm.h
llvm::isPreISelGenericOpcode
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
llvm::TargetRegisterInfo::isInAllocatableClass
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
Definition: TargetRegisterInfo.h:361
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:119
llvm::LiveIntervals::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:231
ErrorHandling.h
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:441
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::LiveQueryResult::isDeadDef
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:117
llvm::LiveRange::Segment
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162
llvm::BitVector::set_bits
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:132
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
MachineBasicBlock.h
INITIALIZE_PASS
INITIALIZE_PASS(MachineVerifierPass, "machineverifier", "Verify generated machine code", false, false) FunctionPass *llvm
Definition: MachineVerifier.cpp:313
stores
hexagon widen stores
Definition: HexagonStoreWidening.cpp:118
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:241
llvm::VNInfo::def
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::LLT::getScalarType
LLT getScalarType() const
Definition: LowLevelTypeImpl.h:168
DenseMap.h
llvm::MachineBasicBlock::liveins
iterator_range< livein_iterator > liveins() const
Definition: MachineBasicBlock.h:412
llvm::AttributeList
Definition: Attributes.h:398
TargetInstrInfo.h
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::HexagonInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
Definition: HexagonInstrInfo.cpp:1578
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
EHPersonalities.h
llvm::ConstantFP::getValueAPF
const APFloat & getValueAPF() const
Definition: Constants.h:297
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:117
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:757
llvm::SmallPtrSet< const MachineBasicBlock *, 8 >
llvm::SlotIndex::isEarlyClobber
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
Definition: SlotIndexes.h:229
llvm::Intrinsic::getAttributes
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
llvm::SlotIndexes::getMBBEndIdx
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:476
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
STLExtras.h
llvm::MachineBasicBlock::back
MachineInstr & back()
Definition: MachineBasicBlock.h:248
llvm::MCRegisterInfo::getNumRegUnits
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
Definition: MCRegisterInfo.h:505
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:331
llvm::LiveQueryResult
Result of a LiveRange query.
Definition: LiveInterval.h:90
llvm::detail::DenseSetImpl::insert
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::APFloat::getSemantics
const fltSemantics & getSemantics() const
Definition: APFloat.h:1223
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
p
the resulting code requires compare and branches when and if * p
Definition: README.txt:396
llvm::LiveIntervals::getMBBFromIndex
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Definition: LiveIntervals.h:255
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
DepthFirstIterator.h
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:52
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:226
llvm::MachineRegisterInfo::use_nodbg_begin
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:518
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::MCRegisterInfo::subregs
iterator_range< mc_subreg_iterator > subregs(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, excluding Reg.
Definition: MCRegisterInfo.h:309
llvm::MachineRegisterInfo::tracksLiveness
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
Definition: MachineRegisterInfo.h:197
llvm::LiveIntervals::print
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Definition: LiveIntervals.cpp:155
isLiveOut
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
Definition: SIOptimizeExecMasking.cpp:286
llvm::classifyEHPersonality
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
Definition: EHPersonalities.cpp:21
llvm::verifyMachineFunction
void verifyMachineFunction(MachineFunctionAnalysisManager *, const std::string &Banner, const MachineFunction &MF)
Definition: MachineVerifier.cpp:320
llvm::df_ext_begin
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
Definition: DepthFirstIterator.h:241
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:83
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::MachineBasicBlock::pred_size
unsigned pred_size() const
Definition: MachineBasicBlock.h:328
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:118
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::APFloatBase::getSizeInBits
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:226
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1581
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:828
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:644
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
llvm::SlotIndexes::hasIndex
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:380
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::LiveStacks::hasInterval
bool hasInterval(int Slot) const
Definition: LiveStacks.h:78
llvm::LiveRange::liveAt
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:393
llvm::MachineFunctionProperties::Property::Selected
@ Selected
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::LiveVariables::VarInfo
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:79
llvm::LiveRange::begin
iterator begin()
Definition: LiveInterval.h:215
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:377
llvm::MCRegisterInfo::subregs_inclusive
iterator_range< mc_subreg_iterator > subregs_inclusive(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, including Reg.
Definition: MCRegisterInfo.h:316
llvm::LiveIntervals::getMBBStartIdx
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
Definition: LiveIntervals.h:236
llvm::LiveIntervals::getCachedRegUnit
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
Definition: LiveIntervals.h:406
llvm::LiveRange::covers
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
Definition: LiveInterval.cpp:494
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::set_subtract
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Definition: SetOperations.h:62
llvm::MachineBasicBlock::succ_end
succ_iterator succ_end()
Definition: MachineBasicBlock.h:334
llvm::Pass::getAnalysisIfAvailable
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Definition: PassAnalysisSupport.h:211
llvm::DstOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:99
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:928
Twine.h
llvm::BitVector::size
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:151
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:153
llvm::MachineOperand::getRegMask
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Definition: MachineOperand.h:630
llvm::MachineBasicBlock::isSuccessor
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
Definition: MachineBasicBlock.cpp:912
llvm::LiveRange::const_iterator
Segments::const_iterator const_iterator
Definition: LiveInterval.h:213
llvm::MachineOperand::MO_FrameIndex
@ MO_FrameIndex
Abstract Stack Frame Index.
Definition: MachineOperand.h:57
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::LaneBitmask::getNone
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:83
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::TargetRegisterInfo::hasRegUnit
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
Definition: TargetRegisterInfo.h:435
b
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
Definition: README.txt:418
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:725
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:329
LiveVariables.h
DenseSet.h
TargetOpcodes.h
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
pass
modulo schedule Modulo Schedule test pass
Definition: ModuloSchedule.cpp:2100
llvm::LiveRange::valnos
VNInfoList valnos
Definition: LiveInterval.h:204
llvm::MachineBasicBlock::RegisterMaskPair
Pair of physical register and lane mask.
Definition: MachineBasicBlock.h:101
MachineInstrBundle.h
llvm::MachineBasicBlock::rend
reverse_iterator rend()
Definition: MachineBasicBlock.h:278
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:138
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::SlotIndexes::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:385
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::PrintLaneMask
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:94
llvm::SmallVectorImpl::resize
void resize(size_type N)
Definition: SmallVector.h:606
llvm::SlotIndex::getDeadSlot
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:259
BitVector.h
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:816
llvm::MachineRegisterInfo::use_nodbg_end
static use_nodbg_iterator use_nodbg_end()
Definition: MachineRegisterInfo.h:521
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:314
llvm::SlotIndex::isRegister
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
Definition: SlotIndexes.h:233
SmallPtrSet.h
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:302
llvm::BitVector
Definition: BitVector.h:74
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:61
llvm::MachineFunction::verify
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
Definition: MachineVerifier.cpp:333
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::MachineRegisterInfo::reservedRegsFrozen
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
Definition: MachineRegisterInfo.h:903
llvm::LiveQueryResult::valueIn
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:105
llvm::MachineFunctionAnalysisManager
An AnalysisManager<MachineFunction> that also exposes IR analysis results.
Definition: MachinePassManager.h:39
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
LowLevelTypeImpl.h
llvm::initializeMachineVerifierPassPass
void initializeMachineVerifierPassPass(PassRegistry &)
llvm::printRegUnit
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
Definition: TargetRegisterInfo.cpp:141
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:426
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:125
llvm::Twine::str
std::string str() const
Return the twine contents as a std::string.
Definition: Twine.cpp:17
llvm::SlotIndexes::MBBIndexEnd
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
Definition: SlotIndexes.h:509
llvm::MachineRegisterInfo::isSSA
bool isSSA() const
Definition: MachineRegisterInfo.h:185
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:111
llvm::MachineFunctionProperties::Property::FailsVerification
@ FailsVerification
LiveIntervalCalc.h
llvm::LLT::getAddressSpace
unsigned getAddressSpace() const
Definition: LowLevelTypeImpl.h:227
llvm::DenseSet
Implements a dense probed hash-table based set.
Definition: DenseSet.h:268
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:634
BasicBlock.h
llvm::ClrHandlerType::Filter
@ Filter
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:617
VI
@ VI
Definition: SIInstrInfo.cpp:7679
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
llvm::LiveRange::getVNInfoBefore
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
Definition: LiveInterval.h:421
llvm::SlotIndexes::getMBBStartIdx
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:466
llvm::MachineBasicBlock::pred_end
pred_iterator pred_end()
Definition: MachineBasicBlock.h:318
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::clear
void clear()
Definition: DenseMap.h:111
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
LiveIntervals.h
llvm::LiveRange
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
llvm::LiveIntervals::getMBBEndIdx
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
Definition: LiveIntervals.h:241
llvm::VNInfo::id
unsigned id
The ID number of this value.
Definition: LiveInterval.h:58
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:745
llvm::ARM_AM::add
@ add
Definition: ARMAddressingModes.h:39
llvm::MCOperandInfo::isGenericType
bool isGenericType() const
Definition: MCInstrDesc.h:116
llvm::SlotIndexes::MBBIndexBegin
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
Definition: SlotIndexes.h:504
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:95
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap
Definition: DenseMap.h:714
llvm::LiveRange::getNumValNums
unsigned getNumValNums() const
Definition: LiveInterval.h:305
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:385
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::LaneBitmask::any
constexpr bool any() const
Definition: LaneBitmask.h:53
llvm::isScopedEHPersonality
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
Definition: EHPersonalities.h:80
llvm::MCOI::OPERAND_REGISTER
@ OPERAND_REGISTER
Definition: MCInstrDesc.h:59
MCRegisterInfo.h
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:123
llvm::SmallPtrSetImpl::begin
iterator begin() const
Definition: SmallPtrSet.h:402
llvm::LLT::getNumElements
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelTypeImpl.h:127
llvm::createMachineVerifierPass
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
llvm::SlotIndex::isSameInstr
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:197
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1646
llvm::LiveRange::Query
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:533
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:219
MachineFunctionPass.h
llvm::MachineFunctionProperties::Property::RegBankSelected
@ RegBankSelected
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MIBundleOperandIteratorBase::isValid
bool isValid() const
isValid - Returns true until all the operands have been visited.
Definition: MachineInstrBundle.h:136
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:651
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:542
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:121
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1639
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:332
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:436
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition: MachineOperand.h:593
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineBasicBlock::predecessors
iterator_range< pred_iterator > predecessors()
Definition: MachineBasicBlock.h:349
llvm::ErrorInfo
Base class for user error types.
Definition: Error.h:349
llvm::MachineRegisterInfo::def_end
static def_iterator def_end()
Definition: MachineRegisterInfo.h:387
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:813
isStore
static bool isStore(int Opcode)
Definition: ARCInstrInfo.cpp:58
llvm::LLT::isScalar
bool isScalar() const
Definition: LowLevelTypeImpl.h:119
llvm::SlotIndex::getRegSlot
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:254
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::SmallPtrSetImpl::count
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:382
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::df_iterator_default_set
Definition: DepthFirstIterator.h:69
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1562
llvm::MachineOperand::isShuffleMask
bool isShuffleMask() const
Definition: MachineOperand.h:354
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:478
llvm::SmallPtrSetImplBase::clear
void clear()
Definition: SmallPtrSet.h:94
llvm::MachineBasicBlock::phis
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
Definition: MachineBasicBlock.h:296
llvm::ArrayRef< int >
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:1056
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:171
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:355
llvm::MachineBasicBlock::isEHPad
bool isEHPad() const
Returns true if the block is a landing pad.
Definition: MachineBasicBlock.h:526
isLoad
static bool isLoad(int Opcode)
Definition: ARCInstrInfo.cpp:53
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineBasicBlock::rbegin
reverse_iterator rbegin()
Definition: MachineBasicBlock.h:272
llvm::LaneBitmask::none
constexpr bool none() const
Definition: LaneBitmask.h:52
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineOperand::isIntrinsicID
bool isIntrinsicID() const
Definition: MachineOperand.h:352
uint32_t
llvm::append_range
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
Definition: STLExtras.h:1778
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:56
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
TargetSubtargetInfo.h
verify
ppc ctr loops verify
Definition: PPCCTRLoops.cpp:76
llvm::MachineFrameInfo::getPristineRegs
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
Definition: MachineFrameInfo.cpp:115
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:847
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MachineFunctionProperties::Property::TiedOpsRewritten
@ TiedOpsRewritten
llvm::MCInstrDesc::variadicOpsAreDefs
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:409
llvm::df_ext_end
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Definition: DepthFirstIterator.h:246
llvm::LiveInterval::SubRange
A live range for subregisters.
Definition: LiveInterval.h:687
llvm::MachineRegisterInfo::getReservedRegs
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
Definition: MachineRegisterInfo.h:917
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SmallPtrSetImplBase::size
size_type size() const
Definition: SmallPtrSet.h:92
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::VNInfo::isPHIDef
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:78
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LiveRangeCalc::isJointlyDominated
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
Definition: LiveRangeCalc.cpp:434
llvm::MCOperandInfo::getGenericTypeIndex
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:121
llvm::MachineFunctionProperties::Property::FailedISel
@ FailedISel
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:447
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:491
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
std
Definition: BitVector.h:838
llvm::MachineFunctionProperties::Property::NoPHIs
@ NoPHIs
llvm::MachineOperand::readsReg
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Definition: MachineOperand.h:458
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:276
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:630
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::ConstMIBundleOperands
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
Definition: MachineInstrBundle.h:185
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::RegisterBank::getName
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:51
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:236
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:557
llvm::LLT::getSizeInBytes
TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelTypeImpl.h:163
llvm::RegisterBank::getSize
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:54
Casting.h
llvm::FixedStackPseudoSourceValue
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
Definition: PseudoSourceValue.h:94
Function.h
llvm::MachineFunction::print
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
Definition: MachineFunction.cpp:546
llvm::SlotIndexes::MBBIndexIterator
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
Definition: SlotIndexes.h:487
llvm::MachineRegisterInfo::getRegBankOrNull
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
Definition: MachineRegisterInfo.h:660
StackMaps.h
llvm::LiveRange::getValNumInfo
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
Definition: LiveInterval.h:309
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::LiveRange::getVNInfoAt
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:413
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::ReversePostOrderTraversal
Definition: PostOrderIterator.h:290
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:446
LiveInterval.h
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:762
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:677
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:217
Instructions.h
PostOrderIterator.h
SmallVector.h
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:339
LiveStacks.h
RegisterBank.h
llvm::SmallPtrSetImplBase::empty
LLVM_NODISCARD bool empty() const
Definition: SmallPtrSet.h:91
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::DstOp
Definition: MachineIRBuilder.h:58
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:711
llvm::LiveInterval::hasSubRanges
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:797
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::df_ext_iterator
Definition: DepthFirstIterator.h:235
llvm::LiveVariables::getVarInfo
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
Definition: LiveVariables.cpp:84
LaneBitmask.h
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:431
MachineMemOperand.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
MachineOperand.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::LiveVariables
Definition: LiveVariables.h:46
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:34
llvm::VNInfo::isUnused
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:81
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:125
llvm::MachineRegisterInfo::isReservedRegUnit
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
Definition: MachineRegisterInfo.cpp:638
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:64
SlotIndexes.h
llvm::LLT::getElementType
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelTypeImpl.h:237
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:377
raw_ostream.h
llvm::MachineFunction::empty
bool empty() const
Definition: MachineFunction.h:827
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:210
llvm::MachineInstr::isBarrier
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:838
llvm::ConnectedVNInfoEqClasses
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
Definition: LiveInterval.h:992
InitializePasses.h
llvm::LiveStacks
Definition: LiveStacks.h:31
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
TargetRegisterInfo.h
llvm::MachineBasicBlock::getName
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
Definition: MachineBasicBlock.cpp:313
llvm::LiveQueryResult::isKill
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:112
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::LaneBitmask::getAll
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:84
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SrcOp
Definition: MachineIRBuilder.h:119
llvm::LiveRange::end
iterator end()
Definition: LiveInterval.h:216
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
llvm::MachineRegisterInfo::verifyUseLists
void verifyUseLists() const
Verify the use list of all registers.
Definition: MachineRegisterInfo.cpp:255
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:213
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:364
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::MCRegisterInfo::getSubRegIdxSize
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
Definition: MCRegisterInfo.cpp:56
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::LiveInterval::subranges
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:769