92 struct MachineVerifier {
93 MachineVerifier(
Pass *
pass,
const char *b) : PASS(
pass), Banner(
b) {}
98 : Banner(
b), LiveVars(LiveVars), LiveInts(LiveInts), LiveStks(LiveStks),
103 Pass *
const PASS =
nullptr;
112 unsigned foundErrors = 0;
115 bool isFunctionRegBankSelected =
false;
116 bool isFunctionSelected =
false;
117 bool isFunctionTracksDebugUserValues =
false;
127 BlockSet FunctionBlocks;
131 RegVector regsDefined, regsDead, regsKilled;
132 RegMaskVector regMasks;
137 void addRegWithSubRegs(RegVector &RV,
Register Reg) {
139 if (
Reg.isPhysical())
145 bool reachable =
false;
166 RegSet vregsRequired;
169 BlockSet Preds, Succs;
176 if (!
Reg.isVirtual())
178 if (regsLiveOut.count(Reg))
180 return vregsRequired.insert(Reg).second;
184 bool addRequired(
const RegSet &RS) {
185 bool Changed =
false;
187 Changed |= addRequired(Reg);
192 bool addRequired(
const RegMap &RM) {
193 bool Changed =
false;
194 for (
const auto &
I : RM)
195 Changed |= addRequired(
I.first);
201 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
209 return Reg.id() < regsReserved.
size() && regsReserved.
test(
Reg.id());
212 bool isAllocatable(
Register Reg)
const {
213 return Reg.id() <
TRI->getNumRegs() &&
TRI->isInAllocatableClass(Reg) &&
223 void visitMachineFunctionBefore();
239 void visitMachineOperand(
const MachineOperand *MO,
unsigned MONum);
242 void visitMachineFunctionAfter();
247 void report(
const char *msg,
const MachineOperand *MO,
unsigned MONum,
255 void report_context(
const VNInfo &VNI)
const;
256 void report_context(
SlotIndex Pos)
const;
257 void report_context(
MCPhysReg PhysReg)
const;
258 void report_context_liverange(
const LiveRange &LR)
const;
259 void report_context_lanemask(
LaneBitmask LaneMask)
const;
260 void report_context_vreg(
Register VReg)
const;
261 void report_context_vreg_regunit(
Register VRegOrUnit)
const;
272 Register VRegOrUnit,
bool SubRangeCheck =
false,
276 void calcRegsPassed();
279 void calcRegsRequired();
280 void verifyLiveVariables();
281 void verifyLiveIntervals();
285 void verifyLiveRangeSegment(
const LiveRange &,
291 void verifyStackFrame();
293 void verifySlotIndexes()
const;
300 const std::string Banner;
302 MachineVerifierPass(std::string banner = std::string())
321 MachineFunctionProperties::Property::FailsVerification))
324 unsigned FoundErrors = MachineVerifier(
this, Banner.c_str()).verify(MF);
333char MachineVerifierPass::ID = 0;
336 "Verify generated machine code",
false,
false)
339 return new MachineVerifierPass(Banner);
343 const std::string &Banner,
350 unsigned FoundErrors = MachineVerifier(
nullptr, Banner.c_str()).verify(MF);
358 unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
359 if (AbortOnErrors && FoundErrors)
361 return FoundErrors == 0;
365 const char *Banner,
bool AbortOnErrors)
const {
367 unsigned FoundErrors =
368 MachineVerifier(Banner,
nullptr, LiveInts,
nullptr, Indexes).verify(MF);
369 if (AbortOnErrors && FoundErrors)
371 return FoundErrors == 0;
374void MachineVerifier::verifySlotIndexes()
const {
375 if (Indexes ==
nullptr)
393 MRI->getNumVirtRegs())
394 report(
"Function has NoVRegs property but there are VReg operands", &MF);
413 if (isFunctionFailedISel)
434 verifyProperties(MF);
436 visitMachineFunctionBefore();
438 visitMachineBasicBlockBefore(&
MBB);
442 bool InBundle =
false;
445 if (
MI.getParent() != &
MBB) {
446 report(
"Bad instruction parent pointer", &
MBB);
447 errs() <<
"Instruction: " <<
MI;
452 if (InBundle && !
MI.isBundledWithPred())
453 report(
"Missing BundledPred flag, "
454 "BundledSucc was set on predecessor",
456 if (!InBundle &&
MI.isBundledWithPred())
457 report(
"BundledPred flag is set, "
458 "but BundledSucc not set on predecessor",
462 if (!
MI.isInsideBundle()) {
464 visitMachineBundleAfter(CurBundle);
466 visitMachineBundleBefore(CurBundle);
467 }
else if (!CurBundle)
468 report(
"No bundle header", &
MI);
469 visitMachineInstrBefore(&
MI);
470 for (
unsigned I = 0,
E =
MI.getNumOperands();
I !=
E; ++
I) {
472 if (
Op.getParent() != &
MI) {
475 report(
"Instruction has operand with wrong parent set", &
MI);
478 visitMachineOperand(&
Op,
I);
482 InBundle =
MI.isBundledWithSucc();
485 visitMachineBundleAfter(CurBundle);
487 report(
"BundledSucc flag set on last instruction in block", &
MBB.
back());
488 visitMachineBasicBlockAfter(&
MBB);
490 visitMachineFunctionAfter();
503void MachineVerifier::report(
const char *msg,
const MachineFunction *MF) {
506 if (!foundErrors++) {
508 errs() <<
"# " << Banner <<
'\n';
509 if (LiveInts !=
nullptr)
514 errs() <<
"*** Bad machine code: " << msg <<
" ***\n"
515 <<
"- function: " << MF->
getName() <<
"\n";
529void MachineVerifier::report(
const char *msg,
const MachineInstr *
MI) {
531 report(msg,
MI->getParent());
532 errs() <<
"- instruction: ";
538void MachineVerifier::report(
const char *msg,
const MachineOperand *MO,
539 unsigned MONum,
LLT MOVRegType) {
542 errs() <<
"- operand " << MONum <<
": ";
548 report(
Msg.str().c_str(),
MI);
551void MachineVerifier::report_context(
SlotIndex Pos)
const {
552 errs() <<
"- at: " << Pos <<
'\n';
555void MachineVerifier::report_context(
const LiveInterval &LI)
const {
556 errs() <<
"- interval: " << LI <<
'\n';
561 report_context_liverange(LR);
562 report_context_vreg_regunit(VRegUnit);
564 report_context_lanemask(LaneMask);
568 errs() <<
"- segment: " << S <<
'\n';
571void MachineVerifier::report_context(
const VNInfo &VNI)
const {
572 errs() <<
"- ValNo: " << VNI.
id <<
" (def " << VNI.
def <<
")\n";
575void MachineVerifier::report_context_liverange(
const LiveRange &LR)
const {
576 errs() <<
"- liverange: " << LR <<
'\n';
579void MachineVerifier::report_context(
MCPhysReg PReg)
const {
583void MachineVerifier::report_context_vreg(
Register VReg)
const {
587void MachineVerifier::report_context_vreg_regunit(
Register VRegOrUnit)
const {
589 report_context_vreg(VRegOrUnit);
595void MachineVerifier::report_context_lanemask(
LaneBitmask LaneMask)
const {
600 BBInfo &MInfo = MBBInfoMap[
MBB];
601 if (!MInfo.reachable) {
602 MInfo.reachable =
true;
608void MachineVerifier::visitMachineFunctionBefore() {
610 regsReserved =
MRI->reservedRegsFrozen() ?
MRI->getReservedRegs()
611 :
TRI->getReservedRegs(*MF);
614 markReachable(&MF->
front());
617 FunctionBlocks.clear();
618 for (
const auto &
MBB : *MF) {
619 FunctionBlocks.insert(&
MBB);
620 BBInfo &MInfo = MBBInfoMap[&
MBB];
624 report(
"MBB has duplicate entries in its predecessor list.", &
MBB);
628 report(
"MBB has duplicate entries in its successor list.", &
MBB);
632 MRI->verifyUseLists();
640 FirstTerminator =
nullptr;
641 FirstNonPHI =
nullptr;
643 if (!MF->getProperties().hasProperty(
648 if (isAllocatable(LI.PhysReg) && !
MBB->
isEHPad() &&
651 report(
"MBB has allocatable live-in, but isn't entry, landing-pad, or "
652 "inlineasm-br-indirect-target.",
654 report_context(LI.PhysReg);
661 report(
"ir-block-address-taken is associated with basic block not used by "
670 LandingPadSuccs.
insert(succ);
671 if (!FunctionBlocks.count(succ))
672 report(
"MBB has successor that isn't part of the function.",
MBB);
673 if (!MBBInfoMap[succ].Preds.count(
MBB)) {
674 report(
"Inconsistent CFG",
MBB);
675 errs() <<
"MBB is not in the predecessor list of the successor "
682 if (!FunctionBlocks.count(Pred))
683 report(
"MBB has predecessor that isn't part of the function.",
MBB);
684 if (!MBBInfoMap[Pred].Succs.count(
MBB)) {
685 report(
"Inconsistent CFG",
MBB);
686 errs() <<
"MBB is not in the successor list of the predecessor "
694 if (LandingPadSuccs.
size() > 1 &&
699 report(
"MBB has more than one landing pad successor",
MBB);
712 report(
"MBB exits via unconditional fall-through but ends with a "
713 "barrier instruction!",
MBB);
716 report(
"MBB exits via unconditional fall-through but has a condition!",
719 }
else if (
TBB && !FBB &&
Cond.empty()) {
722 report(
"MBB exits via unconditional branch but doesn't contain "
723 "any instructions!",
MBB);
725 report(
"MBB exits via unconditional branch but doesn't end with a "
726 "barrier instruction!",
MBB);
728 report(
"MBB exits via unconditional branch but the branch isn't a "
729 "terminator instruction!",
MBB);
731 }
else if (
TBB && !FBB && !
Cond.empty()) {
734 report(
"MBB exits via conditional branch/fall-through but doesn't "
735 "contain any instructions!",
MBB);
737 report(
"MBB exits via conditional branch/fall-through but ends with a "
738 "barrier instruction!",
MBB);
740 report(
"MBB exits via conditional branch/fall-through but the branch "
741 "isn't a terminator instruction!",
MBB);
743 }
else if (
TBB && FBB) {
747 report(
"MBB exits via conditional branch/branch but doesn't "
748 "contain any instructions!",
MBB);
750 report(
"MBB exits via conditional branch/branch but doesn't end with a "
751 "barrier instruction!",
MBB);
753 report(
"MBB exits via conditional branch/branch but the branch "
754 "isn't a terminator instruction!",
MBB);
757 report(
"MBB exits via conditional branch/branch but there's no "
761 report(
"analyzeBranch returned invalid data!",
MBB);
767 report(
"MBB exits via jump or conditional branch, but its target isn't a "
771 report(
"MBB exits via conditional branch, but its target isn't a CFG "
778 bool Fallthrough = !
TBB || (!
Cond.empty() && !FBB);
783 if (!
Cond.empty() && !FBB) {
786 report(
"MBB conditionally falls through out of function!",
MBB);
788 report(
"MBB exits via conditional branch/fall-through but the CFG "
789 "successors don't match the actual successors!",
796 if (SuccMBB ==
TBB || SuccMBB == FBB)
804 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
806 report(
"MBB has unexpected successors which are not branch targets, "
807 "fallthrough, EHPads, or inlineasm_br targets.",
813 if (
MRI->tracksLiveness()) {
816 report(
"MBB live-in list contains non-physical register",
MBB);
840void MachineVerifier::visitMachineBundleBefore(
const MachineInstr *
MI) {
843 if (!(idx > lastIndex)) {
844 report(
"Instruction index out of order",
MI);
845 errs() <<
"Last instruction was at " << lastIndex <<
'\n';
851 if (
MI->isTerminator()) {
852 if (!FirstTerminator)
853 FirstTerminator =
MI;
854 }
else if (FirstTerminator) {
857 if (FirstTerminator->
getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
858 report(
"Non-terminator instruction after the first terminator",
MI);
859 errs() <<
"First terminator was:\t" << *FirstTerminator;
868 if (
MI->getNumOperands() < 2) {
869 report(
"Too few operands on inline asm",
MI);
872 if (!
MI->getOperand(0).isSymbol())
873 report(
"Asm string must be an external symbol",
MI);
874 if (!
MI->getOperand(1).isImm())
875 report(
"Asm flags must be an immediate",
MI);
879 if (!isUInt<6>(
MI->getOperand(1).getImm()))
880 report(
"Unknown asm flags", &
MI->getOperand(1), 1);
886 for (
unsigned e =
MI->getNumOperands(); OpNo <
e; OpNo += NumOps) {
892 NumOps = 1 +
F.getNumOperandRegisters();
895 if (OpNo >
MI->getNumOperands())
896 report(
"Missing operands in last group",
MI);
899 if (OpNo < MI->getNumOperands() &&
MI->getOperand(OpNo).isMetadata())
903 for (
unsigned e =
MI->getNumOperands(); OpNo < e; ++OpNo) {
906 report(
"Expected implicit register after groups", &MO, OpNo);
909 if (
MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
922 if (!IndirectTargetMBB) {
923 report(
"INLINEASM_BR indirect target does not exist", &MO, i);
928 report(
"INLINEASM_BR indirect target missing from successor list", &MO,
932 report(
"INLINEASM_BR indirect target predecessor list missing parent",
938bool MachineVerifier::verifyAllRegOpsScalar(
const MachineInstr &
MI,
943 const auto Reg = Op.getReg();
944 if (Reg.isPhysical())
946 return !MRI.getType(Reg).isScalar();
949 report(
"All register operands must have scalar types", &
MI);
956bool MachineVerifier::verifyVectorElementMatch(
LLT Ty0,
LLT Ty1,
959 report(
"operand types must be all-vector or all-scalar",
MI);
969 report(
"operand types must preserve number of vector elements",
MI);
976bool MachineVerifier::verifyGIntrinsicSideEffects(
const MachineInstr *
MI) {
978 bool NoSideEffects =
Opcode == TargetOpcode::G_INTRINSIC ||
979 Opcode == TargetOpcode::G_INTRINSIC_CONVERGENT;
980 unsigned IntrID = cast<GIntrinsic>(
MI)->getIntrinsicID();
981 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
983 MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
984 bool DeclHasSideEffects = !
Attrs.getMemoryEffects().doesNotAccessMemory();
985 if (NoSideEffects && DeclHasSideEffects) {
987 " used with intrinsic that accesses memory"),
991 if (!NoSideEffects && !DeclHasSideEffects) {
1000bool MachineVerifier::verifyGIntrinsicConvergence(
const MachineInstr *
MI) {
1002 bool NotConvergent =
Opcode == TargetOpcode::G_INTRINSIC ||
1003 Opcode == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;
1004 unsigned IntrID = cast<GIntrinsic>(
MI)->getIntrinsicID();
1005 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1007 MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
1008 bool DeclIsConvergent =
Attrs.hasFnAttr(Attribute::Convergent);
1009 if (NotConvergent && DeclIsConvergent) {
1010 report(
Twine(
TII->getName(
Opcode),
" used with a convergent intrinsic"),
1014 if (!NotConvergent && !DeclIsConvergent) {
1016 Twine(
TII->getName(
Opcode),
" used with a non-convergent intrinsic"),
1025void MachineVerifier::verifyPreISelGenericInstruction(
const MachineInstr *
MI) {
1026 if (isFunctionSelected)
1027 report(
"Unexpected generic instruction in a Selected function",
MI);
1030 unsigned NumOps =
MI->getNumOperands();
1033 if (
MI->isBranch() && !
MI->isIndirectBranch()) {
1034 bool HasMBB =
false;
1043 report(
"Branch instruction is missing a basic block operand or "
1044 "isIndirectBranch property",
1053 if (!MCID.
operands()[
I].isGenericType())
1057 size_t TypeIdx = MCID.
operands()[
I].getGenericTypeIndex();
1058 Types.resize(std::max(TypeIdx + 1,
Types.size()));
1062 report(
"generic instruction must use register operands",
MI);
1072 if (!Types[TypeIdx].
isValid())
1073 Types[TypeIdx] = OpTy;
1074 else if (Types[TypeIdx] != OpTy)
1075 report(
"Type mismatch in generic instruction", MO,
I, OpTy);
1078 report(
"Generic instruction is missing a virtual register type", MO,
I);
1083 for (
unsigned I = 0;
I <
MI->getNumOperands(); ++
I) {
1086 report(
"Generic instruction cannot have physical register", MO,
I);
1098 unsigned Opc =
MI->getOpcode();
1100 case TargetOpcode::G_ASSERT_SEXT:
1101 case TargetOpcode::G_ASSERT_ZEXT: {
1102 std::string OpcName =
1103 Opc == TargetOpcode::G_ASSERT_ZEXT ?
"G_ASSERT_ZEXT" :
"G_ASSERT_SEXT";
1104 if (!
MI->getOperand(2).isImm()) {
1105 report(
Twine(OpcName,
" expects an immediate operand #2"),
MI);
1111 LLT SrcTy =
MRI->getType(Src);
1112 int64_t
Imm =
MI->getOperand(2).getImm();
1114 report(
Twine(OpcName,
" size must be >= 1"),
MI);
1119 report(
Twine(OpcName,
" size must be less than source bit width"),
MI);
1127 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1128 report(
Twine(OpcName,
" cannot change register bank"),
MI);
1134 if (DstRC && DstRC !=
MRI->getRegClassOrNull(Src)) {
1136 Twine(OpcName,
" source and destination register classes must match"),
1144 case TargetOpcode::G_CONSTANT:
1145 case TargetOpcode::G_FCONSTANT: {
1146 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1148 report(
"Instruction cannot use a vector result type",
MI);
1150 if (
MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1151 if (!
MI->getOperand(1).isCImm()) {
1152 report(
"G_CONSTANT operand must be cimm",
MI);
1158 report(
"inconsistent constant size",
MI);
1160 if (!
MI->getOperand(1).isFPImm()) {
1161 report(
"G_FCONSTANT operand must be fpimm",
MI);
1168 report(
"inconsistent constant size",
MI);
1174 case TargetOpcode::G_LOAD:
1175 case TargetOpcode::G_STORE:
1176 case TargetOpcode::G_ZEXTLOAD:
1177 case TargetOpcode::G_SEXTLOAD: {
1178 LLT ValTy =
MRI->getType(
MI->getOperand(0).getReg());
1179 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1181 report(
"Generic memory instruction must access a pointer",
MI);
1185 if (!
MI->hasOneMemOperand()) {
1186 report(
"Generic instruction accessing memory must have one mem operand",
1190 if (
MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1191 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1193 report(
"Generic extload must have a narrower memory type",
MI);
1194 }
else if (
MI->getOpcode() == TargetOpcode::G_LOAD) {
1196 report(
"load memory size cannot exceed result size",
MI);
1197 }
else if (
MI->getOpcode() == TargetOpcode::G_STORE) {
1199 report(
"store memory size cannot exceed value size",
MI);
1203 if (Opc == TargetOpcode::G_STORE) {
1206 report(
"atomic store cannot use acquire ordering",
MI);
1211 report(
"atomic load cannot use release ordering",
MI);
1217 case TargetOpcode::G_PHI: {
1218 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1223 LLT Ty = MRI->getType(MO.getReg());
1224 if (!Ty.isValid() || (Ty != DstTy))
1228 report(
"Generic Instruction G_PHI has operands with incompatible/missing "
1233 case TargetOpcode::G_BITCAST: {
1234 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1235 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1240 report(
"bitcast cannot convert between pointers and other types",
MI);
1243 report(
"bitcast sizes must match",
MI);
1246 report(
"bitcast must change the type",
MI);
1250 case TargetOpcode::G_INTTOPTR:
1251 case TargetOpcode::G_PTRTOINT:
1252 case TargetOpcode::G_ADDRSPACE_CAST: {
1253 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1254 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1258 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1263 if (
MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1265 report(
"inttoptr result type must be a pointer",
MI);
1267 report(
"inttoptr source type must not be a pointer",
MI);
1268 }
else if (
MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1270 report(
"ptrtoint source type must be a pointer",
MI);
1272 report(
"ptrtoint result type must not be a pointer",
MI);
1274 assert(
MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1276 report(
"addrspacecast types must be pointers",
MI);
1279 report(
"addrspacecast must convert different address spaces",
MI);
1285 case TargetOpcode::G_PTR_ADD: {
1286 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1287 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1288 LLT OffsetTy =
MRI->getType(
MI->getOperand(2).getReg());
1293 report(
"gep first operand must be a pointer",
MI);
1296 report(
"gep offset operand must not be a pointer",
MI);
1301 case TargetOpcode::G_PTRMASK: {
1302 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1303 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1304 LLT MaskTy =
MRI->getType(
MI->getOperand(2).getReg());
1309 report(
"ptrmask result type must be a pointer",
MI);
1312 report(
"ptrmask mask type must be an integer",
MI);
1314 verifyVectorElementMatch(DstTy, MaskTy,
MI);
1317 case TargetOpcode::G_SEXT:
1318 case TargetOpcode::G_ZEXT:
1319 case TargetOpcode::G_ANYEXT:
1320 case TargetOpcode::G_TRUNC:
1321 case TargetOpcode::G_FPEXT:
1322 case TargetOpcode::G_FPTRUNC: {
1329 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1330 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1337 report(
"Generic extend/truncate can not operate on pointers",
MI);
1339 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1343 switch (
MI->getOpcode()) {
1345 if (DstSize <= SrcSize)
1346 report(
"Generic extend has destination type no larger than source",
MI);
1348 case TargetOpcode::G_TRUNC:
1349 case TargetOpcode::G_FPTRUNC:
1350 if (DstSize >= SrcSize)
1351 report(
"Generic truncate has destination type no smaller than source",
1357 case TargetOpcode::G_SELECT: {
1358 LLT SelTy =
MRI->getType(
MI->getOperand(0).getReg());
1359 LLT CondTy =
MRI->getType(
MI->getOperand(1).getReg());
1365 verifyVectorElementMatch(SelTy, CondTy,
MI);
1368 case TargetOpcode::G_MERGE_VALUES: {
1373 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1374 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1376 report(
"G_MERGE_VALUES cannot operate on vectors",
MI);
1378 const unsigned NumOps =
MI->getNumOperands();
1380 report(
"G_MERGE_VALUES result size is inconsistent",
MI);
1382 for (
unsigned I = 2;
I != NumOps; ++
I) {
1383 if (
MRI->getType(
MI->getOperand(
I).getReg()) != SrcTy)
1384 report(
"G_MERGE_VALUES source types do not match",
MI);
1389 case TargetOpcode::G_UNMERGE_VALUES: {
1390 unsigned NumDsts =
MI->getNumOperands() - 1;
1391 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1392 for (
unsigned i = 1; i < NumDsts; ++i) {
1393 if (
MRI->getType(
MI->getOperand(i).getReg()) != DstTy) {
1394 report(
"G_UNMERGE_VALUES destination types do not match",
MI);
1399 LLT SrcTy =
MRI->getType(
MI->getOperand(NumDsts).getReg());
1404 report(
"G_UNMERGE_VALUES source operand does not match vector "
1405 "destination operands",
1412 report(
"G_UNMERGE_VALUES vector source operand does not match scalar "
1413 "destination operands",
1418 report(
"G_UNMERGE_VALUES scalar source operand does not match scalar "
1419 "destination operands",
1425 case TargetOpcode::G_BUILD_VECTOR: {
1428 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1429 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1431 report(
"G_BUILD_VECTOR must produce a vector from scalar operands",
MI);
1436 report(
"G_BUILD_VECTOR result element type must match source type",
MI);
1439 report(
"G_BUILD_VECTOR must have an operand for each elemement",
MI);
1442 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1443 report(
"G_BUILD_VECTOR source operand types are not homogeneous",
MI);
1447 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1450 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1451 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1453 report(
"G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1456 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1457 report(
"G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1460 report(
"G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1465 case TargetOpcode::G_CONCAT_VECTORS: {
1468 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1469 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1471 report(
"G_CONCAT_VECTOR requires vector source and destination operands",
1474 if (
MI->getNumOperands() < 3)
1475 report(
"G_CONCAT_VECTOR requires at least 2 source operands",
MI);
1478 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1479 report(
"G_CONCAT_VECTOR source operand types are not homogeneous",
MI);
1482 report(
"G_CONCAT_VECTOR num dest and source elements should match",
MI);
1485 case TargetOpcode::G_ICMP:
1486 case TargetOpcode::G_FCMP: {
1487 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1488 LLT SrcTy =
MRI->getType(
MI->getOperand(2).getReg());
1492 report(
"Generic vector icmp/fcmp must preserve number of lanes",
MI);
1496 case TargetOpcode::G_EXTRACT: {
1498 if (!
SrcOp.isReg()) {
1499 report(
"extract source must be a register",
MI);
1504 if (!OffsetOp.
isImm()) {
1505 report(
"extract offset must be a constant",
MI);
1509 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1511 if (SrcSize == DstSize)
1512 report(
"extract source must be larger than result",
MI);
1514 if (DstSize + OffsetOp.
getImm() > SrcSize)
1515 report(
"extract reads past end of register",
MI);
1518 case TargetOpcode::G_INSERT: {
1520 if (!
SrcOp.isReg()) {
1521 report(
"insert source must be a register",
MI);
1526 if (!OffsetOp.
isImm()) {
1527 report(
"insert offset must be a constant",
MI);
1531 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1534 if (DstSize <= SrcSize)
1535 report(
"inserted size must be smaller than total register",
MI);
1537 if (SrcSize + OffsetOp.
getImm() > DstSize)
1538 report(
"insert writes past end of register",
MI);
1542 case TargetOpcode::G_JUMP_TABLE: {
1543 if (!
MI->getOperand(1).isJTI())
1544 report(
"G_JUMP_TABLE source operand must be a jump table index",
MI);
1545 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1547 report(
"G_JUMP_TABLE dest operand must have a pointer type",
MI);
1550 case TargetOpcode::G_BRJT: {
1551 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
1552 report(
"G_BRJT src operand 0 must be a pointer type",
MI);
1554 if (!
MI->getOperand(1).isJTI())
1555 report(
"G_BRJT src operand 1 must be a jump table index",
MI);
1557 const auto &IdxOp =
MI->getOperand(2);
1558 if (!IdxOp.isReg() ||
MRI->getType(IdxOp.getReg()).isPointer())
1559 report(
"G_BRJT src operand 2 must be a scalar reg type",
MI);
1562 case TargetOpcode::G_INTRINSIC:
1563 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
1564 case TargetOpcode::G_INTRINSIC_CONVERGENT:
1565 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: {
1570 report(
"G_INTRINSIC first src operand must be an intrinsic ID",
MI);
1574 if (!verifyGIntrinsicSideEffects(
MI))
1576 if (!verifyGIntrinsicConvergence(
MI))
1581 case TargetOpcode::G_SEXT_INREG: {
1582 if (!
MI->getOperand(2).isImm()) {
1583 report(
"G_SEXT_INREG expects an immediate operand #2",
MI);
1587 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1588 int64_t
Imm =
MI->getOperand(2).getImm();
1590 report(
"G_SEXT_INREG size must be >= 1",
MI);
1592 report(
"G_SEXT_INREG size must be less than source bit width",
MI);
1595 case TargetOpcode::G_BSWAP: {
1596 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1598 report(
"G_BSWAP size must be a multiple of 16 bits",
MI);
1601 case TargetOpcode::G_SHUFFLE_VECTOR: {
1604 report(
"Incorrect mask operand type for G_SHUFFLE_VECTOR",
MI);
1608 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1609 LLT Src0Ty =
MRI->getType(
MI->getOperand(1).getReg());
1610 LLT Src1Ty =
MRI->getType(
MI->getOperand(2).getReg());
1612 if (Src0Ty != Src1Ty)
1613 report(
"Source operands must be the same type",
MI);
1616 report(
"G_SHUFFLE_VECTOR cannot change element type",
MI);
1625 if (
static_cast<int>(MaskIdxes.
size()) != DstNumElts)
1626 report(
"Wrong result type for shufflemask",
MI);
1628 for (
int Idx : MaskIdxes) {
1632 if (
Idx >= 2 * SrcNumElts)
1633 report(
"Out of bounds shuffle index",
MI);
1638 case TargetOpcode::G_DYN_STACKALLOC: {
1644 report(
"dst operand 0 must be a pointer type",
MI);
1648 if (!AllocOp.
isReg() || !
MRI->getType(AllocOp.
getReg()).isScalar()) {
1649 report(
"src operand 1 must be a scalar reg type",
MI);
1653 if (!AlignOp.
isImm()) {
1654 report(
"src operand 2 must be an immediate type",
MI);
1659 case TargetOpcode::G_MEMCPY_INLINE:
1660 case TargetOpcode::G_MEMCPY:
1661 case TargetOpcode::G_MEMMOVE: {
1663 if (MMOs.
size() != 2) {
1664 report(
"memcpy/memmove must have 2 memory operands",
MI);
1670 report(
"wrong memory operand types",
MI);
1675 report(
"inconsistent memory operand sizes",
MI);
1677 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1678 LLT SrcPtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1681 report(
"memory instruction operand must be a pointer",
MI);
1686 report(
"inconsistent store address space",
MI);
1688 report(
"inconsistent load address space",
MI);
1690 if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1691 if (!
MI->getOperand(3).isImm() || (
MI->getOperand(3).getImm() & ~1LL))
1692 report(
"'tail' flag (operand 3) must be an immediate 0 or 1",
MI);
1696 case TargetOpcode::G_BZERO:
1697 case TargetOpcode::G_MEMSET: {
1699 std::string
Name = Opc == TargetOpcode::G_MEMSET ?
"memset" :
"bzero";
1700 if (MMOs.
size() != 1) {
1701 report(
Twine(
Name,
" must have 1 memory operand"),
MI);
1706 report(
Twine(
Name,
" memory operand must be a store"),
MI);
1710 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1712 report(
Twine(
Name,
" operand must be a pointer"),
MI);
1717 report(
"inconsistent " +
Twine(
Name,
" address space"),
MI);
1719 if (!
MI->getOperand(
MI->getNumOperands() - 1).isImm() ||
1720 (
MI->getOperand(
MI->getNumOperands() - 1).getImm() & ~1LL))
1721 report(
"'tail' flag (last operand) must be an immediate 0 or 1",
MI);
1725 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1726 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1727 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1728 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1729 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1731 report(
"Vector reduction requires a scalar destination type",
MI);
1733 report(
"Sequential FADD/FMUL vector reduction requires a scalar 1st operand",
MI);
1735 report(
"Sequential FADD/FMUL vector reduction must have a vector 2nd operand",
MI);
1738 case TargetOpcode::G_VECREDUCE_FADD:
1739 case TargetOpcode::G_VECREDUCE_FMUL:
1740 case TargetOpcode::G_VECREDUCE_FMAX:
1741 case TargetOpcode::G_VECREDUCE_FMIN:
1742 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1743 case TargetOpcode::G_VECREDUCE_FMINIMUM:
1744 case TargetOpcode::G_VECREDUCE_ADD:
1745 case TargetOpcode::G_VECREDUCE_MUL:
1746 case TargetOpcode::G_VECREDUCE_AND:
1747 case TargetOpcode::G_VECREDUCE_OR:
1748 case TargetOpcode::G_VECREDUCE_XOR:
1749 case TargetOpcode::G_VECREDUCE_SMAX:
1750 case TargetOpcode::G_VECREDUCE_SMIN:
1751 case TargetOpcode::G_VECREDUCE_UMAX:
1752 case TargetOpcode::G_VECREDUCE_UMIN: {
1753 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1755 report(
"Vector reduction requires a scalar destination type",
MI);
1759 case TargetOpcode::G_SBFX:
1760 case TargetOpcode::G_UBFX: {
1761 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1763 report(
"Bitfield extraction is not supported on vectors",
MI);
1768 case TargetOpcode::G_SHL:
1769 case TargetOpcode::G_LSHR:
1770 case TargetOpcode::G_ASHR:
1771 case TargetOpcode::G_ROTR:
1772 case TargetOpcode::G_ROTL: {
1773 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1774 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1776 report(
"Shifts and rotates require operands to be either all scalars or "
1783 case TargetOpcode::G_LLROUND:
1784 case TargetOpcode::G_LROUND: {
1785 verifyAllRegOpsScalar(*
MI, *
MRI);
1788 case TargetOpcode::G_IS_FPCLASS: {
1789 LLT DestTy =
MRI->getType(
MI->getOperand(0).getReg());
1792 report(
"Destination must be a scalar or vector of scalars",
MI);
1795 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1798 report(
"Source must be a scalar or vector of scalars",
MI);
1801 if (!verifyVectorElementMatch(DestTy, SrcTy,
MI))
1804 if (!TestMO.
isImm()) {
1805 report(
"floating-point class set (operand 2) must be an immediate",
MI);
1810 report(
"Incorrect floating-point class set (operand 2)",
MI);
1815 case TargetOpcode::G_ASSERT_ALIGN: {
1816 if (
MI->getOperand(2).getImm() < 1)
1817 report(
"alignment immediate must be >= 1",
MI);
1820 case TargetOpcode::G_CONSTANT_POOL: {
1821 if (!
MI->getOperand(1).isCPI())
1822 report(
"Src operand 1 must be a constant pool index",
MI);
1823 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
1824 report(
"Dst operand 0 must be a pointer",
MI);
1832void MachineVerifier::visitMachineInstrBefore(
const MachineInstr *
MI) {
1835 report(
"Too few operands",
MI);
1837 <<
MI->getNumOperands() <<
" given.\n";
1841 report(
"NoConvergent flag expected only on convergent instructions.",
MI);
1844 if (MF->getProperties().hasProperty(
1846 report(
"Found PHI instruction with NoPHIs property set",
MI);
1849 report(
"Found PHI instruction after non-PHI",
MI);
1850 }
else if (FirstNonPHI ==
nullptr)
1854 if (
MI->isInlineAsm())
1855 verifyInlineAsm(
MI);
1858 if (
TII->isUnspillableTerminator(
MI)) {
1859 if (!
MI->getOperand(0).isReg() || !
MI->getOperand(0).isDef())
1860 report(
"Unspillable Terminator does not define a reg",
MI);
1862 if (
Def.isVirtual() &&
1863 !MF->getProperties().hasProperty(
1865 std::distance(
MRI->use_nodbg_begin(Def),
MRI->use_nodbg_end()) > 1)
1866 report(
"Unspillable Terminator expected to have at most one use!",
MI);
1872 if (
MI->isDebugValue() &&
MI->getNumOperands() == 4)
1873 if (!
MI->getDebugLoc())
1874 report(
"Missing DebugLoc for debug instruction",
MI);
1878 if (
MI->isMetaInstruction() &&
MI->peekDebugInstrNum())
1879 report(
"Metadata instruction should not have a value tracking number",
MI);
1883 if (
Op->isLoad() && !
MI->mayLoad())
1884 report(
"Missing mayLoad flag",
MI);
1885 if (
Op->isStore() && !
MI->mayStore())
1886 report(
"Missing mayStore flag",
MI);
1893 if (
MI->isDebugOrPseudoInstr()) {
1895 report(
"Debug instruction has a slot index",
MI);
1896 }
else if (
MI->isInsideBundle()) {
1898 report(
"Instruction inside bundle has a slot index",
MI);
1901 report(
"Missing slot index",
MI);
1907 verifyPreISelGenericInstruction(
MI);
1916 switch (
MI->getOpcode()) {
1917 case TargetOpcode::COPY: {
1923 LLT DstTy =
MRI->getType(DstReg);
1924 LLT SrcTy =
MRI->getType(SrcReg);
1927 if (SrcTy != DstTy) {
1928 report(
"Copy Instruction is illegal with mismatching types",
MI);
1929 errs() <<
"Def = " << DstTy <<
", Src = " << SrcTy <<
"\n";
1944 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
1946 SrcSize =
TRI->getRegSizeInBits(*SrcRC);
1951 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
1953 DstSize =
TRI->getRegSizeInBits(*DstRC);
1971 if (!
DstOp.getSubReg() && !
SrcOp.getSubReg()) {
1972 report(
"Copy Instruction is illegal with mismatching sizes",
MI);
1973 errs() <<
"Def Size = " << DstSize <<
", Src Size = " << SrcSize
1979 case TargetOpcode::STATEPOINT: {
1981 if (!
MI->getOperand(SO.getIDPos()).isImm() ||
1982 !
MI->getOperand(SO.getNBytesPos()).isImm() ||
1983 !
MI->getOperand(SO.getNCallArgsPos()).isImm()) {
1984 report(
"meta operands to STATEPOINT not constant!",
MI);
1988 auto VerifyStackMapConstant = [&](
unsigned Offset) {
1989 if (
Offset >=
MI->getNumOperands()) {
1990 report(
"stack map constant to STATEPOINT is out of range!",
MI);
1993 if (!
MI->getOperand(
Offset - 1).isImm() ||
1994 MI->getOperand(
Offset - 1).getImm() != StackMaps::ConstantOp ||
1996 report(
"stack map constant to STATEPOINT not well formed!",
MI);
1998 VerifyStackMapConstant(SO.getCCIdx());
1999 VerifyStackMapConstant(SO.getFlagsIdx());
2000 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
2001 VerifyStackMapConstant(SO.getNumGCPtrIdx());
2002 VerifyStackMapConstant(SO.getNumAllocaIdx());
2003 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
2007 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
2008 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
2009 for (
unsigned Idx = 0;
Idx <
MI->getNumDefs();
Idx++) {
2011 if (!
MI->isRegTiedToUseOperand(
Idx, &UseOpIdx)) {
2012 report(
"STATEPOINT defs expected to be tied",
MI);
2015 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
2016 report(
"STATEPOINT def tied to non-gc operand",
MI);
2023 case TargetOpcode::INSERT_SUBREG: {
2024 unsigned InsertedSize;
2025 if (
unsigned SubIdx =
MI->getOperand(2).getSubReg())
2026 InsertedSize =
TRI->getSubRegIdxSize(SubIdx);
2028 InsertedSize =
TRI->getRegSizeInBits(
MI->getOperand(2).getReg(), *
MRI);
2029 unsigned SubRegSize =
TRI->getSubRegIdxSize(
MI->getOperand(3).getImm());
2030 if (SubRegSize < InsertedSize) {
2031 report(
"INSERT_SUBREG expected inserted value to have equal or lesser "
2032 "size than the subreg it was inserted into",
MI);
2036 case TargetOpcode::REG_SEQUENCE: {
2037 unsigned NumOps =
MI->getNumOperands();
2038 if (!(NumOps & 1)) {
2039 report(
"Invalid number of operands for REG_SEQUENCE",
MI);
2043 for (
unsigned I = 1;
I != NumOps;
I += 2) {
2048 report(
"Invalid register operand for REG_SEQUENCE", &RegOp,
I);
2050 if (!SubRegOp.
isImm() || SubRegOp.
getImm() == 0 ||
2051 SubRegOp.
getImm() >=
TRI->getNumSubRegIndices()) {
2052 report(
"Invalid subregister index operand for REG_SEQUENCE",
2057 Register DstReg =
MI->getOperand(0).getReg();
2059 report(
"REG_SEQUENCE does not support physical register results",
MI);
2061 if (
MI->getOperand(0).getSubReg())
2062 report(
"Invalid subreg result for REG_SEQUENCE",
MI);
2070MachineVerifier::visitMachineOperand(
const MachineOperand *MO,
unsigned MONum) {
2074 if (MCID.
getOpcode() == TargetOpcode::PATCHPOINT)
2075 NumDefs = (MONum == 0 && MO->
isReg()) ? NumDefs : 0;
2078 if (MONum < NumDefs) {
2081 report(
"Explicit definition must be a register", MO, MONum);
2083 report(
"Explicit definition marked as use", MO, MONum);
2085 report(
"Explicit definition marked as implicit", MO, MONum);
2094 report(
"Explicit operand marked as def", MO, MONum);
2096 report(
"Explicit operand marked as implicit", MO, MONum);
2102 report(
"Expected a register operand.", MO, MONum);
2106 !
TII->isPCRelRegisterOperandLegal(*MO)))
2107 report(
"Expected a non-register operand.", MO, MONum);
2114 report(
"Tied use must be a register", MO, MONum);
2116 report(
"Operand should be tied", MO, MONum);
2117 else if (
unsigned(TiedTo) !=
MI->findTiedOperandIdx(MONum))
2118 report(
"Tied def doesn't match MCInstrDesc", MO, MONum);
2121 if (!MOTied.
isReg())
2122 report(
"Tied counterpart must be a register", &MOTied, TiedTo);
2125 report(
"Tied physical registers must match.", &MOTied, TiedTo);
2128 report(
"Explicit operand should not be tied", MO, MONum);
2129 }
else if (!
MI->isVariadic()) {
2132 report(
"Extra explicit operand on non-variadic instruction", MO, MONum);
2139 if (
MI->isDebugInstr() && MO->
isUse()) {
2141 report(
"Register operand must be marked debug", MO, MONum);
2143 report(
"Register operand must not be marked debug", MO, MONum);
2149 if (
MRI->tracksLiveness() && !
MI->isDebugInstr())
2150 checkLiveness(MO, MONum);
2154 report(
"Undef virtual register def operands require a subregister", MO, MONum);
2158 unsigned OtherIdx =
MI->findTiedOperandIdx(MONum);
2160 if (!OtherMO.
isReg())
2161 report(
"Must be tied to a register", MO, MONum);
2163 report(
"Missing tie flags on tied operand", MO, MONum);
2164 if (
MI->findTiedOperandIdx(OtherIdx) != MONum)
2165 report(
"Inconsistent tie links", MO, MONum);
2169 report(
"Explicit def tied to explicit use without tie constraint",
2173 report(
"Explicit def should be tied to implicit use", MO, MONum);
2186 if (MF->getProperties().hasProperty(
2188 MO->
isUse() &&
MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2189 Reg !=
MI->getOperand(DefIdx).getReg())
2190 report(
"Two-address instruction operands must be identical", MO, MONum);
2195 if (
Reg.isPhysical()) {
2197 report(
"Illegal subregister index for physical register", MO, MONum);
2202 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2203 if (!DRC->contains(Reg)) {
2204 report(
"Illegal physical register for instruction", MO, MONum);
2206 <<
TRI->getRegClassName(DRC) <<
" register.\n";
2211 if (
MRI->isReserved(Reg)) {
2212 report(
"isRenamable set on reserved register", MO, MONum);
2229 report(
"Generic virtual register use cannot be undef", MO, MONum);
2236 if (isFunctionTracksDebugUserValues || !MO->
isUse() ||
2237 !
MI->isDebugValue() || !
MRI->def_empty(Reg)) {
2239 if (isFunctionSelected) {
2240 report(
"Generic virtual register invalid in a Selected function",
2246 LLT Ty =
MRI->getType(Reg);
2248 report(
"Generic virtual register must have a valid type", MO,
2257 if (!RegBank && isFunctionRegBankSelected) {
2258 report(
"Generic virtual register must have a bank in a "
2259 "RegBankSelected function",
2267 report(
"Register bank is too small for virtual register", MO,
2269 errs() <<
"Register bank " << RegBank->
getName() <<
" too small("
2277 report(
"Generic virtual register does not allow subregister index", MO,
2287 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2288 report(
"Virtual register does not match instruction constraint", MO,
2290 errs() <<
"Expect register class "
2291 <<
TRI->getRegClassName(
2292 TII->getRegClass(MCID, MONum,
TRI, *MF))
2293 <<
" but got nothing\n";
2301 TRI->getSubClassWithSubReg(RC, SubIdx);
2303 report(
"Invalid subregister index for virtual register", MO, MONum);
2304 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2305 <<
" does not support subreg index " << SubIdx <<
"\n";
2309 report(
"Invalid register class for subregister index", MO, MONum);
2310 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2311 <<
" does not fully support subreg index " << SubIdx <<
"\n";
2317 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2320 TRI->getLargestLegalSuperClass(RC, *MF);
2322 report(
"No largest legal super class exists.", MO, MONum);
2325 DRC =
TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2327 report(
"No matching super-reg register class.", MO, MONum);
2332 report(
"Illegal virtual register for instruction", MO, MONum);
2333 errs() <<
"Expected a " <<
TRI->getRegClassName(DRC)
2334 <<
" register, but got a " <<
TRI->getRegClassName(RC)
2349 report(
"PHI operand is not in the CFG", MO, MONum);
2360 bool loads =
MI->mayLoad();
2365 for (
auto *MMO :
MI->memoperands()) {
2367 if (PSV ==
nullptr)
continue;
2369 dyn_cast<FixedStackPseudoSourceValue>(PSV);
2370 if (
Value ==
nullptr)
continue;
2371 if (
Value->getFrameIndex() != FI)
continue;
2380 report(
"Missing fixed stack memoperand.",
MI);
2382 if (loads && !LI.
liveAt(
Idx.getRegSlot(
true))) {
2383 report(
"Instruction loads from dead spill slot", MO, MONum);
2384 errs() <<
"Live stack: " << LI <<
'\n';
2387 report(
"Instruction stores to dead spill slot", MO, MONum);
2388 errs() <<
"Live stack: " << LI <<
'\n';
2394 if (MO->
getCFIIndex() >= MF->getFrameInstructions().size())
2395 report(
"CFI instruction has invalid index", MO, MONum);
2403void MachineVerifier::checkLivenessAtUse(
const MachineOperand *MO,
2414 report(
"No live segment at use", MO, MONum);
2415 report_context_liverange(LR);
2416 report_context_vreg_regunit(VRegOrUnit);
2417 report_context(UseIdx);
2420 report(
"Live range continues after kill flag", MO, MONum);
2421 report_context_liverange(LR);
2422 report_context_vreg_regunit(VRegOrUnit);
2424 report_context_lanemask(LaneMask);
2425 report_context(UseIdx);
2429void MachineVerifier::checkLivenessAtDef(
const MachineOperand *MO,
2444 if (((SubRangeCheck || MO->
getSubReg() == 0) && VNI->def != DefIdx) ||
2446 (VNI->def != DefIdx &&
2447 (!VNI->def.isEarlyClobber() || !DefIdx.
isRegister()))) {
2448 report(
"Inconsistent valno->def", MO, MONum);
2449 report_context_liverange(LR);
2450 report_context_vreg_regunit(VRegOrUnit);
2452 report_context_lanemask(LaneMask);
2453 report_context(*VNI);
2454 report_context(DefIdx);
2457 report(
"No live segment at def", MO, MONum);
2458 report_context_liverange(LR);
2459 report_context_vreg_regunit(VRegOrUnit);
2461 report_context_lanemask(LaneMask);
2462 report_context(DefIdx);
2474 if (SubRangeCheck || MO->
getSubReg() == 0) {
2475 report(
"Live range continues after dead def flag", MO, MONum);
2476 report_context_liverange(LR);
2477 report_context_vreg_regunit(VRegOrUnit);
2479 report_context_lanemask(LaneMask);
2485void MachineVerifier::checkLiveness(
const MachineOperand *MO,
unsigned MONum) {
2488 const unsigned SubRegIdx = MO->
getSubReg();
2491 if (LiveInts &&
Reg.isVirtual()) {
2496 report(
"Live interval for subreg operand has no subranges", MO, MONum);
2498 report(
"Virtual register has no live interval", MO, MONum);
2505 addRegWithSubRegs(regsKilled, Reg);
2510 if (LiveVars &&
Reg.isVirtual() && MO->
isKill() &&
2511 !
MI->isBundledWithPred()) {
2514 report(
"Kill missing from LiveVariables", MO, MONum);
2528 if (
Reg.isPhysical() && !isReserved(Reg)) {
2530 if (
MRI->isReservedRegUnit(Unit))
2533 checkLivenessAtUse(MO, MONum, UseIdx, *LR, Unit);
2537 if (
Reg.isVirtual()) {
2539 checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2543 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2544 :
MRI->getMaxLaneMaskForVReg(Reg);
2547 if ((MOMask & SR.LaneMask).none())
2549 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2552 LiveInMask |= SR.LaneMask;
2555 if ((LiveInMask & MOMask).
none()) {
2556 report(
"No live subrange at use", MO, MONum);
2557 report_context(*LI);
2558 report_context(UseIdx);
2561 if (
MI->isPHI() && LiveInMask != MOMask) {
2562 report(
"Not all lanes of PHI source live at use", MO, MONum);
2563 report_context(*LI);
2564 report_context(UseIdx);
2571 if (!regsLive.count(Reg)) {
2572 if (
Reg.isPhysical()) {
2574 bool Bad = !isReserved(Reg);
2579 if (regsLive.count(
SubReg)) {
2591 if (!MOP.isReg() || !MOP.isImplicit())
2594 if (!MOP.getReg().isPhysical())
2602 report(
"Using an undefined physical register", MO, MONum);
2603 }
else if (
MRI->def_empty(Reg)) {
2604 report(
"Reading virtual register without a def", MO, MONum);
2606 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2610 if (MInfo.regsKilled.count(Reg))
2611 report(
"Using a killed virtual register", MO, MONum);
2612 else if (!
MI->isPHI())
2613 MInfo.vregsLiveIn.insert(std::make_pair(Reg,
MI));
2622 addRegWithSubRegs(regsDead, Reg);
2624 addRegWithSubRegs(regsDefined, Reg);
2627 if (
MRI->isSSA() &&
Reg.isVirtual() &&
2628 std::next(
MRI->def_begin(Reg)) !=
MRI->def_end())
2629 report(
"Multiple virtual register defs in SSA form", MO, MONum);
2636 if (
Reg.isVirtual()) {
2637 checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
2641 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2642 :
MRI->getMaxLaneMaskForVReg(Reg);
2644 if ((SR.LaneMask & MOMask).none())
2646 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg,
true, SR.LaneMask);
2658void MachineVerifier::visitMachineBundleAfter(
const MachineInstr *
MI) {
2659 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2660 set_union(MInfo.regsKilled, regsKilled);
2661 set_subtract(regsLive, regsKilled); regsKilled.clear();
2663 while (!regMasks.empty()) {
2666 if (
Reg.isPhysical() &&
2668 regsDead.push_back(Reg);
2671 set_union(regsLive, regsDefined); regsDefined.clear();
2676 MBBInfoMap[
MBB].regsLiveOut = regsLive;
2681 if (!(stop > lastIndex)) {
2682 report(
"Block ends before last instruction index",
MBB);
2683 errs() <<
"Block ends at " << stop
2684 <<
" last instruction was at " << lastIndex <<
'\n';
2699 template <
typename RegSetT>
void add(
const RegSetT &FromRegSet) {
2701 filterAndAdd(FromRegSet, VRegsBuffer);
2706 template <
typename RegSetT>
2707 bool filterAndAdd(
const RegSetT &FromRegSet,
2709 unsigned SparseUniverse = Sparse.size();
2710 unsigned NewSparseUniverse = SparseUniverse;
2711 unsigned NewDenseSize =
Dense.size();
2712 size_t Begin = ToVRegs.
size();
2714 if (!
Reg.isVirtual())
2717 if (
Index < SparseUniverseMax) {
2718 if (
Index < SparseUniverse && Sparse.test(
Index))
2720 NewSparseUniverse = std::max(NewSparseUniverse,
Index + 1);
2735 Sparse.resize(NewSparseUniverse);
2736 Dense.reserve(NewDenseSize);
2737 for (
unsigned I = Begin;
I <
End; ++
I) {
2740 if (
Index < SparseUniverseMax)
2749 static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2769class FilteringVRegSet {
2776 template <
typename RegSetT>
void addToFilter(
const RegSetT &RS) {
2781 template <
typename RegSetT>
bool add(
const RegSetT &RS) {
2784 return Filter.filterAndAdd(RS, VRegs);
2789 size_t size()
const {
return VRegs.
size(); }
2796void MachineVerifier::calcRegsPassed() {
2803 FilteringVRegSet VRegs;
2804 BBInfo &
Info = MBBInfoMap[MB];
2807 VRegs.addToFilter(
Info.regsKilled);
2808 VRegs.addToFilter(
Info.regsLiveOut);
2810 const BBInfo &PredInfo = MBBInfoMap[Pred];
2811 if (!PredInfo.reachable)
2814 VRegs.add(PredInfo.regsLiveOut);
2815 VRegs.add(PredInfo.vregsPassed);
2817 Info.vregsPassed.reserve(VRegs.size());
2818 Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2825void MachineVerifier::calcRegsRequired() {
2828 for (
const auto &
MBB : *MF) {
2829 BBInfo &MInfo = MBBInfoMap[&
MBB];
2831 BBInfo &PInfo = MBBInfoMap[Pred];
2832 if (PInfo.addRequired(MInfo.vregsLiveIn))
2838 for (
unsigned i = 1, e =
MI.getNumOperands(); i != e; i += 2) {
2840 if (!
MI.getOperand(i).isReg() || !
MI.getOperand(i).readsReg())
2847 BBInfo &PInfo = MBBInfoMap[Pred];
2848 if (PInfo.addRequired(Reg))
2856 while (!todo.
empty()) {
2859 BBInfo &MInfo = MBBInfoMap[
MBB];
2863 BBInfo &SInfo = MBBInfoMap[Pred];
2864 if (SInfo.addRequired(MInfo.vregsRequired))
2873 BBInfo &MInfo = MBBInfoMap[&
MBB];
2883 report(
"Expected first PHI operand to be a register def", &MODef, 0);
2888 report(
"Unexpected flag on PHI operand", &MODef, 0);
2891 report(
"Expected first PHI operand to be a virtual register", &MODef, 0);
2893 for (
unsigned I = 1,
E =
Phi.getNumOperands();
I !=
E;
I += 2) {
2896 report(
"Expected PHI operand to be a register", &MO0,
I);
2901 report(
"Unexpected flag on PHI operand", &MO0,
I);
2905 report(
"Expected PHI operand to be a basic block", &MO1,
I + 1);
2911 report(
"PHI input is not a predecessor block", &MO1,
I + 1);
2915 if (MInfo.reachable) {
2917 BBInfo &PrInfo = MBBInfoMap[&Pre];
2918 if (!MO0.
isUndef() && PrInfo.reachable &&
2919 !PrInfo.isLiveOut(MO0.
getReg()))
2920 report(
"PHI operand is not live-out from predecessor", &MO0,
I);
2925 if (MInfo.reachable) {
2927 if (!seen.
count(Pred)) {
2928 report(
"Missing PHI operand", &Phi);
2930 <<
" is a predecessor according to the CFG.\n";
2937void MachineVerifier::visitMachineFunctionAfter() {
2947 for (
const auto &
MBB : *MF) {
2948 BBInfo &MInfo = MBBInfoMap[&
MBB];
2949 for (
Register VReg : MInfo.vregsRequired)
2950 if (MInfo.regsKilled.count(VReg)) {
2951 report(
"Virtual register killed in block, but needed live out.", &
MBB);
2953 <<
" is used after the block.\n";
2958 BBInfo &MInfo = MBBInfoMap[&MF->front()];
2959 for (
Register VReg : MInfo.vregsRequired) {
2960 report(
"Virtual register defs don't dominate all uses.", MF);
2961 report_context_vreg(VReg);
2966 verifyLiveVariables();
2968 verifyLiveIntervals();
2977 if (
MRI->tracksLiveness())
2978 for (
const auto &
MBB : *MF)
2982 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
2985 BBInfo &PInfo = MBBInfoMap[Pred];
2986 if (!PInfo.regsLiveOut.count(LiveInReg)) {
2987 report(
"Live in register not found to be live out from predecessor.",
2989 errs() <<
TRI->getName(LiveInReg)
2990 <<
" not found to be live out from "
2996 for (
auto CSInfo : MF->getCallSitesInfo())
2997 if (!CSInfo.first->isCall())
2998 report(
"Call site info referencing instruction that is not call", MF);
3002 if (MF->getFunction().getSubprogram()) {
3004 for (
const auto &
MBB : *MF) {
3005 for (
const auto &
MI :
MBB) {
3006 if (
auto Num =
MI.peekDebugInstrNum()) {
3009 report(
"Instruction has a duplicated value tracking number", &
MI);
3016void MachineVerifier::verifyLiveVariables() {
3017 assert(LiveVars &&
"Don't call verifyLiveVariables without LiveVars");
3018 for (
unsigned I = 0,
E =
MRI->getNumVirtRegs();
I !=
E; ++
I) {
3021 for (
const auto &
MBB : *MF) {
3022 BBInfo &MInfo = MBBInfoMap[&
MBB];
3025 if (MInfo.vregsRequired.count(Reg)) {
3027 report(
"LiveVariables: Block missing from AliveBlocks", &
MBB);
3029 <<
" must be live through the block.\n";
3033 report(
"LiveVariables: Block should not be in AliveBlocks", &
MBB);
3035 <<
" is not needed live through the block.\n";
3042void MachineVerifier::verifyLiveIntervals() {
3043 assert(LiveInts &&
"Don't call verifyLiveIntervals without LiveInts");
3044 for (
unsigned I = 0,
E =
MRI->getNumVirtRegs();
I !=
E; ++
I) {
3048 if (
MRI->reg_nodbg_empty(Reg))
3052 report(
"Missing live interval for virtual register", MF);
3058 assert(Reg == LI.
reg() &&
"Invalid reg to interval mapping");
3059 verifyLiveInterval(LI);
3063 for (
unsigned i = 0, e =
TRI->getNumRegUnits(); i != e; ++i)
3065 verifyLiveRange(*LR, i);
3068void MachineVerifier::verifyLiveRangeValue(
const LiveRange &LR,
3077 report(
"Value not live at VNInfo def and not marked unused", MF);
3078 report_context(LR, Reg, LaneMask);
3079 report_context(*VNI);
3083 if (DefVNI != VNI) {
3084 report(
"Live segment at def has different VNInfo", MF);
3085 report_context(LR, Reg, LaneMask);
3086 report_context(*VNI);
3092 report(
"Invalid VNInfo definition index", MF);
3093 report_context(LR, Reg, LaneMask);
3094 report_context(*VNI);
3100 report(
"PHIDef VNInfo is not defined at MBB start",
MBB);
3101 report_context(LR, Reg, LaneMask);
3102 report_context(*VNI);
3110 report(
"No instruction at VNInfo def index",
MBB);
3111 report_context(LR, Reg, LaneMask);
3112 report_context(*VNI);
3117 bool hasDef =
false;
3118 bool isEarlyClobber =
false;
3120 if (!MOI->isReg() || !MOI->isDef())
3122 if (
Reg.isVirtual()) {
3123 if (MOI->getReg() != Reg)
3126 if (!MOI->getReg().isPhysical() || !
TRI->hasRegUnit(MOI->getReg(), Reg))
3129 if (LaneMask.
any() &&
3130 (
TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3133 if (MOI->isEarlyClobber())
3134 isEarlyClobber =
true;
3138 report(
"Defining instruction does not modify register",
MI);
3139 report_context(LR, Reg, LaneMask);
3140 report_context(*VNI);
3145 if (isEarlyClobber) {
3147 report(
"Early clobber def must be at an early-clobber slot",
MBB);
3148 report_context(LR, Reg, LaneMask);
3149 report_context(*VNI);
3152 report(
"Non-PHI, non-early clobber def must be at a register slot",
MBB);
3153 report_context(LR, Reg, LaneMask);
3154 report_context(*VNI);
3159void MachineVerifier::verifyLiveRangeSegment(
const LiveRange &LR,
3165 assert(VNI &&
"Live segment has no valno");
3168 report(
"Foreign valno in live segment", MF);
3169 report_context(LR, Reg, LaneMask);
3171 report_context(*VNI);
3175 report(
"Live segment valno is marked unused", MF);
3176 report_context(LR, Reg, LaneMask);
3182 report(
"Bad start of live segment, no basic block", MF);
3183 report_context(LR, Reg, LaneMask);
3189 report(
"Live segment must begin at MBB entry or valno def",
MBB);
3190 report_context(LR, Reg, LaneMask);
3197 report(
"Bad end of live segment, no basic block", MF);
3198 report_context(LR, Reg, LaneMask);
3214 report(
"Live segment doesn't end at a valid instruction", EndMBB);
3215 report_context(LR, Reg, LaneMask);
3222 report(
"Live segment ends at B slot of an instruction", EndMBB);
3223 report_context(LR, Reg, LaneMask);
3231 report(
"Live segment ending at dead slot spans instructions", EndMBB);
3232 report_context(LR, Reg, LaneMask);
3241 if (MF->getProperties().hasProperty(
3244 if (
I + 1 == LR.
end() || (
I + 1)->start != S.
end) {
3245 report(
"Live segment ending at early clobber slot must be "
3246 "redefined by an EC def in the same instruction",
3248 report_context(LR, Reg, LaneMask);
3255 if (
Reg.isVirtual()) {
3258 bool hasRead =
false;
3259 bool hasSubRegDef =
false;
3260 bool hasDeadDef =
false;
3262 if (!MOI->isReg() || MOI->getReg() != Reg)
3264 unsigned Sub = MOI->getSubReg();
3269 hasSubRegDef =
true;
3278 if (LaneMask.
any() && (LaneMask & SLM).none())
3280 if (MOI->readsReg())
3287 if (LaneMask.
none() && !hasDeadDef) {
3289 "Instruction ending live segment on dead slot has no dead flag",
3291 report_context(LR, Reg, LaneMask);
3298 if (!
MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.
any() ||
3300 report(
"Instruction ending live segment doesn't read the register",
3302 report_context(LR, Reg, LaneMask);
3322 if (LaneMask.
any()) {
3330 if (!
Reg.isVirtual() && MFI->isEHPad()) {
3331 if (&*MFI == EndMBB)
3345 if (MFI->isEHPad()) {
3359 if (!PVNI && (LaneMask.
none() || !IsPHI)) {
3362 report(
"Register not marked live out of predecessor", Pred);
3363 report_context(LR, Reg, LaneMask);
3364 report_context(*VNI);
3372 if (!IsPHI && PVNI != VNI) {
3373 report(
"Different value live out of predecessor", Pred);
3374 report_context(LR, Reg, LaneMask);
3375 errs() <<
"Valno #" << PVNI->
id <<
" live out of "
3381 if (&*MFI == EndMBB)
3390 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3393 verifyLiveRangeSegment(LR,
I, Reg, LaneMask);
3396void MachineVerifier::verifyLiveInterval(
const LiveInterval &LI) {
3399 verifyLiveRange(LI, Reg);
3405 if ((Mask & SR.LaneMask).any()) {
3406 report(
"Lane masks of sub ranges overlap in live interval", MF);
3409 if ((SR.LaneMask & ~MaxMask).any()) {
3410 report(
"Subrange lanemask is invalid", MF);
3414 report(
"Subrange must not be empty", MF);
3415 report_context(SR, LI.
reg(), SR.LaneMask);
3417 Mask |= SR.LaneMask;
3418 verifyLiveRange(SR, LI.
reg(), SR.LaneMask);
3420 report(
"A Subrange is not covered by the main range", MF);
3428 unsigned NumComp = ConEQ.Classify(LI);
3430 report(
"Multiple connected components in live interval", MF);
3432 for (
unsigned comp = 0; comp != NumComp; ++comp) {
3433 errs() << comp <<
": valnos";
3435 if (comp == ConEQ.getEqClass(
I))
3436 errs() <<
' ' <<
I->id;
3448 struct StackStateOfBB {
3449 StackStateOfBB() =
default;
3450 StackStateOfBB(
int EntryVal,
int ExitVal,
bool EntrySetup,
bool ExitSetup) :
3451 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3452 ExitIsSetup(ExitSetup) {}
3457 bool EntryIsSetup =
false;
3458 bool ExitIsSetup =
false;
3466void MachineVerifier::verifyStackFrame() {
3467 unsigned FrameSetupOpcode =
TII->getCallFrameSetupOpcode();
3468 unsigned FrameDestroyOpcode =
TII->getCallFrameDestroyOpcode();
3469 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3473 SPState.
resize(MF->getNumBlockIDs());
3480 DFI != DFE; ++DFI) {
3483 StackStateOfBB BBState;
3485 if (DFI.getPathLength() >= 2) {
3488 "DFS stack predecessor is already visited.\n");
3489 BBState.EntryValue = SPState[StackPred->
getNumber()].ExitValue;
3490 BBState.EntryIsSetup = SPState[StackPred->
getNumber()].ExitIsSetup;
3491 BBState.ExitValue = BBState.EntryValue;
3492 BBState.ExitIsSetup = BBState.EntryIsSetup;
3496 report(
"Call frame size on entry does not match value computed from "
3500 <<
" does not match value computed from predecessor "
3501 << -BBState.EntryValue <<
'\n';
3505 for (
const auto &
I : *
MBB) {
3506 if (
I.getOpcode() == FrameSetupOpcode) {
3507 if (BBState.ExitIsSetup)
3508 report(
"FrameSetup is after another FrameSetup", &
I);
3509 BBState.ExitValue -=
TII->getFrameTotalSize(
I);
3510 BBState.ExitIsSetup =
true;
3513 if (
I.getOpcode() == FrameDestroyOpcode) {
3514 int Size =
TII->getFrameTotalSize(
I);
3515 if (!BBState.ExitIsSetup)
3516 report(
"FrameDestroy is not after a FrameSetup", &
I);
3517 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3519 if (BBState.ExitIsSetup && AbsSPAdj !=
Size) {
3520 report(
"FrameDestroy <n> is after FrameSetup <m>", &
I);
3521 errs() <<
"FrameDestroy <" <<
Size <<
"> is after FrameSetup <"
3522 << AbsSPAdj <<
">.\n";
3524 BBState.ExitValue +=
Size;
3525 BBState.ExitIsSetup =
false;
3533 if (Reachable.
count(Pred) &&
3534 (SPState[Pred->
getNumber()].ExitValue != BBState.EntryValue ||
3535 SPState[Pred->
getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3536 report(
"The exit stack state of a predecessor is inconsistent.",
MBB);
3538 <<
" has exit state (" << SPState[Pred->
getNumber()].ExitValue
3539 <<
", " << SPState[Pred->
getNumber()].ExitIsSetup <<
"), while "
3541 << BBState.EntryValue <<
", " << BBState.EntryIsSetup <<
").\n";
3548 if (Reachable.
count(Succ) &&
3549 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3550 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3551 report(
"The entry stack state of a successor is inconsistent.",
MBB);
3553 <<
" has entry state (" << SPState[Succ->getNumber()].EntryValue
3554 <<
", " << SPState[Succ->getNumber()].EntryIsSetup <<
"), while "
3556 << BBState.ExitValue <<
", " << BBState.ExitIsSetup <<
").\n";
3562 if (BBState.ExitIsSetup)
3563 report(
"A return block ends with a FrameSetup.",
MBB);
3564 if (BBState.ExitValue)
3565 report(
"A return block ends with a nonzero stack adjustment.",
MBB);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator MBBI
static bool isLoad(int Opcode)
static bool isStore(int Opcode)
This file implements the BitVector class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
This file defines the DenseSet and SmallDenseSet classes.
This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
A common definition of LaneBitmask for use in TableGen and CodeGen.
Implement a low-level type suitable for MachineInstr level instruction selection.
unsigned const TargetRegisterInfo * TRI
modulo schedule Modulo Schedule test pass
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
This file defines generic set operations that may be used on set's of different types,...
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
static unsigned getSize(unsigned Kind)
static constexpr uint32_t Opcode
const fltSemantics & getSemantics() const
Represent the analysis usage information of a pass.
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
void setPreservesAll()
Set by analyses that do not transform their input at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches,...
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
bool test(unsigned Idx) const
void clear()
clear - Removes all bits from the bitvector.
iterator_range< const_set_bits_iterator > set_bits() const
size_type size() const
size - Returns the number of bits in this bitvector.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
This class represents an Operation in the Expression.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Implements a dense probed hash-table based set.
Base class for user error types.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
FunctionPass class - This class is used to implement most global optimizations.
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
constexpr bool isScalableVector() const
Returns true if the LLT is a scalable vector.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
constexpr unsigned getAddressSpace() const
constexpr LLT getScalarType() const
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
bool hasInterval(Register Reg) const
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Result of a LiveRange query.
bool isDeadDef() const
Return true if this instruction has a dead def.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
VNInfo * valueOut() const
Return the value leaving the instruction, if any.
bool isKill() const
Return true if the live-in value is killed by this instruction.
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
This class represents the liveness of a register, stack slot, etc.
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
bool liveAt(SlotIndex index) const
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
unsigned getNumValNums() const
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
LiveInterval & getInterval(int Slot)
bool hasInterval(int Slot) const
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
This class is intended to be used as a base class for asm properties and features specific to the tar...
ExceptionHandling getExceptionHandlingType() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
bool isConvergent() const
Return true if this instruction is convergent.
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getOpcode() const
Return the opcode number for this descriptor.
This holds information about one operand of a machine instruction, indicating the register class for ...
bool isOptionalDef() const
Set if this operand is a optional def.
uint8_t OperandType
Information about the type of the operand.
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isValid() const
isValid - Returns true until all the operands have been visited.
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
iterator_range< livein_iterator > liveins() const
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
succ_iterator succ_begin()
bool isIRBlockAddressTaken() const
Test whether this block is the target of an IR BlockAddress.
unsigned succ_size() const
BasicBlock * getAddressTakenIRBlock() const
Retrieves the BasicBlock which corresponds to this MachineBasicBlock.
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
pred_iterator pred_begin()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
unsigned getCallFrameSize() const
Return the call frame size on entry to this basic block.
iterator_range< succ_iterator > successors()
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
An AnalysisManager<MachineFunction> that also exposes IR analysis results.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
BasicBlockListType::const_iterator const_iterator
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isReturn(QueryType Type=AnyInBundle) const
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
A description of a memory reference used in the backend.
const PseudoSourceValue * getPseudoValue() const
uint64_t getSize() const
Return the size in bytes of the memory reference.
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isIntrinsicID() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isValidExcessOperand() const
Return true if this operand can validly be appended to an arbitrary operand list.
bool isShuffleMask() const
unsigned getCFIIndex() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
This class implements the register bank concept.
const char * getName() const
Get a user friendly name of this register bank.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SlotIndex - An opaque wrapper around machine indexes.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
VNInfo - Value Number Information.
bool isUnused() const
Returns true if this value is unused.
unsigned id
The ID number of this value.
SlotIndex def
The index of the defining instruction.
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
constexpr bool isNonZero() const
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
self_iterator getIterator()
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
const CustomOperand< const MCSubtargetInfo & > Msg[]
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< PhiNode * > Phi
NodeAddr< DefNode * > Def
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
const_iterator end(StringRef path)
Get end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
@ SjLj
setjmp/longjmp based exceptions
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
void initializeMachineVerifierPassPass(PassRegistry &)
auto reverse(ContainerTy &&C)
detail::ValueMatchesPoly< M > HasValue(M Matcher)
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
void verifyMachineFunction(MachineFunctionAnalysisManager *, const std::string &Banner, const MachineFunction &MF)
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
Implement std::hash so that hash_code can be used in STL containers.
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
static constexpr LaneBitmask getAll()
constexpr bool none() const
constexpr bool any() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
Pair of physical register and lane mask.