91 struct MachineVerifier {
92 MachineVerifier(
Pass *
pass,
const char *b) : PASS(
pass), Banner(b) {}
105 unsigned foundErrors;
108 bool isFunctionRegBankSelected;
109 bool isFunctionSelected;
110 bool isFunctionTracksDebugUserValues;
120 BlockSet FunctionBlocks;
124 RegVector regsDefined, regsDead, regsKilled;
125 RegMaskVector regMasks;
130 void addRegWithSubRegs(RegVector &RV,
Register Reg) {
132 if (
Reg.isPhysical())
138 bool reachable =
false;
159 RegSet vregsRequired;
162 BlockSet Preds, Succs;
169 if (!
Reg.isVirtual())
171 if (regsLiveOut.count(Reg))
173 return vregsRequired.insert(Reg).second;
177 bool addRequired(
const RegSet &RS) {
178 bool Changed =
false;
180 Changed |= addRequired(Reg);
185 bool addRequired(
const RegMap &RM) {
186 bool Changed =
false;
187 for (
const auto &
I : RM)
188 Changed |= addRequired(
I.first);
194 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
202 return Reg.id() < regsReserved.
size() && regsReserved.
test(
Reg.id());
205 bool isAllocatable(
Register Reg)
const {
206 return Reg.id() <
TRI->getNumRegs() &&
TRI->isInAllocatableClass(Reg) &&
216 void visitMachineFunctionBefore();
228 void visitMachineOperand(
const MachineOperand *MO,
unsigned MONum);
231 void visitMachineFunctionAfter();
236 void report(
const char *msg,
const MachineOperand *MO,
unsigned MONum,
244 void report_context(
const VNInfo &VNI)
const;
245 void report_context(
SlotIndex Pos)
const;
246 void report_context(
MCPhysReg PhysReg)
const;
247 void report_context_liverange(
const LiveRange &LR)
const;
248 void report_context_lanemask(
LaneBitmask LaneMask)
const;
249 void report_context_vreg(
Register VReg)
const;
250 void report_context_vreg_regunit(
Register VRegOrUnit)
const;
261 Register VRegOrUnit,
bool SubRangeCheck =
false,
265 void calcRegsPassed();
268 void calcRegsRequired();
269 void verifyLiveVariables();
270 void verifyLiveIntervals();
274 void verifyLiveRangeSegment(
const LiveRange &,
280 void verifyStackFrame();
282 void verifySlotIndexes()
const;
289 const std::string Banner;
291 MachineVerifierPass(std::string banner = std::string())
308 MachineFunctionProperties::Property::FailsVerification))
311 unsigned FoundErrors = MachineVerifier(
this, Banner.c_str()).verify(MF);
320char MachineVerifierPass::ID = 0;
323 "Verify generated machine code",
false,
false)
326 return new MachineVerifierPass(Banner);
330 const std::string &Banner,
337 unsigned FoundErrors = MachineVerifier(
nullptr, Banner.c_str()).verify(MF);
345 unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
346 if (AbortOnErrors && FoundErrors)
348 return FoundErrors == 0;
351void MachineVerifier::verifySlotIndexes()
const {
352 if (Indexes ==
nullptr)
370 MRI->getNumVirtRegs())
371 report(
"Function has NoVRegs property but there are VReg operands", &MF);
390 if (isFunctionFailedISel)
415 verifyProperties(MF);
417 visitMachineFunctionBefore();
419 visitMachineBasicBlockBefore(&
MBB);
423 bool InBundle =
false;
426 if (
MI.getParent() != &
MBB) {
427 report(
"Bad instruction parent pointer", &
MBB);
428 errs() <<
"Instruction: " <<
MI;
433 if (InBundle && !
MI.isBundledWithPred())
434 report(
"Missing BundledPred flag, "
435 "BundledSucc was set on predecessor",
437 if (!InBundle &&
MI.isBundledWithPred())
438 report(
"BundledPred flag is set, "
439 "but BundledSucc not set on predecessor",
443 if (!
MI.isInsideBundle()) {
445 visitMachineBundleAfter(CurBundle);
447 visitMachineBundleBefore(CurBundle);
448 }
else if (!CurBundle)
449 report(
"No bundle header", &
MI);
450 visitMachineInstrBefore(&
MI);
451 for (
unsigned I = 0,
E =
MI.getNumOperands();
I !=
E; ++
I) {
453 if (
Op.getParent() != &
MI) {
456 report(
"Instruction has operand with wrong parent set", &
MI);
459 visitMachineOperand(&Op,
I);
463 InBundle =
MI.isBundledWithSucc();
466 visitMachineBundleAfter(CurBundle);
468 report(
"BundledSucc flag set on last instruction in block", &
MBB.
back());
469 visitMachineBasicBlockAfter(&
MBB);
471 visitMachineFunctionAfter();
484void MachineVerifier::report(
const char *msg,
const MachineFunction *MF) {
487 if (!foundErrors++) {
489 errs() <<
"# " << Banner <<
'\n';
490 if (LiveInts !=
nullptr)
495 errs() <<
"*** Bad machine code: " << msg <<
" ***\n"
496 <<
"- function: " << MF->
getName() <<
"\n";
510void MachineVerifier::report(
const char *msg,
const MachineInstr *
MI) {
512 report(msg,
MI->getParent());
513 errs() <<
"- instruction: ";
519void MachineVerifier::report(
const char *msg,
const MachineOperand *MO,
520 unsigned MONum,
LLT MOVRegType) {
523 errs() <<
"- operand " << MONum <<
": ";
529 report(
Msg.str().c_str(),
MI);
532void MachineVerifier::report_context(
SlotIndex Pos)
const {
533 errs() <<
"- at: " << Pos <<
'\n';
536void MachineVerifier::report_context(
const LiveInterval &LI)
const {
537 errs() <<
"- interval: " << LI <<
'\n';
542 report_context_liverange(LR);
543 report_context_vreg_regunit(VRegUnit);
545 report_context_lanemask(LaneMask);
549 errs() <<
"- segment: " << S <<
'\n';
552void MachineVerifier::report_context(
const VNInfo &VNI)
const {
553 errs() <<
"- ValNo: " << VNI.
id <<
" (def " << VNI.
def <<
")\n";
556void MachineVerifier::report_context_liverange(
const LiveRange &LR)
const {
557 errs() <<
"- liverange: " << LR <<
'\n';
560void MachineVerifier::report_context(
MCPhysReg PReg)
const {
564void MachineVerifier::report_context_vreg(
Register VReg)
const {
568void MachineVerifier::report_context_vreg_regunit(
Register VRegOrUnit)
const {
570 report_context_vreg(VRegOrUnit);
576void MachineVerifier::report_context_lanemask(
LaneBitmask LaneMask)
const {
581 BBInfo &MInfo = MBBInfoMap[
MBB];
582 if (!MInfo.reachable) {
583 MInfo.reachable =
true;
589void MachineVerifier::visitMachineFunctionBefore() {
591 regsReserved =
MRI->reservedRegsFrozen() ?
MRI->getReservedRegs()
592 :
TRI->getReservedRegs(*MF);
595 markReachable(&MF->
front());
598 FunctionBlocks.clear();
599 for (
const auto &
MBB : *MF) {
600 FunctionBlocks.insert(&
MBB);
601 BBInfo &MInfo = MBBInfoMap[&
MBB];
605 report(
"MBB has duplicate entries in its predecessor list.", &
MBB);
609 report(
"MBB has duplicate entries in its successor list.", &
MBB);
613 MRI->verifyUseLists();
621 FirstTerminator =
nullptr;
622 FirstNonPHI =
nullptr;
624 if (!MF->getProperties().hasProperty(
629 if (isAllocatable(LI.PhysReg) && !
MBB->
isEHPad() &&
631 report(
"MBB has allocatable live-in, but isn't entry or landing-pad.",
MBB);
632 report_context(LI.PhysReg);
639 report(
"ir-block-address-taken is associated with basic block not used by "
648 LandingPadSuccs.
insert(succ);
649 if (!FunctionBlocks.count(succ))
650 report(
"MBB has successor that isn't part of the function.",
MBB);
651 if (!MBBInfoMap[succ].Preds.count(
MBB)) {
652 report(
"Inconsistent CFG",
MBB);
653 errs() <<
"MBB is not in the predecessor list of the successor "
660 if (!FunctionBlocks.count(Pred))
661 report(
"MBB has predecessor that isn't part of the function.",
MBB);
662 if (!MBBInfoMap[Pred].Succs.count(
MBB)) {
663 report(
"Inconsistent CFG",
MBB);
664 errs() <<
"MBB is not in the successor list of the predecessor "
672 if (LandingPadSuccs.
size() > 1 &&
677 report(
"MBB has more than one landing pad successor",
MBB);
690 report(
"MBB exits via unconditional fall-through but ends with a "
691 "barrier instruction!",
MBB);
694 report(
"MBB exits via unconditional fall-through but has a condition!",
697 }
else if (
TBB && !FBB &&
Cond.empty()) {
700 report(
"MBB exits via unconditional branch but doesn't contain "
701 "any instructions!",
MBB);
703 report(
"MBB exits via unconditional branch but doesn't end with a "
704 "barrier instruction!",
MBB);
706 report(
"MBB exits via unconditional branch but the branch isn't a "
707 "terminator instruction!",
MBB);
709 }
else if (
TBB && !FBB && !
Cond.empty()) {
712 report(
"MBB exits via conditional branch/fall-through but doesn't "
713 "contain any instructions!",
MBB);
715 report(
"MBB exits via conditional branch/fall-through but ends with a "
716 "barrier instruction!",
MBB);
718 report(
"MBB exits via conditional branch/fall-through but the branch "
719 "isn't a terminator instruction!",
MBB);
721 }
else if (
TBB && FBB) {
725 report(
"MBB exits via conditional branch/branch but doesn't "
726 "contain any instructions!",
MBB);
728 report(
"MBB exits via conditional branch/branch but doesn't end with a "
729 "barrier instruction!",
MBB);
731 report(
"MBB exits via conditional branch/branch but the branch "
732 "isn't a terminator instruction!",
MBB);
735 report(
"MBB exits via conditional branch/branch but there's no "
739 report(
"analyzeBranch returned invalid data!",
MBB);
745 report(
"MBB exits via jump or conditional branch, but its target isn't a "
749 report(
"MBB exits via conditional branch, but its target isn't a CFG "
756 bool Fallthrough = !
TBB || (!
Cond.empty() && !FBB);
761 if (!
Cond.empty() && !FBB) {
764 report(
"MBB conditionally falls through out of function!",
MBB);
766 report(
"MBB exits via conditional branch/fall-through but the CFG "
767 "successors don't match the actual successors!",
774 if (SuccMBB ==
TBB || SuccMBB == FBB)
782 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
784 report(
"MBB has unexpected successors which are not branch targets, "
785 "fallthrough, EHPads, or inlineasm_br targets.",
791 if (
MRI->tracksLiveness()) {
794 report(
"MBB live-in list contains non-physical register",
MBB);
818void MachineVerifier::visitMachineBundleBefore(
const MachineInstr *
MI) {
821 if (!(idx > lastIndex)) {
822 report(
"Instruction index out of order",
MI);
823 errs() <<
"Last instruction was at " << lastIndex <<
'\n';
829 if (
MI->isTerminator()) {
830 if (!FirstTerminator)
831 FirstTerminator =
MI;
832 }
else if (FirstTerminator) {
835 if (FirstTerminator->
getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
836 report(
"Non-terminator instruction after the first terminator",
MI);
837 errs() <<
"First terminator was:\t" << *FirstTerminator;
846 if (
MI->getNumOperands() < 2) {
847 report(
"Too few operands on inline asm",
MI);
850 if (!
MI->getOperand(0).isSymbol())
851 report(
"Asm string must be an external symbol",
MI);
852 if (!
MI->getOperand(1).isImm())
853 report(
"Asm flags must be an immediate",
MI);
857 if (!isUInt<6>(
MI->getOperand(1).getImm()))
858 report(
"Unknown asm flags", &
MI->getOperand(1), 1);
864 for (
unsigned e =
MI->getNumOperands(); OpNo <
e; OpNo += NumOps) {
872 if (OpNo >
MI->getNumOperands())
873 report(
"Missing operands in last group",
MI);
876 if (OpNo < MI->getNumOperands() &&
MI->getOperand(OpNo).isMetadata())
880 for (
unsigned e =
MI->getNumOperands(); OpNo < e; ++OpNo) {
883 report(
"Expected implicit register after groups", &MO, OpNo);
886 if (
MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
899 if (!IndirectTargetMBB) {
900 report(
"INLINEASM_BR indirect target does not exist", &MO, i);
905 report(
"INLINEASM_BR indirect target missing from successor list", &MO,
909 report(
"INLINEASM_BR indirect target predecessor list missing parent",
915bool MachineVerifier::verifyAllRegOpsScalar(
const MachineInstr &
MI,
920 const auto Reg = Op.getReg();
921 if (Reg.isPhysical())
923 return !MRI.getType(Reg).isScalar();
926 report(
"All register operands must have scalar types", &
MI);
933bool MachineVerifier::verifyVectorElementMatch(
LLT Ty0,
LLT Ty1,
936 report(
"operand types must be all-vector or all-scalar",
MI);
946 report(
"operand types must preserve number of vector elements",
MI);
953void MachineVerifier::verifyPreISelGenericInstruction(
const MachineInstr *
MI) {
954 if (isFunctionSelected)
955 report(
"Unexpected generic instruction in a Selected function",
MI);
958 unsigned NumOps =
MI->getNumOperands();
961 if (
MI->isBranch() && !
MI->isIndirectBranch()) {
971 report(
"Branch instruction is missing a basic block operand or "
972 "isIndirectBranch property",
985 size_t TypeIdx = MCID.
operands()[
I].getGenericTypeIndex();
986 Types.resize(std::max(TypeIdx + 1,
Types.size()));
990 report(
"generic instruction must use register operands",
MI);
1000 if (!Types[TypeIdx].
isValid())
1001 Types[TypeIdx] = OpTy;
1002 else if (Types[TypeIdx] != OpTy)
1003 report(
"Type mismatch in generic instruction", MO,
I, OpTy);
1006 report(
"Generic instruction is missing a virtual register type", MO,
I);
1011 for (
unsigned I = 0;
I <
MI->getNumOperands(); ++
I) {
1014 report(
"Generic instruction cannot have physical register", MO,
I);
1026 unsigned Opc =
MI->getOpcode();
1028 case TargetOpcode::G_ASSERT_SEXT:
1029 case TargetOpcode::G_ASSERT_ZEXT: {
1030 std::string OpcName =
1031 Opc == TargetOpcode::G_ASSERT_ZEXT ?
"G_ASSERT_ZEXT" :
"G_ASSERT_SEXT";
1032 if (!
MI->getOperand(2).isImm()) {
1033 report(
Twine(OpcName,
" expects an immediate operand #2"),
MI);
1039 LLT SrcTy =
MRI->getType(Src);
1040 int64_t
Imm =
MI->getOperand(2).getImm();
1042 report(
Twine(OpcName,
" size must be >= 1"),
MI);
1047 report(
Twine(OpcName,
" size must be less than source bit width"),
MI);
1055 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1056 report(
Twine(OpcName,
" cannot change register bank"),
MI);
1062 if (DstRC && DstRC !=
MRI->getRegClassOrNull(Src)) {
1064 Twine(OpcName,
" source and destination register classes must match"),
1072 case TargetOpcode::G_CONSTANT:
1073 case TargetOpcode::G_FCONSTANT: {
1074 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1076 report(
"Instruction cannot use a vector result type",
MI);
1078 if (
MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1079 if (!
MI->getOperand(1).isCImm()) {
1080 report(
"G_CONSTANT operand must be cimm",
MI);
1086 report(
"inconsistent constant size",
MI);
1088 if (!
MI->getOperand(1).isFPImm()) {
1089 report(
"G_FCONSTANT operand must be fpimm",
MI);
1096 report(
"inconsistent constant size",
MI);
1102 case TargetOpcode::G_LOAD:
1103 case TargetOpcode::G_STORE:
1104 case TargetOpcode::G_ZEXTLOAD:
1105 case TargetOpcode::G_SEXTLOAD: {
1106 LLT ValTy =
MRI->getType(
MI->getOperand(0).getReg());
1107 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1109 report(
"Generic memory instruction must access a pointer",
MI);
1113 if (!
MI->hasOneMemOperand()) {
1114 report(
"Generic instruction accessing memory must have one mem operand",
1118 if (
MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1119 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1121 report(
"Generic extload must have a narrower memory type",
MI);
1122 }
else if (
MI->getOpcode() == TargetOpcode::G_LOAD) {
1124 report(
"load memory size cannot exceed result size",
MI);
1125 }
else if (
MI->getOpcode() == TargetOpcode::G_STORE) {
1127 report(
"store memory size cannot exceed value size",
MI);
1131 if (Opc == TargetOpcode::G_STORE) {
1134 report(
"atomic store cannot use acquire ordering",
MI);
1139 report(
"atomic load cannot use release ordering",
MI);
1145 case TargetOpcode::G_PHI: {
1146 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1151 LLT Ty = MRI->getType(MO.getReg());
1152 if (!Ty.isValid() || (Ty != DstTy))
1156 report(
"Generic Instruction G_PHI has operands with incompatible/missing "
1161 case TargetOpcode::G_BITCAST: {
1162 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1163 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1168 report(
"bitcast cannot convert between pointers and other types",
MI);
1171 report(
"bitcast sizes must match",
MI);
1174 report(
"bitcast must change the type",
MI);
1178 case TargetOpcode::G_INTTOPTR:
1179 case TargetOpcode::G_PTRTOINT:
1180 case TargetOpcode::G_ADDRSPACE_CAST: {
1181 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1182 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1186 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1191 if (
MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1193 report(
"inttoptr result type must be a pointer",
MI);
1195 report(
"inttoptr source type must not be a pointer",
MI);
1196 }
else if (
MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1198 report(
"ptrtoint source type must be a pointer",
MI);
1200 report(
"ptrtoint result type must not be a pointer",
MI);
1202 assert(
MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1204 report(
"addrspacecast types must be pointers",
MI);
1207 report(
"addrspacecast must convert different address spaces",
MI);
1213 case TargetOpcode::G_PTR_ADD: {
1214 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1215 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1216 LLT OffsetTy =
MRI->getType(
MI->getOperand(2).getReg());
1221 report(
"gep first operand must be a pointer",
MI);
1224 report(
"gep offset operand must not be a pointer",
MI);
1229 case TargetOpcode::G_PTRMASK: {
1230 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1231 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1232 LLT MaskTy =
MRI->getType(
MI->getOperand(2).getReg());
1237 report(
"ptrmask result type must be a pointer",
MI);
1240 report(
"ptrmask mask type must be an integer",
MI);
1242 verifyVectorElementMatch(DstTy, MaskTy,
MI);
1245 case TargetOpcode::G_SEXT:
1246 case TargetOpcode::G_ZEXT:
1247 case TargetOpcode::G_ANYEXT:
1248 case TargetOpcode::G_TRUNC:
1249 case TargetOpcode::G_FPEXT:
1250 case TargetOpcode::G_FPTRUNC: {
1257 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1258 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1265 report(
"Generic extend/truncate can not operate on pointers",
MI);
1267 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1271 switch (
MI->getOpcode()) {
1273 if (DstSize <= SrcSize)
1274 report(
"Generic extend has destination type no larger than source",
MI);
1276 case TargetOpcode::G_TRUNC:
1277 case TargetOpcode::G_FPTRUNC:
1278 if (DstSize >= SrcSize)
1279 report(
"Generic truncate has destination type no smaller than source",
1285 case TargetOpcode::G_SELECT: {
1286 LLT SelTy =
MRI->getType(
MI->getOperand(0).getReg());
1287 LLT CondTy =
MRI->getType(
MI->getOperand(1).getReg());
1293 verifyVectorElementMatch(SelTy, CondTy,
MI);
1296 case TargetOpcode::G_MERGE_VALUES: {
1301 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1302 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1304 report(
"G_MERGE_VALUES cannot operate on vectors",
MI);
1306 const unsigned NumOps =
MI->getNumOperands();
1308 report(
"G_MERGE_VALUES result size is inconsistent",
MI);
1310 for (
unsigned I = 2;
I != NumOps; ++
I) {
1311 if (
MRI->getType(
MI->getOperand(
I).getReg()) != SrcTy)
1312 report(
"G_MERGE_VALUES source types do not match",
MI);
1317 case TargetOpcode::G_UNMERGE_VALUES: {
1318 unsigned NumDsts =
MI->getNumOperands() - 1;
1319 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1320 for (
unsigned i = 1; i < NumDsts; ++i) {
1321 if (
MRI->getType(
MI->getOperand(i).getReg()) != DstTy) {
1322 report(
"G_UNMERGE_VALUES destination types do not match",
MI);
1327 LLT SrcTy =
MRI->getType(
MI->getOperand(NumDsts).getReg());
1332 report(
"G_UNMERGE_VALUES source operand does not match vector "
1333 "destination operands",
1340 report(
"G_UNMERGE_VALUES vector source operand does not match scalar "
1341 "destination operands",
1346 report(
"G_UNMERGE_VALUES scalar source operand does not match scalar "
1347 "destination operands",
1353 case TargetOpcode::G_BUILD_VECTOR: {
1356 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1357 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1359 report(
"G_BUILD_VECTOR must produce a vector from scalar operands",
MI);
1364 report(
"G_BUILD_VECTOR result element type must match source type",
MI);
1367 report(
"G_BUILD_VECTOR must have an operand for each elemement",
MI);
1370 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1371 report(
"G_BUILD_VECTOR source operand types are not homogeneous",
MI);
1375 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1378 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1379 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1381 report(
"G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1384 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1385 report(
"G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1388 report(
"G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1393 case TargetOpcode::G_CONCAT_VECTORS: {
1396 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1397 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1399 report(
"G_CONCAT_VECTOR requires vector source and destination operands",
1402 if (
MI->getNumOperands() < 3)
1403 report(
"G_CONCAT_VECTOR requires at least 2 source operands",
MI);
1406 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1407 report(
"G_CONCAT_VECTOR source operand types are not homogeneous",
MI);
1410 report(
"G_CONCAT_VECTOR num dest and source elements should match",
MI);
1413 case TargetOpcode::G_ICMP:
1414 case TargetOpcode::G_FCMP: {
1415 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1416 LLT SrcTy =
MRI->getType(
MI->getOperand(2).getReg());
1420 report(
"Generic vector icmp/fcmp must preserve number of lanes",
MI);
1424 case TargetOpcode::G_EXTRACT: {
1426 if (!
SrcOp.isReg()) {
1427 report(
"extract source must be a register",
MI);
1432 if (!OffsetOp.
isImm()) {
1433 report(
"extract offset must be a constant",
MI);
1437 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1439 if (SrcSize == DstSize)
1440 report(
"extract source must be larger than result",
MI);
1442 if (DstSize + OffsetOp.
getImm() > SrcSize)
1443 report(
"extract reads past end of register",
MI);
1446 case TargetOpcode::G_INSERT: {
1448 if (!
SrcOp.isReg()) {
1449 report(
"insert source must be a register",
MI);
1454 if (!OffsetOp.
isImm()) {
1455 report(
"insert offset must be a constant",
MI);
1459 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1462 if (DstSize <= SrcSize)
1463 report(
"inserted size must be smaller than total register",
MI);
1465 if (SrcSize + OffsetOp.
getImm() > DstSize)
1466 report(
"insert writes past end of register",
MI);
1470 case TargetOpcode::G_JUMP_TABLE: {
1471 if (!
MI->getOperand(1).isJTI())
1472 report(
"G_JUMP_TABLE source operand must be a jump table index",
MI);
1473 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1475 report(
"G_JUMP_TABLE dest operand must have a pointer type",
MI);
1478 case TargetOpcode::G_BRJT: {
1479 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
1480 report(
"G_BRJT src operand 0 must be a pointer type",
MI);
1482 if (!
MI->getOperand(1).isJTI())
1483 report(
"G_BRJT src operand 1 must be a jump table index",
MI);
1485 const auto &IdxOp =
MI->getOperand(2);
1486 if (!IdxOp.isReg() ||
MRI->getType(IdxOp.getReg()).isPointer())
1487 report(
"G_BRJT src operand 2 must be a scalar reg type",
MI);
1490 case TargetOpcode::G_INTRINSIC:
1491 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1496 report(
"G_INTRINSIC first src operand must be an intrinsic ID",
MI);
1500 bool NoSideEffects =
MI->getOpcode() == TargetOpcode::G_INTRINSIC;
1502 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1504 MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
1505 bool DeclHasSideEffects = !
Attrs.getMemoryEffects().doesNotAccessMemory();
1506 if (NoSideEffects && DeclHasSideEffects) {
1507 report(
"G_INTRINSIC used with intrinsic that accesses memory",
MI);
1510 if (!NoSideEffects && !DeclHasSideEffects) {
1511 report(
"G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic",
MI);
1518 case TargetOpcode::G_SEXT_INREG: {
1519 if (!
MI->getOperand(2).isImm()) {
1520 report(
"G_SEXT_INREG expects an immediate operand #2",
MI);
1524 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1525 int64_t
Imm =
MI->getOperand(2).getImm();
1527 report(
"G_SEXT_INREG size must be >= 1",
MI);
1529 report(
"G_SEXT_INREG size must be less than source bit width",
MI);
1532 case TargetOpcode::G_SHUFFLE_VECTOR: {
1535 report(
"Incorrect mask operand type for G_SHUFFLE_VECTOR",
MI);
1539 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1540 LLT Src0Ty =
MRI->getType(
MI->getOperand(1).getReg());
1541 LLT Src1Ty =
MRI->getType(
MI->getOperand(2).getReg());
1543 if (Src0Ty != Src1Ty)
1544 report(
"Source operands must be the same type",
MI);
1547 report(
"G_SHUFFLE_VECTOR cannot change element type",
MI);
1556 if (
static_cast<int>(MaskIdxes.
size()) != DstNumElts)
1557 report(
"Wrong result type for shufflemask",
MI);
1559 for (
int Idx : MaskIdxes) {
1563 if (
Idx >= 2 * SrcNumElts)
1564 report(
"Out of bounds shuffle index",
MI);
1569 case TargetOpcode::G_DYN_STACKALLOC: {
1575 report(
"dst operand 0 must be a pointer type",
MI);
1579 if (!AllocOp.
isReg() || !
MRI->getType(AllocOp.
getReg()).isScalar()) {
1580 report(
"src operand 1 must be a scalar reg type",
MI);
1584 if (!AlignOp.
isImm()) {
1585 report(
"src operand 2 must be an immediate type",
MI);
1590 case TargetOpcode::G_MEMCPY_INLINE:
1591 case TargetOpcode::G_MEMCPY:
1592 case TargetOpcode::G_MEMMOVE: {
1594 if (MMOs.
size() != 2) {
1595 report(
"memcpy/memmove must have 2 memory operands",
MI);
1601 report(
"wrong memory operand types",
MI);
1606 report(
"inconsistent memory operand sizes",
MI);
1608 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1609 LLT SrcPtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1612 report(
"memory instruction operand must be a pointer",
MI);
1617 report(
"inconsistent store address space",
MI);
1619 report(
"inconsistent load address space",
MI);
1621 if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1622 if (!
MI->getOperand(3).isImm() || (
MI->getOperand(3).getImm() & ~1LL))
1623 report(
"'tail' flag (operand 3) must be an immediate 0 or 1",
MI);
1627 case TargetOpcode::G_BZERO:
1628 case TargetOpcode::G_MEMSET: {
1630 std::string
Name = Opc == TargetOpcode::G_MEMSET ?
"memset" :
"bzero";
1631 if (MMOs.
size() != 1) {
1632 report(
Twine(
Name,
" must have 1 memory operand"),
MI);
1637 report(
Twine(
Name,
" memory operand must be a store"),
MI);
1641 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1643 report(
Twine(
Name,
" operand must be a pointer"),
MI);
1648 report(
"inconsistent " +
Twine(
Name,
" address space"),
MI);
1650 if (!
MI->getOperand(
MI->getNumOperands() - 1).isImm() ||
1651 (
MI->getOperand(
MI->getNumOperands() - 1).getImm() & ~1LL))
1652 report(
"'tail' flag (last operand) must be an immediate 0 or 1",
MI);
1656 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1657 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1658 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1659 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1660 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1662 report(
"Vector reduction requires a scalar destination type",
MI);
1664 report(
"Sequential FADD/FMUL vector reduction requires a scalar 1st operand",
MI);
1666 report(
"Sequential FADD/FMUL vector reduction must have a vector 2nd operand",
MI);
1669 case TargetOpcode::G_VECREDUCE_FADD:
1670 case TargetOpcode::G_VECREDUCE_FMUL:
1671 case TargetOpcode::G_VECREDUCE_FMAX:
1672 case TargetOpcode::G_VECREDUCE_FMIN:
1673 case TargetOpcode::G_VECREDUCE_ADD:
1674 case TargetOpcode::G_VECREDUCE_MUL:
1675 case TargetOpcode::G_VECREDUCE_AND:
1676 case TargetOpcode::G_VECREDUCE_OR:
1677 case TargetOpcode::G_VECREDUCE_XOR:
1678 case TargetOpcode::G_VECREDUCE_SMAX:
1679 case TargetOpcode::G_VECREDUCE_SMIN:
1680 case TargetOpcode::G_VECREDUCE_UMAX:
1681 case TargetOpcode::G_VECREDUCE_UMIN: {
1682 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1684 report(
"Vector reduction requires a scalar destination type",
MI);
1688 case TargetOpcode::G_SBFX:
1689 case TargetOpcode::G_UBFX: {
1690 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1692 report(
"Bitfield extraction is not supported on vectors",
MI);
1697 case TargetOpcode::G_SHL:
1698 case TargetOpcode::G_LSHR:
1699 case TargetOpcode::G_ASHR:
1700 case TargetOpcode::G_ROTR:
1701 case TargetOpcode::G_ROTL: {
1702 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1703 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1705 report(
"Shifts and rotates require operands to be either all scalars or "
1712 case TargetOpcode::G_LLROUND:
1713 case TargetOpcode::G_LROUND: {
1714 verifyAllRegOpsScalar(*
MI, *
MRI);
1717 case TargetOpcode::G_IS_FPCLASS: {
1718 LLT DestTy =
MRI->getType(
MI->getOperand(0).getReg());
1721 report(
"Destination must be a scalar or vector of scalars",
MI);
1724 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1727 report(
"Source must be a scalar or vector of scalars",
MI);
1730 if (!verifyVectorElementMatch(DestTy, SrcTy,
MI))
1733 if (!TestMO.
isImm()) {
1734 report(
"floating-point class set (operand 2) must be an immediate",
MI);
1739 report(
"Incorrect floating-point class set (operand 2)",
MI);
1744 case TargetOpcode::G_ASSERT_ALIGN: {
1745 if (
MI->getOperand(2).getImm() < 1)
1746 report(
"alignment immediate must be >= 1",
MI);
1754void MachineVerifier::visitMachineInstrBefore(
const MachineInstr *
MI) {
1757 report(
"Too few operands",
MI);
1759 <<
MI->getNumOperands() <<
" given.\n";
1763 if (MF->getProperties().hasProperty(
1765 report(
"Found PHI instruction with NoPHIs property set",
MI);
1768 report(
"Found PHI instruction after non-PHI",
MI);
1769 }
else if (FirstNonPHI ==
nullptr)
1773 if (
MI->isInlineAsm())
1774 verifyInlineAsm(
MI);
1777 if (
TII->isUnspillableTerminator(
MI)) {
1778 if (!
MI->getOperand(0).isReg() || !
MI->getOperand(0).isDef())
1779 report(
"Unspillable Terminator does not define a reg",
MI);
1781 if (
Def.isVirtual() &&
1782 !MF->getProperties().hasProperty(
1784 std::distance(
MRI->use_nodbg_begin(Def),
MRI->use_nodbg_end()) > 1)
1785 report(
"Unspillable Terminator expected to have at most one use!",
MI);
1791 if (
MI->isDebugValue() &&
MI->getNumOperands() == 4)
1792 if (!
MI->getDebugLoc())
1793 report(
"Missing DebugLoc for debug instruction",
MI);
1797 if (
MI->isMetaInstruction() &&
MI->peekDebugInstrNum())
1798 report(
"Metadata instruction should not have a value tracking number",
MI);
1802 if (
Op->isLoad() && !
MI->mayLoad())
1803 report(
"Missing mayLoad flag",
MI);
1804 if (
Op->isStore() && !
MI->mayStore())
1805 report(
"Missing mayStore flag",
MI);
1812 if (
MI->isDebugOrPseudoInstr()) {
1814 report(
"Debug instruction has a slot index",
MI);
1815 }
else if (
MI->isInsideBundle()) {
1817 report(
"Instruction inside bundle has a slot index",
MI);
1820 report(
"Missing slot index",
MI);
1826 verifyPreISelGenericInstruction(
MI);
1835 switch (
MI->getOpcode()) {
1836 case TargetOpcode::COPY: {
1842 LLT DstTy =
MRI->getType(DstReg);
1843 LLT SrcTy =
MRI->getType(SrcReg);
1846 if (SrcTy != DstTy) {
1847 report(
"Copy Instruction is illegal with mismatching types",
MI);
1848 errs() <<
"Def = " << DstTy <<
", Src = " << SrcTy <<
"\n";
1859 unsigned SrcSize = 0;
1860 unsigned DstSize = 0;
1863 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
1865 SrcSize =
TRI->getRegSizeInBits(*SrcRC);
1869 SrcSize =
TRI->getRegSizeInBits(SrcReg, *
MRI);
1873 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
1875 DstSize =
TRI->getRegSizeInBits(*DstRC);
1879 DstSize =
TRI->getRegSizeInBits(DstReg, *
MRI);
1881 if (SrcSize != 0 && DstSize != 0 && SrcSize != DstSize) {
1882 if (!
DstOp.getSubReg() && !
SrcOp.getSubReg()) {
1883 report(
"Copy Instruction is illegal with mismatching sizes",
MI);
1884 errs() <<
"Def Size = " << DstSize <<
", Src Size = " << SrcSize
1890 case TargetOpcode::STATEPOINT: {
1892 if (!
MI->getOperand(SO.getIDPos()).isImm() ||
1893 !
MI->getOperand(SO.getNBytesPos()).isImm() ||
1894 !
MI->getOperand(SO.getNCallArgsPos()).isImm()) {
1895 report(
"meta operands to STATEPOINT not constant!",
MI);
1899 auto VerifyStackMapConstant = [&](
unsigned Offset) {
1900 if (
Offset >=
MI->getNumOperands()) {
1901 report(
"stack map constant to STATEPOINT is out of range!",
MI);
1904 if (!
MI->getOperand(
Offset - 1).isImm() ||
1905 MI->getOperand(
Offset - 1).getImm() != StackMaps::ConstantOp ||
1907 report(
"stack map constant to STATEPOINT not well formed!",
MI);
1909 VerifyStackMapConstant(SO.getCCIdx());
1910 VerifyStackMapConstant(SO.getFlagsIdx());
1911 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
1912 VerifyStackMapConstant(SO.getNumGCPtrIdx());
1913 VerifyStackMapConstant(SO.getNumAllocaIdx());
1914 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
1918 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
1919 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
1920 for (
unsigned Idx = 0;
Idx <
MI->getNumDefs();
Idx++) {
1923 report(
"STATEPOINT defs expected to be tied",
MI);
1926 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
1927 report(
"STATEPOINT def tied to non-gc operand",
MI);
1934 case TargetOpcode::INSERT_SUBREG: {
1935 unsigned InsertedSize;
1936 if (
unsigned SubIdx =
MI->getOperand(2).getSubReg())
1937 InsertedSize =
TRI->getSubRegIdxSize(SubIdx);
1939 InsertedSize =
TRI->getRegSizeInBits(
MI->getOperand(2).getReg(), *
MRI);
1940 unsigned SubRegSize =
TRI->getSubRegIdxSize(
MI->getOperand(3).getImm());
1941 if (SubRegSize < InsertedSize) {
1942 report(
"INSERT_SUBREG expected inserted value to have equal or lesser "
1943 "size than the subreg it was inserted into",
MI);
1947 case TargetOpcode::REG_SEQUENCE: {
1948 unsigned NumOps =
MI->getNumOperands();
1949 if (!(NumOps & 1)) {
1950 report(
"Invalid number of operands for REG_SEQUENCE",
MI);
1954 for (
unsigned I = 1;
I != NumOps;
I += 2) {
1959 report(
"Invalid register operand for REG_SEQUENCE", &RegOp,
I);
1961 if (!SubRegOp.
isImm() || SubRegOp.
getImm() == 0 ||
1962 SubRegOp.
getImm() >=
TRI->getNumSubRegIndices()) {
1963 report(
"Invalid subregister index operand for REG_SEQUENCE",
1968 Register DstReg =
MI->getOperand(0).getReg();
1970 report(
"REG_SEQUENCE does not support physical register results",
MI);
1972 if (
MI->getOperand(0).getSubReg())
1973 report(
"Invalid subreg result for REG_SEQUENCE",
MI);
1981MachineVerifier::visitMachineOperand(
const MachineOperand *MO,
unsigned MONum) {
1985 if (MCID.
getOpcode() == TargetOpcode::PATCHPOINT)
1986 NumDefs = (MONum == 0 && MO->
isReg()) ? NumDefs : 0;
1989 if (MONum < NumDefs) {
1992 report(
"Explicit definition must be a register", MO, MONum);
1994 report(
"Explicit definition marked as use", MO, MONum);
1996 report(
"Explicit definition marked as implicit", MO, MONum);
2005 report(
"Explicit operand marked as def", MO, MONum);
2007 report(
"Explicit operand marked as implicit", MO, MONum);
2013 report(
"Expected a register operand.", MO, MONum);
2017 !
TII->isPCRelRegisterOperandLegal(*MO)))
2018 report(
"Expected a non-register operand.", MO, MONum);
2025 report(
"Tied use must be a register", MO, MONum);
2027 report(
"Operand should be tied", MO, MONum);
2028 else if (
unsigned(TiedTo) !=
MI->findTiedOperandIdx(MONum))
2029 report(
"Tied def doesn't match MCInstrDesc", MO, MONum);
2032 if (!MOTied.
isReg())
2033 report(
"Tied counterpart must be a register", &MOTied, TiedTo);
2036 report(
"Tied physical registers must match.", &MOTied, TiedTo);
2039 report(
"Explicit operand should not be tied", MO, MONum);
2043 report(
"Extra explicit operand on non-variadic instruction", MO, MONum);
2050 if (
MI->isDebugInstr() && MO->
isUse()) {
2052 report(
"Register operand must be marked debug", MO, MONum);
2054 report(
"Register operand must not be marked debug", MO, MONum);
2060 if (
MRI->tracksLiveness() && !
MI->isDebugInstr())
2061 checkLiveness(MO, MONum);
2065 report(
"Undef virtual register def operands require a subregister", MO, MONum);
2069 unsigned OtherIdx =
MI->findTiedOperandIdx(MONum);
2071 if (!OtherMO.
isReg())
2072 report(
"Must be tied to a register", MO, MONum);
2074 report(
"Missing tie flags on tied operand", MO, MONum);
2075 if (
MI->findTiedOperandIdx(OtherIdx) != MONum)
2076 report(
"Inconsistent tie links", MO, MONum);
2080 report(
"Explicit def tied to explicit use without tie constraint",
2084 report(
"Explicit def should be tied to implicit use", MO, MONum);
2097 if (MF->getProperties().hasProperty(
2099 MO->
isUse() &&
MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2100 Reg !=
MI->getOperand(DefIdx).getReg())
2101 report(
"Two-address instruction operands must be identical", MO, MONum);
2106 if (
Reg.isPhysical()) {
2108 report(
"Illegal subregister index for physical register", MO, MONum);
2113 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2114 if (!DRC->contains(Reg)) {
2115 report(
"Illegal physical register for instruction", MO, MONum);
2117 <<
TRI->getRegClassName(DRC) <<
" register.\n";
2122 if (
MRI->isReserved(Reg)) {
2123 report(
"isRenamable set on reserved register", MO, MONum);
2140 report(
"Generic virtual register use cannot be undef", MO, MONum);
2147 if (isFunctionTracksDebugUserValues || !MO->
isUse() ||
2148 !
MI->isDebugValue() || !
MRI->def_empty(Reg)) {
2150 if (isFunctionSelected) {
2151 report(
"Generic virtual register invalid in a Selected function",
2157 LLT Ty =
MRI->getType(Reg);
2159 report(
"Generic virtual register must have a valid type", MO,
2167 if (!RegBank && isFunctionRegBankSelected) {
2168 report(
"Generic virtual register must have a bank in a "
2169 "RegBankSelected function",
2175 if (RegBank && Ty.
isValid() &&
2177 report(
"Register bank is too small for virtual register", MO,
2179 errs() <<
"Register bank " << RegBank->
getName() <<
" too small("
2187 report(
"Generic virtual register does not allow subregister index", MO,
2197 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2198 report(
"Virtual register does not match instruction constraint", MO,
2200 errs() <<
"Expect register class "
2201 <<
TRI->getRegClassName(
2202 TII->getRegClass(MCID, MONum,
TRI, *MF))
2203 <<
" but got nothing\n";
2211 TRI->getSubClassWithSubReg(RC, SubIdx);
2213 report(
"Invalid subregister index for virtual register", MO, MONum);
2214 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2215 <<
" does not support subreg index " << SubIdx <<
"\n";
2219 report(
"Invalid register class for subregister index", MO, MONum);
2220 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2221 <<
" does not fully support subreg index " << SubIdx <<
"\n";
2227 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2230 TRI->getLargestLegalSuperClass(RC, *MF);
2232 report(
"No largest legal super class exists.", MO, MONum);
2235 DRC =
TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2237 report(
"No matching super-reg register class.", MO, MONum);
2242 report(
"Illegal virtual register for instruction", MO, MONum);
2243 errs() <<
"Expected a " <<
TRI->getRegClassName(DRC)
2244 <<
" register, but got a " <<
TRI->getRegClassName(RC)
2259 report(
"PHI operand is not in the CFG", MO, MONum);
2270 bool loads =
MI->mayLoad();
2275 for (
auto *MMO :
MI->memoperands()) {
2277 if (PSV ==
nullptr)
continue;
2279 dyn_cast<FixedStackPseudoSourceValue>(PSV);
2280 if (
Value ==
nullptr)
continue;
2281 if (
Value->getFrameIndex() != FI)
continue;
2290 report(
"Missing fixed stack memoperand.",
MI);
2292 if (loads && !LI.
liveAt(
Idx.getRegSlot(
true))) {
2293 report(
"Instruction loads from dead spill slot", MO, MONum);
2294 errs() <<
"Live stack: " << LI <<
'\n';
2297 report(
"Instruction stores to dead spill slot", MO, MONum);
2298 errs() <<
"Live stack: " << LI <<
'\n';
2304 if (MO->
getCFIIndex() >= MF->getFrameInstructions().size())
2305 report(
"CFI instruction has invalid index", MO, MONum);
2313void MachineVerifier::checkLivenessAtUse(
const MachineOperand *MO,
2322 report(
"No live segment at use", MO, MONum);
2323 report_context_liverange(LR);
2324 report_context_vreg_regunit(VRegOrUnit);
2325 report_context(UseIdx);
2328 report(
"Live range continues after kill flag", MO, MONum);
2329 report_context_liverange(LR);
2330 report_context_vreg_regunit(VRegOrUnit);
2332 report_context_lanemask(LaneMask);
2333 report_context(UseIdx);
2337void MachineVerifier::checkLivenessAtDef(
const MachineOperand *MO,
2352 if (((SubRangeCheck || MO->
getSubReg() == 0) && VNI->def != DefIdx) ||
2354 (VNI->def != DefIdx &&
2355 (!VNI->def.isEarlyClobber() || !DefIdx.
isRegister()))) {
2356 report(
"Inconsistent valno->def", MO, MONum);
2357 report_context_liverange(LR);
2358 report_context_vreg_regunit(VRegOrUnit);
2360 report_context_lanemask(LaneMask);
2361 report_context(*VNI);
2362 report_context(DefIdx);
2365 report(
"No live segment at def", MO, MONum);
2366 report_context_liverange(LR);
2367 report_context_vreg_regunit(VRegOrUnit);
2369 report_context_lanemask(LaneMask);
2370 report_context(DefIdx);
2382 if (SubRangeCheck || MO->
getSubReg() == 0) {
2383 report(
"Live range continues after dead def flag", MO, MONum);
2384 report_context_liverange(LR);
2385 report_context_vreg_regunit(VRegOrUnit);
2387 report_context_lanemask(LaneMask);
2393void MachineVerifier::checkLiveness(
const MachineOperand *MO,
unsigned MONum) {
2396 const unsigned SubRegIdx = MO->
getSubReg();
2399 if (LiveInts &&
Reg.isVirtual()) {
2404 report(
"Live interval for subreg operand has no subranges", MO, MONum);
2406 report(
"Virtual register has no live interval", MO, MONum);
2413 addRegWithSubRegs(regsKilled, Reg);
2418 if (LiveVars &&
Reg.isVirtual() && MO->
isKill() &&
2419 !
MI->isBundledWithPred()) {
2422 report(
"Kill missing from LiveVariables", MO, MONum);
2429 if (
Reg.isPhysical() && !isReserved(Reg)) {
2432 if (
MRI->isReservedRegUnit(*Units))
2435 checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
2439 if (
Reg.isVirtual()) {
2441 checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2445 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2446 :
MRI->getMaxLaneMaskForVReg(Reg);
2449 if ((MOMask & SR.LaneMask).none())
2451 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2454 LiveInMask |= SR.LaneMask;
2457 if ((LiveInMask & MOMask).
none()) {
2458 report(
"No live subrange at use", MO, MONum);
2459 report_context(*LI);
2460 report_context(UseIdx);
2467 if (!regsLive.count(Reg)) {
2468 if (
Reg.isPhysical()) {
2470 bool Bad = !isReserved(Reg);
2475 if (regsLive.count(
SubReg)) {
2487 if (!MOP.isReg() || !MOP.isImplicit())
2490 if (!MOP.getReg().isPhysical())
2498 report(
"Using an undefined physical register", MO, MONum);
2499 }
else if (
MRI->def_empty(Reg)) {
2500 report(
"Reading virtual register without a def", MO, MONum);
2502 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2506 if (MInfo.regsKilled.count(Reg))
2507 report(
"Using a killed virtual register", MO, MONum);
2508 else if (!
MI->isPHI())
2509 MInfo.vregsLiveIn.insert(std::make_pair(Reg,
MI));
2518 addRegWithSubRegs(regsDead, Reg);
2520 addRegWithSubRegs(regsDefined, Reg);
2523 if (
MRI->isSSA() &&
Reg.isVirtual() &&
2524 std::next(
MRI->def_begin(Reg)) !=
MRI->def_end())
2525 report(
"Multiple virtual register defs in SSA form", MO, MONum);
2532 if (
Reg.isVirtual()) {
2533 checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
2537 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2538 :
MRI->getMaxLaneMaskForVReg(Reg);
2540 if ((SR.LaneMask & MOMask).none())
2542 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg,
true, SR.LaneMask);
2554void MachineVerifier::visitMachineBundleAfter(
const MachineInstr *
MI) {
2555 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2556 set_union(MInfo.regsKilled, regsKilled);
2557 set_subtract(regsLive, regsKilled); regsKilled.clear();
2559 while (!regMasks.empty()) {
2562 if (
Reg.isPhysical() &&
2564 regsDead.push_back(Reg);
2567 set_union(regsLive, regsDefined); regsDefined.clear();
2572 MBBInfoMap[
MBB].regsLiveOut = regsLive;
2577 if (!(stop > lastIndex)) {
2578 report(
"Block ends before last instruction index",
MBB);
2579 errs() <<
"Block ends at " << stop
2580 <<
" last instruction was at " << lastIndex <<
'\n';
2595 template <
typename RegSetT>
void add(
const RegSetT &FromRegSet) {
2597 filterAndAdd(FromRegSet, VRegsBuffer);
2602 template <
typename RegSetT>
2603 bool filterAndAdd(
const RegSetT &FromRegSet,
2605 unsigned SparseUniverse = Sparse.size();
2606 unsigned NewSparseUniverse = SparseUniverse;
2607 unsigned NewDenseSize =
Dense.size();
2608 size_t Begin = ToVRegs.
size();
2610 if (!
Reg.isVirtual())
2613 if (
Index < SparseUniverseMax) {
2614 if (
Index < SparseUniverse && Sparse.test(
Index))
2616 NewSparseUniverse = std::max(NewSparseUniverse,
Index + 1);
2624 size_t End = ToVRegs.
size();
2631 Sparse.resize(NewSparseUniverse);
2632 Dense.reserve(NewDenseSize);
2633 for (
unsigned I = Begin;
I < End; ++
I) {
2636 if (
Index < SparseUniverseMax)
2645 static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2665class FilteringVRegSet {
2672 template <
typename RegSetT>
void addToFilter(
const RegSetT &RS) {
2677 template <
typename RegSetT>
bool add(
const RegSetT &RS) {
2680 return Filter.filterAndAdd(RS, VRegs);
2685 size_t size()
const {
return VRegs.
size(); }
2692void MachineVerifier::calcRegsPassed() {
2699 FilteringVRegSet VRegs;
2700 BBInfo &
Info = MBBInfoMap[MB];
2703 VRegs.addToFilter(
Info.regsKilled);
2704 VRegs.addToFilter(
Info.regsLiveOut);
2706 const BBInfo &PredInfo = MBBInfoMap[Pred];
2707 if (!PredInfo.reachable)
2710 VRegs.add(PredInfo.regsLiveOut);
2711 VRegs.add(PredInfo.vregsPassed);
2713 Info.vregsPassed.reserve(VRegs.size());
2714 Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2721void MachineVerifier::calcRegsRequired() {
2724 for (
const auto &
MBB : *MF) {
2725 BBInfo &MInfo = MBBInfoMap[&
MBB];
2727 BBInfo &PInfo = MBBInfoMap[Pred];
2728 if (PInfo.addRequired(MInfo.vregsLiveIn))
2734 for (
unsigned i = 1, e =
MI.getNumOperands(); i != e; i += 2) {
2736 if (!
MI.getOperand(i).isReg() || !
MI.getOperand(i).readsReg())
2743 BBInfo &PInfo = MBBInfoMap[Pred];
2744 if (PInfo.addRequired(Reg))
2752 while (!todo.
empty()) {
2755 BBInfo &MInfo = MBBInfoMap[
MBB];
2759 BBInfo &SInfo = MBBInfoMap[Pred];
2760 if (SInfo.addRequired(MInfo.vregsRequired))
2769 BBInfo &MInfo = MBBInfoMap[&
MBB];
2779 report(
"Expected first PHI operand to be a register def", &MODef, 0);
2784 report(
"Unexpected flag on PHI operand", &MODef, 0);
2787 report(
"Expected first PHI operand to be a virtual register", &MODef, 0);
2789 for (
unsigned I = 1,
E = Phi.getNumOperands();
I !=
E;
I += 2) {
2792 report(
"Expected PHI operand to be a register", &MO0,
I);
2797 report(
"Unexpected flag on PHI operand", &MO0,
I);
2801 report(
"Expected PHI operand to be a basic block", &MO1,
I + 1);
2807 report(
"PHI input is not a predecessor block", &MO1,
I + 1);
2811 if (MInfo.reachable) {
2813 BBInfo &PrInfo = MBBInfoMap[&Pre];
2814 if (!MO0.
isUndef() && PrInfo.reachable &&
2815 !PrInfo.isLiveOut(MO0.
getReg()))
2816 report(
"PHI operand is not live-out from predecessor", &MO0,
I);
2821 if (MInfo.reachable) {
2823 if (!seen.
count(Pred)) {
2824 report(
"Missing PHI operand", &Phi);
2826 <<
" is a predecessor according to the CFG.\n";
2833void MachineVerifier::visitMachineFunctionAfter() {
2843 for (
const auto &
MBB : *MF) {
2844 BBInfo &MInfo = MBBInfoMap[&
MBB];
2845 for (
Register VReg : MInfo.vregsRequired)
2846 if (MInfo.regsKilled.count(VReg)) {
2847 report(
"Virtual register killed in block, but needed live out.", &
MBB);
2849 <<
" is used after the block.\n";
2854 BBInfo &MInfo = MBBInfoMap[&MF->front()];
2855 for (
Register VReg : MInfo.vregsRequired) {
2856 report(
"Virtual register defs don't dominate all uses.", MF);
2857 report_context_vreg(VReg);
2862 verifyLiveVariables();
2864 verifyLiveIntervals();
2873 if (
MRI->tracksLiveness())
2874 for (
const auto &
MBB : *MF)
2878 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
2881 BBInfo &PInfo = MBBInfoMap[Pred];
2882 if (!PInfo.regsLiveOut.count(LiveInReg)) {
2883 report(
"Live in register not found to be live out from predecessor.",
2885 errs() <<
TRI->getName(LiveInReg)
2886 <<
" not found to be live out from "
2892 for (
auto CSInfo : MF->getCallSitesInfo())
2893 if (!CSInfo.first->isCall())
2894 report(
"Call site info referencing instruction that is not call", MF);
2898 if (MF->getFunction().getSubprogram()) {
2900 for (
const auto &
MBB : *MF) {
2901 for (
const auto &
MI :
MBB) {
2902 if (
auto Num =
MI.peekDebugInstrNum()) {
2905 report(
"Instruction has a duplicated value tracking number", &
MI);
2912void MachineVerifier::verifyLiveVariables() {
2913 assert(LiveVars &&
"Don't call verifyLiveVariables without LiveVars");
2914 for (
unsigned I = 0,
E =
MRI->getNumVirtRegs();
I !=
E; ++
I) {
2917 for (
const auto &
MBB : *MF) {
2918 BBInfo &MInfo = MBBInfoMap[&
MBB];
2921 if (MInfo.vregsRequired.count(Reg)) {
2923 report(
"LiveVariables: Block missing from AliveBlocks", &
MBB);
2925 <<
" must be live through the block.\n";
2929 report(
"LiveVariables: Block should not be in AliveBlocks", &
MBB);
2931 <<
" is not needed live through the block.\n";
2938void MachineVerifier::verifyLiveIntervals() {
2939 assert(LiveInts &&
"Don't call verifyLiveIntervals without LiveInts");
2940 for (
unsigned I = 0,
E =
MRI->getNumVirtRegs();
I !=
E; ++
I) {
2944 if (
MRI->reg_nodbg_empty(Reg))
2948 report(
"Missing live interval for virtual register", MF);
2954 assert(Reg == LI.
reg() &&
"Invalid reg to interval mapping");
2955 verifyLiveInterval(LI);
2959 for (
unsigned i = 0, e =
TRI->getNumRegUnits(); i != e; ++i)
2961 verifyLiveRange(*LR, i);
2964void MachineVerifier::verifyLiveRangeValue(
const LiveRange &LR,
2973 report(
"Value not live at VNInfo def and not marked unused", MF);
2974 report_context(LR, Reg, LaneMask);
2975 report_context(*VNI);
2979 if (DefVNI != VNI) {
2980 report(
"Live segment at def has different VNInfo", MF);
2981 report_context(LR, Reg, LaneMask);
2982 report_context(*VNI);
2988 report(
"Invalid VNInfo definition index", MF);
2989 report_context(LR, Reg, LaneMask);
2990 report_context(*VNI);
2996 report(
"PHIDef VNInfo is not defined at MBB start",
MBB);
2997 report_context(LR, Reg, LaneMask);
2998 report_context(*VNI);
3006 report(
"No instruction at VNInfo def index",
MBB);
3007 report_context(LR, Reg, LaneMask);
3008 report_context(*VNI);
3013 bool hasDef =
false;
3014 bool isEarlyClobber =
false;
3016 if (!MOI->isReg() || !MOI->isDef())
3018 if (
Reg.isVirtual()) {
3019 if (MOI->getReg() != Reg)
3022 if (!MOI->getReg().isPhysical() || !
TRI->hasRegUnit(MOI->getReg(), Reg))
3025 if (LaneMask.
any() &&
3026 (
TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3029 if (MOI->isEarlyClobber())
3030 isEarlyClobber =
true;
3034 report(
"Defining instruction does not modify register",
MI);
3035 report_context(LR, Reg, LaneMask);
3036 report_context(*VNI);
3041 if (isEarlyClobber) {
3043 report(
"Early clobber def must be at an early-clobber slot",
MBB);
3044 report_context(LR, Reg, LaneMask);
3045 report_context(*VNI);
3048 report(
"Non-PHI, non-early clobber def must be at a register slot",
MBB);
3049 report_context(LR, Reg, LaneMask);
3050 report_context(*VNI);
3055void MachineVerifier::verifyLiveRangeSegment(
const LiveRange &LR,
3061 assert(VNI &&
"Live segment has no valno");
3064 report(
"Foreign valno in live segment", MF);
3065 report_context(LR, Reg, LaneMask);
3067 report_context(*VNI);
3071 report(
"Live segment valno is marked unused", MF);
3072 report_context(LR, Reg, LaneMask);
3078 report(
"Bad start of live segment, no basic block", MF);
3079 report_context(LR, Reg, LaneMask);
3085 report(
"Live segment must begin at MBB entry or valno def",
MBB);
3086 report_context(LR, Reg, LaneMask);
3093 report(
"Bad end of live segment, no basic block", MF);
3094 report_context(LR, Reg, LaneMask);
3112 report(
"Live segment doesn't end at a valid instruction", EndMBB);
3113 report_context(LR, Reg, LaneMask);
3120 report(
"Live segment ends at B slot of an instruction", EndMBB);
3121 report_context(LR, Reg, LaneMask);
3129 report(
"Live segment ending at dead slot spans instructions", EndMBB);
3130 report_context(LR, Reg, LaneMask);
3139 if (MF->getProperties().hasProperty(
3142 if (
I+1 == LR.
end() || (
I+1)->start != S.
end) {
3143 report(
"Live segment ending at early clobber slot must be "
3144 "redefined by an EC def in the same instruction", EndMBB);
3145 report_context(LR, Reg, LaneMask);
3152 if (
Reg.isVirtual()) {
3155 bool hasRead =
false;
3156 bool hasSubRegDef =
false;
3157 bool hasDeadDef =
false;
3159 if (!MOI->isReg() || MOI->getReg() != Reg)
3161 unsigned Sub = MOI->getSubReg();
3166 hasSubRegDef =
true;
3175 if (LaneMask.
any() && (LaneMask & SLM).none())
3177 if (MOI->readsReg())
3184 if (LaneMask.
none() && !hasDeadDef) {
3185 report(
"Instruction ending live segment on dead slot has no dead flag",
3187 report_context(LR, Reg, LaneMask);
3194 if (!
MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.
any() ||
3196 report(
"Instruction ending live segment doesn't read the register",
3198 report_context(LR, Reg, LaneMask);
3217 if (LaneMask.
any()) {
3225 if (!
Reg.isVirtual() && MFI->isEHPad()) {
3226 if (&*MFI == EndMBB)
3240 if (MFI->isEHPad()) {
3254 if (!PVNI && (LaneMask.
none() || !IsPHI)) {
3257 report(
"Register not marked live out of predecessor", Pred);
3258 report_context(LR, Reg, LaneMask);
3259 report_context(*VNI);
3267 if (!IsPHI && PVNI != VNI) {
3268 report(
"Different value live out of predecessor", Pred);
3269 report_context(LR, Reg, LaneMask);
3270 errs() <<
"Valno #" << PVNI->
id <<
" live out of "
3276 if (&*MFI == EndMBB)
3285 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3288 verifyLiveRangeSegment(LR,
I, Reg, LaneMask);
3291void MachineVerifier::verifyLiveInterval(
const LiveInterval &LI) {
3294 verifyLiveRange(LI, Reg);
3299 if ((Mask & SR.LaneMask).any()) {
3300 report(
"Lane masks of sub ranges overlap in live interval", MF);
3303 if ((SR.LaneMask & ~MaxMask).any()) {
3304 report(
"Subrange lanemask is invalid", MF);
3308 report(
"Subrange must not be empty", MF);
3309 report_context(SR, LI.
reg(), SR.LaneMask);
3311 Mask |= SR.LaneMask;
3312 verifyLiveRange(SR, LI.
reg(), SR.LaneMask);
3314 report(
"A Subrange is not covered by the main range", MF);
3321 unsigned NumComp = ConEQ.Classify(LI);
3323 report(
"Multiple connected components in live interval", MF);
3325 for (
unsigned comp = 0; comp != NumComp; ++comp) {
3326 errs() << comp <<
": valnos";
3328 if (comp == ConEQ.getEqClass(
I))
3329 errs() <<
' ' <<
I->id;
3341 struct StackStateOfBB {
3342 StackStateOfBB() =
default;
3343 StackStateOfBB(
int EntryVal,
int ExitVal,
bool EntrySetup,
bool ExitSetup) :
3344 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3345 ExitIsSetup(ExitSetup) {}
3350 bool EntryIsSetup =
false;
3351 bool ExitIsSetup =
false;
3359void MachineVerifier::verifyStackFrame() {
3360 unsigned FrameSetupOpcode =
TII->getCallFrameSetupOpcode();
3361 unsigned FrameDestroyOpcode =
TII->getCallFrameDestroyOpcode();
3362 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3366 SPState.
resize(MF->getNumBlockIDs());
3373 DFI != DFE; ++DFI) {
3376 StackStateOfBB BBState;
3378 if (DFI.getPathLength() >= 2) {
3381 "DFS stack predecessor is already visited.\n");
3382 BBState.EntryValue = SPState[StackPred->
getNumber()].ExitValue;
3383 BBState.EntryIsSetup = SPState[StackPred->
getNumber()].ExitIsSetup;
3384 BBState.ExitValue = BBState.EntryValue;
3385 BBState.ExitIsSetup = BBState.EntryIsSetup;
3389 for (
const auto &
I : *
MBB) {
3390 if (
I.getOpcode() == FrameSetupOpcode) {
3391 if (BBState.ExitIsSetup)
3392 report(
"FrameSetup is after another FrameSetup", &
I);
3393 BBState.ExitValue -=
TII->getFrameTotalSize(
I);
3394 BBState.ExitIsSetup =
true;
3397 if (
I.getOpcode() == FrameDestroyOpcode) {
3398 int Size =
TII->getFrameTotalSize(
I);
3399 if (!BBState.ExitIsSetup)
3400 report(
"FrameDestroy is not after a FrameSetup", &
I);
3401 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3403 if (BBState.ExitIsSetup && AbsSPAdj !=
Size) {
3404 report(
"FrameDestroy <n> is after FrameSetup <m>", &
I);
3405 errs() <<
"FrameDestroy <" <<
Size <<
"> is after FrameSetup <"
3406 << AbsSPAdj <<
">.\n";
3408 BBState.ExitValue +=
Size;
3409 BBState.ExitIsSetup =
false;
3417 if (Reachable.
count(Pred) &&
3418 (SPState[Pred->
getNumber()].ExitValue != BBState.EntryValue ||
3419 SPState[Pred->
getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3420 report(
"The exit stack state of a predecessor is inconsistent.",
MBB);
3422 <<
" has exit state (" << SPState[Pred->
getNumber()].ExitValue
3423 <<
", " << SPState[Pred->
getNumber()].ExitIsSetup <<
"), while "
3425 << BBState.EntryValue <<
", " << BBState.EntryIsSetup <<
").\n";
3432 if (Reachable.
count(Succ) &&
3433 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3434 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3435 report(
"The entry stack state of a successor is inconsistent.",
MBB);
3437 <<
" has entry state (" << SPState[Succ->getNumber()].EntryValue
3438 <<
", " << SPState[Succ->getNumber()].EntryIsSetup <<
"), while "
3440 << BBState.ExitValue <<
", " << BBState.ExitIsSetup <<
").\n";
3446 if (BBState.ExitIsSetup)
3447 report(
"A return block ends with a FrameSetup.",
MBB);
3448 if (BBState.ExitValue)
3449 report(
"A return block ends with a nonzero stack adjustment.",
MBB);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator MBBI
static bool isLoad(int Opcode)
static bool isStore(int Opcode)
SmallVector< MachineOperand, 4 > Cond
This file implements the BitVector class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
This file defines the DenseSet and SmallDenseSet classes.
This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.
const HexagonInstrInfo * TII
A common definition of LaneBitmask for use in TableGen and CodeGen.
Implement a low-level type suitable for MachineInstr level instruction selection.
unsigned const TargetRegisterInfo * TRI
modulo schedule Modulo Schedule test pass
return ToRemove size() > 0
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
This file defines generic set operations that may be used on set's of different types,...
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
static unsigned getSize(unsigned Kind)
const fltSemantics & getSemantics() const
Represent the analysis usage information of a pass.
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
void setPreservesAll()
Set by analyses that do not transform their input at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches,...
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
bool test(unsigned Idx) const
void clear()
clear - Removes all bits from the bitvector.
iterator_range< const_set_bits_iterator > set_bits() const
size_type size() const
size - Returns the number of bits in this bitvector.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Implements a dense probed hash-table based set.
Base class for user error types.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
FunctionPass class - This class is used to implement most global optimizations.
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr unsigned getAddressSpace() const
constexpr LLT getScalarType() const
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
bool hasInterval(Register Reg) const
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Result of a LiveRange query.
bool isDeadDef() const
Return true if this instruction has a dead def.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
bool isKill() const
Return true if the live-in value is killed by this instruction.
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
This class represents the liveness of a register, stack slot, etc.
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
bool liveAt(SlotIndex index) const
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
unsigned getNumValNums() const
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
LiveInterval & getInterval(int Slot)
bool hasInterval(int Slot) const
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
This class is intended to be used as a base class for asm properties and features specific to the tar...
ExceptionHandling getExceptionHandlingType() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getOpcode() const
Return the opcode number for this descriptor.
This holds information about one operand of a machine instruction, indicating the register class for ...
bool isOptionalDef() const
Set if this operand is a optional def.
uint8_t OperandType
Information about the type of the operand.
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool isValid() const
isValid - Returns true until all the operands have been visited.
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
iterator_range< livein_iterator > liveins() const
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
succ_iterator succ_begin()
bool isIRBlockAddressTaken() const
Test whether this block is the target of an IR BlockAddress.
unsigned succ_size() const
BasicBlock * getAddressTakenIRBlock() const
Retrieves the BasicBlock which corresponds to this MachineBasicBlock.
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
pred_iterator pred_begin()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< succ_iterator > successors()
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
An AnalysisManager<MachineFunction> that also exposes IR analysis results.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isReturn(QueryType Type=AnyInBundle) const
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
A description of a memory reference used in the backend.
const PseudoSourceValue * getPseudoValue() const
uint64_t getSize() const
Return the size in bytes of the memory reference.
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isIntrinsicID() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isShuffleMask() const
unsigned getCFIIndex() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
Intrinsic::ID getIntrinsicID() const
bool isInternalRead() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This class implements the register bank concept.
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
const char * getName() const
Get a user friendly name of this register bank.
Wrapper class representing virtual and physical registers.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
SlotIndex - An opaque wrapper around machine indexes.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
VNInfo - Value Number Information.
bool isUnused() const
Returns true if this value is unused.
unsigned id
The ID number of this value.
SlotIndex def
The index of the defining instruction.
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
Iterator for intrusive lists based on ilist_node.
self_iterator getIterator()
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
const CustomOperand< const MCSubtargetInfo & > Msg[]
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
Reg
All possible values of the reg field in the ModR/M byte.
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
const_iterator end(StringRef path)
Get end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
@ SjLj
setjmp/longjmp based exceptions
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
void initializeMachineVerifierPassPass(PassRegistry &)
auto reverse(ContainerTy &&C)
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
void verifyMachineFunction(MachineFunctionAnalysisManager *, const std::string &Banner, const MachineFunction &MF)
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
static constexpr LaneBitmask getAll()
constexpr bool none() const
constexpr bool any() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
Pair of physical register and lane mask.