35#define DEBUG_TYPE "regalloc"
61void LiveRangeCalc::updateFromLiveIns() {
63 for (
const LiveInBlock &
I : LiveIn) {
67 assert(
I.Value &&
"No live-in value found");
81 Updater.
add(Start,
End,
I.Value);
88 assert(
Use.isValid() &&
"Invalid SlotIndex");
89 assert(Indexes &&
"Missing SlotIndexes");
90 assert(DomTree &&
"Missing dominator tree");
93 assert(UseMBB &&
"No MBB at Use");
97 if (EP.first !=
nullptr || EP.second)
104 if (findReachingDefs(LR, *UseMBB,
Use, PhysReg, Undefs))
115 assert(Indexes &&
"Missing SlotIndexes");
116 assert(DomTree &&
"Missing dominator tree");
127 if (UndefOnEntry[BN])
132 DefOnEntry[S->getNumber()] =
true;
133 DefOnEntry[BN] =
true;
141 WorkList.
insert(
P->getNumber());
143 for (
unsigned i = 0; i != WorkList.
size(); ++i) {
145 unsigned N = WorkList[i];
149 if (LOB.first !=
nullptr && LOB.first != &
UndefVNI)
150 return MarkDefined(
B);
159 if (UB != LR.
begin()) {
161 if (Seg.
end > Begin) {
168 return MarkDefined(
B);
175 UndefOnEntry[
N] =
true;
179 return MarkDefined(
B);
183 WorkList.
insert(
P->getNumber());
186 UndefOnEntry[BN] =
true;
199 bool UniqueVNI =
true;
202 bool FoundUndef =
false;
205 for (
unsigned i = 0; i != WorkList.
size(); ++i) {
212 <<
" does not have a corresponding definition on every path:\n";
228 <<
", but is missing from the live-in list.\n";
237 if (Seen.
test(Pred->getNumber())) {
238 if (
VNInfo *VNI = Map[Pred].first) {
239 if (TheVNI && TheVNI != VNI)
253 FoundUndef |= EP.second;
256 if (TheVNI && TheVNI != VNI)
260 if (VNI || EP.second)
265 WorkList.push_back(Pred->getNumber());
273 FoundUndef |= (TheVNI ==
nullptr || TheVNI == &
UndefVNI);
274 if (!Undefs.
empty() && FoundUndef)
279 if (WorkList.
size() > 4)
286 for (
unsigned BN : WorkList) {
290 if (BN == UseMBBNum &&
Use.isValid())
294 Updater.
add(Start,
End, TheVNI);
302 std::tie(Entry, DidInsert) = EntryInfos.
insert(
307 Entry->second.first.resize(
N);
308 Entry->second.second.resize(
N);
315 LiveIn.reserve(WorkList.size());
316 for (
unsigned BN : WorkList) {
318 if (!Undefs.
empty() &&
319 !isDefOnEntry(LR, Undefs, *
MBB, DefOnEntry, UndefOnEntry))
323 LiveIn.back().Kill =
Use;
331void LiveRangeCalc::updateSSA() {
332 assert(Indexes &&
"Missing SlotIndexes");
333 assert(DomTree &&
"Missing dominator tree");
341 for (LiveInBlock &
I : LiveIn) {
352 bool needPHI = !IDom || !Seen.
test(IDom->
getBlock()->getNumber());
361 if (IDomValue.first && IDomValue.first != &
UndefVNI &&
363 Map[IDom->
getBlock()].second = IDomValue.second =
369 if (!
Value.first ||
Value.first == IDomValue.first)
399 assert(Alloc &&
"Need VNInfo allocator to create PHI-defs");
409 if (
I.Kill.isValid()) {
417 }
else if (IDomValue.first && IDomValue.first != &
UndefVNI) {
419 I.Value = IDomValue.first;
422 if (
I.Kill.isValid())
427 if (LOP.first == IDomValue.first)
447 for (
unsigned i = 0; i != PredQueue.
size(); ++i) {
448 unsigned BN = PredQueue[i];
451 if (BN == EntryNum) {
458 PredQueue.
insert(
P->getNumber());
This file implements the BitVector class.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static VNInfo UndefVNI(0xbad, SlotIndex())
static VNInfo UndefVNI(0xbad, SlotIndex())
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool empty() const
empty - Check if the array is empty.
bool test(unsigned Idx) const
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void clear()
clear - Removes all bits from the bitvector.
Allocate memory in an ever growing pool, as if by bump-pointer.
DenseMapIterator< KeyT, ValueT, KeyInfoT, BucketT > iterator
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Base class for the actual dominator tree node.
DomTreeNodeBase< NodeT > * getNode(const NodeT *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
void resize(typename StorageT::size_type s)
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
void addLiveInBlock(LiveRange &LR, MachineDomTreeNode *DomNode, SlotIndex Kill=SlotIndex())
addLiveInBlock - Add a block with an unknown live-in value.
void resetLiveOutMap()
Reset Map and Seen fields.
void reset(const MachineFunction *mf, SlotIndexes *SI, MachineDominatorTree *MDT, VNInfo::Allocator *VNIA)
reset - Prepare caches for a new set of non-overlapping live ranges.
void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, ArrayRef< SlotIndex > Undefs)
Extend the live range of LR to reach Use.
void calculateValues()
calculateValues - Calculate the value that will be live-in to each block added with addLiveInBlock.
void setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI)
setLiveOutValue - Indicate that VNI is live out from MBB.
Helper class for performant LiveRange bulk updates.
void setDest(LiveRange *lr)
Select a different destination live range.
void add(LiveRange::Segment)
Add a segment to LR and coalesce when possible, just like LR.addSegment().
This class represents the liveness of a register, stack slot, etc.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
std::pair< VNInfo *, bool > extendInBlock(ArrayRef< SlotIndex > Undefs, SlotIndex StartIdx, SlotIndex Kill)
Attempt to extend a value defined after StartIdx to include Use.
bool isUndefIn(ArrayRef< SlotIndex > Undefs, SlotIndex Begin, SlotIndex End) const
Returns true if there is an explicit "undef" between Begin End.
VNInfo * getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
MCRegAliasIterator enumerates all registers aliasing Reg.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< pred_iterator > predecessors()
bool isLiveIn(MCRegister Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool dominates(const MachineInstr *A, const MachineInstr *B) const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
bool verify(Pass *p=nullptr, const char *Banner=nullptr, raw_ostream *OS=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const MachineBasicBlock & front() const
Representation of each machine instruction.
const TargetRegisterInfo * getTargetRegisterInfo() const
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
A vector that has set insertion semantics.
size_type size() const
Determine the number of elements in the SetVector.
iterator end()
Get an iterator to the end of the SetVector.
iterator begin()
Get an iterator to the beginning of the SetVector.
bool insert(const value_type &X)
Insert a new element into the SetVector.
SlotIndex - An opaque wrapper around machine indexes.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
const std::pair< SlotIndex, SlotIndex > & getMBBRange(unsigned Num) const
Return the (start,end) range of the given basic block number.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A Use represents the edge between a Value definition and its users.
VNInfo - Value Number Information.
LLVM Value Representation.
This is an optimization pass for GlobalISel generic memory operations.
auto upper_bound(R &&Range, T &&Value)
Provide wrappers to std::upper_bound which take ranges instead of having to pass begin/end explicitly...
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void array_pod_sort(IteratorTy Start, IteratorTy End)
array_pod_sort - This sorts an array with the specified start and end extent.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
This represents a simple continuous liveness interval for a value.