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14 #ifndef LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
15 #define LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
100 std::pair<unsigned, const TargetRegisterClass *>
105 const char *Constraint)
const override;
107 std::vector<SDValue> &Ops,
113 const APInt &DemandedElts,
115 unsigned Depth = 0)
const override;
157 #endif // LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
This is an optimization pass for GlobalISel generic memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Represents one node in the SelectionDAG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const
unsigned const TargetRegisterInfo * TRI
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Analysis containing CSE Info
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
This is an important class for using LLVM in a threaded context.
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override
Examine constraint string and operand type and determine a weight value.
This contains information for each constraint that we are lowering.
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
This structure contains all information that is necessary for lowering calls.
Primary interface to the complete machine description for the target machine.
Class for arbitrary precision integers.
StringRef - Represent a constant reference to a string, i.e.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Wrapper class representing virtual and physical registers.
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const
amdgpu Simplify well known AMD library false FunctionCallee Callee
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI)
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const char LLVMTargetMachineRef TM
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const