41#define DEBUG_TYPE "function-lowering-info"
47 if (
I->use_empty())
return false;
48 if (isa<PHINode>(
I))
return true;
50 for (
const User *U :
I->users())
51 if (cast<Instruction>(U)->
getParent() != BB || isa<PHINode>(U))
66 unsigned NumOfSigned = 0, NumOfUnsigned = 0;
67 for (
const User *U :
I->users()) {
68 if (
const auto *CI = dyn_cast<CmpInst>(U)) {
69 NumOfSigned += CI->isSigned();
70 NumOfUnsigned += CI->isUnsigned();
73 if (NumOfSigned > NumOfUnsigned)
115 CatchObjects.
insert({AI, {}}).first->second.push_back(
116 &
H.CatchObj.FrameIndex);
118 H.CatchObj.FrameIndex = INT_MAX;
129 if (
const AllocaInst *AI = dyn_cast<AllocaInst>(&
I)) {
130 Type *Ty = AI->getAllocatedType();
131 Align Alignment = AI->getAlign();
136 if (AI->isStaticAlloca() &&
138 const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
143 if (TySize == 0) TySize = 1;
144 int FrameIndex = INT_MAX;
145 auto Iter = CatchObjects.
find(AI);
148 TySize, 0,
false,
true);
164 if (Iter != CatchObjects.
end()) {
165 for (
int *CatchObjPtr : Iter->second)
166 *CatchObjPtr = FrameIndex;
174 Alignment <= StackAlign ?
Align(1) : Alignment, AI);
176 }
else if (
auto *Call = dyn_cast<CallBase>(&
I)) {
178 if (Call->isInlineAsm()) {
181 std::vector<TargetLowering::AsmOperandInfo> Ops =
188 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
191 if (PhysReg.first == SP)
199 if (
const auto *II = dyn_cast<IntrinsicInst>(&
I)) {
200 if (II->getIntrinsicID() == Intrinsic::vastart)
206 if (
const auto *CI = dyn_cast<CallInst>(&
I)) {
235 if (!isa<LandingPadInst>(PadInst)) {
240 if (isa<CatchSwitchInst>(PadInst)) {
241 assert(&*BB.begin() == PadInst &&
242 "WinEHPrepare failed to remove PHIs from imaginary BBs");
245 if (isa<FuncletPadInst>(PadInst))
246 assert(&*BB.begin() == PadInst &&
"WinEHPrepare failed to demote PHIs");
256 if (BB.hasAddressTaken())
265 for (
const PHINode &PN : BB.phis()) {
270 if (PN.getType()->isEmptyTy())
275 assert(PHIReg &&
"PHI node does not have an assigned virtual register!");
279 for (
EVT VT : ValueVTs) {
282 for (
unsigned i = 0; i != NumRegisters; ++i)
284 PHIReg += NumRegisters;
296 H.Handler =
MBBMap[cast<const BasicBlock *>(
H.Handler)];
303 const auto *BB = cast<const BasicBlock *>(UME.Handler);
307 const auto *BB = cast<const BasicBlock *>(CME.
Handler);
317 const auto *Src = cast<const BasicBlock *>(KV.first);
318 const auto *Dest = cast<const BasicBlock *>(KV.second);
324 const auto *Dest = cast<const BasicBlock *>(KV.first);
326 for (
const auto P : KV.second)
328 MBBMap[cast<const BasicBlock *>(
P)]);
342 LiveOutRegInfo.clear();
377 for (
unsigned i = 0; i != NumRegs; ++i) {
379 if (!FirstReg) FirstReg = R;
397 if (!LiveOutRegInfo.inBounds(Reg))
422 "PHIs with non-vector integer types should have a single VT.");
423 EVT IntVT = ValueVTs[0];
438 LiveOutRegInfo.grow(DestReg);
442 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
458 "CopyToReg node was created.");
474 "Masks should have the same bit width as the type.");
478 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
497 "its CopyToReg node was created.");
528 LLVM_DEBUG(
dbgs() <<
"Argument does not have assigned frame index!\n");
538 VReg =
MRI.createVirtualRegister(RC);
539 assert(VReg &&
"null vreg in exception pointer table!");
550 P.first->getType(), ValueVTs);
551 unsigned Reg =
P.second;
552 for (
EVT VT : ValueVTs) {
554 for (
unsigned i = 0, e = NumRegisters; i != e; ++i)
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements a class to represent arbitrary precision integral constant values and operations...
static const Function * getParent(const Value *V)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static ISD::NodeType getPreferredExtendForValue(const Instruction *I)
static bool isUsedOutsideOfDefiningBlock(const Instruction *I)
isUsedOutsideOfDefiningBlock - Return true if this instruction is used by PHI nodes or outside of the...
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
Module.h This file contains the declarations for the Module class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
APInt zext(unsigned width) const
Zero extend to a new width.
unsigned getBitWidth() const
Return the number of bits in the APInt.
unsigned getNumSignBits() const
Computes the number of leading bits of this APInt that are equal to its sign bit.
APInt sext(unsigned width) const
Sign extend to a new width.
an instruction to allocate memory on the stack
This class represents an incoming formal argument to a Function.
LLVM Basic Block Representation.
void clear()
clear - Removes all bits from the bitvector.
This is the shared class of boolean and integer constants.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
This class represents an Operation in the Expression.
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
iterator find(const_arg_type_t< KeyT > Val)
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Register CreateRegs(const Value *V)
void clear()
clear - Clear out all the function-specific state.
DenseSet< Register > RegsWithFixups
void setArgumentFrameIndex(const Argument *A, int FI)
setArgumentFrameIndex - Record frame index for the byval argument.
BitVector DescribedArgs
Bitvector with a bit set if corresponding argument is described in ArgDbgValues.
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block.
const UniformityInfo * UA
SmallPtrSet< const BasicBlock *, 4 > VisitedBBs
VisitedBBs - The set of basic blocks visited thus far by instruction selection.
DenseMap< const Instruction *, StatepointSpillMapTy > StatepointRelocationMaps
int getArgumentFrameIndex(const Argument *A)
getArgumentFrameIndex - Get frame index for the byval argument.
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
const LiveOutInfo * GetLiveOutRegInfo(Register Reg)
GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the register is a PHI destinat...
Register InitializeRegForValue(const Value *V)
SmallPtrSet< const DbgDeclareInst *, 8 > PreprocessedDbgDeclares
Collection of dbg.declare instructions handled after argument lowering and before ISel proper.
SmallVector< unsigned, 50 > StatepointStackSlots
StatepointStackSlots - A list of temporary stack slots (frame indices) used to spill values at a stat...
void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG)
set - Initialize this FunctionLoweringInfo with the given Function and its associated MachineFunction...
MachineBasicBlock * MBB
MBB - The current block.
DenseMap< const Argument *, int > ByValArgFrameIndexMap
ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
DenseMap< Register, Register > RegFixups
RegFixups - Registers which need to be replaced after isel is done.
SmallVector< MachineInstr *, 8 > ArgDbgValues
ArgDbgValues - A list of DBG_VALUE instructions created during isel for function arguments that are i...
void ComputePHILiveOutRegInfo(const PHINode *)
ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination register based on the LiveOutI...
const TargetLowering * TLI
const Value * getValueFromVirtualReg(Register Vreg)
This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence to get the Value correspondi...
DenseMap< Register, const Value * > VirtReg2Value
VirtReg2Value map is needed by the Divergence Analysis driven instruction selection.
MachineRegisterInfo * RegInfo
Register CreateReg(MVT VT, bool isDivergent=false)
CreateReg - Allocate a single virtual register for the given type.
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
DenseMap< const Value *, ISD::NodeType > PreferredExtendType
Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND) for a value.
Register getCatchPadExceptionPointerVReg(const Value *CPI, const TargetRegisterClass *RC)
DenseMap< const Value *, Register > CatchPadExceptionPointers
Track virtual registers created for exception pointers.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasPersonalityFn() const
Check whether this function has a personality function.
Constant * getPersonalityFn() const
Get the personality function associated with this function.
AttributeList getAttributes() const
Return the attribute list for this Function.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Type * getReturnType() const
Returns the type of the ret val.
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Module * getParent()
Get the module that this global value is contained inside of...
void setAddressTakenIRBlock(BasicBlock *BB)
Set this block to reflect that it corresponds to an IR-level basic block with a BlockAddress.
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setStackID(int ObjectIdx, uint8_t ID)
void setHasOpaqueSPAdjustment(bool B)
int CreateVariableSizedObject(Align Alignment, const AllocaInst *Alloca)
Notify the MachineFrameInfo object that a variable sized object has been created.
void setHasVAStart(bool B)
void setHasMustTailInVarArgFunc(bool B)
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
const WinEHFuncInfo * getWinEHFuncInfo() const
getWinEHFuncInfo - Return information about how the current function uses Windows exception handling.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void setHasEHFunclets(bool V)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void push_back(MachineBasicBlock *MBB)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
const WasmEHFuncInfo * getWasmEHFuncInfo() const
getWasmEHFuncInfo - Return information about how the current function uses Wasm exception handling.
void setHasEHScopes(bool V)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
unsigned getNumIncomingValues() const
Return the number of incoming edges.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
const UniformityInfo * getUniformityInfo() const
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Information about stack frame layout on the target.
bool isStackRealignable() const
isStackRealignable - This method returns whether the stack can be realigned.
virtual TargetStackID::Value getStackIDForScalableVectors() const
Returns the StackID that scalable vectors should be associated with.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
virtual bool requiresUniformRegister(MachineFunction &MF, const Value *) const
Allows target to decide about the register class of the specific value that is live outside the defin...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
virtual bool needsFixedCatchObjects() const
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
virtual bool signExtendConstant(const ConstantInt *C) const
Return true if this constant should be sign extended when promoting to a larger type.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo,...
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetLowering * getTargetLowering() const
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
bool isScalableTy() const
Return true if this is a type whose size is a known multiple of vscale.
bool isIntegerTy() const
True if this is an instance of IntegerType.
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
iterator find(const KeyT &Val)
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
LLVMContext & getContext() const
All values hold a context through their type.
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ SIGN_EXTEND
Conversion operators.
This is an optimization pass for GlobalISel generic memory operations.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< TypeSize > *Offsets, TypeSize StartingOffset)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void calculateWinCXXEHStateNumbers(const Function *ParentFn, WinEHFuncInfo &FuncInfo)
Analyze the IR in ParentFn and it's handlers to build WinEHFuncInfo, which describes the state number...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
bool isFuncletEHPersonality(EHPersonality Pers)
Returns true if this is a personality function that invokes handler funclets (which must return to it...
void calculateSEHStateNumbers(const Function *ParentFn, WinEHFuncInfo &FuncInfo)
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
constexpr unsigned BitWidth
void calculateWasmEHInfo(const Function *F, WasmEHFuncInfo &EHInfo)
void calculateClrEHStateNumbers(const Function *Fn, WinEHFuncInfo &FuncInfo)
This struct is a compact representation of a valid (non-zero power of two) alignment.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
static KnownBits makeConstant(const APInt &C)
Create known bits from a known constant.
unsigned getBitWidth() const
Get the bit width of this value.
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
KnownBits anyext(unsigned BitWidth) const
Return known bits for an "any" extension of the value we're tracking, where we don't know anything ab...
Similar to CxxUnwindMapEntry, but supports SEH filters.
This contains information for each constraint that we are lowering.
DenseMap< BBOrMBB, SmallPtrSet< BBOrMBB, 4 > > UnwindDestToSrcs
DenseMap< BBOrMBB, BBOrMBB > SrcToUnwindDest
SmallVector< SEHUnwindMapEntry, 4 > SEHUnwindMap
SmallVector< ClrEHUnwindMapEntry, 4 > ClrEHUnwindMap
SmallVector< WinEHTryBlockMapEntry, 4 > TryBlockMap
SmallVector< CxxUnwindMapEntry, 4 > CxxUnwindMap
SmallVector< WinEHHandlerType, 1 > HandlerArray