14#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
15#define LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H
28 mutable std::set<const MachineFunction *> ProcessedMF;
51 EVT VT)
const override;
53 EVT VT)
const override;
56 unsigned Intrinsic)
const override;
58 std::pair<unsigned, const TargetRegisterClass *>
63 std::optional<MVT> RegisterVT = std::nullopt)
const override {
73 EVT ConditionVT)
const override {
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
This class represents a function call, abstracting a target machine's calling convention.
A parsed version of the target data layout string in and methods for querying it.
This is an important class for using LLVM in a threaded context.
static MVT getIntegerVT(unsigned BitWidth)
MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const override
Returns preferred type for switch condition.
bool areJTsAllowed(const Function *) const override
Return true if lowering to a jump table is allowed.
unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const override
Return the number of registers that this ValueType will eventually require.
MVT getVectorIdxTy(const DataLayout &DL) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
SPIRVTargetLowering(const TargetMachine &TM, const SPIRVSubtarget &ST)
StringRef - Represent a constant reference to a string, i.e.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.