LLVM  15.0.0git
SPIRVISelLowering.cpp
Go to the documentation of this file.
1 //===- SPIRVISelLowering.cpp - SPIR-V DAG Lowering Impl ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SPIRVTargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SPIRVISelLowering.h"
14 #include "SPIRV.h"
15 
16 #define DEBUG_TYPE "spirv-lower"
17 
18 using namespace llvm;
19 
21  LLVMContext &Context, CallingConv::ID CC, EVT VT) const {
22  // This code avoids CallLowering fail inside getVectorTypeBreakdown
23  // on v3i1 arguments. Maybe we need to return 1 for all types.
24  // TODO: remove it once this case is supported by the default implementation.
25  if (VT.isVector() && VT.getVectorNumElements() == 3 &&
26  (VT.getVectorElementType() == MVT::i1 ||
28  return 1;
29  return getNumRegisters(Context, VT);
30 }
31 
33  CallingConv::ID CC,
34  EVT VT) const {
35  // This code avoids CallLowering fail inside getVectorTypeBreakdown
36  // on v3i1 arguments. Maybe we need to return i32 for all types.
37  // TODO: remove it once this case is supported by the default implementation.
38  if (VT.isVector() && VT.getVectorNumElements() == 3) {
39  if (VT.getVectorElementType() == MVT::i1)
40  return MVT::v4i1;
41  else if (VT.getVectorElementType() == MVT::i8)
42  return MVT::v4i8;
43  }
44  return getRegisterType(Context, VT);
45 }
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::SPIRVTargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
Definition: SPIRVISelLowering.cpp:20
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::EVT::getVectorNumElements
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:308
llvm::MVT::v4i8
@ v4i8
Definition: MachineValueType.h:84
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
SPIRV.h
SPIRVISelLowering.h
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: SPIRVISelLowering.cpp:32
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:300
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1513
llvm::TargetLoweringBase::getNumRegisters
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, Optional< MVT > RegisterVT=None) const
Return the number of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1551
llvm::MVT::v4i1
@ v4i1
Definition: MachineValueType.h:68