LLVM  16.0.0git
SPIRVISelLowering.cpp
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1 //===- SPIRVISelLowering.cpp - SPIR-V DAG Lowering Impl ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SPIRVTargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SPIRVISelLowering.h"
14 #include "SPIRV.h"
15 #include "llvm/IR/IntrinsicsSPIRV.h"
16 
17 #define DEBUG_TYPE "spirv-lower"
18 
19 using namespace llvm;
20 
23  // This code avoids CallLowering fail inside getVectorTypeBreakdown
24  // on v3i1 arguments. Maybe we need to return 1 for all types.
25  // TODO: remove it once this case is supported by the default implementation.
26  if (VT.isVector() && VT.getVectorNumElements() == 3 &&
27  (VT.getVectorElementType() == MVT::i1 ||
29  return 1;
30  return getNumRegisters(Context, VT);
31 }
32 
35  EVT VT) const {
36  // This code avoids CallLowering fail inside getVectorTypeBreakdown
37  // on v3i1 arguments. Maybe we need to return i32 for all types.
38  // TODO: remove it once this case is supported by the default implementation.
39  if (VT.isVector() && VT.getVectorNumElements() == 3) {
40  if (VT.getVectorElementType() == MVT::i1)
41  return MVT::v4i1;
42  else if (VT.getVectorElementType() == MVT::i8)
43  return MVT::v4i8;
44  }
45  return getRegisterType(Context, VT);
46 }
47 
49  const CallInst &I,
50  MachineFunction &MF,
51  unsigned Intrinsic) const {
52  unsigned AlignIdx = 3;
53  switch (Intrinsic) {
54  case Intrinsic::spv_load:
55  AlignIdx = 2;
57  case Intrinsic::spv_store: {
58  if (I.getNumOperands() >= AlignIdx + 1) {
59  auto *AlignOp = cast<ConstantInt>(I.getOperand(AlignIdx));
60  Info.align = Align(AlignOp->getZExtValue());
61  }
62  Info.flags = static_cast<MachineMemOperand::Flags>(
63  cast<ConstantInt>(I.getOperand(AlignIdx - 1))->getZExtValue());
64  Info.memVT = MVT::i64;
65  // TODO: take into account opaque pointers (don't use getElementType).
66  // MVT::getVT(PtrTy->getElementType());
67  return true;
68  break;
69  }
70  default:
71  break;
72  }
73  return false;
74 }
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::SPIRVTargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
Definition: SPIRVISelLowering.cpp:21
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::SPIRVTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: SPIRVISelLowering.cpp:48
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::EVT::getVectorNumElements
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:308
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::MVT::v4i8
@ v4i8
Definition: MachineValueType.h:87
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::TargetLoweringBase::getNumRegisters
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1586
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
SPIRV.h
SPIRVISelLowering.h
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:270
llvm::TargetLoweringBase::IntrinsicInfo
Definition: TargetLowering.h:1048
llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: SPIRVISelLowering.cpp:33
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:300
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:1548
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1474
llvm::MVT::v4i1
@ v4i1
Definition: MachineValueType.h:68