LLVM 19.0.0git
SPIRVGlobalRegistry.cpp
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1//===-- SPIRVGlobalRegistry.cpp - SPIR-V Global Registry --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the implementation of the SPIRVGlobalRegistry class,
10// which is used to maintain rich type information required for SPIR-V even
11// after lowering from LLVM IR to GMIR. It can convert an llvm::Type into
12// an OpTypeXXX instruction, and map it to a virtual register. Also it builds
13// and supports consistency of constants and global variables.
14//
15//===----------------------------------------------------------------------===//
16
17#include "SPIRVGlobalRegistry.h"
18#include "SPIRV.h"
19#include "SPIRVBuiltins.h"
20#include "SPIRVSubtarget.h"
21#include "SPIRVTargetMachine.h"
22#include "SPIRVUtils.h"
23#include "llvm/ADT/APInt.h"
24#include "llvm/IR/Constants.h"
25#include "llvm/IR/Type.h"
27#include <cassert>
28
29using namespace llvm;
31 : PointerSize(PointerSize), Bound(0) {}
32
34 Register VReg,
36 const SPIRVInstrInfo &TII) {
38 assignSPIRVTypeToVReg(SpirvType, VReg, *CurMF);
39 return SpirvType;
40}
41
45 const SPIRVInstrInfo &TII) {
47 assignSPIRVTypeToVReg(SpirvType, VReg, *CurMF);
48 return SpirvType;
49}
50
52 SPIRVType *BaseType, unsigned NumElements, Register VReg, MachineInstr &I,
53 const SPIRVInstrInfo &TII) {
54 SPIRVType *SpirvType =
56 assignSPIRVTypeToVReg(SpirvType, VReg, *CurMF);
57 return SpirvType;
58}
59
61 const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder,
62 SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) {
63 SPIRVType *SpirvType =
64 getOrCreateSPIRVType(Type, MIRBuilder, AccessQual, EmitIR);
65 assignSPIRVTypeToVReg(SpirvType, VReg, MIRBuilder.getMF());
66 return SpirvType;
67}
68
70 Register VReg,
71 MachineFunction &MF) {
72 VRegToTypeMap[&MF][VReg] = SpirvType;
73}
74
76 auto &MRI = MIRBuilder.getMF().getRegInfo();
77 auto Res = MRI.createGenericVirtualRegister(LLT::scalar(32));
78 MRI.setRegClass(Res, &SPIRV::TYPERegClass);
79 return Res;
80}
81
83 auto Res = MRI.createGenericVirtualRegister(LLT::scalar(32));
84 MRI.setRegClass(Res, &SPIRV::TYPERegClass);
85 return Res;
86}
87
88SPIRVType *SPIRVGlobalRegistry::getOpTypeBool(MachineIRBuilder &MIRBuilder) {
89 return MIRBuilder.buildInstr(SPIRV::OpTypeBool)
90 .addDef(createTypeVReg(MIRBuilder));
91}
92
93unsigned SPIRVGlobalRegistry::adjustOpTypeIntWidth(unsigned Width) const {
94 if (Width > 64)
95 report_fatal_error("Unsupported integer width!");
96 const SPIRVSubtarget &ST = cast<SPIRVSubtarget>(CurMF->getSubtarget());
97 if (ST.canUseExtension(
98 SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers))
99 return Width;
100 if (Width <= 8)
101 Width = 8;
102 else if (Width <= 16)
103 Width = 16;
104 else if (Width <= 32)
105 Width = 32;
106 else
107 Width = 64;
108 return Width;
109}
110
111SPIRVType *SPIRVGlobalRegistry::getOpTypeInt(unsigned Width,
112 MachineIRBuilder &MIRBuilder,
113 bool IsSigned) {
114 Width = adjustOpTypeIntWidth(Width);
115 const SPIRVSubtarget &ST =
116 cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
117 if (ST.canUseExtension(
118 SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers)) {
119 MIRBuilder.buildInstr(SPIRV::OpExtension)
120 .addImm(SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers);
121 MIRBuilder.buildInstr(SPIRV::OpCapability)
122 .addImm(SPIRV::Capability::ArbitraryPrecisionIntegersINTEL);
123 }
124 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeInt)
125 .addDef(createTypeVReg(MIRBuilder))
126 .addImm(Width)
127 .addImm(IsSigned ? 1 : 0);
128 return MIB;
129}
130
131SPIRVType *SPIRVGlobalRegistry::getOpTypeFloat(uint32_t Width,
132 MachineIRBuilder &MIRBuilder) {
133 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeFloat)
134 .addDef(createTypeVReg(MIRBuilder))
135 .addImm(Width);
136 return MIB;
137}
138
139SPIRVType *SPIRVGlobalRegistry::getOpTypeVoid(MachineIRBuilder &MIRBuilder) {
140 return MIRBuilder.buildInstr(SPIRV::OpTypeVoid)
141 .addDef(createTypeVReg(MIRBuilder));
142}
143
144SPIRVType *SPIRVGlobalRegistry::getOpTypeVector(uint32_t NumElems,
145 SPIRVType *ElemType,
146 MachineIRBuilder &MIRBuilder) {
147 auto EleOpc = ElemType->getOpcode();
148 (void)EleOpc;
149 assert((EleOpc == SPIRV::OpTypeInt || EleOpc == SPIRV::OpTypeFloat ||
150 EleOpc == SPIRV::OpTypeBool) &&
151 "Invalid vector element type");
152
153 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeVector)
154 .addDef(createTypeVReg(MIRBuilder))
155 .addUse(getSPIRVTypeID(ElemType))
156 .addImm(NumElems);
157 return MIB;
158}
159
160std::tuple<Register, ConstantInt *, bool>
161SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType,
162 MachineIRBuilder *MIRBuilder,
164 const SPIRVInstrInfo *TII) {
165 const IntegerType *LLVMIntTy;
166 if (SpvType)
167 LLVMIntTy = cast<IntegerType>(getTypeForSPIRVType(SpvType));
168 else
170 bool NewInstr = false;
171 // Find a constant in DT or build a new one.
172 ConstantInt *CI = ConstantInt::get(const_cast<IntegerType *>(LLVMIntTy), Val);
173 Register Res = DT.find(CI, CurMF);
174 if (!Res.isValid()) {
175 unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
176 // TODO: handle cases where the type is not 32bit wide
177 // TODO: https://github.com/llvm/llvm-project/issues/88129
178 LLT LLTy = LLT::scalar(32);
180 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
181 if (MIRBuilder)
182 assignTypeToVReg(LLVMIntTy, Res, *MIRBuilder);
183 else
185 DT.add(CI, CurMF, Res);
186 NewInstr = true;
187 }
188 return std::make_tuple(Res, CI, NewInstr);
189}
190
191std::tuple<Register, ConstantFP *, bool, unsigned>
192SPIRVGlobalRegistry::getOrCreateConstFloatReg(APFloat Val, SPIRVType *SpvType,
193 MachineIRBuilder *MIRBuilder,
195 const SPIRVInstrInfo *TII) {
196 const Type *LLVMFloatTy;
198 unsigned BitWidth = 32;
199 if (SpvType)
200 LLVMFloatTy = getTypeForSPIRVType(SpvType);
201 else {
202 LLVMFloatTy = Type::getFloatTy(Ctx);
203 if (MIRBuilder)
204 SpvType = getOrCreateSPIRVType(LLVMFloatTy, *MIRBuilder);
205 }
206 bool NewInstr = false;
207 // Find a constant in DT or build a new one.
208 auto *const CI = ConstantFP::get(Ctx, Val);
209 Register Res = DT.find(CI, CurMF);
210 if (!Res.isValid()) {
211 if (SpvType)
213 // TODO: handle cases where the type is not 32bit wide
214 // TODO: https://github.com/llvm/llvm-project/issues/88129
215 LLT LLTy = LLT::scalar(32);
217 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
218 if (MIRBuilder)
219 assignTypeToVReg(LLVMFloatTy, Res, *MIRBuilder);
220 else
222 DT.add(CI, CurMF, Res);
223 NewInstr = true;
224 }
225 return std::make_tuple(Res, CI, NewInstr, BitWidth);
226}
227
229 SPIRVType *SpvType,
230 const SPIRVInstrInfo &TII,
231 bool ZeroAsNull) {
232 assert(SpvType);
233 ConstantFP *CI;
234 Register Res;
235 bool New;
236 unsigned BitWidth;
237 std::tie(Res, CI, New, BitWidth) =
238 getOrCreateConstFloatReg(Val, SpvType, nullptr, &I, &TII);
239 // If we have found Res register which is defined by the passed G_CONSTANT
240 // machine instruction, a new constant instruction should be created.
241 if (!New && (!I.getOperand(0).isReg() || Res != I.getOperand(0).getReg()))
242 return Res;
244 MachineBasicBlock &BB = *I.getParent();
245 // In OpenCL OpConstantNull - Scalar floating point: +0.0 (all bits 0)
246 if (Val.isPosZero() && ZeroAsNull) {
247 MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))
248 .addDef(Res)
249 .addUse(getSPIRVTypeID(SpvType));
250 } else {
251 MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantF))
252 .addDef(Res)
253 .addUse(getSPIRVTypeID(SpvType));
254 addNumImm(
256 MIB);
257 }
258 const auto &ST = CurMF->getSubtarget();
259 constrainSelectedInstRegOperands(*MIB, *ST.getInstrInfo(),
260 *ST.getRegisterInfo(), *ST.getRegBankInfo());
261 return Res;
262}
263
265 SPIRVType *SpvType,
266 const SPIRVInstrInfo &TII,
267 bool ZeroAsNull) {
268 assert(SpvType);
269 ConstantInt *CI;
270 Register Res;
271 bool New;
272 std::tie(Res, CI, New) =
273 getOrCreateConstIntReg(Val, SpvType, nullptr, &I, &TII);
274 // If we have found Res register which is defined by the passed G_CONSTANT
275 // machine instruction, a new constant instruction should be created.
276 if (!New && (!I.getOperand(0).isReg() || Res != I.getOperand(0).getReg()))
277 return Res;
279 MachineBasicBlock &BB = *I.getParent();
280 if (Val || !ZeroAsNull) {
281 MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI))
282 .addDef(Res)
283 .addUse(getSPIRVTypeID(SpvType));
284 addNumImm(APInt(getScalarOrVectorBitWidth(SpvType), Val), MIB);
285 } else {
286 MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))
287 .addDef(Res)
288 .addUse(getSPIRVTypeID(SpvType));
289 }
290 const auto &ST = CurMF->getSubtarget();
291 constrainSelectedInstRegOperands(*MIB, *ST.getInstrInfo(),
292 *ST.getRegisterInfo(), *ST.getRegBankInfo());
293 return Res;
294}
295
297 MachineIRBuilder &MIRBuilder,
298 SPIRVType *SpvType,
299 bool EmitIR) {
300 auto &MF = MIRBuilder.getMF();
301 const IntegerType *LLVMIntTy;
302 if (SpvType)
303 LLVMIntTy = cast<IntegerType>(getTypeForSPIRVType(SpvType));
304 else
305 LLVMIntTy = IntegerType::getInt32Ty(MF.getFunction().getContext());
306 // Find a constant in DT or build a new one.
307 const auto ConstInt =
308 ConstantInt::get(const_cast<IntegerType *>(LLVMIntTy), Val);
309 Register Res = DT.find(ConstInt, &MF);
310 if (!Res.isValid()) {
311 unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
312 LLT LLTy = LLT::scalar(EmitIR ? BitWidth : 32);
313 Res = MF.getRegInfo().createGenericVirtualRegister(LLTy);
314 MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
315 assignTypeToVReg(LLVMIntTy, Res, MIRBuilder,
316 SPIRV::AccessQualifier::ReadWrite, EmitIR);
317 DT.add(ConstInt, &MIRBuilder.getMF(), Res);
318 if (EmitIR) {
319 MIRBuilder.buildConstant(Res, *ConstInt);
320 } else {
322 if (Val) {
323 assert(SpvType);
324 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantI)
325 .addDef(Res)
326 .addUse(getSPIRVTypeID(SpvType));
327 addNumImm(APInt(BitWidth, Val), MIB);
328 } else {
329 assert(SpvType);
330 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantNull)
331 .addDef(Res)
332 .addUse(getSPIRVTypeID(SpvType));
333 }
334 const auto &Subtarget = CurMF->getSubtarget();
335 constrainSelectedInstRegOperands(*MIB, *Subtarget.getInstrInfo(),
336 *Subtarget.getRegisterInfo(),
337 *Subtarget.getRegBankInfo());
338 }
339 }
340 return Res;
341}
342
344 MachineIRBuilder &MIRBuilder,
345 SPIRVType *SpvType) {
346 auto &MF = MIRBuilder.getMF();
347 auto &Ctx = MF.getFunction().getContext();
348 if (!SpvType) {
349 const Type *LLVMFPTy = Type::getFloatTy(Ctx);
350 SpvType = getOrCreateSPIRVType(LLVMFPTy, MIRBuilder);
351 }
352 // Find a constant in DT or build a new one.
353 const auto ConstFP = ConstantFP::get(Ctx, Val);
354 Register Res = DT.find(ConstFP, &MF);
355 if (!Res.isValid()) {
356 Res = MF.getRegInfo().createGenericVirtualRegister(LLT::scalar(32));
357 MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
358 assignSPIRVTypeToVReg(SpvType, Res, MF);
359 DT.add(ConstFP, &MF, Res);
360
362 MIB = MIRBuilder.buildInstr(SPIRV::OpConstantF)
363 .addDef(Res)
364 .addUse(getSPIRVTypeID(SpvType));
365 addNumImm(ConstFP->getValueAPF().bitcastToAPInt(), MIB);
366 }
367
368 return Res;
369}
370
371Register SPIRVGlobalRegistry::getOrCreateBaseRegister(Constant *Val,
373 SPIRVType *SpvType,
374 const SPIRVInstrInfo &TII,
375 unsigned BitWidth) {
376 SPIRVType *Type = SpvType;
377 if (SpvType->getOpcode() == SPIRV::OpTypeVector ||
378 SpvType->getOpcode() == SPIRV::OpTypeArray) {
379 auto EleTypeReg = SpvType->getOperand(1).getReg();
380 Type = getSPIRVTypeForVReg(EleTypeReg);
381 }
382 if (Type->getOpcode() == SPIRV::OpTypeFloat) {
384 return getOrCreateConstFP(dyn_cast<ConstantFP>(Val)->getValue(), I,
385 SpvBaseType, TII);
386 }
387 assert(Type->getOpcode() == SPIRV::OpTypeInt);
390 SpvBaseType, TII);
391}
392
393Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
394 Constant *Val, MachineInstr &I, SPIRVType *SpvType,
395 const SPIRVInstrInfo &TII, Constant *CA, unsigned BitWidth,
396 unsigned ElemCnt, bool ZeroAsNull) {
397 // Find a constant vector in DT or build a new one.
398 Register Res = DT.find(CA, CurMF);
399 // If no values are attached, the composite is null constant.
400 bool IsNull = Val->isNullValue() && ZeroAsNull;
401 if (!Res.isValid()) {
402 // SpvScalConst should be created before SpvVecConst to avoid undefined ID
403 // error on validation.
404 // TODO: can moved below once sorting of types/consts/defs is implemented.
405 Register SpvScalConst;
406 if (!IsNull)
407 SpvScalConst = getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth);
408
409 // TODO: handle cases where the type is not 32bit wide
410 // TODO: https://github.com/llvm/llvm-project/issues/88129
411 LLT LLTy = LLT::scalar(32);
412 Register SpvVecConst =
414 CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass);
415 assignSPIRVTypeToVReg(SpvType, SpvVecConst, *CurMF);
416 DT.add(CA, CurMF, SpvVecConst);
418 MachineBasicBlock &BB = *I.getParent();
419 if (!IsNull) {
420 MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantComposite))
421 .addDef(SpvVecConst)
422 .addUse(getSPIRVTypeID(SpvType));
423 for (unsigned i = 0; i < ElemCnt; ++i)
424 MIB.addUse(SpvScalConst);
425 } else {
426 MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))
427 .addDef(SpvVecConst)
428 .addUse(getSPIRVTypeID(SpvType));
429 }
430 const auto &Subtarget = CurMF->getSubtarget();
431 constrainSelectedInstRegOperands(*MIB, *Subtarget.getInstrInfo(),
432 *Subtarget.getRegisterInfo(),
433 *Subtarget.getRegBankInfo());
434 return SpvVecConst;
435 }
436 return Res;
437}
438
441 SPIRVType *SpvType,
442 const SPIRVInstrInfo &TII,
443 bool ZeroAsNull) {
444 const Type *LLVMTy = getTypeForSPIRVType(SpvType);
445 assert(LLVMTy->isVectorTy());
446 const FixedVectorType *LLVMVecTy = cast<FixedVectorType>(LLVMTy);
447 Type *LLVMBaseTy = LLVMVecTy->getElementType();
448 assert(LLVMBaseTy->isIntegerTy());
449 auto *ConstVal = ConstantInt::get(LLVMBaseTy, Val);
450 auto *ConstVec =
451 ConstantVector::getSplat(LLVMVecTy->getElementCount(), ConstVal);
452 unsigned BW = getScalarOrVectorBitWidth(SpvType);
453 return getOrCreateCompositeOrNull(ConstVal, I, SpvType, TII, ConstVec, BW,
454 SpvType->getOperand(2).getImm(),
455 ZeroAsNull);
456}
457
460 SPIRVType *SpvType,
461 const SPIRVInstrInfo &TII,
462 bool ZeroAsNull) {
463 const Type *LLVMTy = getTypeForSPIRVType(SpvType);
464 assert(LLVMTy->isVectorTy());
465 const FixedVectorType *LLVMVecTy = cast<FixedVectorType>(LLVMTy);
466 Type *LLVMBaseTy = LLVMVecTy->getElementType();
467 assert(LLVMBaseTy->isFloatingPointTy());
468 auto *ConstVal = ConstantFP::get(LLVMBaseTy, Val);
469 auto *ConstVec =
470 ConstantVector::getSplat(LLVMVecTy->getElementCount(), ConstVal);
471 unsigned BW = getScalarOrVectorBitWidth(SpvType);
472 return getOrCreateCompositeOrNull(ConstVal, I, SpvType, TII, ConstVec, BW,
473 SpvType->getOperand(2).getImm(),
474 ZeroAsNull);
475}
476
479 SPIRVType *SpvType,
480 const SPIRVInstrInfo &TII) {
481 const Type *LLVMTy = getTypeForSPIRVType(SpvType);
482 assert(LLVMTy->isArrayTy());
483 const ArrayType *LLVMArrTy = cast<ArrayType>(LLVMTy);
484 Type *LLVMBaseTy = LLVMArrTy->getElementType();
485 auto *ConstInt = ConstantInt::get(LLVMBaseTy, Val);
486 auto *ConstArr =
487 ConstantArray::get(const_cast<ArrayType *>(LLVMArrTy), {ConstInt});
488 SPIRVType *SpvBaseTy = getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
489 unsigned BW = getScalarOrVectorBitWidth(SpvBaseTy);
490 return getOrCreateCompositeOrNull(ConstInt, I, SpvType, TII, ConstArr, BW,
491 LLVMArrTy->getNumElements());
492}
493
494Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull(
495 uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType, bool EmitIR,
496 Constant *CA, unsigned BitWidth, unsigned ElemCnt) {
497 Register Res = DT.find(CA, CurMF);
498 if (!Res.isValid()) {
499 Register SpvScalConst;
500 if (Val || EmitIR) {
501 SPIRVType *SpvBaseType =
503 SpvScalConst = buildConstantInt(Val, MIRBuilder, SpvBaseType, EmitIR);
504 }
505 LLT LLTy = EmitIR ? LLT::fixed_vector(ElemCnt, BitWidth) : LLT::scalar(32);
506 Register SpvVecConst =
508 CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass);
509 assignSPIRVTypeToVReg(SpvType, SpvVecConst, *CurMF);
510 DT.add(CA, CurMF, SpvVecConst);
511 if (EmitIR) {
512 MIRBuilder.buildSplatVector(SpvVecConst, SpvScalConst);
513 } else {
514 if (Val) {
515 auto MIB = MIRBuilder.buildInstr(SPIRV::OpConstantComposite)
516 .addDef(SpvVecConst)
517 .addUse(getSPIRVTypeID(SpvType));
518 for (unsigned i = 0; i < ElemCnt; ++i)
519 MIB.addUse(SpvScalConst);
520 } else {
521 MIRBuilder.buildInstr(SPIRV::OpConstantNull)
522 .addDef(SpvVecConst)
523 .addUse(getSPIRVTypeID(SpvType));
524 }
525 }
526 return SpvVecConst;
527 }
528 return Res;
529}
530
533 MachineIRBuilder &MIRBuilder,
534 SPIRVType *SpvType, bool EmitIR) {
535 const Type *LLVMTy = getTypeForSPIRVType(SpvType);
536 assert(LLVMTy->isVectorTy());
537 const FixedVectorType *LLVMVecTy = cast<FixedVectorType>(LLVMTy);
538 Type *LLVMBaseTy = LLVMVecTy->getElementType();
539 const auto ConstInt = ConstantInt::get(LLVMBaseTy, Val);
540 auto ConstVec =
541 ConstantVector::getSplat(LLVMVecTy->getElementCount(), ConstInt);
542 unsigned BW = getScalarOrVectorBitWidth(SpvType);
543 return getOrCreateIntCompositeOrNull(Val, MIRBuilder, SpvType, EmitIR,
544 ConstVec, BW,
545 SpvType->getOperand(2).getImm());
546}
547
550 MachineIRBuilder &MIRBuilder,
551 SPIRVType *SpvType, bool EmitIR) {
552 const Type *LLVMTy = getTypeForSPIRVType(SpvType);
553 assert(LLVMTy->isArrayTy());
554 const ArrayType *LLVMArrTy = cast<ArrayType>(LLVMTy);
555 Type *LLVMBaseTy = LLVMArrTy->getElementType();
556 const auto ConstInt = ConstantInt::get(LLVMBaseTy, Val);
557 auto ConstArr =
558 ConstantArray::get(const_cast<ArrayType *>(LLVMArrTy), {ConstInt});
559 SPIRVType *SpvBaseTy = getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
560 unsigned BW = getScalarOrVectorBitWidth(SpvBaseTy);
561 return getOrCreateIntCompositeOrNull(Val, MIRBuilder, SpvType, EmitIR,
562 ConstArr, BW,
563 LLVMArrTy->getNumElements());
564}
565
568 SPIRVType *SpvType) {
569 const Type *LLVMTy = getTypeForSPIRVType(SpvType);
570 const TypedPointerType *LLVMPtrTy = cast<TypedPointerType>(LLVMTy);
571 // Find a constant in DT or build a new one.
573 LLVMPtrTy->getElementType(), LLVMPtrTy->getAddressSpace()));
574 Register Res = DT.find(CP, CurMF);
575 if (!Res.isValid()) {
576 LLT LLTy = LLT::pointer(LLVMPtrTy->getAddressSpace(), PointerSize);
578 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
579 assignSPIRVTypeToVReg(SpvType, Res, *CurMF);
580 MIRBuilder.buildInstr(SPIRV::OpConstantNull)
581 .addDef(Res)
582 .addUse(getSPIRVTypeID(SpvType));
583 DT.add(CP, CurMF, Res);
584 }
585 return Res;
586}
587
589 Register ResReg, unsigned AddrMode, unsigned Param, unsigned FilerMode,
590 MachineIRBuilder &MIRBuilder, SPIRVType *SpvType) {
591 SPIRVType *SampTy;
592 if (SpvType)
593 SampTy = getOrCreateSPIRVType(getTypeForSPIRVType(SpvType), MIRBuilder);
594 else if ((SampTy = getOrCreateSPIRVTypeByName("opencl.sampler_t",
595 MIRBuilder)) == nullptr)
596 report_fatal_error("Unable to recognize SPIRV type name: opencl.sampler_t");
597
598 auto Sampler =
599 ResReg.isValid()
600 ? ResReg
601 : MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
602 auto Res = MIRBuilder.buildInstr(SPIRV::OpConstantSampler)
603 .addDef(Sampler)
604 .addUse(getSPIRVTypeID(SampTy))
606 .addImm(Param)
607 .addImm(FilerMode);
608 assert(Res->getOperand(0).isReg());
609 return Res->getOperand(0).getReg();
610}
611
614 const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage,
615 const MachineInstr *Init, bool IsConst, bool HasLinkageTy,
616 SPIRV::LinkageType::LinkageType LinkageType, MachineIRBuilder &MIRBuilder,
617 bool IsInstSelector) {
618 const GlobalVariable *GVar = nullptr;
619 if (GV)
620 GVar = cast<const GlobalVariable>(GV);
621 else {
622 // If GV is not passed explicitly, use the name to find or construct
623 // the global variable.
624 Module *M = MIRBuilder.getMF().getFunction().getParent();
625 GVar = M->getGlobalVariable(Name);
626 if (GVar == nullptr) {
627 const Type *Ty = getTypeForSPIRVType(BaseType); // TODO: check type.
628 // Module takes ownership of the global var.
629 GVar = new GlobalVariable(*M, const_cast<Type *>(Ty), false,
631 Twine(Name));
632 }
633 GV = GVar;
634 }
635 Register Reg = DT.find(GVar, &MIRBuilder.getMF());
636 if (Reg.isValid()) {
637 if (Reg != ResVReg)
638 MIRBuilder.buildCopy(ResVReg, Reg);
639 return ResVReg;
640 }
641
642 auto MIB = MIRBuilder.buildInstr(SPIRV::OpVariable)
643 .addDef(ResVReg)
645 .addImm(static_cast<uint32_t>(Storage));
646
647 if (Init != 0) {
648 MIB.addUse(Init->getOperand(0).getReg());
649 }
650
651 // ISel may introduce a new register on this step, so we need to add it to
652 // DT and correct its type avoiding fails on the next stage.
653 if (IsInstSelector) {
654 const auto &Subtarget = CurMF->getSubtarget();
655 constrainSelectedInstRegOperands(*MIB, *Subtarget.getInstrInfo(),
656 *Subtarget.getRegisterInfo(),
657 *Subtarget.getRegBankInfo());
658 }
659 Reg = MIB->getOperand(0).getReg();
660 DT.add(GVar, &MIRBuilder.getMF(), Reg);
661
662 // Set to Reg the same type as ResVReg has.
663 auto MRI = MIRBuilder.getMRI();
664 assert(MRI->getType(ResVReg).isPointer() && "Pointer type is expected");
665 if (Reg != ResVReg) {
666 LLT RegLLTy =
667 LLT::pointer(MRI->getType(ResVReg).getAddressSpace(), getPointerSize());
668 MRI->setType(Reg, RegLLTy);
669 assignSPIRVTypeToVReg(BaseType, Reg, MIRBuilder.getMF());
670 } else {
671 // Our knowledge about the type may be updated.
672 // If that's the case, we need to update a type
673 // associated with the register.
674 SPIRVType *DefType = getSPIRVTypeForVReg(ResVReg);
675 if (!DefType || DefType != BaseType)
676 assignSPIRVTypeToVReg(BaseType, Reg, MIRBuilder.getMF());
677 }
678
679 // If it's a global variable with name, output OpName for it.
680 if (GVar && GVar->hasName())
681 buildOpName(Reg, GVar->getName(), MIRBuilder);
682
683 // Output decorations for the GV.
684 // TODO: maybe move to GenerateDecorations pass.
685 const SPIRVSubtarget &ST =
686 cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
687 if (IsConst && ST.isOpenCLEnv())
688 buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::Constant, {});
689
690 if (GVar && GVar->getAlign().valueOrOne().value() != 1) {
691 unsigned Alignment = (unsigned)GVar->getAlign().valueOrOne().value();
692 buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::Alignment, {Alignment});
693 }
694
695 if (HasLinkageTy)
696 buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::LinkageAttributes,
697 {static_cast<uint32_t>(LinkageType)}, Name);
698
699 SPIRV::BuiltIn::BuiltIn BuiltInId;
700 if (getSpirvBuiltInIdByName(Name, BuiltInId))
701 buildOpDecorate(Reg, MIRBuilder, SPIRV::Decoration::BuiltIn,
702 {static_cast<uint32_t>(BuiltInId)});
703
704 // If it's a global variable with "spirv.Decorations" metadata node
705 // recognize it as a SPIR-V friendly LLVM IR and parse "spirv.Decorations"
706 // arguments.
707 MDNode *GVarMD = nullptr;
708 if (GVar && (GVarMD = GVar->getMetadata("spirv.Decorations")) != nullptr)
709 buildOpSpirvDecorations(Reg, MIRBuilder, GVarMD);
710
711 return Reg;
712}
713
714SPIRVType *SPIRVGlobalRegistry::getOpTypeArray(uint32_t NumElems,
715 SPIRVType *ElemType,
716 MachineIRBuilder &MIRBuilder,
717 bool EmitIR) {
718 assert((ElemType->getOpcode() != SPIRV::OpTypeVoid) &&
719 "Invalid array element type");
720 Register NumElementsVReg =
721 buildConstantInt(NumElems, MIRBuilder, nullptr, EmitIR);
722 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeArray)
723 .addDef(createTypeVReg(MIRBuilder))
724 .addUse(getSPIRVTypeID(ElemType))
725 .addUse(NumElementsVReg);
726 return MIB;
727}
728
729SPIRVType *SPIRVGlobalRegistry::getOpTypeOpaque(const StructType *Ty,
730 MachineIRBuilder &MIRBuilder) {
731 assert(Ty->hasName());
732 const StringRef Name = Ty->hasName() ? Ty->getName() : "";
733 Register ResVReg = createTypeVReg(MIRBuilder);
734 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeOpaque).addDef(ResVReg);
735 addStringImm(Name, MIB);
736 buildOpName(ResVReg, Name, MIRBuilder);
737 return MIB;
738}
739
740SPIRVType *SPIRVGlobalRegistry::getOpTypeStruct(const StructType *Ty,
741 MachineIRBuilder &MIRBuilder,
742 bool EmitIR) {
743 SmallVector<Register, 4> FieldTypes;
744 for (const auto &Elem : Ty->elements()) {
745 SPIRVType *ElemTy = findSPIRVType(toTypedPointer(Elem), MIRBuilder);
746 assert(ElemTy && ElemTy->getOpcode() != SPIRV::OpTypeVoid &&
747 "Invalid struct element type");
748 FieldTypes.push_back(getSPIRVTypeID(ElemTy));
749 }
750 Register ResVReg = createTypeVReg(MIRBuilder);
751 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeStruct).addDef(ResVReg);
752 for (const auto &Ty : FieldTypes)
753 MIB.addUse(Ty);
754 if (Ty->hasName())
755 buildOpName(ResVReg, Ty->getName(), MIRBuilder);
756 if (Ty->isPacked())
757 buildOpDecorate(ResVReg, MIRBuilder, SPIRV::Decoration::CPacked, {});
758 return MIB;
759}
760
761SPIRVType *SPIRVGlobalRegistry::getOrCreateSpecialType(
762 const Type *Ty, MachineIRBuilder &MIRBuilder,
763 SPIRV::AccessQualifier::AccessQualifier AccQual) {
764 assert(isSpecialOpaqueType(Ty) && "Not a special opaque builtin type");
765 return SPIRV::lowerBuiltinType(Ty, AccQual, MIRBuilder, this);
766}
767
768SPIRVType *SPIRVGlobalRegistry::getOpTypePointer(
769 SPIRV::StorageClass::StorageClass SC, SPIRVType *ElemType,
770 MachineIRBuilder &MIRBuilder, Register Reg) {
771 if (!Reg.isValid())
772 Reg = createTypeVReg(MIRBuilder);
773 return MIRBuilder.buildInstr(SPIRV::OpTypePointer)
774 .addDef(Reg)
775 .addImm(static_cast<uint32_t>(SC))
776 .addUse(getSPIRVTypeID(ElemType));
777}
778
779SPIRVType *SPIRVGlobalRegistry::getOpTypeForwardPointer(
780 SPIRV::StorageClass::StorageClass SC, MachineIRBuilder &MIRBuilder) {
781 return MIRBuilder.buildInstr(SPIRV::OpTypeForwardPointer)
782 .addUse(createTypeVReg(MIRBuilder))
783 .addImm(static_cast<uint32_t>(SC));
784}
785
786SPIRVType *SPIRVGlobalRegistry::getOpTypeFunction(
787 SPIRVType *RetType, const SmallVectorImpl<SPIRVType *> &ArgTypes,
788 MachineIRBuilder &MIRBuilder) {
789 auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeFunction)
790 .addDef(createTypeVReg(MIRBuilder))
791 .addUse(getSPIRVTypeID(RetType));
792 for (const SPIRVType *ArgType : ArgTypes)
793 MIB.addUse(getSPIRVTypeID(ArgType));
794 return MIB;
795}
796
798 const Type *Ty, SPIRVType *RetType,
799 const SmallVectorImpl<SPIRVType *> &ArgTypes,
800 MachineIRBuilder &MIRBuilder) {
801 Register Reg = DT.find(Ty, &MIRBuilder.getMF());
802 if (Reg.isValid())
803 return getSPIRVTypeForVReg(Reg);
804 SPIRVType *SpirvType = getOpTypeFunction(RetType, ArgTypes, MIRBuilder);
805 DT.add(Ty, CurMF, getSPIRVTypeID(SpirvType));
806 return finishCreatingSPIRVType(Ty, SpirvType);
807}
808
809SPIRVType *SPIRVGlobalRegistry::findSPIRVType(
810 const Type *Ty, MachineIRBuilder &MIRBuilder,
811 SPIRV::AccessQualifier::AccessQualifier AccQual, bool EmitIR) {
812 Ty = adjustIntTypeByWidth(Ty);
813 Register Reg = DT.find(Ty, &MIRBuilder.getMF());
814 if (Reg.isValid())
815 return getSPIRVTypeForVReg(Reg);
816 if (ForwardPointerTypes.contains(Ty))
817 return ForwardPointerTypes[Ty];
818 return restOfCreateSPIRVType(Ty, MIRBuilder, AccQual, EmitIR);
819}
820
822 assert(SpirvType && "Attempting to get type id for nullptr type.");
823 if (SpirvType->getOpcode() == SPIRV::OpTypeForwardPointer)
824 return SpirvType->uses().begin()->getReg();
825 return SpirvType->defs().begin()->getReg();
826}
827
828// We need to use a new LLVM integer type if there is a mismatch between
829// number of bits in LLVM and SPIRV integer types to let DuplicateTracker
830// ensure uniqueness of a SPIRV type by the corresponding LLVM type. Without
831// such an adjustment SPIRVGlobalRegistry::getOpTypeInt() could create the
832// same "OpTypeInt 8" type for a series of LLVM integer types with number of
833// bits less than 8. This would lead to duplicate type definitions
834// eventually due to the method that DuplicateTracker utilizes to reason
835// about uniqueness of type records.
836const Type *SPIRVGlobalRegistry::adjustIntTypeByWidth(const Type *Ty) const {
837 if (auto IType = dyn_cast<IntegerType>(Ty)) {
838 unsigned SrcBitWidth = IType->getBitWidth();
839 if (SrcBitWidth > 1) {
840 unsigned BitWidth = adjustOpTypeIntWidth(SrcBitWidth);
841 // Maybe change source LLVM type to keep DuplicateTracker consistent.
842 if (SrcBitWidth != BitWidth)
844 }
845 }
846 return Ty;
847}
848
849SPIRVType *SPIRVGlobalRegistry::createSPIRVType(
850 const Type *Ty, MachineIRBuilder &MIRBuilder,
851 SPIRV::AccessQualifier::AccessQualifier AccQual, bool EmitIR) {
852 if (isSpecialOpaqueType(Ty))
853 return getOrCreateSpecialType(Ty, MIRBuilder, AccQual);
854 auto &TypeToSPIRVTypeMap = DT.getTypes()->getAllUses();
855 auto t = TypeToSPIRVTypeMap.find(Ty);
856 if (t != TypeToSPIRVTypeMap.end()) {
857 auto tt = t->second.find(&MIRBuilder.getMF());
858 if (tt != t->second.end())
859 return getSPIRVTypeForVReg(tt->second);
860 }
861
862 if (auto IType = dyn_cast<IntegerType>(Ty)) {
863 const unsigned Width = IType->getBitWidth();
864 return Width == 1 ? getOpTypeBool(MIRBuilder)
865 : getOpTypeInt(Width, MIRBuilder, false);
866 }
867 if (Ty->isFloatingPointTy())
868 return getOpTypeFloat(Ty->getPrimitiveSizeInBits(), MIRBuilder);
869 if (Ty->isVoidTy())
870 return getOpTypeVoid(MIRBuilder);
871 if (Ty->isVectorTy()) {
872 SPIRVType *El =
873 findSPIRVType(cast<FixedVectorType>(Ty)->getElementType(), MIRBuilder);
874 return getOpTypeVector(cast<FixedVectorType>(Ty)->getNumElements(), El,
875 MIRBuilder);
876 }
877 if (Ty->isArrayTy()) {
878 SPIRVType *El = findSPIRVType(Ty->getArrayElementType(), MIRBuilder);
879 return getOpTypeArray(Ty->getArrayNumElements(), El, MIRBuilder, EmitIR);
880 }
881 if (auto SType = dyn_cast<StructType>(Ty)) {
882 if (SType->isOpaque())
883 return getOpTypeOpaque(SType, MIRBuilder);
884 return getOpTypeStruct(SType, MIRBuilder, EmitIR);
885 }
886 if (auto FType = dyn_cast<FunctionType>(Ty)) {
887 SPIRVType *RetTy = findSPIRVType(FType->getReturnType(), MIRBuilder);
889 for (const auto &t : FType->params()) {
890 ParamTypes.push_back(findSPIRVType(t, MIRBuilder));
891 }
892 return getOpTypeFunction(RetTy, ParamTypes, MIRBuilder);
893 }
894 unsigned AddrSpace = 0xFFFF;
895 if (auto PType = dyn_cast<TypedPointerType>(Ty))
896 AddrSpace = PType->getAddressSpace();
897 else if (auto PType = dyn_cast<PointerType>(Ty))
898 AddrSpace = PType->getAddressSpace();
899 else
900 report_fatal_error("Unable to convert LLVM type to SPIRVType", true);
901
902 SPIRVType *SpvElementType = nullptr;
903 if (auto PType = dyn_cast<TypedPointerType>(Ty))
904 SpvElementType = getOrCreateSPIRVType(PType->getElementType(), MIRBuilder,
905 AccQual, EmitIR);
906 else
907 SpvElementType = getOrCreateSPIRVIntegerType(8, MIRBuilder);
908
909 // Get access to information about available extensions
910 const SPIRVSubtarget *ST =
911 static_cast<const SPIRVSubtarget *>(&MIRBuilder.getMF().getSubtarget());
912 auto SC = addressSpaceToStorageClass(AddrSpace, *ST);
913 // Null pointer means we have a loop in type definitions, make and
914 // return corresponding OpTypeForwardPointer.
915 if (SpvElementType == nullptr) {
916 if (!ForwardPointerTypes.contains(Ty))
917 ForwardPointerTypes[Ty] = getOpTypeForwardPointer(SC, MIRBuilder);
918 return ForwardPointerTypes[Ty];
919 }
920 // If we have forward pointer associated with this type, use its register
921 // operand to create OpTypePointer.
922 if (ForwardPointerTypes.contains(Ty)) {
923 Register Reg = getSPIRVTypeID(ForwardPointerTypes[Ty]);
924 return getOpTypePointer(SC, SpvElementType, MIRBuilder, Reg);
925 }
926
927 return getOrCreateSPIRVPointerType(SpvElementType, MIRBuilder, SC);
928}
929
930SPIRVType *SPIRVGlobalRegistry::restOfCreateSPIRVType(
931 const Type *Ty, MachineIRBuilder &MIRBuilder,
932 SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) {
933 if (TypesInProcessing.count(Ty) && !isPointerTy(Ty))
934 return nullptr;
935 TypesInProcessing.insert(Ty);
936 SPIRVType *SpirvType = createSPIRVType(Ty, MIRBuilder, AccessQual, EmitIR);
937 TypesInProcessing.erase(Ty);
938 VRegToTypeMap[&MIRBuilder.getMF()][getSPIRVTypeID(SpirvType)] = SpirvType;
939 SPIRVToLLVMType[SpirvType] = Ty;
940 Register Reg = DT.find(Ty, &MIRBuilder.getMF());
941 // Do not add OpTypeForwardPointer to DT, a corresponding normal pointer type
942 // will be added later. For special types it is already added to DT.
943 if (SpirvType->getOpcode() != SPIRV::OpTypeForwardPointer && !Reg.isValid() &&
944 !isSpecialOpaqueType(Ty)) {
945 if (!isPointerTy(Ty))
946 DT.add(Ty, &MIRBuilder.getMF(), getSPIRVTypeID(SpirvType));
947 else if (isTypedPointerTy(Ty))
948 DT.add(cast<TypedPointerType>(Ty)->getElementType(),
949 getPointerAddressSpace(Ty), &MIRBuilder.getMF(),
950 getSPIRVTypeID(SpirvType));
951 else
952 DT.add(Type::getInt8Ty(MIRBuilder.getMF().getFunction().getContext()),
953 getPointerAddressSpace(Ty), &MIRBuilder.getMF(),
954 getSPIRVTypeID(SpirvType));
955 }
956
957 return SpirvType;
958}
959
960SPIRVType *
962 const MachineFunction *MF) const {
963 auto t = VRegToTypeMap.find(MF ? MF : CurMF);
964 if (t != VRegToTypeMap.end()) {
965 auto tt = t->second.find(VReg);
966 if (tt != t->second.end())
967 return tt->second;
968 }
969 return nullptr;
970}
971
973 const Type *Ty, MachineIRBuilder &MIRBuilder,
974 SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) {
975 Register Reg;
976 if (!isPointerTy(Ty)) {
977 Ty = adjustIntTypeByWidth(Ty);
978 Reg = DT.find(Ty, &MIRBuilder.getMF());
979 } else if (isTypedPointerTy(Ty)) {
980 Reg = DT.find(cast<TypedPointerType>(Ty)->getElementType(),
981 getPointerAddressSpace(Ty), &MIRBuilder.getMF());
982 } else {
983 Reg =
984 DT.find(Type::getInt8Ty(MIRBuilder.getMF().getFunction().getContext()),
985 getPointerAddressSpace(Ty), &MIRBuilder.getMF());
986 }
987
988 if (Reg.isValid() && !isSpecialOpaqueType(Ty))
989 return getSPIRVTypeForVReg(Reg);
990 TypesInProcessing.clear();
991 SPIRVType *STy = restOfCreateSPIRVType(Ty, MIRBuilder, AccessQual, EmitIR);
992 // Create normal pointer types for the corresponding OpTypeForwardPointers.
993 for (auto &CU : ForwardPointerTypes) {
994 const Type *Ty2 = CU.first;
995 SPIRVType *STy2 = CU.second;
996 if ((Reg = DT.find(Ty2, &MIRBuilder.getMF())).isValid())
997 STy2 = getSPIRVTypeForVReg(Reg);
998 else
999 STy2 = restOfCreateSPIRVType(Ty2, MIRBuilder, AccessQual, EmitIR);
1000 if (Ty == Ty2)
1001 STy = STy2;
1002 }
1003 ForwardPointerTypes.clear();
1004 return STy;
1005}
1006
1008 unsigned TypeOpcode) const {
1010 assert(Type && "isScalarOfType VReg has no type assigned");
1011 return Type->getOpcode() == TypeOpcode;
1012}
1013
1015 unsigned TypeOpcode) const {
1017 assert(Type && "isScalarOrVectorOfType VReg has no type assigned");
1018 if (Type->getOpcode() == TypeOpcode)
1019 return true;
1020 if (Type->getOpcode() == SPIRV::OpTypeVector) {
1021 Register ScalarTypeVReg = Type->getOperand(1).getReg();
1022 SPIRVType *ScalarType = getSPIRVTypeForVReg(ScalarTypeVReg);
1023 return ScalarType->getOpcode() == TypeOpcode;
1024 }
1025 return false;
1026}
1027
1028unsigned
1031}
1032
1033unsigned
1035 if (!Type)
1036 return 0;
1037 return Type->getOpcode() == SPIRV::OpTypeVector
1038 ? static_cast<unsigned>(Type->getOperand(2).getImm())
1039 : 1;
1040}
1041
1042unsigned
1044 assert(Type && "Invalid Type pointer");
1045 if (Type->getOpcode() == SPIRV::OpTypeVector) {
1046 auto EleTypeReg = Type->getOperand(1).getReg();
1047 Type = getSPIRVTypeForVReg(EleTypeReg);
1048 }
1049 if (Type->getOpcode() == SPIRV::OpTypeInt ||
1050 Type->getOpcode() == SPIRV::OpTypeFloat)
1051 return Type->getOperand(1).getImm();
1052 if (Type->getOpcode() == SPIRV::OpTypeBool)
1053 return 1;
1054 llvm_unreachable("Attempting to get bit width of non-integer/float type.");
1055}
1056
1058 const SPIRVType *Type) const {
1059 assert(Type && "Invalid Type pointer");
1060 unsigned NumElements = 1;
1061 if (Type->getOpcode() == SPIRV::OpTypeVector) {
1062 NumElements = static_cast<unsigned>(Type->getOperand(2).getImm());
1063 Type = getSPIRVTypeForVReg(Type->getOperand(1).getReg());
1064 }
1065 return Type->getOpcode() == SPIRV::OpTypeInt ||
1066 Type->getOpcode() == SPIRV::OpTypeFloat
1067 ? NumElements * Type->getOperand(1).getImm()
1068 : 0;
1069}
1070
1072 const SPIRVType *Type) const {
1073 if (Type && Type->getOpcode() == SPIRV::OpTypeVector)
1074 Type = getSPIRVTypeForVReg(Type->getOperand(1).getReg());
1075 return Type && Type->getOpcode() == SPIRV::OpTypeInt ? Type : nullptr;
1076}
1077
1080 return IntType && IntType->getOperand(2).getImm() != 0;
1081}
1082
1084 SPIRVType *PtrType = getSPIRVTypeForVReg(PtrReg);
1085 SPIRVType *ElemType =
1086 PtrType && PtrType->getOpcode() == SPIRV::OpTypePointer
1087 ? getSPIRVTypeForVReg(PtrType->getOperand(2).getReg())
1088 : nullptr;
1089 return ElemType ? ElemType->getOpcode() : 0;
1090}
1091
1093 const SPIRVType *Type2) const {
1094 if (!Type1 || !Type2)
1095 return false;
1096 auto Op1 = Type1->getOpcode(), Op2 = Type2->getOpcode();
1097 // Ignore difference between <1.5 and >=1.5 protocol versions:
1098 // it's valid if either Result Type or Operand is a pointer, and the other
1099 // is a pointer, an integer scalar, or an integer vector.
1100 if (Op1 == SPIRV::OpTypePointer &&
1101 (Op2 == SPIRV::OpTypePointer || retrieveScalarOrVectorIntType(Type2)))
1102 return true;
1103 if (Op2 == SPIRV::OpTypePointer &&
1104 (Op1 == SPIRV::OpTypePointer || retrieveScalarOrVectorIntType(Type1)))
1105 return true;
1106 unsigned Bits1 = getNumScalarOrVectorTotalBitWidth(Type1),
1108 return Bits1 > 0 && Bits1 == Bits2;
1109}
1110
1111SPIRV::StorageClass::StorageClass
1114 assert(Type && Type->getOpcode() == SPIRV::OpTypePointer &&
1115 Type->getOperand(1).isImm() && "Pointer type is expected");
1116 return static_cast<SPIRV::StorageClass::StorageClass>(
1117 Type->getOperand(1).getImm());
1118}
1119
1121 MachineIRBuilder &MIRBuilder, SPIRVType *SampledType, SPIRV::Dim::Dim Dim,
1122 uint32_t Depth, uint32_t Arrayed, uint32_t Multisampled, uint32_t Sampled,
1123 SPIRV::ImageFormat::ImageFormat ImageFormat,
1124 SPIRV::AccessQualifier::AccessQualifier AccessQual) {
1125 SPIRV::ImageTypeDescriptor TD(SPIRVToLLVMType.lookup(SampledType), Dim, Depth,
1126 Arrayed, Multisampled, Sampled, ImageFormat,
1127 AccessQual);
1128 if (auto *Res = checkSpecialInstr(TD, MIRBuilder))
1129 return Res;
1130 Register ResVReg = createTypeVReg(MIRBuilder);
1131 DT.add(TD, &MIRBuilder.getMF(), ResVReg);
1132 return MIRBuilder.buildInstr(SPIRV::OpTypeImage)
1133 .addDef(ResVReg)
1134 .addUse(getSPIRVTypeID(SampledType))
1135 .addImm(Dim)
1136 .addImm(Depth) // Depth (whether or not it is a Depth image).
1137 .addImm(Arrayed) // Arrayed.
1138 .addImm(Multisampled) // Multisampled (0 = only single-sample).
1139 .addImm(Sampled) // Sampled (0 = usage known at runtime).
1140 .addImm(ImageFormat)
1141 .addImm(AccessQual);
1142}
1143
1144SPIRVType *
1147 if (auto *Res = checkSpecialInstr(TD, MIRBuilder))
1148 return Res;
1149 Register ResVReg = createTypeVReg(MIRBuilder);
1150 DT.add(TD, &MIRBuilder.getMF(), ResVReg);
1151 return MIRBuilder.buildInstr(SPIRV::OpTypeSampler).addDef(ResVReg);
1152}
1153
1155 MachineIRBuilder &MIRBuilder,
1156 SPIRV::AccessQualifier::AccessQualifier AccessQual) {
1157 SPIRV::PipeTypeDescriptor TD(AccessQual);
1158 if (auto *Res = checkSpecialInstr(TD, MIRBuilder))
1159 return Res;
1160 Register ResVReg = createTypeVReg(MIRBuilder);
1161 DT.add(TD, &MIRBuilder.getMF(), ResVReg);
1162 return MIRBuilder.buildInstr(SPIRV::OpTypePipe)
1163 .addDef(ResVReg)
1164 .addImm(AccessQual);
1165}
1166
1168 MachineIRBuilder &MIRBuilder) {
1170 if (auto *Res = checkSpecialInstr(TD, MIRBuilder))
1171 return Res;
1172 Register ResVReg = createTypeVReg(MIRBuilder);
1173 DT.add(TD, &MIRBuilder.getMF(), ResVReg);
1174 return MIRBuilder.buildInstr(SPIRV::OpTypeDeviceEvent).addDef(ResVReg);
1175}
1176
1178 SPIRVType *ImageType, MachineIRBuilder &MIRBuilder) {
1180 SPIRVToLLVMType.lookup(MIRBuilder.getMF().getRegInfo().getVRegDef(
1181 ImageType->getOperand(1).getReg())),
1182 ImageType);
1183 if (auto *Res = checkSpecialInstr(TD, MIRBuilder))
1184 return Res;
1185 Register ResVReg = createTypeVReg(MIRBuilder);
1186 DT.add(TD, &MIRBuilder.getMF(), ResVReg);
1187 return MIRBuilder.buildInstr(SPIRV::OpTypeSampledImage)
1188 .addDef(ResVReg)
1189 .addUse(getSPIRVTypeID(ImageType));
1190}
1191
1193 const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode) {
1194 Register ResVReg = DT.find(Ty, &MIRBuilder.getMF());
1195 if (ResVReg.isValid())
1196 return MIRBuilder.getMF().getRegInfo().getUniqueVRegDef(ResVReg);
1197 ResVReg = createTypeVReg(MIRBuilder);
1198 SPIRVType *SpirvTy = MIRBuilder.buildInstr(Opcode).addDef(ResVReg);
1199 DT.add(Ty, &MIRBuilder.getMF(), ResVReg);
1200 return SpirvTy;
1201}
1202
1203const MachineInstr *
1204SPIRVGlobalRegistry::checkSpecialInstr(const SPIRV::SpecialTypeDescriptor &TD,
1205 MachineIRBuilder &MIRBuilder) {
1206 Register Reg = DT.find(TD, &MIRBuilder.getMF());
1207 if (Reg.isValid())
1208 return MIRBuilder.getMF().getRegInfo().getUniqueVRegDef(Reg);
1209 return nullptr;
1210}
1211
1212// Returns nullptr if unable to recognize SPIRV type name
1214 StringRef TypeStr, MachineIRBuilder &MIRBuilder,
1215 SPIRV::StorageClass::StorageClass SC,
1216 SPIRV::AccessQualifier::AccessQualifier AQ) {
1217 unsigned VecElts = 0;
1218 auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
1219
1220 // Parse strings representing either a SPIR-V or OpenCL builtin type.
1221 if (hasBuiltinTypePrefix(TypeStr))
1223 TypeStr.str(), MIRBuilder.getContext()),
1224 MIRBuilder, AQ);
1225
1226 // Parse type name in either "typeN" or "type vector[N]" format, where
1227 // N is the number of elements of the vector.
1228 Type *Ty;
1229
1230 Ty = parseBasicTypeName(TypeStr, Ctx);
1231 if (!Ty)
1232 // Unable to recognize SPIRV type name
1233 return nullptr;
1234
1235 auto SpirvTy = getOrCreateSPIRVType(Ty, MIRBuilder, AQ);
1236
1237 // Handle "type*" or "type* vector[N]".
1238 if (TypeStr.starts_with("*")) {
1239 SpirvTy = getOrCreateSPIRVPointerType(SpirvTy, MIRBuilder, SC);
1240 TypeStr = TypeStr.substr(strlen("*"));
1241 }
1242
1243 // Handle "typeN*" or "type vector[N]*".
1244 bool IsPtrToVec = TypeStr.consume_back("*");
1245
1246 if (TypeStr.consume_front(" vector[")) {
1247 TypeStr = TypeStr.substr(0, TypeStr.find(']'));
1248 }
1249 TypeStr.getAsInteger(10, VecElts);
1250 if (VecElts > 0)
1251 SpirvTy = getOrCreateSPIRVVectorType(SpirvTy, VecElts, MIRBuilder);
1252
1253 if (IsPtrToVec)
1254 SpirvTy = getOrCreateSPIRVPointerType(SpirvTy, MIRBuilder, SC);
1255
1256 return SpirvTy;
1257}
1258
1259SPIRVType *
1261 MachineIRBuilder &MIRBuilder) {
1262 return getOrCreateSPIRVType(
1264 MIRBuilder);
1265}
1266
1267SPIRVType *SPIRVGlobalRegistry::finishCreatingSPIRVType(const Type *LLVMTy,
1268 SPIRVType *SpirvType) {
1269 assert(CurMF == SpirvType->getMF());
1270 VRegToTypeMap[CurMF][getSPIRVTypeID(SpirvType)] = SpirvType;
1271 SPIRVToLLVMType[SpirvType] = LLVMTy;
1272 return SpirvType;
1273}
1274
1276 MachineInstr &I,
1277 const SPIRVInstrInfo &TII,
1278 unsigned SPIRVOPcode,
1279 Type *LLVMTy) {
1280 Register Reg = DT.find(LLVMTy, CurMF);
1281 if (Reg.isValid())
1282 return getSPIRVTypeForVReg(Reg);
1283 MachineBasicBlock &BB = *I.getParent();
1284 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRVOPcode))
1287 .addImm(0);
1288 DT.add(LLVMTy, CurMF, getSPIRVTypeID(MIB));
1289 return finishCreatingSPIRVType(LLVMTy, MIB);
1290}
1291
1293 unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) {
1294 // Maybe adjust bit width to keep DuplicateTracker consistent. Without
1295 // such an adjustment SPIRVGlobalRegistry::getOpTypeInt() could create, for
1296 // example, the same "OpTypeInt 8" type for a series of LLVM integer types
1297 // with number of bits less than 8, causing duplicate type definitions.
1298 BitWidth = adjustOpTypeIntWidth(BitWidth);
1300 return getOrCreateSPIRVType(BitWidth, I, TII, SPIRV::OpTypeInt, LLVMTy);
1301}
1302
1304 unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) {
1306 Type *LLVMTy;
1307 switch (BitWidth) {
1308 case 16:
1309 LLVMTy = Type::getHalfTy(Ctx);
1310 break;
1311 case 32:
1312 LLVMTy = Type::getFloatTy(Ctx);
1313 break;
1314 case 64:
1315 LLVMTy = Type::getDoubleTy(Ctx);
1316 break;
1317 default:
1318 llvm_unreachable("Bit width is of unexpected size.");
1319 }
1320 return getOrCreateSPIRVType(BitWidth, I, TII, SPIRV::OpTypeFloat, LLVMTy);
1321}
1322
1323SPIRVType *
1325 return getOrCreateSPIRVType(
1326 IntegerType::get(MIRBuilder.getMF().getFunction().getContext(), 1),
1327 MIRBuilder);
1328}
1329
1330SPIRVType *
1332 const SPIRVInstrInfo &TII) {
1334 Register Reg = DT.find(LLVMTy, CurMF);
1335 if (Reg.isValid())
1336 return getSPIRVTypeForVReg(Reg);
1337 MachineBasicBlock &BB = *I.getParent();
1338 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypeBool))
1340 DT.add(LLVMTy, CurMF, getSPIRVTypeID(MIB));
1341 return finishCreatingSPIRVType(LLVMTy, MIB);
1342}
1343
1345 SPIRVType *BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder) {
1346 return getOrCreateSPIRVType(
1348 NumElements),
1349 MIRBuilder);
1350}
1351
1353 SPIRVType *BaseType, unsigned NumElements, MachineInstr &I,
1354 const SPIRVInstrInfo &TII) {
1355 Type *LLVMTy = FixedVectorType::get(
1356 const_cast<Type *>(getTypeForSPIRVType(BaseType)), NumElements);
1357 Register Reg = DT.find(LLVMTy, CurMF);
1358 if (Reg.isValid())
1359 return getSPIRVTypeForVReg(Reg);
1360 MachineBasicBlock &BB = *I.getParent();
1361 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypeVector))
1364 .addImm(NumElements);
1365 DT.add(LLVMTy, CurMF, getSPIRVTypeID(MIB));
1366 return finishCreatingSPIRVType(LLVMTy, MIB);
1367}
1368
1370 SPIRVType *BaseType, unsigned NumElements, MachineInstr &I,
1371 const SPIRVInstrInfo &TII) {
1372 Type *LLVMTy = ArrayType::get(
1373 const_cast<Type *>(getTypeForSPIRVType(BaseType)), NumElements);
1374 Register Reg = DT.find(LLVMTy, CurMF);
1375 if (Reg.isValid())
1376 return getSPIRVTypeForVReg(Reg);
1377 MachineBasicBlock &BB = *I.getParent();
1378 SPIRVType *SpirvType = getOrCreateSPIRVIntegerType(32, I, TII);
1379 Register Len = getOrCreateConstInt(NumElements, I, SpirvType, TII);
1380 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypeArray))
1383 .addUse(Len);
1384 DT.add(LLVMTy, CurMF, getSPIRVTypeID(MIB));
1385 return finishCreatingSPIRVType(LLVMTy, MIB);
1386}
1387
1389 SPIRVType *BaseType, MachineIRBuilder &MIRBuilder,
1390 SPIRV::StorageClass::StorageClass SC) {
1391 const Type *PointerElementType = getTypeForSPIRVType(BaseType);
1393 Type *LLVMTy = TypedPointerType::get(const_cast<Type *>(PointerElementType),
1394 AddressSpace);
1395 // check if this type is already available
1396 Register Reg = DT.find(PointerElementType, AddressSpace, CurMF);
1397 if (Reg.isValid())
1398 return getSPIRVTypeForVReg(Reg);
1399 // create a new type
1400 auto MIB = BuildMI(MIRBuilder.getMBB(), MIRBuilder.getInsertPt(),
1401 MIRBuilder.getDebugLoc(),
1402 MIRBuilder.getTII().get(SPIRV::OpTypePointer))
1404 .addImm(static_cast<uint32_t>(SC))
1406 DT.add(PointerElementType, AddressSpace, CurMF, getSPIRVTypeID(MIB));
1407 return finishCreatingSPIRVType(LLVMTy, MIB);
1408}
1409
1412 SPIRV::StorageClass::StorageClass SC) {
1413 MachineIRBuilder MIRBuilder(I);
1414 return getOrCreateSPIRVPointerType(BaseType, MIRBuilder, SC);
1415}
1416
1418 SPIRVType *SpvType,
1419 const SPIRVInstrInfo &TII) {
1420 assert(SpvType);
1421 const Type *LLVMTy = getTypeForSPIRVType(SpvType);
1422 assert(LLVMTy);
1423 // Find a constant in DT or build a new one.
1424 UndefValue *UV = UndefValue::get(const_cast<Type *>(LLVMTy));
1425 Register Res = DT.find(UV, CurMF);
1426 if (Res.isValid())
1427 return Res;
1428 LLT LLTy = LLT::scalar(32);
1430 CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
1431 assignSPIRVTypeToVReg(SpvType, Res, *CurMF);
1432 DT.add(UV, CurMF, Res);
1433
1435 MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpUndef))
1436 .addDef(Res)
1437 .addUse(getSPIRVTypeID(SpvType));
1438 const auto &ST = CurMF->getSubtarget();
1439 constrainSelectedInstRegOperands(*MIB, *ST.getInstrInfo(),
1440 *ST.getRegisterInfo(), *ST.getRegBankInfo());
1441 return Res;
1442}
unsigned const MachineRegisterInfo * MRI
This file implements a class to represent arbitrary precision integral constant values and operations...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
return RetTy
std::string Name
ELFYAML::ELF_REL Type2
Definition: ELFYAML.cpp:1812
const HexagonInstrInfo * TII
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static Register createTypeVReg(MachineIRBuilder &MIRBuilder)
APInt bitcastToAPInt() const
Definition: APFloat.h:1221
bool isPosZero() const
Definition: APFloat.h:1326
Class for arbitrary precision integers.
Definition: APInt.h:77
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1499
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1521
Class to represent array types.
Definition: DerivedTypes.h:371
uint64_t getNumElements() const
Definition: DerivedTypes.h:383
static ArrayType * get(Type *ElementType, uint64_t NumElements)
This static method is the primary way to construct an ArrayType.
Definition: Type.cpp:647
Type * getElementType() const
Definition: DerivedTypes.h:384
static Constant * get(ArrayType *T, ArrayRef< Constant * > V)
Definition: Constants.cpp:1292
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:269
const APFloat & getValueAPF() const
Definition: Constants.h:312
This is the shared class of boolean and integer constants.
Definition: Constants.h:81
static ConstantPointerNull * get(PointerType *T)
Static factory methods - Return objects of the specified value.
Definition: Constants.cpp:1762
static Constant * getSplat(ElementCount EC, Constant *Elt)
Return a ConstantVector with the specified constant in each element.
Definition: Constants.cpp:1450
This is an important base class in LLVM.
Definition: Constant.h:41
const APInt & getUniqueInteger() const
If C is a constant integer then return its value, otherwise C must be a vector of constant integers,...
Definition: Constants.cpp:1745
bool isNullValue() const
Return true if this is the value that would be returned by getNullValue.
Definition: Constants.cpp:90
Class to represent fixed width SIMD vectors.
Definition: DerivedTypes.h:539
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:692
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:358
MaybeAlign getAlign() const
Returns the alignment of the given variable or function.
Definition: GlobalObject.h:80
MDNode * getMetadata(unsigned KindID) const
Get the current metadata attachments for the given kind, if any.
Definition: Value.h:565
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:655
@ ExternalLinkage
Externally visible function.
Definition: GlobalValue.h:51
Class to represent integer types.
Definition: DerivedTypes.h:40
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:278
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelType.h:57
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelType.h:100
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Metadata node.
Definition: Metadata.h:1067
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
LLVMContext & getContext() const
const TargetInstrInfo & getTII()
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
const DebugLoc & getDebugLoc()
Get the current instruction's debug location.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Val)
Build and insert Res = G_SPLAT_VECTOR Val.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:564
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:728
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:717
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:574
int64_t getImm() const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isValid() const
Definition: Register.h:116
void add(const Type *Ty, const MachineFunction *MF, Register R)
Register find(const Type *Ty, const MachineFunction *MF)
const SPIRVDuplicatesTracker< Type > * getTypes()
SPIRVType * getOrCreateOpTypePipe(MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccQual)
unsigned getNumScalarOrVectorTotalBitWidth(const SPIRVType *Type) const
SPIRVType * getSPIRVTypeForVReg(Register VReg, const MachineFunction *MF=nullptr) const
Register getOrCreateConstInt(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)
SPIRVType * assignFloatTypeToVReg(unsigned BitWidth, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII)
SPIRVType * assignVectTypeToVReg(SPIRVType *BaseType, unsigned NumElements, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII)
Register getOrCreateUndef(MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII)
SPIRVType * getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder)
Register getOrCreateConsIntVector(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType, bool EmitIR=true)
const Type * getTypeForSPIRVType(const SPIRVType *Ty) const
Register buildConstantSampler(Register Res, unsigned AddrMode, unsigned Param, unsigned FilerMode, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType)
bool isBitcastCompatible(const SPIRVType *Type1, const SPIRVType *Type2) const
unsigned getScalarOrVectorComponentCount(Register VReg) const
SPIRVType * getOrCreateSPIRVFloatType(unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII)
SPIRVType * getOrCreateOpTypeImage(MachineIRBuilder &MIRBuilder, SPIRVType *SampledType, SPIRV::Dim::Dim Dim, uint32_t Depth, uint32_t Arrayed, uint32_t Multisampled, uint32_t Sampled, SPIRV::ImageFormat::ImageFormat ImageFormat, SPIRV::AccessQualifier::AccessQualifier AccQual)
bool isScalarOrVectorSigned(const SPIRVType *Type) const
SPIRVGlobalRegistry(unsigned PointerSize)
SPIRVType * getOrCreateOpTypeByOpcode(const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode)
Register buildConstantFP(APFloat Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr)
Register getSPIRVTypeID(const SPIRVType *SpirvType) const
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, MachineFunction &MF)
bool isScalarOfType(Register VReg, unsigned TypeOpcode) const
Register buildGlobalVariable(Register Reg, SPIRVType *BaseType, StringRef Name, const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage, const MachineInstr *Init, bool IsConst, bool HasLinkageTy, SPIRV::LinkageType::LinkageType LinkageType, MachineIRBuilder &MIRBuilder, bool IsInstSelector)
SPIRVType * assignIntTypeToVReg(unsigned BitWidth, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII)
unsigned getPointeeTypeOp(Register PtrReg)
SPIRVType * getOrCreateOpTypeSampledImage(SPIRVType *ImageType, MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVTypeByName(StringRef TypeStr, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SC=SPIRV::StorageClass::Function, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite)
SPIRVType * assignTypeToVReg(const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
SPIRVType * getOrCreateOpTypeFunctionWithArgs(const Type *Ty, SPIRVType *RetType, const SmallVectorImpl< SPIRVType * > &ArgTypes, MachineIRBuilder &MIRBuilder)
bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const
Register getOrCreateConstVector(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)
SPIRVType * getOrCreateOpTypeDeviceEvent(MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVPointerType(SPIRVType *BaseType, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SClass=SPIRV::StorageClass::Function)
SPIRVType * getOrCreateSPIRVVectorType(SPIRVType *BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVIntegerType(unsigned BitWidth, MachineIRBuilder &MIRBuilder)
Register getOrCreateConsIntArray(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII)
SPIRVType * getOrCreateSPIRVArrayType(SPIRVType *BaseType, unsigned NumElements, MachineInstr &I, const SPIRVInstrInfo &TII)
SPIRV::StorageClass::StorageClass getPointerStorageClass(Register VReg) const
SPIRVType * getOrCreateOpTypeSampler(MachineIRBuilder &MIRBuilder)
Register buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr, bool EmitIR=true)
Register getOrCreateConstFP(APFloat Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull=true)
Register getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder, SPIRVType *SpvType)
unsigned getScalarOrVectorBitWidth(const SPIRVType *Type) const
const SPIRVType * retrieveScalarOrVectorIntType(const SPIRVType *Type) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool consume_back(StringRef Suffix)
Returns true if this StringRef has the given suffix and removes that suffix.
Definition: StringRef.h:648
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:463
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:223
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:564
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:258
bool consume_front(StringRef Prefix)
Returns true if this StringRef has the given prefix and removes that prefix.
Definition: StringRef.h:628
size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:290
Class to represent struct types.
Definition: DerivedTypes.h:216
ArrayRef< Type * > elements() const
Definition: DerivedTypes.h:333
bool isPacked() const
Definition: DerivedTypes.h:278
bool hasName() const
Return true if this is a named struct that has a non-empty name.
Definition: DerivedTypes.h:304
StringRef getName() const
Return the name for this struct type if it has an identity.
Definition: Type.cpp:590
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
static Type * getHalfTy(LLVMContext &C)
static Type * getDoubleTy(LLVMContext &C)
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:265
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:252
Type * getArrayElementType() const
Definition: Type.h:404
uint64_t getArrayNumElements() const
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
static IntegerType * getInt8Ty(LLVMContext &C)
bool isFloatingPointTy() const
Return true if this is one of the floating-point types.
Definition: Type.h:185
static IntegerType * getInt32Ty(LLVMContext &C)
static Type * getFloatTy(LLVMContext &C)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:228
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
bool isVoidTy() const
Return true if this is 'void'.
Definition: Type.h:140
A few GPU targets, such as DXIL and SPIR-V, have typed pointers.
Type * getElementType() const
static TypedPointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
unsigned getAddressSpace() const
Return the address space of the Pointer type.
'undef' values are things that do not have specified contents.
Definition: Constants.h:1395
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
Definition: Constants.cpp:1795
bool hasName() const
Definition: Value.h:261
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:309
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
Definition: DerivedTypes.h:641
Type * getElementType() const
Definition: DerivedTypes.h:436
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
TargetExtType * parseBuiltinTypeNameToTargetExtType(std::string TypeName, LLVMContext &Context)
Translates a string representing a SPIR-V or OpenCL builtin type to a TargetExtType that can be furth...
SPIRVType * lowerBuiltinType(const Type *OpaqueType, SPIRV::AccessQualifier::AccessQualifier AccessQual, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
Definition: SPIRVUtils.cpp:100
unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC)
Definition: SPIRVUtils.cpp:166
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getPointerAddressSpace(const Type *T)
Definition: SPIRVUtils.h:126
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)
Definition: SPIRVUtils.cpp:80
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:155
AddressSpace
Definition: NVPTXBaseInfo.h:21
bool getSpirvBuiltInIdByName(llvm::StringRef Name, SPIRV::BuiltIn::BuiltIn &BI)
bool isTypedPointerTy(const Type *T)
Definition: SPIRVUtils.h:110
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
Definition: SPIRVUtils.cpp:117
Type * toTypedPointer(Type *Ty)
Definition: SPIRVUtils.h:156
bool isSpecialOpaqueType(const Type *Ty)
Definition: SPIRVUtils.cpp:379
bool isPointerTy(const Type *T)
Definition: SPIRVUtils.h:120
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:159
SPIRV::StorageClass::StorageClass addressSpaceToStorageClass(unsigned AddrSpace, const SPIRVSubtarget &STI)
Definition: SPIRVUtils.cpp:190
Type * parseBasicTypeName(StringRef &TypeName, LLVMContext &Ctx)
Definition: SPIRVUtils.cpp:400
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:191
bool hasBuiltinTypePrefix(StringRef Name)
Definition: SPIRVUtils.cpp:372
void addStringImm(const StringRef &Str, MCInst &Inst)
Definition: SPIRVUtils.cpp:51
void buildOpSpirvDecorations(Register Reg, MachineIRBuilder &MIRBuilder, const MDNode *GVarMD)
Definition: SPIRVUtils.cpp:136
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
Definition: Alignment.h:141