LLVM  15.0.0git
SPIRVGlobalRegistry.cpp
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1 //===-- SPIRVGlobalRegistry.cpp - SPIR-V Global Registry --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the implementation of the SPIRVGlobalRegistry class,
10 // which is used to maintain rich type information required for SPIR-V even
11 // after lowering from LLVM IR to GMIR. It can convert an llvm::Type into
12 // an OpTypeXXX instruction, and map it to a virtual register. Also it builds
13 // and supports consistency of constants and global variables.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "SPIRVGlobalRegistry.h"
18 #include "SPIRV.h"
19 #include "SPIRVSubtarget.h"
20 #include "SPIRVTargetMachine.h"
21 #include "SPIRVUtils.h"
22 
23 using namespace llvm;
26 
28  const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder,
29  SPIRV::AccessQualifier AccessQual, bool EmitIR) {
30 
31  SPIRVType *SpirvType =
32  getOrCreateSPIRVType(Type, MIRBuilder, AccessQual, EmitIR);
33  assignSPIRVTypeToVReg(SpirvType, VReg, MIRBuilder.getMF());
34  return SpirvType;
35 }
36 
38  Register VReg,
39  MachineFunction &MF) {
40  VRegToTypeMap[&MF][VReg] = SpirvType;
41 }
42 
44  auto &MRI = MIRBuilder.getMF().getRegInfo();
46  MRI.setRegClass(Res, &SPIRV::TYPERegClass);
47  return Res;
48 }
49 
52  MRI.setRegClass(Res, &SPIRV::TYPERegClass);
53  return Res;
54 }
55 
56 SPIRVType *SPIRVGlobalRegistry::getOpTypeBool(MachineIRBuilder &MIRBuilder) {
57  return MIRBuilder.buildInstr(SPIRV::OpTypeBool)
58  .addDef(createTypeVReg(MIRBuilder));
59 }
60 
61 SPIRVType *SPIRVGlobalRegistry::getOpTypeInt(uint32_t Width,
62  MachineIRBuilder &MIRBuilder,
63  bool IsSigned) {
64  auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeInt)
65  .addDef(createTypeVReg(MIRBuilder))
66  .addImm(Width)
67  .addImm(IsSigned ? 1 : 0);
68  return MIB;
69 }
70 
71 SPIRVType *SPIRVGlobalRegistry::getOpTypeFloat(uint32_t Width,
72  MachineIRBuilder &MIRBuilder) {
73  auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeFloat)
74  .addDef(createTypeVReg(MIRBuilder))
75  .addImm(Width);
76  return MIB;
77 }
78 
79 SPIRVType *SPIRVGlobalRegistry::getOpTypeVoid(MachineIRBuilder &MIRBuilder) {
80  return MIRBuilder.buildInstr(SPIRV::OpTypeVoid)
81  .addDef(createTypeVReg(MIRBuilder));
82 }
83 
84 SPIRVType *SPIRVGlobalRegistry::getOpTypeVector(uint32_t NumElems,
85  SPIRVType *ElemType,
86  MachineIRBuilder &MIRBuilder) {
87  auto EleOpc = ElemType->getOpcode();
88  assert((EleOpc == SPIRV::OpTypeInt || EleOpc == SPIRV::OpTypeFloat ||
89  EleOpc == SPIRV::OpTypeBool) &&
90  "Invalid vector element type");
91 
92  auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeVector)
93  .addDef(createTypeVReg(MIRBuilder))
94  .addUse(getSPIRVTypeID(ElemType))
95  .addImm(NumElems);
96  return MIB;
97 }
98 
100  MachineIRBuilder &MIRBuilder,
101  SPIRVType *SpvType,
102  bool EmitIR) {
103  auto &MF = MIRBuilder.getMF();
104  Register Res;
105  const IntegerType *LLVMIntTy;
106  if (SpvType)
107  LLVMIntTy = cast<IntegerType>(getTypeForSPIRVType(SpvType));
108  else
109  LLVMIntTy = IntegerType::getInt32Ty(MF.getFunction().getContext());
110  // Find a constant in DT or build a new one.
111  const auto ConstInt =
112  ConstantInt::get(const_cast<IntegerType *>(LLVMIntTy), Val);
113  unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
114  Res = MF.getRegInfo().createGenericVirtualRegister(LLT::scalar(BitWidth));
115  assignTypeToVReg(LLVMIntTy, Res, MIRBuilder);
116  if (EmitIR)
117  MIRBuilder.buildConstant(Res, *ConstInt);
118  else
119  MIRBuilder.buildInstr(SPIRV::OpConstantI)
120  .addDef(Res)
121  .addImm(ConstInt->getSExtValue());
122  return Res;
123 }
124 
126  MachineIRBuilder &MIRBuilder,
127  SPIRVType *SpvType) {
128  auto &MF = MIRBuilder.getMF();
129  Register Res;
130  const Type *LLVMFPTy;
131  if (SpvType) {
132  LLVMFPTy = getTypeForSPIRVType(SpvType);
133  assert(LLVMFPTy->isFloatingPointTy());
134  } else {
135  LLVMFPTy = IntegerType::getFloatTy(MF.getFunction().getContext());
136  }
137  // Find a constant in DT or build a new one.
138  const auto ConstFP = ConstantFP::get(LLVMFPTy->getContext(), Val);
139  unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
140  Res = MF.getRegInfo().createGenericVirtualRegister(LLT::scalar(BitWidth));
141  assignTypeToVReg(LLVMFPTy, Res, MIRBuilder);
142  MIRBuilder.buildFConstant(Res, *ConstFP);
143  return Res;
144 }
145 
148  const GlobalValue *GV, SPIRV::StorageClass Storage,
149  const MachineInstr *Init, bool IsConst, bool HasLinkageTy,
151  bool IsInstSelector) {
152  const GlobalVariable *GVar = nullptr;
153  if (GV)
154  GVar = cast<const GlobalVariable>(GV);
155  else {
156  // If GV is not passed explicitly, use the name to find or construct
157  // the global variable.
158  Module *M = MIRBuilder.getMF().getFunction().getParent();
159  GVar = M->getGlobalVariable(Name);
160  if (GVar == nullptr) {
161  const Type *Ty = getTypeForSPIRVType(BaseType); // TODO: check type.
162  GVar = new GlobalVariable(*M, const_cast<Type *>(Ty), false,
164  Twine(Name));
165  }
166  GV = GVar;
167  }
168  Register Reg;
169  auto MIB = MIRBuilder.buildInstr(SPIRV::OpVariable)
170  .addDef(ResVReg)
172  .addImm(static_cast<uint32_t>(Storage));
173 
174  if (Init != 0) {
175  MIB.addUse(Init->getOperand(0).getReg());
176  }
177 
178  // ISel may introduce a new register on this step, so we need to add it to
179  // DT and correct its type avoiding fails on the next stage.
180  if (IsInstSelector) {
181  const auto &Subtarget = CurMF->getSubtarget();
182  constrainSelectedInstRegOperands(*MIB, *Subtarget.getInstrInfo(),
183  *Subtarget.getRegisterInfo(),
184  *Subtarget.getRegBankInfo());
185  }
186  Reg = MIB->getOperand(0).getReg();
187 
188  // Set to Reg the same type as ResVReg has.
189  auto MRI = MIRBuilder.getMRI();
190  assert(MRI->getType(ResVReg).isPointer() && "Pointer type is expected");
191  if (Reg != ResVReg) {
192  LLT RegLLTy = LLT::pointer(MRI->getType(ResVReg).getAddressSpace(), 32);
193  MRI->setType(Reg, RegLLTy);
194  assignSPIRVTypeToVReg(BaseType, Reg, MIRBuilder.getMF());
195  }
196 
197  // If it's a global variable with name, output OpName for it.
198  if (GVar && GVar->hasName())
199  buildOpName(Reg, GVar->getName(), MIRBuilder);
200 
201  // Output decorations for the GV.
202  // TODO: maybe move to GenerateDecorations pass.
203  if (IsConst)
205 
206  if (GVar && GVar->getAlign().valueOrOne().value() != 1)
208  Reg, MIRBuilder, SPIRV::Decoration::Alignment,
209  {static_cast<uint32_t>(GVar->getAlign().valueOrOne().value())});
210 
211  if (HasLinkageTy)
213  {static_cast<uint32_t>(LinkageType)}, Name);
214  return Reg;
215 }
216 
217 SPIRVType *SPIRVGlobalRegistry::getOpTypeArray(uint32_t NumElems,
218  SPIRVType *ElemType,
219  MachineIRBuilder &MIRBuilder,
220  bool EmitIR) {
221  assert((ElemType->getOpcode() != SPIRV::OpTypeVoid) &&
222  "Invalid array element type");
223  Register NumElementsVReg =
224  buildConstantInt(NumElems, MIRBuilder, nullptr, EmitIR);
225  auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeArray)
226  .addDef(createTypeVReg(MIRBuilder))
227  .addUse(getSPIRVTypeID(ElemType))
228  .addUse(NumElementsVReg);
229  return MIB;
230 }
231 
232 SPIRVType *SPIRVGlobalRegistry::getOpTypePointer(SPIRV::StorageClass SC,
233  SPIRVType *ElemType,
234  MachineIRBuilder &MIRBuilder) {
235  auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypePointer)
236  .addDef(createTypeVReg(MIRBuilder))
237  .addImm(static_cast<uint32_t>(SC))
238  .addUse(getSPIRVTypeID(ElemType));
239  return MIB;
240 }
241 
242 SPIRVType *SPIRVGlobalRegistry::getOpTypeFunction(
243  SPIRVType *RetType, const SmallVectorImpl<SPIRVType *> &ArgTypes,
244  MachineIRBuilder &MIRBuilder) {
245  auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeFunction)
246  .addDef(createTypeVReg(MIRBuilder))
247  .addUse(getSPIRVTypeID(RetType));
248  for (const SPIRVType *ArgType : ArgTypes)
249  MIB.addUse(getSPIRVTypeID(ArgType));
250  return MIB;
251 }
252 
253 SPIRVType *SPIRVGlobalRegistry::createSPIRVType(const Type *Ty,
254  MachineIRBuilder &MIRBuilder,
256  bool EmitIR) {
257  if (auto IType = dyn_cast<IntegerType>(Ty)) {
258  const unsigned Width = IType->getBitWidth();
259  return Width == 1 ? getOpTypeBool(MIRBuilder)
260  : getOpTypeInt(Width, MIRBuilder, false);
261  }
262  if (Ty->isFloatingPointTy())
263  return getOpTypeFloat(Ty->getPrimitiveSizeInBits(), MIRBuilder);
264  if (Ty->isVoidTy())
265  return getOpTypeVoid(MIRBuilder);
266  if (Ty->isVectorTy()) {
267  auto El = getOrCreateSPIRVType(cast<FixedVectorType>(Ty)->getElementType(),
268  MIRBuilder);
269  return getOpTypeVector(cast<FixedVectorType>(Ty)->getNumElements(), El,
270  MIRBuilder);
271  }
272  if (Ty->isArrayTy()) {
273  auto *El = getOrCreateSPIRVType(Ty->getArrayElementType(), MIRBuilder);
274  return getOpTypeArray(Ty->getArrayNumElements(), El, MIRBuilder, EmitIR);
275  }
276  assert(!isa<StructType>(Ty) && "Unsupported StructType");
277  if (auto FType = dyn_cast<FunctionType>(Ty)) {
278  SPIRVType *RetTy = getOrCreateSPIRVType(FType->getReturnType(), MIRBuilder);
279  SmallVector<SPIRVType *, 4> ParamTypes;
280  for (const auto &t : FType->params()) {
281  ParamTypes.push_back(getOrCreateSPIRVType(t, MIRBuilder));
282  }
283  return getOpTypeFunction(RetTy, ParamTypes, MIRBuilder);
284  }
285  if (auto PType = dyn_cast<PointerType>(Ty)) {
286  SPIRVType *SpvElementType;
287  // At the moment, all opaque pointers correspond to i8 element type.
288  // TODO: change the implementation once opaque pointers are supported
289  // in the SPIR-V specification.
290  if (PType->isOpaque()) {
291  SpvElementType = getOrCreateSPIRVIntegerType(8, MIRBuilder);
292  } else {
293  Type *ElemType = PType->getNonOpaquePointerElementType();
294  // TODO: support OpenCL and SPIRV builtins like image2d_t that are passed
295  // as pointers, but should be treated as custom types like OpTypeImage.
296  assert(!isa<StructType>(ElemType) && "Unsupported StructType pointer");
297 
298  // Otherwise, treat it as a regular pointer type.
299  SpvElementType = getOrCreateSPIRVType(
300  ElemType, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, EmitIR);
301  }
302  auto SC = addressSpaceToStorageClass(PType->getAddressSpace());
303  return getOpTypePointer(SC, SpvElementType, MIRBuilder);
304  }
305  llvm_unreachable("Unable to convert LLVM type to SPIRVType");
306 }
307 
309  auto t = VRegToTypeMap.find(CurMF);
310  if (t != VRegToTypeMap.end()) {
311  auto tt = t->second.find(VReg);
312  if (tt != t->second.end())
313  return tt->second;
314  }
315  return nullptr;
316 }
317 
319  const Type *Type, MachineIRBuilder &MIRBuilder,
320  SPIRV::AccessQualifier AccessQual, bool EmitIR) {
321  SPIRVType *SpirvType = createSPIRVType(Type, MIRBuilder, AccessQual, EmitIR);
322  VRegToTypeMap[&MIRBuilder.getMF()][getSPIRVTypeID(SpirvType)] = SpirvType;
323  SPIRVToLLVMType[SpirvType] = Type;
324  return SpirvType;
325 }
326 
328  unsigned TypeOpcode) const {
330  assert(Type && "isScalarOfType VReg has no type assigned");
331  return Type->getOpcode() == TypeOpcode;
332 }
333 
335  unsigned TypeOpcode) const {
337  assert(Type && "isScalarOrVectorOfType VReg has no type assigned");
338  if (Type->getOpcode() == TypeOpcode)
339  return true;
340  if (Type->getOpcode() == SPIRV::OpTypeVector) {
341  Register ScalarTypeVReg = Type->getOperand(1).getReg();
342  SPIRVType *ScalarType = getSPIRVTypeForVReg(ScalarTypeVReg);
343  return ScalarType->getOpcode() == TypeOpcode;
344  }
345  return false;
346 }
347 
348 unsigned
350  assert(Type && "Invalid Type pointer");
351  if (Type->getOpcode() == SPIRV::OpTypeVector) {
352  auto EleTypeReg = Type->getOperand(1).getReg();
353  Type = getSPIRVTypeForVReg(EleTypeReg);
354  }
355  if (Type->getOpcode() == SPIRV::OpTypeInt ||
356  Type->getOpcode() == SPIRV::OpTypeFloat)
357  return Type->getOperand(1).getImm();
358  if (Type->getOpcode() == SPIRV::OpTypeBool)
359  return 1;
360  llvm_unreachable("Attempting to get bit width of non-integer/float type.");
361 }
362 
364  assert(Type && "Invalid Type pointer");
365  if (Type->getOpcode() == SPIRV::OpTypeVector) {
366  auto EleTypeReg = Type->getOperand(1).getReg();
367  Type = getSPIRVTypeForVReg(EleTypeReg);
368  }
369  if (Type->getOpcode() == SPIRV::OpTypeInt)
370  return Type->getOperand(2).getImm() != 0;
371  llvm_unreachable("Attempting to get sign of non-integer type.");
372 }
373 
377  assert(Type && Type->getOpcode() == SPIRV::OpTypePointer &&
378  Type->getOperand(1).isImm() && "Pointer type is expected");
379  return static_cast<SPIRV::StorageClass>(Type->getOperand(1).getImm());
380 }
381 
382 SPIRVType *
384  MachineIRBuilder &MIRBuilder) {
385  return getOrCreateSPIRVType(
387  MIRBuilder);
388 }
389 
390 SPIRVType *SPIRVGlobalRegistry::restOfCreateSPIRVType(Type *LLVMTy,
391  MachineInstrBuilder MIB) {
392  SPIRVType *SpirvType = MIB;
393  VRegToTypeMap[CurMF][getSPIRVTypeID(SpirvType)] = SpirvType;
394  SPIRVToLLVMType[SpirvType] = LLVMTy;
395  return SpirvType;
396 }
397 
399  unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) {
401  MachineBasicBlock &BB = *I.getParent();
402  auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypeInt))
404  .addImm(BitWidth)
405  .addImm(0);
406  return restOfCreateSPIRVType(LLVMTy, MIB);
407 }
408 
409 SPIRVType *
411  return getOrCreateSPIRVType(
412  IntegerType::get(MIRBuilder.getMF().getFunction().getContext(), 1),
413  MIRBuilder);
414 }
415 
417  SPIRVType *BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder) {
418  return getOrCreateSPIRVType(
420  NumElements),
421  MIRBuilder);
422 }
423 
425  SPIRVType *BaseType, unsigned NumElements, MachineInstr &I,
426  const SPIRVInstrInfo &TII) {
427  Type *LLVMTy = FixedVectorType::get(
428  const_cast<Type *>(getTypeForSPIRVType(BaseType)), NumElements);
429  MachineBasicBlock &BB = *I.getParent();
430  auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypeVector))
433  .addImm(NumElements);
434  return restOfCreateSPIRVType(LLVMTy, MIB);
435 }
436 
437 SPIRVType *
439  MachineIRBuilder &MIRBuilder,
440  SPIRV::StorageClass SClass) {
441  return getOrCreateSPIRVType(
444  MIRBuilder);
445 }
446 
450  Type *LLVMTy =
453  MachineBasicBlock &BB = *I.getParent();
454  auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypePointer))
456  .addImm(static_cast<uint32_t>(SC))
458  return restOfCreateSPIRVType(LLVMTy, MIB);
459 }
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::SPIRVGlobalRegistry::isScalarOrVectorOfType
bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const
Definition: SPIRVGlobalRegistry.cpp:334
llvm::SPIRV::LinkageType
LinkageType
Definition: SPIRVBaseInfo.h:431
llvm::SPIRVGlobalRegistry::isScalarOfType
bool isScalarOfType(Register VReg, unsigned TypeOpcode) const
Definition: SPIRVGlobalRegistry.cpp:327
llvm::SPIRVGlobalRegistry::SPIRVGlobalRegistry
SPIRVGlobalRegistry(unsigned PointerSize)
Definition: SPIRVGlobalRegistry.cpp:24
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
createTypeVReg
static Register createTypeVReg(MachineIRBuilder &MIRBuilder)
Definition: SPIRVGlobalRegistry.cpp:43
llvm::PointerType::get
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Definition: Type.cpp:727
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:287
llvm::GlobalObject::getAlign
MaybeAlign getAlign() const
Returns the alignment of the given variable or function.
Definition: GlobalObject.h:79
llvm::SPIRVGlobalRegistry::getScalarOrVectorBitWidth
unsigned getScalarOrVectorBitWidth(const SPIRVType *Type) const
Definition: SPIRVGlobalRegistry.cpp:349
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bool hasName() const
Definition: Value.h:261
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
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Definition: GlobalVariable.h:39
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LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:320
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The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
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void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, MachineFunction &MF)
Definition: SPIRVGlobalRegistry.cpp:37
llvm::MaybeAlign::valueOrOne
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
Definition: Alignment.h:142
SPIRVSubtarget.h
BaseType
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:163
llvm::Type::getInt32Ty
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:239
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MachineFunction * CurMF
Definition: SPIRVGlobalRegistry.h:49
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bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:150
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:283
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SPIRVType * getSPIRVTypeForVReg(Register VReg) const
Definition: SPIRVGlobalRegistry.cpp:308
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Register buildGlobalVariable(Register Reg, SPIRVType *BaseType, StringRef Name, const GlobalValue *GV, SPIRV::StorageClass Storage, const MachineInstr *Init, bool IsConst, bool HasLinkageTy, SPIRV::LinkageType LinkageType, MachineIRBuilder &MIRBuilder, bool IsInstSelector)
Definition: SPIRVGlobalRegistry.cpp:146
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const Type * getTypeForSPIRVType(const SPIRVType *Ty) const
Definition: SPIRVGlobalRegistry.h:73
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::Type::isArrayTy
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:215
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::SPIRVGlobalRegistry::buildConstantFP
Register buildConstantFP(APFloat Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr)
Definition: SPIRVGlobalRegistry.cpp:125
llvm::PPCISD::SC
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
Definition: PPCISelLowering.h:418
llvm::MachineRegisterInfo::setType
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
Definition: MachineRegisterInfo.cpp:180
llvm::AMDGPU::HSAMD::Kernel::Arg::Key::AccQual
constexpr char AccQual[]
Key for Kernel::Arg::Metadata::mAccQual.
Definition: AMDGPUMetadata.h:191
t
bitcast float %x to i32 %s=and i32 %t, 2147483647 %d=bitcast i32 %s to float ret float %d } declare float @fabsf(float %n) define float @bar(float %x) nounwind { %d=call float @fabsf(float %x) ret float %d } This IR(from PR6194):target datalayout="e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple="x86_64-apple-darwin10.0.0" %0=type { double, double } %struct.float3=type { float, float, float } define void @test(%0, %struct.float3 *nocapture %res) nounwind noinline ssp { entry:%tmp18=extractvalue %0 %0, 0 t
Definition: README-SSE.txt:788
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AccessQualifier
Definition: SPIRVBaseInfo.h:437
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bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
false
Definition: StackSlotColoring.cpp:141
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
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Class to represent integer types.
Definition: DerivedTypes.h:40
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MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:269
SPIRVUtils.h
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:924
llvm::FixedVectorType::get
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:684
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SPIRV::Decoration::LinkageAttributes
@ LinkageAttributes
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:49
llvm::LLT::getAddressSpace
unsigned getAddressSpace() const
Definition: LowLevelTypeImpl.h:238
SPIRVTargetMachine.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::Type::getArrayElementType
Type * getArrayElementType() const
Definition: Type.h:365
llvm::SPIRV::Decoration::Alignment
@ Alignment
llvm::APFloat
Definition: APFloat.h:701
addressSpaceToStorageClass
SPIRV::StorageClass addressSpaceToStorageClass(unsigned AddrSpace)
Definition: SPIRVUtils.cpp:148
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineIRBuilder::buildFConstant
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
Definition: MachineIRBuilder.cpp:312
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:219
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
SPIRVGlobalRegistry.h
llvm::SPIRV::StorageClass
StorageClass
Definition: SPIRVBaseInfo.h:255
uint64_t
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:620
storageClassToAddressSpace
unsigned storageClassToAddressSpace(SPIRV::StorageClass SC)
Definition: SPIRVUtils.cpp:129
I
#define I(x, y, z)
Definition: MD5.cpp:58
SPIRV.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:120
llvm::SPIRV::AccessQualifier::ReadWrite
@ ReadWrite
llvm::Type::getArrayNumElements
uint64_t getArrayNumElements() const
Definition: DerivedTypes.h:384
llvm::Type::isVoidTy
bool isVoidTy() const
Return true if this is 'void'.
Definition: Type.h:139
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:186
buildOpDecorate
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, llvm::SPIRV::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
Definition: SPIRVUtils.cpp:108
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:374
llvm::AMDGPU::HSAMD::Kernel::Arg::Key::IsConst
constexpr char IsConst[]
Key for Kernel::Arg::Metadata::mIsConst.
Definition: AMDGPUMetadata.h:195
llvm::SPIRVInstrInfo
Definition: SPIRVInstrInfo.h:24
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
uint32_t
buildOpName
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
Definition: SPIRVUtils.cpp:91
llvm::Value::getName
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:305
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVBoolType
SPIRVType * getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder)
Definition: SPIRVGlobalRegistry.cpp:410
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:128
llvm::Init
Definition: Record.h:281
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVPointerType
SPIRVType * getOrCreateSPIRVPointerType(SPIRVType *BaseType, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass SClass=SPIRV::StorageClass::Function)
Definition: SPIRVGlobalRegistry.cpp:438
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType
SPIRVType * getOrCreateSPIRVIntegerType(unsigned BitWidth, MachineIRBuilder &MIRBuilder)
Definition: SPIRVGlobalRegistry.cpp:383
llvm::ConstantFP::get
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
Definition: Constants.cpp:971
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::SPIRVGlobalRegistry::getSPIRVTypeID
Register getSPIRVTypeID(const SPIRVType *SpirvType) const
Definition: SPIRVGlobalRegistry.h:89
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::GlobalValue::ExternalLinkage
@ ExternalLinkage
Externally visible function.
Definition: GlobalValue.h:48
llvm::SPIRVGlobalRegistry::getPointerStorageClass
SPIRV::StorageClass getPointerStorageClass(Register VReg) const
Definition: SPIRVGlobalRegistry.cpp:375
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
llvm::SPIRVGlobalRegistry::buildConstantInt
Register buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr, bool EmitIR=true)
Definition: SPIRVGlobalRegistry.cpp:99
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::SPIRVGlobalRegistry::assignTypeToVReg
SPIRVType * assignTypeToVReg(const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
Definition: SPIRVGlobalRegistry.cpp:27
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::IntegerType::get
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:311
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVType
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
Definition: SPIRVGlobalRegistry.cpp:318
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::SPIRVGlobalRegistry::isScalarOrVectorSigned
bool isScalarOrVectorSigned(const SPIRVType *Type) const
Definition: SPIRVGlobalRegistry.cpp:363
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVVectorType
SPIRVType * getOrCreateSPIRVVectorType(SPIRVType *BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder)
Definition: SPIRVGlobalRegistry.cpp:416
llvm::SPIRV::Decoration::Constant
@ Constant
llvm::Type::getFloatTy
static Type * getFloatTy(LLVMContext &C)
Definition: Type.cpp:226
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:56
llvm::Type::getPrimitiveSizeInBits
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:164
llvm::LLT
Definition: LowLevelTypeImpl.h:39