19#include "llvm/IR/IntrinsicsSPIRV.h"
23#define DEBUG_TYPE "spirv-builtins"
27#define GET_BuiltinGroup_DECL
28#include "SPIRVGenTables.inc"
32 InstructionSet::InstructionSet
Set;
38#define GET_DemangledBuiltins_DECL
39#define GET_DemangledBuiltins_IMPL
59 InstructionSet::InstructionSet
Set;
63#define GET_NativeBuiltins_DECL
64#define GET_NativeBuiltins_IMPL
82#define GET_GroupBuiltins_DECL
83#define GET_GroupBuiltins_IMPL
87 InstructionSet::InstructionSet
Set;
91using namespace BuiltIn;
92#define GET_GetBuiltins_DECL
93#define GET_GetBuiltins_IMPL
97 InstructionSet::InstructionSet
Set;
101#define GET_ImageQueryBuiltins_DECL
102#define GET_ImageQueryBuiltins_IMPL
106 InstructionSet::InstructionSet
Set;
115 InstructionSet::InstructionSet
Set;
121using namespace FPRoundingMode;
122#define GET_ConvertBuiltins_DECL
123#define GET_ConvertBuiltins_IMPL
125using namespace InstructionSet;
126#define GET_VectorLoadStoreBuiltins_DECL
127#define GET_VectorLoadStoreBuiltins_IMPL
129#define GET_CLMemoryScope_DECL
130#define GET_CLSamplerAddressingMode_DECL
131#define GET_CLMemoryFenceFlags_DECL
132#define GET_ExtendedBuiltins_DECL
133#include "SPIRVGenTables.inc"
151static std::unique_ptr<const SPIRV::IncomingCall>
153 SPIRV::InstructionSet::InstructionSet Set,
158 std::string BuiltinName =
164 if (BuiltinName.find(
'<') && BuiltinName.back() ==
'>') {
165 BuiltinName = BuiltinName.substr(0, BuiltinName.find(
'<'));
166 BuiltinName = BuiltinName.substr(BuiltinName.find_last_of(
" ") + 1);
174 BuiltinName = BuiltinName.substr(0, BuiltinName.find(
"_R"));
179 DemangledCall.
slice(DemangledCall.
find(
'(') + 1, DemangledCall.
find(
')'));
180 BuiltinArgs.
split(BuiltinArgumentTypes,
',', -1,
false);
185 if ((Builtin = SPIRV::lookupBuiltin(BuiltinName, Set)))
186 return std::make_unique<SPIRV::IncomingCall>(
187 BuiltinName, Builtin, ReturnRegister, ReturnType,
Arguments);
192 if (BuiltinArgumentTypes.
size() >= 1) {
193 char FirstArgumentType = BuiltinArgumentTypes[0][0];
198 switch (FirstArgumentType) {
201 if (Set == SPIRV::InstructionSet::OpenCL_std)
203 else if (Set == SPIRV::InstructionSet::GLSL_std_450)
211 if (Set == SPIRV::InstructionSet::OpenCL_std)
213 else if (Set == SPIRV::InstructionSet::GLSL_std_450)
220 if (Set == SPIRV::InstructionSet::OpenCL_std ||
221 Set == SPIRV::InstructionSet::GLSL_std_450)
227 if (!Prefix.empty() &&
228 (Builtin = SPIRV::lookupBuiltin(Prefix + BuiltinName, Set)))
229 return std::make_unique<SPIRV::IncomingCall>(
230 BuiltinName, Builtin, ReturnRegister, ReturnType,
Arguments);
237 switch (FirstArgumentType) {
258 if (!Suffix.empty() &&
259 (Builtin = SPIRV::lookupBuiltin(BuiltinName + Suffix, Set)))
260 return std::make_unique<SPIRV::IncomingCall>(
261 BuiltinName, Builtin, ReturnRegister, ReturnType,
Arguments);
276static std::tuple<Register, SPIRVType *>
282 if (ResultType->
getOpcode() == SPIRV::OpTypeVector) {
297 return std::make_tuple(ResultRegister, BoolType);
308 if (ReturnType->getOpcode() == SPIRV::OpTypeVector) {
317 return MIRBuilder.
buildSelect(ReturnRegister, SourceRegister, TrueConst,
328 if (!DestinationReg.isValid()) {
329 DestinationReg =
MRI->createVirtualRegister(&SPIRV::IDRegClass);
336 MIRBuilder.
buildLoad(DestinationReg, PtrRegister, PtrInfo,
Align());
337 return DestinationReg;
345 SPIRV::BuiltIn::BuiltIn BuiltinValue,
353 VariableType, MIRBuilder, SPIRV::StorageClass::Input);
359 SPIRV::StorageClass::Input,
nullptr,
true,
true,
360 SPIRV::LinkageType::Import, MIRBuilder,
false);
366 return LoadedRegister;
375 SPIRVGlobalRegistry *GR,
376 MachineIRBuilder &MIB,
377 MachineRegisterInfo &
MRI);
380static SPIRV::MemorySemantics::MemorySemantics
383 case std::memory_order::memory_order_relaxed:
384 return SPIRV::MemorySemantics::None;
385 case std::memory_order::memory_order_acquire:
386 return SPIRV::MemorySemantics::Acquire;
387 case std::memory_order::memory_order_release:
388 return SPIRV::MemorySemantics::Release;
389 case std::memory_order::memory_order_acq_rel:
390 return SPIRV::MemorySemantics::AcquireRelease;
391 case std::memory_order::memory_order_seq_cst:
392 return SPIRV::MemorySemantics::SequentiallyConsistent;
400 case SPIRV::CLMemoryScope::memory_scope_work_item:
401 return SPIRV::Scope::Invocation;
402 case SPIRV::CLMemoryScope::memory_scope_work_group:
403 return SPIRV::Scope::Workgroup;
404 case SPIRV::CLMemoryScope::memory_scope_device:
405 return SPIRV::Scope::Device;
406 case SPIRV::CLMemoryScope::memory_scope_all_svm_devices:
407 return SPIRV::Scope::CrossDevice;
408 case SPIRV::CLMemoryScope::memory_scope_sub_group:
409 return SPIRV::Scope::Subgroup;
422 SPIRV::Scope::Scope Scope,
426 if (CLScopeRegister.
isValid()) {
431 if (CLScope ==
static_cast<unsigned>(Scope)) {
432 MRI->setRegClass(CLScopeRegister, &SPIRV::IDRegClass);
433 return CLScopeRegister;
440 Register PtrRegister,
unsigned &Semantics,
443 if (SemanticsRegister.
isValid()) {
445 std::memory_order Order =
451 if (Order == Semantics) {
452 MRI->setRegClass(SemanticsRegister, &SPIRV::IDRegClass);
453 return SemanticsRegister;
462 assert(Call->Arguments.size() == 2 &&
463 "Need 2 arguments for atomic init translation");
467 .
addUse(Call->Arguments[0])
468 .
addUse(Call->Arguments[1]);
476 Register PtrRegister = Call->Arguments[0];
482 if (Call->Arguments.size() > 1) {
483 ScopeRegister = Call->Arguments[1];
489 if (Call->Arguments.size() > 2) {
491 MemSemanticsReg = Call->Arguments[2];
495 SPIRV::MemorySemantics::SequentiallyConsistent |
501 .
addDef(Call->ReturnRegister)
515 Register PtrRegister = Call->Arguments[0];
518 SPIRV::MemorySemantics::SequentiallyConsistent |
526 .
addUse(Call->Arguments[1]);
536 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
537 bool IsCmpxchg = Call->Builtin->Name.contains(
"cmpxchg");
540 Register ObjectPtr = Call->Arguments[0];
541 Register ExpectedArg = Call->Arguments[1];
542 Register Desired = Call->Arguments[2];
543 MRI->setRegClass(ObjectPtr, &SPIRV::IDRegClass);
544 MRI->setRegClass(ExpectedArg, &SPIRV::IDRegClass);
545 MRI->setRegClass(Desired, &SPIRV::IDRegClass);
547 LLT DesiredLLT =
MRI->getType(Desired);
550 SPIRV::OpTypePointer);
552 assert(IsCmpxchg ? ExpectedType == SPIRV::OpTypeInt
553 : ExpectedType == SPIRV::OpTypePointer);
558 auto StorageClass =
static_cast<SPIRV::StorageClass::StorageClass
>(
566 ? SPIRV::MemorySemantics::None
567 : SPIRV::MemorySemantics::SequentiallyConsistent | MemSemStorage;
570 ? SPIRV::MemorySemantics::None
571 : SPIRV::MemorySemantics::SequentiallyConsistent | MemSemStorage;
572 if (Call->Arguments.size() >= 4) {
573 assert(Call->Arguments.size() >= 5 &&
574 "Need 5+ args for explicit atomic cmpxchg");
581 if (MemOrdEq == MemSemEqual)
582 MemSemEqualReg = Call->Arguments[3];
583 if (MemOrdNeq == MemSemEqual)
584 MemSemUnequalReg = Call->Arguments[4];
585 MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass);
586 MRI->setRegClass(Call->Arguments[4], &SPIRV::IDRegClass);
590 if (!MemSemUnequalReg.
isValid())
594 auto Scope = IsCmpxchg ? SPIRV::Scope::Workgroup : SPIRV::Scope::Device;
595 if (Call->Arguments.size() >= 6) {
596 assert(Call->Arguments.size() == 6 &&
597 "Extra args for explicit atomic cmpxchg");
598 auto ClScope =
static_cast<SPIRV::CLMemoryScope
>(
601 if (ClScope ==
static_cast<unsigned>(Scope))
602 ScopeReg = Call->Arguments[5];
603 MRI->setRegClass(Call->Arguments[5], &SPIRV::IDRegClass);
613 Register Tmp = !IsCmpxchg ?
MRI->createGenericVirtualRegister(DesiredLLT)
614 : Call->ReturnRegister;
615 if (!
MRI->getRegClassOrNull(Tmp))
616 MRI->setRegClass(Tmp, &SPIRV::IDRegClass);
642 Call->Arguments.size() >= 4 ? Call->Arguments[3] :
Register();
644 assert(Call->Arguments.size() <= 4 &&
645 "Too many args for explicit atomic RMW");
646 ScopeRegister =
buildScopeReg(ScopeRegister, SPIRV::Scope::Workgroup,
647 MIRBuilder, GR,
MRI);
649 Register PtrRegister = Call->Arguments[0];
650 unsigned Semantics = SPIRV::MemorySemantics::None;
651 MRI->setRegClass(PtrRegister, &SPIRV::IDRegClass);
653 Call->Arguments.size() >= 3 ? Call->Arguments[2] :
Register();
655 Semantics, MIRBuilder, GR);
656 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
658 .
addDef(Call->ReturnRegister)
663 .
addUse(Call->Arguments[1]);
673 Register PtrRegister = Call->Arguments[0];
674 unsigned Semantics = SPIRV::MemorySemantics::SequentiallyConsistent;
676 Call->Arguments.size() >= 2 ? Call->Arguments[1] :
Register();
678 Semantics, MIRBuilder, GR);
680 assert((Opcode != SPIRV::OpAtomicFlagClear ||
681 (Semantics != SPIRV::MemorySemantics::Acquire &&
682 Semantics != SPIRV::MemorySemantics::AcquireRelease)) &&
683 "Invalid memory order argument!");
686 Call->Arguments.size() >= 3 ? Call->Arguments[2] :
Register();
691 if (Opcode == SPIRV::OpAtomicFlagTestAndSet)
692 MIB.
addDef(Call->ReturnRegister)
706 unsigned MemSemantics = SPIRV::MemorySemantics::None;
708 if (MemFlags & SPIRV::CLK_LOCAL_MEM_FENCE)
709 MemSemantics |= SPIRV::MemorySemantics::WorkgroupMemory;
711 if (MemFlags & SPIRV::CLK_GLOBAL_MEM_FENCE)
712 MemSemantics |= SPIRV::MemorySemantics::CrossWorkgroupMemory;
714 if (MemFlags & SPIRV::CLK_IMAGE_MEM_FENCE)
715 MemSemantics |= SPIRV::MemorySemantics::ImageMemory;
717 if (Opcode == SPIRV::OpMemoryBarrier) {
718 std::memory_order MemOrder =
722 MemSemantics |= SPIRV::MemorySemantics::SequentiallyConsistent;
726 if (MemFlags == MemSemantics) {
727 MemSemanticsReg = Call->Arguments[0];
728 MRI->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass);
733 SPIRV::Scope::Scope Scope = SPIRV::Scope::Workgroup;
734 SPIRV::Scope::Scope MemScope = Scope;
735 if (Call->Arguments.size() >= 2) {
737 ((Opcode != SPIRV::OpMemoryBarrier && Call->Arguments.size() == 2) ||
738 (Opcode == SPIRV::OpMemoryBarrier && Call->Arguments.size() == 3)) &&
739 "Extra args for explicitly scoped barrier");
740 Register ScopeArg = (Opcode == SPIRV::OpMemoryBarrier) ? Call->Arguments[2]
741 : Call->Arguments[1];
742 SPIRV::CLMemoryScope CLScope =
745 if (!(MemFlags & SPIRV::CLK_LOCAL_MEM_FENCE) ||
746 (Opcode == SPIRV::OpMemoryBarrier))
749 if (CLScope ==
static_cast<unsigned>(Scope)) {
750 ScopeReg = Call->Arguments[1];
751 MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass);
759 if (Opcode != SPIRV::OpMemoryBarrier)
761 MIB.
addUse(MemSemanticsReg);
767 case SPIRV::Dim::DIM_1D:
768 case SPIRV::Dim::DIM_Buffer:
770 case SPIRV::Dim::DIM_2D:
771 case SPIRV::Dim::DIM_Cube:
772 case SPIRV::Dim::DIM_Rect:
774 case SPIRV::Dim::DIM_3D:
787 return arrayed ? numComps + 1 : numComps;
800 SPIRV::lookupExtendedBuiltin(Builtin->
Name, Builtin->
Set)->Number;
805 .
addDef(Call->ReturnRegister)
810 for (
auto Argument : Call->Arguments)
821 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
825 std::tie(CompareRegister, RelationType) =
833 for (
auto Argument : Call->Arguments)
837 return buildSelectInst(MIRBuilder, Call->ReturnRegister, CompareRegister,
838 Call->ReturnType, GR);
846 SPIRV::lookupGroupBuiltin(Builtin->
Name);
850 Register ConstRegister = Call->Arguments[0];
853 assert(ArgInstruction->getOpcode() == TargetOpcode::G_CONSTANT &&
854 "Only constant bool value args are supported");
861 Register GroupResultRegister = Call->ReturnRegister;
862 SPIRVType *GroupResultType = Call->ReturnType;
866 const bool HasBoolReturnTy =
872 std::tie(GroupResultRegister, GroupResultType) =
875 auto Scope = Builtin->
Name.
startswith(
"sub_group") ? SPIRV::Scope::Subgroup
876 : SPIRV::Scope::Workgroup;
881 .
addDef(GroupResultRegister)
887 if (Call->Arguments.size() > 0) {
889 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
890 for (
unsigned i = 1; i < Call->Arguments.size(); i++) {
891 MIB.addUse(Call->Arguments[i]);
892 MRI->setRegClass(Call->Arguments[i], &SPIRV::IDRegClass);
899 Call->ReturnType, GR);
932 SPIRV::BuiltIn::BuiltIn BuiltinValue,
934 Register IndexRegister = Call->Arguments[0];
935 const unsigned ResultWidth = Call->ReturnType->getOperand(1).getImm();
943 Register ToTruncate = Call->ReturnRegister;
946 bool IsConstantIndex =
947 IndexInstruction->getOpcode() == TargetOpcode::G_CONSTANT;
952 Register DefaultReg = Call->ReturnRegister;
953 if (PointerSize != ResultWidth) {
954 DefaultReg =
MRI->createGenericVirtualRegister(
LLT::scalar(PointerSize));
955 MRI->setRegClass(DefaultReg, &SPIRV::IDRegClass);
958 ToTruncate = DefaultReg;
962 MIRBuilder.
buildCopy(DefaultReg, NewRegister);
970 Register Extracted = Call->ReturnRegister;
971 if (!IsConstantIndex || PointerSize != ResultWidth) {
972 Extracted =
MRI->createGenericVirtualRegister(
LLT::scalar(PointerSize));
973 MRI->setRegClass(Extracted, &SPIRV::IDRegClass);
983 if (!IsConstantIndex) {
992 MRI->setRegClass(CompareRegister, &SPIRV::IDRegClass);
1005 Register SelectionResult = Call->ReturnRegister;
1006 if (PointerSize != ResultWidth) {
1009 MRI->setRegClass(SelectionResult, &SPIRV::IDRegClass);
1011 MIRBuilder.
getMF());
1014 MIRBuilder.
buildSelect(SelectionResult, CompareRegister, Extracted,
1016 ToTruncate = SelectionResult;
1018 ToTruncate = Extracted;
1022 if (PointerSize != ResultWidth)
1032 SPIRV::BuiltIn::BuiltIn
Value =
1033 SPIRV::lookupGetBuiltin(Builtin->
Name, Builtin->
Set)->
Value;
1035 if (
Value == SPIRV::BuiltIn::GlobalInvocationId)
1041 if (Call->ReturnType->getOpcode() == SPIRV::OpTypeVector)
1048 LLType, Call->ReturnRegister);
1057 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1060 case SPIRV::OpStore:
1062 case SPIRV::OpAtomicLoad:
1064 case SPIRV::OpAtomicStore:
1066 case SPIRV::OpAtomicCompareExchange:
1067 case SPIRV::OpAtomicCompareExchangeWeak:
1069 case SPIRV::OpAtomicIAdd:
1070 case SPIRV::OpAtomicISub:
1071 case SPIRV::OpAtomicOr:
1072 case SPIRV::OpAtomicXor:
1073 case SPIRV::OpAtomicAnd:
1074 case SPIRV::OpAtomicExchange:
1076 case SPIRV::OpMemoryBarrier:
1078 case SPIRV::OpAtomicFlagTestAndSet:
1079 case SPIRV::OpAtomicFlagClear:
1092 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1101 bool IsVec = Opcode == SPIRV::OpTypeVector;
1103 MIRBuilder.
buildInstr(IsVec ? SPIRV::OpDot : SPIRV::OpFMulS)
1104 .
addDef(Call->ReturnRegister)
1106 .
addUse(Call->Arguments[0])
1107 .
addUse(Call->Arguments[1]);
1115 SPIRV::BuiltIn::BuiltIn
Value =
1116 SPIRV::lookupGetBuiltin(Call->Builtin->Name, Call->Builtin->Set)->
Value;
1117 uint64_t IsDefault = (
Value == SPIRV::BuiltIn::GlobalSize ||
1118 Value == SPIRV::BuiltIn::WorkgroupSize ||
1119 Value == SPIRV::BuiltIn::EnqueuedWorkgroupSize);
1129 SPIRV::lookupImageQueryBuiltin(Builtin->
Name, Builtin->
Set)->Component;
1134 unsigned NumExpectedRetComponents =
RetTy->getOpcode() == SPIRV::OpTypeVector
1135 ?
RetTy->getOperand(2).getImm()
1140 Register QueryResult = Call->ReturnRegister;
1141 SPIRVType *QueryResultType = Call->ReturnType;
1142 if (NumExpectedRetComponents != NumActualRetComponents) {
1148 IntTy, NumActualRetComponents, MIRBuilder);
1153 IsDimBuf ? SPIRV::OpImageQuerySize : SPIRV::OpImageQuerySizeLod;
1158 .
addUse(Call->Arguments[0]);
1161 if (NumExpectedRetComponents == NumActualRetComponents)
1163 if (NumExpectedRetComponents == 1) {
1165 unsigned ExtractedComposite =
1166 Component == 3 ? NumActualRetComponents - 1 : Component;
1167 assert(ExtractedComposite < NumActualRetComponents &&
1168 "Invalid composite index!");
1169 MIRBuilder.
buildInstr(SPIRV::OpCompositeExtract)
1170 .
addDef(Call->ReturnRegister)
1173 .
addImm(ExtractedComposite);
1176 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpVectorShuffle)
1177 .
addDef(Call->ReturnRegister)
1181 for (
unsigned i = 0; i < NumExpectedRetComponents; ++i)
1182 MIB.
addImm(i < NumActualRetComponents ? i : 0xffffffff);
1190 assert(Call->ReturnType->getOpcode() == SPIRV::OpTypeInt &&
1191 "Image samples query result must be of int type!");
1196 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1198 Register Image = Call->Arguments[0];
1200 SPIRV::Dim::Dim ImageDimensionality =
static_cast<SPIRV::Dim::Dim
>(
1204 case SPIRV::OpImageQuerySamples:
1205 assert(ImageDimensionality == SPIRV::Dim::DIM_2D &&
1206 "Image must be of 2D dimensionality");
1208 case SPIRV::OpImageQueryLevels:
1209 assert((ImageDimensionality == SPIRV::Dim::DIM_1D ||
1210 ImageDimensionality == SPIRV::Dim::DIM_2D ||
1211 ImageDimensionality == SPIRV::Dim::DIM_3D ||
1212 ImageDimensionality == SPIRV::Dim::DIM_Cube) &&
1213 "Image must be of 1D/2D/3D/Cube dimensionality");
1218 .
addDef(Call->ReturnRegister)
1225static SPIRV::SamplerAddressingMode::SamplerAddressingMode
1227 switch (Bitmask & SPIRV::CLK_ADDRESS_MODE_MASK) {
1228 case SPIRV::CLK_ADDRESS_CLAMP:
1229 return SPIRV::SamplerAddressingMode::Clamp;
1230 case SPIRV::CLK_ADDRESS_CLAMP_TO_EDGE:
1231 return SPIRV::SamplerAddressingMode::ClampToEdge;
1232 case SPIRV::CLK_ADDRESS_REPEAT:
1233 return SPIRV::SamplerAddressingMode::Repeat;
1234 case SPIRV::CLK_ADDRESS_MIRRORED_REPEAT:
1235 return SPIRV::SamplerAddressingMode::RepeatMirrored;
1236 case SPIRV::CLK_ADDRESS_NONE:
1237 return SPIRV::SamplerAddressingMode::None;
1244 return (Bitmask & SPIRV::CLK_NORMALIZED_COORDS_TRUE) ? 1 : 0;
1247static SPIRV::SamplerFilterMode::SamplerFilterMode
1249 if (Bitmask & SPIRV::CLK_FILTER_LINEAR)
1250 return SPIRV::SamplerFilterMode::Linear;
1251 if (Bitmask & SPIRV::CLK_FILTER_NEAREST)
1252 return SPIRV::SamplerFilterMode::Nearest;
1253 return SPIRV::SamplerFilterMode::Nearest;
1260 Register Image = Call->Arguments[0];
1262 MRI->setRegClass(Image, &SPIRV::IDRegClass);
1263 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
1266 if (HasOclSampler || HasMsaa)
1267 MRI->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
1268 if (HasOclSampler) {
1269 Register Sampler = Call->Arguments[1];
1283 Register SampledImage =
MRI->createVirtualRegister(&SPIRV::IDRegClass);
1294 bool NeedsExtraction =
false;
1295 if (TempType->
getOpcode() != SPIRV::OpTypeVector) {
1298 NeedsExtraction =
true;
1301 Register TempRegister =
MRI->createGenericVirtualRegister(LLType);
1302 MRI->setRegClass(TempRegister, &SPIRV::IDRegClass);
1305 MIRBuilder.
buildInstr(SPIRV::OpImageSampleExplicitLod)
1306 .
addDef(NeedsExtraction ? TempRegister : Call->ReturnRegister)
1309 .
addUse(Call->Arguments[2])
1310 .
addImm(SPIRV::ImageOperand::Lod)
1313 if (NeedsExtraction)
1314 MIRBuilder.
buildInstr(SPIRV::OpCompositeExtract)
1315 .
addDef(Call->ReturnRegister)
1319 }
else if (HasMsaa) {
1321 .
addDef(Call->ReturnRegister)
1324 .
addUse(Call->Arguments[1])
1325 .
addImm(SPIRV::ImageOperand::Sample)
1326 .
addUse(Call->Arguments[2]);
1329 .
addDef(Call->ReturnRegister)
1332 .
addUse(Call->Arguments[1]);
1344 .
addUse(Call->Arguments[0])
1345 .
addUse(Call->Arguments[1])
1346 .
addUse(Call->Arguments[2]);
1355 if (Call->Builtin->Name.contains_insensitive(
1356 "__translate_sampler_initializer")) {
1363 return Sampler.isValid();
1364 }
else if (Call->Builtin->Name.contains_insensitive(
"__spirv_SampledImage")) {
1366 Register Image = Call->Arguments[0];
1371 Call->ReturnRegister.isValid()
1372 ? Call->ReturnRegister
1373 :
MRI->createVirtualRegister(&SPIRV::IDRegClass);
1378 .
addUse(Call->Arguments[1]);
1380 }
else if (Call->Builtin->Name.contains_insensitive(
1381 "__spirv_ImageSampleExplicitLod")) {
1383 std::string ReturnType = DemangledCall.
str();
1384 if (DemangledCall.
contains(
"_R")) {
1385 ReturnType = ReturnType.substr(ReturnType.find(
"_R") + 2);
1386 ReturnType = ReturnType.substr(0, ReturnType.find(
'('));
1389 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1390 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
1391 MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass);
1393 MIRBuilder.
buildInstr(SPIRV::OpImageSampleExplicitLod)
1394 .
addDef(Call->ReturnRegister)
1396 .
addUse(Call->Arguments[0])
1397 .
addUse(Call->Arguments[1])
1398 .
addImm(SPIRV::ImageOperand::Lod)
1399 .
addUse(Call->Arguments[3]);
1407 MIRBuilder.
buildSelect(Call->ReturnRegister, Call->Arguments[0],
1408 Call->Arguments[1], Call->Arguments[2]);
1418 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1422 case SPIRV::OpSpecConstant: {
1426 buildOpDecorate(Call->ReturnRegister, MIRBuilder, SPIRV::Decoration::SpecId,
1429 Register ConstRegister = Call->Arguments[1];
1432 (Const->getOpcode() == TargetOpcode::G_CONSTANT ||
1433 Const->getOpcode() == TargetOpcode::G_FCONSTANT) &&
1434 "Argument should be either an int or floating-point constant");
1437 if (Call->ReturnType->getOpcode() == SPIRV::OpTypeBool) {
1438 assert(ConstOperand.
isCImm() &&
"Int constant operand is expected");
1440 ? SPIRV::OpSpecConstantTrue
1441 : SPIRV::OpSpecConstantFalse;
1444 .
addDef(Call->ReturnRegister)
1447 if (Call->ReturnType->getOpcode() != SPIRV::OpTypeBool) {
1448 if (Const->getOpcode() == TargetOpcode::G_CONSTANT)
1455 case SPIRV::OpSpecConstantComposite: {
1457 .
addDef(Call->ReturnRegister)
1459 for (
unsigned i = 0; i < Call->Arguments.size(); i++)
1460 MIB.
addUse(Call->Arguments[i]);
1472 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1479 Register TmpReg =
MRI->createVirtualRegister(&SPIRV::IDRegClass);
1483 unsigned NumArgs = Call->Arguments.size();
1485 Register GlobalWorkSize = Call->Arguments[NumArgs < 4 ? 1 : 2];
1486 MRI->setRegClass(GlobalWorkSize, &SPIRV::IDRegClass);
1488 NumArgs == 2 ?
Register(0) : Call->Arguments[NumArgs < 4 ? 2 : 3];
1490 MRI->setRegClass(LocalWorkSize, &SPIRV::IDRegClass);
1491 Register GlobalWorkOffset = NumArgs <= 3 ?
Register(0) : Call->Arguments[1];
1492 if (GlobalWorkOffset.
isValid())
1493 MRI->setRegClass(GlobalWorkOffset, &SPIRV::IDRegClass);
1497 if (SpvTy->
getOpcode() == SPIRV::OpTypePointer) {
1502 if (!
MRI->getRegClassOrNull(GWSPtr))
1503 MRI->setRegClass(GWSPtr, &SPIRV::IDRegClass);
1505 unsigned Size = Call->Builtin->Name.equals(
"ndrange_3D") ? 3 : 2;
1510 GlobalWorkSize =
MRI->createVirtualRegister(&SPIRV::IDRegClass);
1521 LocalWorkSize = Const;
1522 if (!GlobalWorkOffset.
isValid())
1523 GlobalWorkOffset = Const;
1531 .
addUse(GlobalWorkOffset);
1533 .
addUse(Call->Arguments[0])
1545 assert(
MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST &&
1546 MI->getOperand(1).isReg());
1547 Register BitcastReg =
MI->getOperand(1).getReg();
1575 Register ValueReg =
MI->getOperand(0).getReg();
1580 assert(Ty &&
"Type is expected");
1592 if (
MI->getOpcode() == TargetOpcode::G_GLOBAL_VALUE)
1595 "Blocks in OpenCL C must be traceable to allocation site");
1620 bool HasEvents = Call->Builtin->Name.find(
"events") !=
StringRef::npos;
1628 const unsigned LocalSizeArrayIdx = HasEvents ? 9 : 6;
1629 Register GepReg = Call->Arguments[LocalSizeArrayIdx];
1636 assert(LocalSizeTy &&
"Local size type is expected");
1638 cast<ArrayType>(LocalSizeTy)->getNumElements();
1642 Int32Ty, MIRBuilder, SPIRV::StorageClass::Function);
1643 for (
unsigned I = 0;
I < LocalSizeNum; ++
I) {
1645 MRI->setType(
Reg, LLType);
1659 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpEnqueueKernel)
1660 .
addDef(Call->ReturnRegister)
1664 const unsigned BlockFIdx = HasEvents ? 6 : 3;
1665 for (
unsigned i = 0; i < BlockFIdx; i++)
1666 MIB.addUse(Call->Arguments[i]);
1673 MIB.addUse(NullPtr);
1674 MIB.addUse(NullPtr);
1682 Register BlockLiteralReg = Call->Arguments[BlockFIdx + 1];
1684 MIB.addUse(BlockLiteralReg);
1694 for (
unsigned i = 0; i < LocalSizes.
size(); i++)
1695 MIB.addUse(LocalSizes[i]);
1705 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1708 case SPIRV::OpRetainEvent:
1709 case SPIRV::OpReleaseEvent:
1712 case SPIRV::OpCreateUserEvent:
1713 case SPIRV::OpGetDefaultQueue:
1715 .
addDef(Call->ReturnRegister)
1717 case SPIRV::OpIsValidEvent:
1720 .
addDef(Call->ReturnRegister)
1722 .
addUse(Call->Arguments[0]);
1723 case SPIRV::OpSetUserEventStatus:
1727 .
addUse(Call->Arguments[0])
1728 .
addUse(Call->Arguments[1]);
1729 case SPIRV::OpCaptureEventProfilingInfo:
1734 .
addUse(Call->Arguments[0])
1735 .
addUse(Call->Arguments[1])
1736 .
addUse(Call->Arguments[2]);
1737 case SPIRV::OpBuildNDRange:
1739 case SPIRV::OpEnqueueKernel:
1752 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1756 case SPIRV::OpGroupAsyncCopy:
1758 .
addDef(Call->ReturnRegister)
1761 .
addUse(Call->Arguments[0])
1762 .
addUse(Call->Arguments[1])
1763 .
addUse(Call->Arguments[2])
1765 .
addUse(Call->Arguments[3]);
1766 case SPIRV::OpGroupWaitEvents:
1769 .
addUse(Call->Arguments[0])
1770 .
addUse(Call->Arguments[1]);
1782 SPIRV::lookupConvertBuiltin(Call->Builtin->Name, Call->Builtin->Set);
1786 SPIRV::Decoration::SaturatedConversion, {});
1789 SPIRV::Decoration::FPRoundingMode,
1790 {(unsigned)Builtin->RoundingMode});
1792 unsigned Opcode = SPIRV::OpNop;
1799 : SPIRV::OpSatConvertSToU;
1802 : SPIRV::OpSConvert;
1804 SPIRV::OpTypeFloat)) {
1806 bool IsSourceSigned =
1808 Opcode = IsSourceSigned ? SPIRV::OpConvertSToF : SPIRV::OpConvertUToF;
1811 SPIRV::OpTypeFloat)) {
1816 : SPIRV::OpConvertFToU;
1818 SPIRV::OpTypeFloat))
1820 Opcode = SPIRV::OpFConvert;
1823 assert(Opcode != SPIRV::OpNop &&
1824 "Conversion between the types not implemented!");
1827 .
addDef(Call->ReturnRegister)
1829 .
addUse(Call->Arguments[0]);
1838 SPIRV::lookupVectorLoadStoreBuiltin(Call->Builtin->Name,
1839 Call->Builtin->Set);
1843 .
addDef(Call->ReturnRegister)
1845 .
addImm(
static_cast<uint32_t>(SPIRV::InstructionSet::OpenCL_std))
1847 for (
auto Argument : Call->Arguments)
1863 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1864 bool IsLoad = Opcode == SPIRV::OpLoad;
1868 MIB.
addDef(Call->ReturnRegister);
1872 MIB.
addUse(Call->Arguments[0]);
1874 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1877 MIB.addUse(Call->Arguments[1]);
1878 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
1881 unsigned NumArgs = Call->Arguments.size();
1882 if ((IsLoad && NumArgs >= 2) || NumArgs >= 3) {
1884 MRI->setRegClass(Call->Arguments[IsLoad ? 1 : 2], &SPIRV::IDRegClass);
1886 if ((IsLoad && NumArgs >= 3) || NumArgs >= 4) {
1888 MRI->setRegClass(Call->Arguments[IsLoad ? 2 : 3], &SPIRV::IDRegClass);
1897 SPIRV::InstructionSet::InstructionSet Set,
1902 LLVM_DEBUG(
dbgs() <<
"Lowering builtin call: " << DemangledCall <<
"\n");
1907 if (OrigRetTy && !OrigRetTy->
isVoidTy()) {
1911 }
else if (OrigRetTy && OrigRetTy->
isVoidTy()) {
1918 std::unique_ptr<const IncomingCall> Call =
1919 lookupBuiltin(DemangledCall, Set, ReturnRegister, ReturnType, Args);
1923 return std::nullopt;
1927 assert(Args.size() >= Call->Builtin->MinNumArgs &&
1928 "Too few arguments to generate the builtin");
1929 if (Call->Builtin->MaxNumArgs && Args.size() > Call->Builtin->MaxNumArgs)
1930 LLVM_DEBUG(
dbgs() <<
"More arguments provided than required!\n");
1933 switch (Call->Builtin->Group) {
1934 case SPIRV::Extended:
1936 case SPIRV::Relational:
1940 case SPIRV::Variable:
1944 case SPIRV::Barrier:
1948 case SPIRV::GetQuery:
1950 case SPIRV::ImageSizeQuery:
1952 case SPIRV::ImageMiscQuery:
1954 case SPIRV::ReadImage:
1956 case SPIRV::WriteImage:
1958 case SPIRV::SampleImage:
1962 case SPIRV::SpecConstant:
1964 case SPIRV::Enqueue:
1966 case SPIRV::AsyncCopy:
1968 case SPIRV::Convert:
1970 case SPIRV::VectorLoadStore:
1972 case SPIRV::LoadStore:
1983#define GET_BuiltinTypes_DECL
1984#define GET_BuiltinTypes_IMPL
1991#define GET_OpenCLTypes_DECL
1992#define GET_OpenCLTypes_IMPL
1994#include "SPIRVGenTables.inc"
2002 if (
Name.startswith(
"void"))
2004 else if (
Name.startswith(
"int") ||
Name.startswith(
"uint"))
2006 else if (
Name.startswith(
"float"))
2008 else if (
Name.startswith(
"half"))
2016 "Not a SPIR-V/OpenCL special opaque type!");
2018 "This already is SPIR-V/OpenCL TargetExtType!");
2025 if (NameWithParameters.
startswith(
"opencl.")) {
2027 SPIRV::lookupOpenCLType(NameWithParameters);
2030 NameWithParameters);
2038 "Unknown builtin opaque type!");
2042 if (NameWithParameters.
find(
'_') == std::string::npos)
2046 unsigned BaseNameLength = NameWithParameters.
find(
'_') - 1;
2047 SplitString(NameWithParameters.
substr(BaseNameLength + 1), Parameters,
"_");
2050 bool HasTypeParameter = !
isDigit(Parameters[0][0]);
2051 if (HasTypeParameter)
2055 for (
unsigned i = HasTypeParameter ? 1 : 0; i < Parameters.
size(); i++) {
2056 unsigned IntParameter = 0;
2057 bool ValidLiteral = !Parameters[i].getAsInteger(10, IntParameter);
2059 "Invalid format of SPIR-V builtin parameter literal!");
2063 NameWithParameters.
substr(0, BaseNameLength),
2064 TypeParameters, IntParameters);
2075 unsigned Opcode = TypeRecord->
Opcode;
2090 "Invalid number of parameters for SPIR-V pipe builtin!");
2093 SPIRV::AccessQualifier::AccessQualifier(
2099 const SPIRV::AccessQualifier::AccessQualifier Qualifier,
2102 "SPIR-V image builtin type must have sampled type parameter!");
2106 "Invalid number of parameters for SPIR-V image builtin!");
2109 MIRBuilder, SampledType,
2114 Qualifier == SPIRV::AccessQualifier::WriteOnly
2115 ? SPIRV::AccessQualifier::WriteOnly
2116 : SPIRV::AccessQualifier::AccessQualifier(
2124 OpaqueType, SPIRV::AccessQualifier::ReadOnly, MIRBuilder, GR);
2131 SPIRV::AccessQualifier::AccessQualifier AccessQual,
2161 switch (TypeRecord->
Opcode) {
2162 case SPIRV::OpTypeImage:
2165 case SPIRV::OpTypePipe:
2168 case SPIRV::OpTypeDeviceEvent:
2171 case SPIRV::OpTypeSampler:
2174 case SPIRV::OpTypeSampledImage:
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
AMDGPU Lower Kernel Arguments
static bool isDigit(const char C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
APInt bitcastToAPInt() const
static APFloat getZero(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Zero.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
uint64_t getZExtValue() const
Get zero extended value.
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
static ArrayType * get(Type *ElementType, uint64_t NumElements)
This static method is the primary way to construct an ArrayType.
@ ICMP_ULT
unsigned less than
const APFloat & getValueAPF() const
const APInt & getValue() const
Return the constant as an APInt value reference.
A parsed version of the target data layout string in and methods for querying it.
Tagged union holding either a T or a Error.
Class to represent fixed width SIMD vectors.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
This is an important class for using LLVM in a threaded context.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)
Build and insert a G_INTRINSIC instruction.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
const DataLayout & getDataLayout() const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
const ConstantInt * getCImm() const
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const MDNode * getMetadata() const
Register getReg() const
getReg - Returns the register number.
const ConstantFP * getFPImm() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Wrapper class representing virtual and physical registers.
constexpr bool isValid() const
SPIRVType * getOrCreateOpTypePipe(MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccQual)
Register getOrCreateConsIntVector(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII)
SPIRVType * getOrCreateSPIRVTypeByName(StringRef TypeStr, MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder)
const Type * getTypeForSPIRVType(const SPIRVType *Ty) const
Register buildConstantSampler(Register Res, unsigned AddrMode, unsigned Param, unsigned FilerMode, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType)
SPIRVType * getOrCreateOpTypeImage(MachineIRBuilder &MIRBuilder, SPIRVType *SampledType, SPIRV::Dim::Dim Dim, uint32_t Depth, uint32_t Arrayed, uint32_t Multisampled, uint32_t Sampled, SPIRV::ImageFormat::ImageFormat ImageFormat, SPIRV::AccessQualifier::AccessQualifier AccQual)
SPIRVType * getSPIRVTypeForVReg(Register VReg) const
unsigned getPointerSize() const
SPIRVType * getOrCreateOpTypeByOpcode(const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode)
Register buildConstantFP(APFloat Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr)
Register getSPIRVTypeID(const SPIRVType *SpirvType) const
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, MachineFunction &MF)
bool isScalarOfType(Register VReg, unsigned TypeOpcode) const
Register buildGlobalVariable(Register Reg, SPIRVType *BaseType, StringRef Name, const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage, const MachineInstr *Init, bool IsConst, bool HasLinkageTy, SPIRV::LinkageType::LinkageType LinkageType, MachineIRBuilder &MIRBuilder, bool IsInstSelector)
SPIRVType * getOrCreateOpTypeSampledImage(SPIRVType *ImageType, MachineIRBuilder &MIRBuilder)
SPIRVType * assignTypeToVReg(const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const
SPIRVType * getOrCreateOpTypeDeviceEvent(MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVPointerType(SPIRVType *BaseType, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SClass=SPIRV::StorageClass::Function)
SPIRVType * getOrCreateSPIRVVectorType(SPIRVType *BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVIntegerType(unsigned BitWidth, MachineIRBuilder &MIRBuilder)
Register getOrCreateConsIntArray(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII)
SPIRV::StorageClass::StorageClass getPointerStorageClass(Register VReg) const
SPIRVType * getOrCreateOpTypeSampler(MachineIRBuilder &MIRBuilder)
Register buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr, bool EmitIR=true)
Register getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder, SPIRVType *SpvType)
unsigned getScalarOrVectorBitWidth(const SPIRVType *Type) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
std::string str() const
str - Get the contents as an std::string.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
bool contains_insensitive(StringRef Other) const
Return true if the given string is a substring of *this, and false otherwise.
StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
bool contains(StringRef Other) const
Return true if the given string is a substring of *this, and false otherwise.
bool startswith(StringRef Prefix) const
size_t find_first_of(char C, size_t From=0) const
Find the first character in the string that is C, or npos if not found.
size_t find(char C, size_t From=0) const
Search for the first character C in the string.
static constexpr size_t npos
Class to represent struct types.
static StructType * getTypeByName(LLVMContext &C, StringRef Name)
Return the type with the specified name, or null if there is none by that name.
static StructType * create(LLVMContext &Context, StringRef Name)
This creates an identified struct.
Class to represent target extensions types, which are generally unintrospectable from target-independ...
unsigned getNumIntParameters() const
static TargetExtType * get(LLVMContext &Context, StringRef Name, ArrayRef< Type * > Types=std::nullopt, ArrayRef< unsigned > Ints=std::nullopt)
Return a target extension type having the specified name and optional type and integer parameters.
Type * getTypeParameter(unsigned i) const
unsigned getNumTypeParameters() const
unsigned getIntParameter(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed.
static Type * getHalfTy(LLVMContext &C)
StringRef getStructName() const
static Type * getVoidTy(LLVMContext &C)
bool isTargetExtTy() const
Return true if this is a target extension type.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
static IntegerType * getInt32Ty(LLVMContext &C)
static Type * getFloatTy(LLVMContext &C)
bool isVoidTy() const
Return true if this is 'void'.
LLVM Value Representation.
Value(Type *Ty, unsigned scid)
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
LLVMTypeRef LLVMVectorType(LLVMTypeRef ElementType, unsigned ElementCount)
Create a vector type that contains a defined type and has a specific number of elements.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::optional< bool > lowerBuiltin(const StringRef DemangledCall, SPIRV::InstructionSet::InstructionSet Set, MachineIRBuilder &MIRBuilder, const Register OrigRet, const Type *OrigRetTy, const SmallVectorImpl< Register > &Args, SPIRVGlobalRegistry *GR)
SPIRVType * lowerBuiltinType(const Type *OpaqueType, SPIRV::AccessQualifier::AccessQualifier AccessQual, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
This is an optimization pass for GlobalISel generic memory operations.
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC)
static bool buildAtomicCompareExchangeInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building an atomic compare-exchange instruction.
static bool generateGetQueryInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateLoadStoreInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static Register buildConstantIntReg(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR, unsigned BitWidth=32)
static bool buildAtomicFlagInst(const SPIRV::IncomingCall *Call, unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building atomic flag instructions (e.g.
static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static Register buildBuiltinVariableLoad(MachineIRBuilder &MIRBuilder, SPIRVType *VariableType, SPIRVGlobalRegistry *GR, SPIRV::BuiltIn::BuiltIn BuiltinValue, LLT LLType, Register Reg=Register(0))
Helper function for building a load instruction for loading a builtin global variable of BuiltinValue...
static SPIRV::SamplerFilterMode::SamplerFilterMode getSamplerFilterModeFromBitmask(unsigned Bitmask)
static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building an atomic store instruction.
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)
static const Type * getBlockStructType(Register ParamReg, MachineRegisterInfo *MRI)
static bool generateGroupInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static unsigned getNumComponentsForDim(SPIRV::Dim::Dim dim)
Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy, SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB, MachineRegisterInfo &MRI)
Helper external function for inserting ASSIGN_TYPE instuction between Reg and its definition,...
static Register buildScopeReg(Register CLScopeRegister, SPIRV::Scope::Scope Scope, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR, MachineRegisterInfo *MRI)
static std::tuple< Register, SPIRVType * > buildBoolRegister(MachineIRBuilder &MIRBuilder, const SPIRVType *ResultType, SPIRVGlobalRegistry *GR)
Helper function building either a resulting scalar or vector bool register depending on the expected ...
static unsigned getNumSizeComponents(SPIRVType *imgType)
Helper function for obtaining the number of size components.
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI)
static SPIRVType * getSampledImageType(const TargetExtType *OpaqueType, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
SPIRV::MemorySemantics::MemorySemantics getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC)
static bool generateDotOrFMulInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateSampleImageInst(const StringRef DemangledCall, const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateBarrierInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRVType * getImageType(const TargetExtType *ExtensionType, const SPIRV::AccessQualifier::AccessQualifier Qualifier, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building barriers, i.e., memory/control ordering operations.
static bool generateAsyncCopy(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRV::Scope::Scope getSPIRVScope(SPIRV::CLMemoryScope ClScope)
static SPIRVType * getSamplerType(MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
bool isSpecialOpaqueType(const Type *Ty)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static Register buildLoadInst(SPIRVType *BaseType, Register PtrRegister, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR, LLT LowLevelType, Register DestinationReg=Register(0))
Helper function for building a load instruction loading into the DestinationReg.
static bool generateEnqueueInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
static bool buildSelectInst(MachineIRBuilder &MIRBuilder, Register ReturnRegister, Register SourceRegister, const SPIRVType *ReturnType, SPIRVGlobalRegistry *GR)
Helper function for building either a vector or scalar select instruction depending on the expected R...
static const Type * getMachineInstrType(MachineInstr *MI)
bool isSpvIntrinsic(MachineInstr &MI, Intrinsic::ID IntrinsicID)
static SPIRV::SamplerAddressingMode::SamplerAddressingMode getSamplerAddressingModeFromBitmask(unsigned Bitmask)
static bool generateAtomicInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateConvertInst(const StringRef DemangledCall, const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static Register buildMemSemanticsReg(Register SemanticsRegister, Register PtrRegister, unsigned &Semantics, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static unsigned getConstFromIntrinsic(Register Reg, MachineRegisterInfo *MRI)
static bool generateImageMiscQueryInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateSelectInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder)
static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building an atomic load instruction.
static bool generateSpecConstantInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRVType * getOrCreateSPIRVDeviceEventPointer(MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateVectorLoadStoreInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR, SPIRV::BuiltIn::BuiltIn BuiltinValue, uint64_t DefaultValue)
const Type * getTypedPtrEltType(const Type *Ty)
static std::unique_ptr< const SPIRV::IncomingCall > lookupBuiltin(StringRef DemangledCall, SPIRV::InstructionSet::InstructionSet Set, Register ReturnRegister, const SPIRVType *ReturnType, const SmallVectorImpl< Register > &Arguments)
Looks up the demangled builtin call in the SPIRVBuiltins.td records using the provided DemangledCall ...
MachineInstr * getDefInstrMaybeConstant(Register &ConstReg, const MachineRegisterInfo *MRI)
constexpr unsigned BitWidth
const MachineInstr SPIRVType
static bool generateReadImageInst(const StringRef DemangledCall, const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Type * getMDOperandAsType(const MDNode *N, unsigned I)
static const TargetExtType * parseToTargetExtType(const Type *OpaqueType, MachineIRBuilder &MIRBuilder)
static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building an atomic load instruction.
static SPIRV::MemorySemantics::MemorySemantics getSPIRVMemSemantics(std::memory_order MemOrder)
static bool generateRelationalInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool buildAtomicInitInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder)
Helper function for translating atomic init to OpStore.
static bool generateWriteImageInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRVType * getPipeType(const TargetExtType *ExtensionType, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static Type * parseTypeString(const StringRef Name, LLVMContext &Context)
static bool generateExtInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool buildNDRange(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRVType * getNonParameterizedType(const TargetExtType *ExtensionType, const SPIRV::BuiltinType *TypeRecord, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static MachineInstr * getBlockStructInstr(Register ParamReg, MachineRegisterInfo *MRI)
static unsigned getSamplerParamFromBitmask(unsigned Bitmask)
std::string getLinkStringForBuiltIn(SPIRV::BuiltIn::BuiltIn BuiltInValue)
static bool generateBuiltinVar(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static const fltSemantics & IEEEsingle() LLVM_READNONE
This struct is a compact representation of a valid (non-zero power of two) alignment.
This class contains a discriminated union of information about pointers in memory operands,...
FPRoundingMode::FPRoundingMode RoundingMode
InstructionSet::InstructionSet Set
InstructionSet::InstructionSet Set
InstructionSet::InstructionSet Set
InstructionSet::InstructionSet Set
const SmallVectorImpl< Register > & Arguments
const std::string BuiltinName
const SPIRVType * ReturnType
const Register ReturnRegister
const DemangledBuiltin * Builtin
IncomingCall(const std::string BuiltinName, const DemangledBuiltin *Builtin, const Register ReturnRegister, const SPIRVType *ReturnType, const SmallVectorImpl< Register > &Arguments)
InstructionSet::InstructionSet Set
StringRef SpirvTypeLiteral
InstructionSet::InstructionSet Set
FPRoundingMode::FPRoundingMode RoundingMode