18#include "llvm/IR/IntrinsicsSPIRV.h"
22#define DEBUG_TYPE "spirv-builtins"
26#define GET_BuiltinGroup_DECL
27#include "SPIRVGenTables.inc"
31 InstructionSet::InstructionSet
Set;
37#define GET_DemangledBuiltins_DECL
38#define GET_DemangledBuiltins_IMPL
58 InstructionSet::InstructionSet
Set;
62#define GET_NativeBuiltins_DECL
63#define GET_NativeBuiltins_IMPL
81#define GET_GroupBuiltins_DECL
82#define GET_GroupBuiltins_IMPL
86 InstructionSet::InstructionSet
Set;
90using namespace BuiltIn;
91#define GET_GetBuiltins_DECL
92#define GET_GetBuiltins_IMPL
96 InstructionSet::InstructionSet
Set;
100#define GET_ImageQueryBuiltins_DECL
101#define GET_ImageQueryBuiltins_IMPL
105 InstructionSet::InstructionSet
Set;
114 InstructionSet::InstructionSet
Set;
120using namespace FPRoundingMode;
121#define GET_ConvertBuiltins_DECL
122#define GET_ConvertBuiltins_IMPL
124using namespace InstructionSet;
125#define GET_VectorLoadStoreBuiltins_DECL
126#define GET_VectorLoadStoreBuiltins_IMPL
128#define GET_CLMemoryScope_DECL
129#define GET_CLSamplerAddressingMode_DECL
130#define GET_CLMemoryFenceFlags_DECL
131#define GET_ExtendedBuiltins_DECL
132#include "SPIRVGenTables.inc"
150static std::unique_ptr<const SPIRV::IncomingCall>
152 SPIRV::InstructionSet::InstructionSet Set,
157 std::string BuiltinName =
163 if (BuiltinName.find(
'<') && BuiltinName.back() ==
'>') {
164 BuiltinName = BuiltinName.substr(0, BuiltinName.find(
'<'));
165 BuiltinName = BuiltinName.substr(BuiltinName.find_last_of(
" ") + 1);
173 BuiltinName = BuiltinName.substr(0, BuiltinName.find(
"_R"));
178 DemangledCall.
slice(DemangledCall.
find(
'(') + 1, DemangledCall.
find(
')'));
179 BuiltinArgs.
split(BuiltinArgumentTypes,
',', -1,
false);
184 if ((Builtin = SPIRV::lookupBuiltin(BuiltinName, Set)))
185 return std::make_unique<SPIRV::IncomingCall>(
186 BuiltinName, Builtin, ReturnRegister, ReturnType,
Arguments);
191 if (BuiltinArgumentTypes.
size() >= 1) {
192 char FirstArgumentType = BuiltinArgumentTypes[0][0];
197 switch (FirstArgumentType) {
200 if (Set == SPIRV::InstructionSet::OpenCL_std)
202 else if (Set == SPIRV::InstructionSet::GLSL_std_450)
210 if (Set == SPIRV::InstructionSet::OpenCL_std)
212 else if (Set == SPIRV::InstructionSet::GLSL_std_450)
219 if (Set == SPIRV::InstructionSet::OpenCL_std ||
220 Set == SPIRV::InstructionSet::GLSL_std_450)
226 if (!Prefix.empty() &&
227 (Builtin = SPIRV::lookupBuiltin(Prefix + BuiltinName, Set)))
228 return std::make_unique<SPIRV::IncomingCall>(
229 BuiltinName, Builtin, ReturnRegister, ReturnType,
Arguments);
236 switch (FirstArgumentType) {
257 if (!Suffix.empty() &&
258 (Builtin = SPIRV::lookupBuiltin(BuiltinName + Suffix, Set)))
259 return std::make_unique<SPIRV::IncomingCall>(
260 BuiltinName, Builtin, ReturnRegister, ReturnType,
Arguments);
275static std::tuple<Register, SPIRVType *>
281 if (ResultType->
getOpcode() == SPIRV::OpTypeVector) {
296 return std::make_tuple(ResultRegister, BoolType);
307 if (ReturnType->getOpcode() == SPIRV::OpTypeVector) {
316 return MIRBuilder.
buildSelect(ReturnRegister, SourceRegister, TrueConst,
327 if (!DestinationReg.isValid()) {
328 DestinationReg =
MRI->createVirtualRegister(&SPIRV::IDRegClass);
335 MIRBuilder.
buildLoad(DestinationReg, PtrRegister, PtrInfo,
Align());
336 return DestinationReg;
344 SPIRV::BuiltIn::BuiltIn BuiltinValue,
352 VariableType, MIRBuilder, SPIRV::StorageClass::Input);
358 SPIRV::StorageClass::Input,
nullptr,
true,
true,
359 SPIRV::LinkageType::Import, MIRBuilder,
false);
365 return LoadedRegister;
374 SPIRVGlobalRegistry *GR,
375 MachineIRBuilder &MIB,
376 MachineRegisterInfo &
MRI);
379static SPIRV::MemorySemantics::MemorySemantics
382 case std::memory_order::memory_order_relaxed:
383 return SPIRV::MemorySemantics::None;
384 case std::memory_order::memory_order_acquire:
385 return SPIRV::MemorySemantics::Acquire;
386 case std::memory_order::memory_order_release:
387 return SPIRV::MemorySemantics::Release;
388 case std::memory_order::memory_order_acq_rel:
389 return SPIRV::MemorySemantics::AcquireRelease;
390 case std::memory_order::memory_order_seq_cst:
391 return SPIRV::MemorySemantics::SequentiallyConsistent;
399 case SPIRV::CLMemoryScope::memory_scope_work_item:
400 return SPIRV::Scope::Invocation;
401 case SPIRV::CLMemoryScope::memory_scope_work_group:
402 return SPIRV::Scope::Workgroup;
403 case SPIRV::CLMemoryScope::memory_scope_device:
404 return SPIRV::Scope::Device;
405 case SPIRV::CLMemoryScope::memory_scope_all_svm_devices:
406 return SPIRV::Scope::CrossDevice;
407 case SPIRV::CLMemoryScope::memory_scope_sub_group:
408 return SPIRV::Scope::Subgroup;
421 SPIRV::Scope::Scope Scope,
425 if (CLScopeRegister.
isValid()) {
430 if (CLScope ==
static_cast<unsigned>(Scope)) {
431 MRI->setRegClass(CLScopeRegister, &SPIRV::IDRegClass);
432 return CLScopeRegister;
439 Register PtrRegister,
unsigned &Semantics,
442 if (SemanticsRegister.
isValid()) {
444 std::memory_order Order =
450 if (Order == Semantics) {
451 MRI->setRegClass(SemanticsRegister, &SPIRV::IDRegClass);
452 return SemanticsRegister;
461 assert(Call->Arguments.size() == 2 &&
462 "Need 2 arguments for atomic init translation");
466 .
addUse(Call->Arguments[0])
467 .
addUse(Call->Arguments[1]);
475 Register PtrRegister = Call->Arguments[0];
481 if (Call->Arguments.size() > 1) {
482 ScopeRegister = Call->Arguments[1];
488 if (Call->Arguments.size() > 2) {
490 MemSemanticsReg = Call->Arguments[2];
494 SPIRV::MemorySemantics::SequentiallyConsistent |
500 .
addDef(Call->ReturnRegister)
514 Register PtrRegister = Call->Arguments[0];
517 SPIRV::MemorySemantics::SequentiallyConsistent |
525 .
addUse(Call->Arguments[1]);
535 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
536 bool IsCmpxchg = Call->Builtin->Name.contains(
"cmpxchg");
539 Register ObjectPtr = Call->Arguments[0];
540 Register ExpectedArg = Call->Arguments[1];
541 Register Desired = Call->Arguments[2];
542 MRI->setRegClass(ObjectPtr, &SPIRV::IDRegClass);
543 MRI->setRegClass(ExpectedArg, &SPIRV::IDRegClass);
544 MRI->setRegClass(Desired, &SPIRV::IDRegClass);
546 LLT DesiredLLT =
MRI->getType(Desired);
549 SPIRV::OpTypePointer);
551 assert(IsCmpxchg ? ExpectedType == SPIRV::OpTypeInt
552 : ExpectedType == SPIRV::OpTypePointer);
557 auto StorageClass =
static_cast<SPIRV::StorageClass::StorageClass
>(
565 ? SPIRV::MemorySemantics::None
566 : SPIRV::MemorySemantics::SequentiallyConsistent | MemSemStorage;
569 ? SPIRV::MemorySemantics::None
570 : SPIRV::MemorySemantics::SequentiallyConsistent | MemSemStorage;
571 if (Call->Arguments.size() >= 4) {
572 assert(Call->Arguments.size() >= 5 &&
573 "Need 5+ args for explicit atomic cmpxchg");
580 if (MemOrdEq == MemSemEqual)
581 MemSemEqualReg = Call->Arguments[3];
582 if (MemOrdNeq == MemSemEqual)
583 MemSemUnequalReg = Call->Arguments[4];
584 MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass);
585 MRI->setRegClass(Call->Arguments[4], &SPIRV::IDRegClass);
589 if (!MemSemUnequalReg.
isValid())
593 auto Scope = IsCmpxchg ? SPIRV::Scope::Workgroup : SPIRV::Scope::Device;
594 if (Call->Arguments.size() >= 6) {
595 assert(Call->Arguments.size() == 6 &&
596 "Extra args for explicit atomic cmpxchg");
597 auto ClScope =
static_cast<SPIRV::CLMemoryScope
>(
600 if (ClScope ==
static_cast<unsigned>(Scope))
601 ScopeReg = Call->Arguments[5];
602 MRI->setRegClass(Call->Arguments[5], &SPIRV::IDRegClass);
612 Register Tmp = !IsCmpxchg ?
MRI->createGenericVirtualRegister(DesiredLLT)
613 : Call->ReturnRegister;
614 if (!
MRI->getRegClassOrNull(Tmp))
615 MRI->setRegClass(Tmp, &SPIRV::IDRegClass);
641 Call->Arguments.size() >= 4 ? Call->Arguments[3] :
Register();
643 assert(Call->Arguments.size() <= 4 &&
644 "Too many args for explicit atomic RMW");
645 ScopeRegister =
buildScopeReg(ScopeRegister, SPIRV::Scope::Workgroup,
646 MIRBuilder, GR,
MRI);
648 Register PtrRegister = Call->Arguments[0];
649 unsigned Semantics = SPIRV::MemorySemantics::None;
650 MRI->setRegClass(PtrRegister, &SPIRV::IDRegClass);
652 Call->Arguments.size() >= 3 ? Call->Arguments[2] :
Register();
654 Semantics, MIRBuilder, GR);
655 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
657 .
addDef(Call->ReturnRegister)
662 .
addUse(Call->Arguments[1]);
672 Register PtrRegister = Call->Arguments[0];
673 unsigned Semantics = SPIRV::MemorySemantics::SequentiallyConsistent;
675 Call->Arguments.size() >= 2 ? Call->Arguments[1] :
Register();
677 Semantics, MIRBuilder, GR);
679 assert((Opcode != SPIRV::OpAtomicFlagClear ||
680 (Semantics != SPIRV::MemorySemantics::Acquire &&
681 Semantics != SPIRV::MemorySemantics::AcquireRelease)) &&
682 "Invalid memory order argument!");
685 Call->Arguments.size() >= 3 ? Call->Arguments[2] :
Register();
690 if (Opcode == SPIRV::OpAtomicFlagTestAndSet)
691 MIB.
addDef(Call->ReturnRegister)
705 unsigned MemSemantics = SPIRV::MemorySemantics::None;
707 if (MemFlags & SPIRV::CLK_LOCAL_MEM_FENCE)
708 MemSemantics |= SPIRV::MemorySemantics::WorkgroupMemory;
710 if (MemFlags & SPIRV::CLK_GLOBAL_MEM_FENCE)
711 MemSemantics |= SPIRV::MemorySemantics::CrossWorkgroupMemory;
713 if (MemFlags & SPIRV::CLK_IMAGE_MEM_FENCE)
714 MemSemantics |= SPIRV::MemorySemantics::ImageMemory;
716 if (Opcode == SPIRV::OpMemoryBarrier) {
717 std::memory_order MemOrder =
721 MemSemantics |= SPIRV::MemorySemantics::SequentiallyConsistent;
725 if (MemFlags == MemSemantics) {
726 MemSemanticsReg = Call->Arguments[0];
727 MRI->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass);
732 SPIRV::Scope::Scope Scope = SPIRV::Scope::Workgroup;
733 SPIRV::Scope::Scope MemScope = Scope;
734 if (Call->Arguments.size() >= 2) {
736 ((Opcode != SPIRV::OpMemoryBarrier && Call->Arguments.size() == 2) ||
737 (Opcode == SPIRV::OpMemoryBarrier && Call->Arguments.size() == 3)) &&
738 "Extra args for explicitly scoped barrier");
739 Register ScopeArg = (Opcode == SPIRV::OpMemoryBarrier) ? Call->Arguments[2]
740 : Call->Arguments[1];
741 SPIRV::CLMemoryScope CLScope =
744 if (!(MemFlags & SPIRV::CLK_LOCAL_MEM_FENCE) ||
745 (Opcode == SPIRV::OpMemoryBarrier))
748 if (CLScope ==
static_cast<unsigned>(Scope)) {
749 ScopeReg = Call->Arguments[1];
750 MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass);
758 if (Opcode != SPIRV::OpMemoryBarrier)
760 MIB.
addUse(MemSemanticsReg);
766 case SPIRV::Dim::DIM_1D:
767 case SPIRV::Dim::DIM_Buffer:
769 case SPIRV::Dim::DIM_2D:
770 case SPIRV::Dim::DIM_Cube:
771 case SPIRV::Dim::DIM_Rect:
773 case SPIRV::Dim::DIM_3D:
786 return arrayed ? numComps + 1 : numComps;
799 SPIRV::lookupExtendedBuiltin(Builtin->
Name, Builtin->
Set)->Number;
804 .
addDef(Call->ReturnRegister)
809 for (
auto Argument : Call->Arguments)
820 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
824 std::tie(CompareRegister, RelationType) =
832 for (
auto Argument : Call->Arguments)
836 return buildSelectInst(MIRBuilder, Call->ReturnRegister, CompareRegister,
837 Call->ReturnType, GR);
845 SPIRV::lookupGroupBuiltin(Builtin->
Name);
849 Register ConstRegister = Call->Arguments[0];
852 assert(ArgInstruction->getOpcode() == TargetOpcode::G_CONSTANT &&
853 "Only constant bool value args are supported");
860 Register GroupResultRegister = Call->ReturnRegister;
861 SPIRVType *GroupResultType = Call->ReturnType;
865 const bool HasBoolReturnTy =
871 std::tie(GroupResultRegister, GroupResultType) =
874 auto Scope = Builtin->
Name.
startswith(
"sub_group") ? SPIRV::Scope::Subgroup
875 : SPIRV::Scope::Workgroup;
880 .
addDef(GroupResultRegister)
886 if (Call->Arguments.size() > 0) {
888 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
889 for (
unsigned i = 1; i < Call->Arguments.size(); i++) {
890 MIB.addUse(Call->Arguments[i]);
891 MRI->setRegClass(Call->Arguments[i], &SPIRV::IDRegClass);
898 Call->ReturnType, GR);
931 SPIRV::BuiltIn::BuiltIn BuiltinValue,
933 Register IndexRegister = Call->Arguments[0];
934 const unsigned ResultWidth = Call->ReturnType->getOperand(1).getImm();
942 Register ToTruncate = Call->ReturnRegister;
945 bool IsConstantIndex =
946 IndexInstruction->getOpcode() == TargetOpcode::G_CONSTANT;
951 Register DefaultReg = Call->ReturnRegister;
952 if (PointerSize != ResultWidth) {
953 DefaultReg =
MRI->createGenericVirtualRegister(
LLT::scalar(PointerSize));
954 MRI->setRegClass(DefaultReg, &SPIRV::IDRegClass);
957 ToTruncate = DefaultReg;
961 MIRBuilder.
buildCopy(DefaultReg, NewRegister);
969 Register Extracted = Call->ReturnRegister;
970 if (!IsConstantIndex || PointerSize != ResultWidth) {
971 Extracted =
MRI->createGenericVirtualRegister(
LLT::scalar(PointerSize));
972 MRI->setRegClass(Extracted, &SPIRV::IDRegClass);
982 if (!IsConstantIndex) {
991 MRI->setRegClass(CompareRegister, &SPIRV::IDRegClass);
1004 Register SelectionResult = Call->ReturnRegister;
1005 if (PointerSize != ResultWidth) {
1008 MRI->setRegClass(SelectionResult, &SPIRV::IDRegClass);
1010 MIRBuilder.
getMF());
1013 MIRBuilder.
buildSelect(SelectionResult, CompareRegister, Extracted,
1015 ToTruncate = SelectionResult;
1017 ToTruncate = Extracted;
1021 if (PointerSize != ResultWidth)
1031 SPIRV::BuiltIn::BuiltIn
Value =
1032 SPIRV::lookupGetBuiltin(Builtin->
Name, Builtin->
Set)->
Value;
1034 if (
Value == SPIRV::BuiltIn::GlobalInvocationId)
1040 if (Call->ReturnType->getOpcode() == SPIRV::OpTypeVector)
1047 LLType, Call->ReturnRegister);
1056 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1059 case SPIRV::OpStore:
1061 case SPIRV::OpAtomicLoad:
1063 case SPIRV::OpAtomicStore:
1065 case SPIRV::OpAtomicCompareExchange:
1066 case SPIRV::OpAtomicCompareExchangeWeak:
1068 case SPIRV::OpAtomicIAdd:
1069 case SPIRV::OpAtomicISub:
1070 case SPIRV::OpAtomicOr:
1071 case SPIRV::OpAtomicXor:
1072 case SPIRV::OpAtomicAnd:
1073 case SPIRV::OpAtomicExchange:
1075 case SPIRV::OpMemoryBarrier:
1077 case SPIRV::OpAtomicFlagTestAndSet:
1078 case SPIRV::OpAtomicFlagClear:
1091 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1100 bool IsVec = Opcode == SPIRV::OpTypeVector;
1102 MIRBuilder.
buildInstr(IsVec ? SPIRV::OpDot : SPIRV::OpFMulS)
1103 .
addDef(Call->ReturnRegister)
1105 .
addUse(Call->Arguments[0])
1106 .
addUse(Call->Arguments[1]);
1114 SPIRV::BuiltIn::BuiltIn
Value =
1115 SPIRV::lookupGetBuiltin(Call->Builtin->Name, Call->Builtin->Set)->
Value;
1116 uint64_t IsDefault = (
Value == SPIRV::BuiltIn::GlobalSize ||
1117 Value == SPIRV::BuiltIn::WorkgroupSize ||
1118 Value == SPIRV::BuiltIn::EnqueuedWorkgroupSize);
1128 SPIRV::lookupImageQueryBuiltin(Builtin->
Name, Builtin->
Set)->Component;
1133 unsigned NumExpectedRetComponents =
RetTy->getOpcode() == SPIRV::OpTypeVector
1134 ?
RetTy->getOperand(2).getImm()
1139 Register QueryResult = Call->ReturnRegister;
1140 SPIRVType *QueryResultType = Call->ReturnType;
1141 if (NumExpectedRetComponents != NumActualRetComponents) {
1147 IntTy, NumActualRetComponents, MIRBuilder);
1152 IsDimBuf ? SPIRV::OpImageQuerySize : SPIRV::OpImageQuerySizeLod;
1157 .
addUse(Call->Arguments[0]);
1160 if (NumExpectedRetComponents == NumActualRetComponents)
1162 if (NumExpectedRetComponents == 1) {
1164 unsigned ExtractedComposite =
1165 Component == 3 ? NumActualRetComponents - 1 : Component;
1166 assert(ExtractedComposite < NumActualRetComponents &&
1167 "Invalid composite index!");
1168 MIRBuilder.
buildInstr(SPIRV::OpCompositeExtract)
1169 .
addDef(Call->ReturnRegister)
1172 .
addImm(ExtractedComposite);
1175 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpVectorShuffle)
1176 .
addDef(Call->ReturnRegister)
1180 for (
unsigned i = 0; i < NumExpectedRetComponents; ++i)
1181 MIB.
addImm(i < NumActualRetComponents ? i : 0xffffffff);
1189 assert(Call->ReturnType->getOpcode() == SPIRV::OpTypeInt &&
1190 "Image samples query result must be of int type!");
1195 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1197 Register Image = Call->Arguments[0];
1199 SPIRV::Dim::Dim ImageDimensionality =
static_cast<SPIRV::Dim::Dim
>(
1203 case SPIRV::OpImageQuerySamples:
1204 assert(ImageDimensionality == SPIRV::Dim::DIM_2D &&
1205 "Image must be of 2D dimensionality");
1207 case SPIRV::OpImageQueryLevels:
1208 assert((ImageDimensionality == SPIRV::Dim::DIM_1D ||
1209 ImageDimensionality == SPIRV::Dim::DIM_2D ||
1210 ImageDimensionality == SPIRV::Dim::DIM_3D ||
1211 ImageDimensionality == SPIRV::Dim::DIM_Cube) &&
1212 "Image must be of 1D/2D/3D/Cube dimensionality");
1217 .
addDef(Call->ReturnRegister)
1224static SPIRV::SamplerAddressingMode::SamplerAddressingMode
1226 switch (Bitmask & SPIRV::CLK_ADDRESS_MODE_MASK) {
1227 case SPIRV::CLK_ADDRESS_CLAMP:
1228 return SPIRV::SamplerAddressingMode::Clamp;
1229 case SPIRV::CLK_ADDRESS_CLAMP_TO_EDGE:
1230 return SPIRV::SamplerAddressingMode::ClampToEdge;
1231 case SPIRV::CLK_ADDRESS_REPEAT:
1232 return SPIRV::SamplerAddressingMode::Repeat;
1233 case SPIRV::CLK_ADDRESS_MIRRORED_REPEAT:
1234 return SPIRV::SamplerAddressingMode::RepeatMirrored;
1235 case SPIRV::CLK_ADDRESS_NONE:
1236 return SPIRV::SamplerAddressingMode::None;
1243 return (Bitmask & SPIRV::CLK_NORMALIZED_COORDS_TRUE) ? 1 : 0;
1246static SPIRV::SamplerFilterMode::SamplerFilterMode
1248 if (Bitmask & SPIRV::CLK_FILTER_LINEAR)
1249 return SPIRV::SamplerFilterMode::Linear;
1250 if (Bitmask & SPIRV::CLK_FILTER_NEAREST)
1251 return SPIRV::SamplerFilterMode::Nearest;
1252 return SPIRV::SamplerFilterMode::Nearest;
1259 Register Image = Call->Arguments[0];
1261 MRI->setRegClass(Image, &SPIRV::IDRegClass);
1262 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
1265 if (HasOclSampler || HasMsaa)
1266 MRI->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
1267 if (HasOclSampler) {
1268 Register Sampler = Call->Arguments[1];
1282 Register SampledImage =
MRI->createVirtualRegister(&SPIRV::IDRegClass);
1293 bool NeedsExtraction =
false;
1294 if (TempType->
getOpcode() != SPIRV::OpTypeVector) {
1297 NeedsExtraction =
true;
1300 Register TempRegister =
MRI->createGenericVirtualRegister(LLType);
1301 MRI->setRegClass(TempRegister, &SPIRV::IDRegClass);
1304 MIRBuilder.
buildInstr(SPIRV::OpImageSampleExplicitLod)
1305 .
addDef(NeedsExtraction ? TempRegister : Call->ReturnRegister)
1308 .
addUse(Call->Arguments[2])
1309 .
addImm(SPIRV::ImageOperand::Lod)
1312 if (NeedsExtraction)
1313 MIRBuilder.
buildInstr(SPIRV::OpCompositeExtract)
1314 .
addDef(Call->ReturnRegister)
1318 }
else if (HasMsaa) {
1320 .
addDef(Call->ReturnRegister)
1323 .
addUse(Call->Arguments[1])
1324 .
addImm(SPIRV::ImageOperand::Sample)
1325 .
addUse(Call->Arguments[2]);
1328 .
addDef(Call->ReturnRegister)
1331 .
addUse(Call->Arguments[1]);
1343 .
addUse(Call->Arguments[0])
1344 .
addUse(Call->Arguments[1])
1345 .
addUse(Call->Arguments[2]);
1354 if (Call->Builtin->Name.contains_insensitive(
1355 "__translate_sampler_initializer")) {
1362 return Sampler.isValid();
1363 }
else if (Call->Builtin->Name.contains_insensitive(
"__spirv_SampledImage")) {
1365 Register Image = Call->Arguments[0];
1370 Call->ReturnRegister.isValid()
1371 ? Call->ReturnRegister
1372 :
MRI->createVirtualRegister(&SPIRV::IDRegClass);
1377 .
addUse(Call->Arguments[1]);
1379 }
else if (Call->Builtin->Name.contains_insensitive(
1380 "__spirv_ImageSampleExplicitLod")) {
1382 std::string ReturnType = DemangledCall.
str();
1383 if (DemangledCall.
contains(
"_R")) {
1384 ReturnType = ReturnType.substr(ReturnType.find(
"_R") + 2);
1385 ReturnType = ReturnType.substr(0, ReturnType.find(
'('));
1388 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1389 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
1390 MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass);
1392 MIRBuilder.
buildInstr(SPIRV::OpImageSampleExplicitLod)
1393 .
addDef(Call->ReturnRegister)
1395 .
addUse(Call->Arguments[0])
1396 .
addUse(Call->Arguments[1])
1397 .
addImm(SPIRV::ImageOperand::Lod)
1398 .
addUse(Call->Arguments[3]);
1406 MIRBuilder.
buildSelect(Call->ReturnRegister, Call->Arguments[0],
1407 Call->Arguments[1], Call->Arguments[2]);
1417 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1421 case SPIRV::OpSpecConstant: {
1425 buildOpDecorate(Call->ReturnRegister, MIRBuilder, SPIRV::Decoration::SpecId,
1428 Register ConstRegister = Call->Arguments[1];
1431 (Const->getOpcode() == TargetOpcode::G_CONSTANT ||
1432 Const->getOpcode() == TargetOpcode::G_FCONSTANT) &&
1433 "Argument should be either an int or floating-point constant");
1436 if (Call->ReturnType->getOpcode() == SPIRV::OpTypeBool) {
1437 assert(ConstOperand.
isCImm() &&
"Int constant operand is expected");
1439 ? SPIRV::OpSpecConstantTrue
1440 : SPIRV::OpSpecConstantFalse;
1443 .
addDef(Call->ReturnRegister)
1446 if (Call->ReturnType->getOpcode() != SPIRV::OpTypeBool) {
1447 if (Const->getOpcode() == TargetOpcode::G_CONSTANT)
1454 case SPIRV::OpSpecConstantComposite: {
1456 .
addDef(Call->ReturnRegister)
1458 for (
unsigned i = 0; i < Call->Arguments.size(); i++)
1459 MIB.
addUse(Call->Arguments[i]);
1471 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1478 Register TmpReg =
MRI->createVirtualRegister(&SPIRV::IDRegClass);
1482 unsigned NumArgs = Call->Arguments.size();
1484 Register GlobalWorkSize = Call->Arguments[NumArgs < 4 ? 1 : 2];
1485 MRI->setRegClass(GlobalWorkSize, &SPIRV::IDRegClass);
1487 NumArgs == 2 ?
Register(0) : Call->Arguments[NumArgs < 4 ? 2 : 3];
1489 MRI->setRegClass(LocalWorkSize, &SPIRV::IDRegClass);
1490 Register GlobalWorkOffset = NumArgs <= 3 ?
Register(0) : Call->Arguments[1];
1491 if (GlobalWorkOffset.
isValid())
1492 MRI->setRegClass(GlobalWorkOffset, &SPIRV::IDRegClass);
1496 if (SpvTy->
getOpcode() == SPIRV::OpTypePointer) {
1501 if (!
MRI->getRegClassOrNull(GWSPtr))
1502 MRI->setRegClass(GWSPtr, &SPIRV::IDRegClass);
1504 unsigned Size = Call->Builtin->Name.equals(
"ndrange_3D") ? 3 : 2;
1509 GlobalWorkSize =
MRI->createVirtualRegister(&SPIRV::IDRegClass);
1520 LocalWorkSize = Const;
1521 if (!GlobalWorkOffset.
isValid())
1522 GlobalWorkOffset = Const;
1530 .
addUse(GlobalWorkOffset);
1532 .
addUse(Call->Arguments[0])
1544 assert(
MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST &&
1545 MI->getOperand(1).isReg());
1546 Register BitcastReg =
MI->getOperand(1).getReg();
1574 Register ValueReg =
MI->getOperand(0).getReg();
1579 assert(Ty &&
"Type is expected");
1591 if (
MI->getOpcode() == TargetOpcode::G_GLOBAL_VALUE)
1594 "Blocks in OpenCL C must be traceable to allocation site");
1619 bool HasEvents = Call->Builtin->Name.find(
"events") !=
StringRef::npos;
1627 const unsigned LocalSizeArrayIdx = HasEvents ? 9 : 6;
1628 Register GepReg = Call->Arguments[LocalSizeArrayIdx];
1635 assert(LocalSizeTy &&
"Local size type is expected");
1637 cast<ArrayType>(LocalSizeTy)->getNumElements();
1641 Int32Ty, MIRBuilder, SPIRV::StorageClass::Function);
1642 for (
unsigned I = 0;
I < LocalSizeNum; ++
I) {
1644 MRI->setType(
Reg, LLType);
1658 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpEnqueueKernel)
1659 .
addDef(Call->ReturnRegister)
1663 const unsigned BlockFIdx = HasEvents ? 6 : 3;
1664 for (
unsigned i = 0; i < BlockFIdx; i++)
1665 MIB.addUse(Call->Arguments[i]);
1672 MIB.addUse(NullPtr);
1673 MIB.addUse(NullPtr);
1681 Register BlockLiteralReg = Call->Arguments[BlockFIdx + 1];
1683 MIB.addUse(BlockLiteralReg);
1693 for (
unsigned i = 0; i < LocalSizes.
size(); i++)
1694 MIB.addUse(LocalSizes[i]);
1704 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1707 case SPIRV::OpRetainEvent:
1708 case SPIRV::OpReleaseEvent:
1711 case SPIRV::OpCreateUserEvent:
1712 case SPIRV::OpGetDefaultQueue:
1714 .
addDef(Call->ReturnRegister)
1716 case SPIRV::OpIsValidEvent:
1719 .
addDef(Call->ReturnRegister)
1721 .
addUse(Call->Arguments[0]);
1722 case SPIRV::OpSetUserEventStatus:
1726 .
addUse(Call->Arguments[0])
1727 .
addUse(Call->Arguments[1]);
1728 case SPIRV::OpCaptureEventProfilingInfo:
1733 .
addUse(Call->Arguments[0])
1734 .
addUse(Call->Arguments[1])
1735 .
addUse(Call->Arguments[2]);
1736 case SPIRV::OpBuildNDRange:
1738 case SPIRV::OpEnqueueKernel:
1751 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1755 case SPIRV::OpGroupAsyncCopy:
1757 .
addDef(Call->ReturnRegister)
1760 .
addUse(Call->Arguments[0])
1761 .
addUse(Call->Arguments[1])
1762 .
addUse(Call->Arguments[2])
1764 .
addUse(Call->Arguments[3]);
1765 case SPIRV::OpGroupWaitEvents:
1768 .
addUse(Call->Arguments[0])
1769 .
addUse(Call->Arguments[1]);
1781 SPIRV::lookupConvertBuiltin(Call->Builtin->Name, Call->Builtin->Set);
1785 SPIRV::Decoration::SaturatedConversion, {});
1788 SPIRV::Decoration::FPRoundingMode,
1789 {(unsigned)Builtin->RoundingMode});
1791 unsigned Opcode = SPIRV::OpNop;
1798 : SPIRV::OpSatConvertSToU;
1801 : SPIRV::OpSConvert;
1803 SPIRV::OpTypeFloat)) {
1805 bool IsSourceSigned =
1807 Opcode = IsSourceSigned ? SPIRV::OpConvertSToF : SPIRV::OpConvertUToF;
1810 SPIRV::OpTypeFloat)) {
1815 : SPIRV::OpConvertFToU;
1817 SPIRV::OpTypeFloat))
1819 Opcode = SPIRV::OpFConvert;
1822 assert(Opcode != SPIRV::OpNop &&
1823 "Conversion between the types not implemented!");
1826 .
addDef(Call->ReturnRegister)
1828 .
addUse(Call->Arguments[0]);
1837 SPIRV::lookupVectorLoadStoreBuiltin(Call->Builtin->Name,
1838 Call->Builtin->Set);
1842 .
addDef(Call->ReturnRegister)
1844 .
addImm(
static_cast<uint32_t>(SPIRV::InstructionSet::OpenCL_std))
1846 for (
auto Argument : Call->Arguments)
1862 SPIRV::lookupNativeBuiltin(Builtin->
Name, Builtin->
Set)->Opcode;
1863 bool IsLoad = Opcode == SPIRV::OpLoad;
1867 MIB.
addDef(Call->ReturnRegister);
1871 MIB.
addUse(Call->Arguments[0]);
1873 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1876 MIB.addUse(Call->Arguments[1]);
1877 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
1880 unsigned NumArgs = Call->Arguments.size();
1881 if ((IsLoad && NumArgs >= 2) || NumArgs >= 3) {
1883 MRI->setRegClass(Call->Arguments[IsLoad ? 1 : 2], &SPIRV::IDRegClass);
1885 if ((IsLoad && NumArgs >= 3) || NumArgs >= 4) {
1887 MRI->setRegClass(Call->Arguments[IsLoad ? 2 : 3], &SPIRV::IDRegClass);
1896 SPIRV::InstructionSet::InstructionSet Set,
1901 LLVM_DEBUG(
dbgs() <<
"Lowering builtin call: " << DemangledCall <<
"\n");
1906 if (OrigRetTy && !OrigRetTy->
isVoidTy()) {
1910 }
else if (OrigRetTy && OrigRetTy->
isVoidTy()) {
1917 std::unique_ptr<const IncomingCall> Call =
1918 lookupBuiltin(DemangledCall, Set, ReturnRegister, ReturnType, Args);
1922 return std::nullopt;
1926 assert(Args.size() >= Call->Builtin->MinNumArgs &&
1927 "Too few arguments to generate the builtin");
1928 if (Call->Builtin->MaxNumArgs && Args.size() > Call->Builtin->MaxNumArgs)
1929 LLVM_DEBUG(
dbgs() <<
"More arguments provided than required!\n");
1932 switch (Call->Builtin->Group) {
1933 case SPIRV::Extended:
1935 case SPIRV::Relational:
1939 case SPIRV::Variable:
1943 case SPIRV::Barrier:
1947 case SPIRV::GetQuery:
1949 case SPIRV::ImageSizeQuery:
1951 case SPIRV::ImageMiscQuery:
1953 case SPIRV::ReadImage:
1955 case SPIRV::WriteImage:
1957 case SPIRV::SampleImage:
1961 case SPIRV::SpecConstant:
1963 case SPIRV::Enqueue:
1965 case SPIRV::AsyncCopy:
1967 case SPIRV::Convert:
1969 case SPIRV::VectorLoadStore:
1971 case SPIRV::LoadStore:
1982#define GET_BuiltinTypes_DECL
1983#define GET_BuiltinTypes_IMPL
1990#define GET_OpenCLTypes_DECL
1991#define GET_OpenCLTypes_IMPL
1993#include "SPIRVGenTables.inc"
2001 if (
Name.startswith(
"void"))
2003 else if (
Name.startswith(
"int") ||
Name.startswith(
"uint"))
2005 else if (
Name.startswith(
"float"))
2007 else if (
Name.startswith(
"half"))
2015 "Not a SPIR-V/OpenCL special opaque type!");
2017 "This already is SPIR-V/OpenCL TargetExtType!");
2024 if (NameWithParameters.
startswith(
"opencl.")) {
2026 SPIRV::lookupOpenCLType(NameWithParameters);
2029 NameWithParameters);
2037 "Unknown builtin opaque type!");
2041 if (NameWithParameters.
find(
'_') == std::string::npos)
2045 unsigned BaseNameLength = NameWithParameters.
find(
'_') - 1;
2046 SplitString(NameWithParameters.
substr(BaseNameLength + 1), Parameters,
"_");
2049 bool HasTypeParameter = !
isDigit(Parameters[0][0]);
2050 if (HasTypeParameter)
2054 for (
unsigned i = HasTypeParameter ? 1 : 0; i < Parameters.
size(); i++) {
2055 unsigned IntParameter = 0;
2056 bool ValidLiteral = !Parameters[i].getAsInteger(10, IntParameter);
2058 "Invalid format of SPIR-V builtin parameter literal!");
2062 NameWithParameters.
substr(0, BaseNameLength),
2063 TypeParameters, IntParameters);
2074 unsigned Opcode = TypeRecord->
Opcode;
2089 "Invalid number of parameters for SPIR-V pipe builtin!");
2092 SPIRV::AccessQualifier::AccessQualifier(
2098 const SPIRV::AccessQualifier::AccessQualifier Qualifier,
2101 "SPIR-V image builtin type must have sampled type parameter!");
2105 "Invalid number of parameters for SPIR-V image builtin!");
2108 MIRBuilder, SampledType,
2113 Qualifier == SPIRV::AccessQualifier::WriteOnly
2114 ? SPIRV::AccessQualifier::WriteOnly
2115 : SPIRV::AccessQualifier::AccessQualifier(
2123 OpaqueType, SPIRV::AccessQualifier::ReadOnly, MIRBuilder, GR);
2130 SPIRV::AccessQualifier::AccessQualifier AccessQual,
2160 switch (TypeRecord->
Opcode) {
2161 case SPIRV::OpTypeImage:
2164 case SPIRV::OpTypePipe:
2167 case SPIRV::OpTypeDeviceEvent:
2170 case SPIRV::OpTypeSampler:
2173 case SPIRV::OpTypeSampledImage:
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
AMDGPU Lower Kernel Arguments
static bool isDigit(const char C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
APInt bitcastToAPInt() const
static APFloat getZero(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Zero.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
uint64_t getZExtValue() const
Get zero extended value.
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
static ArrayType * get(Type *ElementType, uint64_t NumElements)
This static method is the primary way to construct an ArrayType.
@ ICMP_ULT
unsigned less than
const APFloat & getValueAPF() const
const APInt & getValue() const
Return the constant as an APInt value reference.
A parsed version of the target data layout string in and methods for querying it.
Tagged union holding either a T or a Error.
Class to represent fixed width SIMD vectors.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
This is an important class for using LLVM in a threaded context.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
const DataLayout & getDataLayout() const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
const ConstantInt * getCImm() const
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const MDNode * getMetadata() const
Register getReg() const
getReg - Returns the register number.
const ConstantFP * getFPImm() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Wrapper class representing virtual and physical registers.
SPIRVType * getOrCreateOpTypePipe(MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccQual)
Register getOrCreateConsIntVector(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII)
SPIRVType * getOrCreateSPIRVTypeByName(StringRef TypeStr, MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder)
const Type * getTypeForSPIRVType(const SPIRVType *Ty) const
Register buildConstantSampler(Register Res, unsigned AddrMode, unsigned Param, unsigned FilerMode, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType)
SPIRVType * getOrCreateOpTypeImage(MachineIRBuilder &MIRBuilder, SPIRVType *SampledType, SPIRV::Dim::Dim Dim, uint32_t Depth, uint32_t Arrayed, uint32_t Multisampled, uint32_t Sampled, SPIRV::ImageFormat::ImageFormat ImageFormat, SPIRV::AccessQualifier::AccessQualifier AccQual)
SPIRVType * getSPIRVTypeForVReg(Register VReg) const
unsigned getPointerSize() const
SPIRVType * getOrCreateOpTypeByOpcode(const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode)
Register buildConstantFP(APFloat Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr)
Register getSPIRVTypeID(const SPIRVType *SpirvType) const
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, MachineFunction &MF)
bool isScalarOfType(Register VReg, unsigned TypeOpcode) const
Register buildGlobalVariable(Register Reg, SPIRVType *BaseType, StringRef Name, const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage, const MachineInstr *Init, bool IsConst, bool HasLinkageTy, SPIRV::LinkageType::LinkageType LinkageType, MachineIRBuilder &MIRBuilder, bool IsInstSelector)
SPIRVType * getOrCreateOpTypeSampledImage(SPIRVType *ImageType, MachineIRBuilder &MIRBuilder)
SPIRVType * assignTypeToVReg(const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
bool isScalarOrVectorOfType(Register VReg, unsigned TypeOpcode) const
SPIRVType * getOrCreateOpTypeDeviceEvent(MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVPointerType(SPIRVType *BaseType, MachineIRBuilder &MIRBuilder, SPIRV::StorageClass::StorageClass SClass=SPIRV::StorageClass::Function)
SPIRVType * getOrCreateSPIRVVectorType(SPIRVType *BaseType, unsigned NumElements, MachineIRBuilder &MIRBuilder)
SPIRVType * getOrCreateSPIRVIntegerType(unsigned BitWidth, MachineIRBuilder &MIRBuilder)
Register getOrCreateConsIntArray(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII)
SPIRV::StorageClass::StorageClass getPointerStorageClass(Register VReg) const
SPIRVType * getOrCreateOpTypeSampler(MachineIRBuilder &MIRBuilder)
Register buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType=nullptr, bool EmitIR=true)
Register getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder, SPIRVType *SpvType)
unsigned getScalarOrVectorBitWidth(const SPIRVType *Type) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
std::string str() const
str - Get the contents as an std::string.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
bool contains_insensitive(StringRef Other) const
Return true if the given string is a substring of *this, and false otherwise.
StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
bool contains(StringRef Other) const
Return true if the given string is a substring of *this, and false otherwise.
bool startswith(StringRef Prefix) const
size_t find_first_of(char C, size_t From=0) const
Find the first character in the string that is C, or npos if not found.
size_t find(char C, size_t From=0) const
Search for the first character C in the string.
static constexpr size_t npos
Class to represent struct types.
static StructType * getTypeByName(LLVMContext &C, StringRef Name)
Return the type with the specified name, or null if there is none by that name.
static StructType * create(LLVMContext &Context, StringRef Name)
This creates an identified struct.
Class to represent target extensions types, which are generally unintrospectable from target-independ...
unsigned getNumIntParameters() const
static TargetExtType * get(LLVMContext &Context, StringRef Name, ArrayRef< Type * > Types=std::nullopt, ArrayRef< unsigned > Ints=std::nullopt)
Return a target extension type having the specified name and optional type and integer parameters.
Type * getTypeParameter(unsigned i) const
unsigned getNumTypeParameters() const
unsigned getIntParameter(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed.
static Type * getHalfTy(LLVMContext &C)
StringRef getStructName() const
static Type * getVoidTy(LLVMContext &C)
bool isTargetExtTy() const
Return true if this is a target extension type.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
static IntegerType * getInt32Ty(LLVMContext &C)
static Type * getFloatTy(LLVMContext &C)
bool isVoidTy() const
Return true if this is 'void'.
LLVM Value Representation.
Value(Type *Ty, unsigned scid)
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
LLVMTypeRef LLVMVectorType(LLVMTypeRef ElementType, unsigned ElementCount)
Create a vector type that contains a defined type and has a specific number of elements.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::optional< bool > lowerBuiltin(const StringRef DemangledCall, SPIRV::InstructionSet::InstructionSet Set, MachineIRBuilder &MIRBuilder, const Register OrigRet, const Type *OrigRetTy, const SmallVectorImpl< Register > &Args, SPIRVGlobalRegistry *GR)
SPIRVType * lowerBuiltinType(const Type *OpaqueType, SPIRV::AccessQualifier::AccessQualifier AccessQual, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
This is an optimization pass for GlobalISel generic memory operations.
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC)
static bool buildAtomicCompareExchangeInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building an atomic compare-exchange instruction.
static bool generateGetQueryInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateLoadStoreInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static Register buildConstantIntReg(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR, unsigned BitWidth=32)
static bool buildAtomicFlagInst(const SPIRV::IncomingCall *Call, unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building atomic flag instructions (e.g.
static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static Register buildBuiltinVariableLoad(MachineIRBuilder &MIRBuilder, SPIRVType *VariableType, SPIRVGlobalRegistry *GR, SPIRV::BuiltIn::BuiltIn BuiltinValue, LLT LLType, Register Reg=Register(0))
Helper function for building a load instruction for loading a builtin global variable of BuiltinValue...
static SPIRV::SamplerFilterMode::SamplerFilterMode getSamplerFilterModeFromBitmask(unsigned Bitmask)
static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building an atomic store instruction.
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)
static const Type * getBlockStructType(Register ParamReg, MachineRegisterInfo *MRI)
static bool generateGroupInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static unsigned getNumComponentsForDim(SPIRV::Dim::Dim dim)
Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy, SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB, MachineRegisterInfo &MRI)
Helper external function for inserting ASSIGN_TYPE instuction between Reg and its definition,...
static Register buildScopeReg(Register CLScopeRegister, SPIRV::Scope::Scope Scope, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR, MachineRegisterInfo *MRI)
static std::tuple< Register, SPIRVType * > buildBoolRegister(MachineIRBuilder &MIRBuilder, const SPIRVType *ResultType, SPIRVGlobalRegistry *GR)
Helper function building either a resulting scalar or vector bool register depending on the expected ...
static unsigned getNumSizeComponents(SPIRVType *imgType)
Helper function for obtaining the number of size components.
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI)
static SPIRVType * getSampledImageType(const TargetExtType *OpaqueType, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
SPIRV::MemorySemantics::MemorySemantics getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC)
static bool generateDotOrFMulInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateSampleImageInst(const StringRef DemangledCall, const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateBarrierInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRVType * getImageType(const TargetExtType *ExtensionType, const SPIRV::AccessQualifier::AccessQualifier Qualifier, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building barriers, i.e., memory/control ordering operations.
static bool generateAsyncCopy(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRV::Scope::Scope getSPIRVScope(SPIRV::CLMemoryScope ClScope)
static SPIRVType * getSamplerType(MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
bool isSpecialOpaqueType(const Type *Ty)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static Register buildLoadInst(SPIRVType *BaseType, Register PtrRegister, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR, LLT LowLevelType, Register DestinationReg=Register(0))
Helper function for building a load instruction loading into the DestinationReg.
static bool generateEnqueueInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
static bool buildSelectInst(MachineIRBuilder &MIRBuilder, Register ReturnRegister, Register SourceRegister, const SPIRVType *ReturnType, SPIRVGlobalRegistry *GR)
Helper function for building either a vector or scalar select instruction depending on the expected R...
static const Type * getMachineInstrType(MachineInstr *MI)
bool isSpvIntrinsic(MachineInstr &MI, Intrinsic::ID IntrinsicID)
static SPIRV::SamplerAddressingMode::SamplerAddressingMode getSamplerAddressingModeFromBitmask(unsigned Bitmask)
static bool generateAtomicInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateConvertInst(const StringRef DemangledCall, const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static Register buildMemSemanticsReg(Register SemanticsRegister, Register PtrRegister, unsigned &Semantics, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static unsigned getConstFromIntrinsic(Register Reg, MachineRegisterInfo *MRI)
static bool generateImageMiscQueryInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateSelectInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder)
static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building an atomic load instruction.
static bool generateSpecConstantInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRVType * getOrCreateSPIRVDeviceEventPointer(MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool generateVectorLoadStoreInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR, SPIRV::BuiltIn::BuiltIn BuiltinValue, uint64_t DefaultValue)
const Type * getTypedPtrEltType(const Type *Ty)
static std::unique_ptr< const SPIRV::IncomingCall > lookupBuiltin(StringRef DemangledCall, SPIRV::InstructionSet::InstructionSet Set, Register ReturnRegister, const SPIRVType *ReturnType, const SmallVectorImpl< Register > &Arguments)
Looks up the demangled builtin call in the SPIRVBuiltins.td records using the provided DemangledCall ...
MachineInstr * getDefInstrMaybeConstant(Register &ConstReg, const MachineRegisterInfo *MRI)
constexpr unsigned BitWidth
const MachineInstr SPIRVType
static bool generateReadImageInst(const StringRef DemangledCall, const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Type * getMDOperandAsType(const MDNode *N, unsigned I)
static const TargetExtType * parseToTargetExtType(const Type *OpaqueType, MachineIRBuilder &MIRBuilder)
static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
Helper function for building an atomic load instruction.
static SPIRV::MemorySemantics::MemorySemantics getSPIRVMemSemantics(std::memory_order MemOrder)
static bool generateRelationalInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool buildAtomicInitInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder)
Helper function for translating atomic init to OpStore.
static bool generateWriteImageInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRVType * getPipeType(const TargetExtType *ExtensionType, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static Type * parseTypeString(const StringRef Name, LLVMContext &Context)
static bool generateExtInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static bool buildNDRange(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static SPIRVType * getNonParameterizedType(const TargetExtType *ExtensionType, const SPIRV::BuiltinType *TypeRecord, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static MachineInstr * getBlockStructInstr(Register ParamReg, MachineRegisterInfo *MRI)
static unsigned getSamplerParamFromBitmask(unsigned Bitmask)
std::string getLinkStringForBuiltIn(SPIRV::BuiltIn::BuiltIn BuiltInValue)
static bool generateBuiltinVar(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR)
static const fltSemantics & IEEEsingle() LLVM_READNONE
This struct is a compact representation of a valid (non-zero power of two) alignment.
This class contains a discriminated union of information about pointers in memory operands,...
FPRoundingMode::FPRoundingMode RoundingMode
InstructionSet::InstructionSet Set
InstructionSet::InstructionSet Set
InstructionSet::InstructionSet Set
InstructionSet::InstructionSet Set
const SmallVectorImpl< Register > & Arguments
const std::string BuiltinName
const SPIRVType * ReturnType
const Register ReturnRegister
const DemangledBuiltin * Builtin
IncomingCall(const std::string BuiltinName, const DemangledBuiltin *Builtin, const Register ReturnRegister, const SPIRVType *ReturnType, const SmallVectorImpl< Register > &Arguments)
InstructionSet::InstructionSet Set
StringRef SpirvTypeLiteral
InstructionSet::InstructionSet Set
FPRoundingMode::FPRoundingMode RoundingMode