LLVM  15.0.0git
SPIRVPreLegalizer.cpp
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1 //===-- SPIRVPreLegalizer.cpp - prepare IR for legalization -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The pass prepares IR for legalization: it assigns SPIR-V types to registers
10 // and removes intrinsics which holded these types during IR translation.
11 // Also it processes constants and registers them in GR to avoid duplication.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "SPIRV.h"
16 #include "SPIRVGlobalRegistry.h"
17 #include "SPIRVSubtarget.h"
18 #include "SPIRVUtils.h"
21 #include "llvm/IR/Attributes.h"
22 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/IntrinsicsSPIRV.h"
26 
27 #define DEBUG_TYPE "spirv-prelegalizer"
28 
29 using namespace llvm;
30 
31 namespace {
32 class SPIRVPreLegalizer : public MachineFunctionPass {
33 public:
34  static char ID;
35  SPIRVPreLegalizer() : MachineFunctionPass(ID) {
37  }
38  bool runOnMachineFunction(MachineFunction &MF) override;
39 };
40 } // namespace
41 
42 static bool isSpvIntrinsic(MachineInstr &MI, Intrinsic::ID IntrinsicID) {
43  if (MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS &&
44  MI.getIntrinsicID() == IntrinsicID)
45  return true;
46  return false;
47 }
48 
52  const unsigned AssignNameOperandShift = 2;
53  for (MachineBasicBlock &MBB : MF) {
54  for (MachineInstr &MI : MBB) {
55  if (!isSpvIntrinsic(MI, Intrinsic::spv_assign_name))
56  continue;
57  unsigned NumOp = MI.getNumExplicitDefs() + AssignNameOperandShift;
58  while (MI.getOperand(NumOp).isReg()) {
59  MachineOperand &MOp = MI.getOperand(NumOp);
60  MachineInstr *ConstMI = MRI.getVRegDef(MOp.getReg());
61  assert(ConstMI->getOpcode() == TargetOpcode::G_CONSTANT);
62  MI.removeOperand(NumOp);
63  MI.addOperand(MachineOperand::CreateImm(
64  ConstMI->getOperand(1).getCImm()->getZExtValue()));
65  if (MRI.use_empty(ConstMI->getOperand(0).getReg()))
66  ToErase.push_back(ConstMI);
67  }
68  }
69  }
70  for (MachineInstr *MI : ToErase)
71  MI->eraseFromParent();
72 }
73 
75  MachineIRBuilder MIB) {
77  for (MachineBasicBlock &MBB : MF) {
78  for (MachineInstr &MI : MBB) {
79  if (!isSpvIntrinsic(MI, Intrinsic::spv_bitcast))
80  continue;
81  assert(MI.getOperand(2).isReg());
82  MIB.setInsertPt(*MI.getParent(), MI);
83  MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg());
84  ToErase.push_back(&MI);
85  }
86  }
87  for (MachineInstr *MI : ToErase)
88  MI->eraseFromParent();
89 }
90 
91 // Translating GV, IRTranslator sometimes generates following IR:
92 // %1 = G_GLOBAL_VALUE
93 // %2 = COPY %1
94 // %3 = G_ADDRSPACE_CAST %2
95 // New registers have no SPIRVType and no register class info.
96 //
97 // Set SPIRVType for GV, propagate it from GV to other instructions,
98 // also set register classes.
101  MachineIRBuilder &MIB) {
102  SPIRVType *SpirvTy = nullptr;
103  assert(MI && "Machine instr is expected");
104  if (MI->getOperand(0).isReg()) {
105  Register Reg = MI->getOperand(0).getReg();
106  SpirvTy = GR->getSPIRVTypeForVReg(Reg);
107  if (!SpirvTy) {
108  switch (MI->getOpcode()) {
109  case TargetOpcode::G_CONSTANT: {
110  MIB.setInsertPt(*MI->getParent(), MI);
111  Type *Ty = MI->getOperand(1).getCImm()->getType();
112  SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB);
113  break;
114  }
115  case TargetOpcode::G_GLOBAL_VALUE: {
116  MIB.setInsertPt(*MI->getParent(), MI);
117  Type *Ty = MI->getOperand(1).getGlobal()->getType();
118  SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB);
119  break;
120  }
121  case TargetOpcode::G_TRUNC:
122  case TargetOpcode::G_ADDRSPACE_CAST:
123  case TargetOpcode::COPY: {
124  MachineOperand &Op = MI->getOperand(1);
125  MachineInstr *Def = Op.isReg() ? MRI.getVRegDef(Op.getReg()) : nullptr;
126  if (Def)
127  SpirvTy = propagateSPIRVType(Def, GR, MRI, MIB);
128  break;
129  }
130  default:
131  break;
132  }
133  if (SpirvTy)
134  GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF());
135  if (!MRI.getRegClassOrNull(Reg))
136  MRI.setRegClass(Reg, &SPIRV::IDRegClass);
137  }
138  }
139  return SpirvTy;
140 }
141 
142 // Insert ASSIGN_TYPE instuction between Reg and its definition, set NewReg as
143 // a dst of the definition, assign SPIRVType to both registers. If SpirvTy is
144 // provided, use it as SPIRVType in ASSIGN_TYPE, otherwise create it from Ty.
145 // TODO: maybe move to SPIRVUtils.
148  MachineIRBuilder &MIB,
151  assert((Ty || SpirvTy) && "Either LLVM or SPIRV type is expected.");
152  MIB.setInsertPt(*Def->getParent(),
153  (Def->getNextNode() ? Def->getNextNode()->getIterator()
154  : Def->getParent()->end()));
156  if (auto *RC = MRI.getRegClassOrNull(Reg))
157  MRI.setRegClass(NewReg, RC);
158  SpirvTy = SpirvTy ? SpirvTy : GR->getOrCreateSPIRVType(Ty, MIB);
159  GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF());
160  // This is to make it convenient for Legalizer to get the SPIRVType
161  // when processing the actual MI (i.e. not pseudo one).
162  GR->assignSPIRVTypeToVReg(SpirvTy, NewReg, MIB.getMF());
163  MIB.buildInstr(SPIRV::ASSIGN_TYPE)
164  .addDef(Reg)
165  .addUse(NewReg)
166  .addUse(GR->getSPIRVTypeID(SpirvTy));
167  Def->getOperand(0).setReg(NewReg);
168  MRI.setRegClass(Reg, &SPIRV::ANYIDRegClass);
169  return NewReg;
170 }
171 
173  MachineIRBuilder MIB) {
176 
177  for (MachineBasicBlock *MBB : post_order(&MF)) {
178  if (MBB->empty())
179  continue;
180 
181  bool ReachedBegin = false;
182  for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
183  !ReachedBegin;) {
184  MachineInstr &MI = *MII;
185 
186  if (isSpvIntrinsic(MI, Intrinsic::spv_assign_type)) {
187  Register Reg = MI.getOperand(1).getReg();
188  Type *Ty = getMDOperandAsType(MI.getOperand(2).getMetadata(), 0);
190  assert(Def && "Expecting an instruction that defines the register");
191  // G_GLOBAL_VALUE already has type info.
192  if (Def->getOpcode() != TargetOpcode::G_GLOBAL_VALUE)
193  insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MF.getRegInfo());
194  ToErase.push_back(&MI);
195  } else if (MI.getOpcode() == TargetOpcode::G_CONSTANT ||
196  MI.getOpcode() == TargetOpcode::G_FCONSTANT ||
197  MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR) {
198  // %rc = G_CONSTANT ty Val
199  // ===>
200  // %cty = OpType* ty
201  // %rctmp = G_CONSTANT ty Val
202  // %rc = ASSIGN_TYPE %rctmp, %cty
203  Register Reg = MI.getOperand(0).getReg();
204  if (MRI.hasOneUse(Reg)) {
206  if (isSpvIntrinsic(UseMI, Intrinsic::spv_assign_type) ||
207  isSpvIntrinsic(UseMI, Intrinsic::spv_assign_name))
208  continue;
209  }
210  Type *Ty = nullptr;
211  if (MI.getOpcode() == TargetOpcode::G_CONSTANT)
212  Ty = MI.getOperand(1).getCImm()->getType();
213  else if (MI.getOpcode() == TargetOpcode::G_FCONSTANT)
214  Ty = MI.getOperand(1).getFPImm()->getType();
215  else {
216  assert(MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR);
217  Type *ElemTy = nullptr;
218  MachineInstr *ElemMI = MRI.getVRegDef(MI.getOperand(1).getReg());
219  assert(ElemMI);
220 
221  if (ElemMI->getOpcode() == TargetOpcode::G_CONSTANT)
222  ElemTy = ElemMI->getOperand(1).getCImm()->getType();
223  else if (ElemMI->getOpcode() == TargetOpcode::G_FCONSTANT)
224  ElemTy = ElemMI->getOperand(1).getFPImm()->getType();
225  else
226  llvm_unreachable("Unexpected opcode");
227  unsigned NumElts =
228  MI.getNumExplicitOperands() - MI.getNumExplicitDefs();
229  Ty = VectorType::get(ElemTy, NumElts, false);
230  }
231  insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MRI);
232  } else if (MI.getOpcode() == TargetOpcode::G_TRUNC ||
233  MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
234  MI.getOpcode() == TargetOpcode::COPY ||
235  MI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST) {
236  propagateSPIRVType(&MI, GR, MRI, MIB);
237  }
238 
239  if (MII == Begin)
240  ReachedBegin = true;
241  else
242  --MII;
243  }
244  }
245  for (MachineInstr *MI : ToErase)
246  MI->eraseFromParent();
247 }
248 
249 static std::pair<Register, unsigned>
250 createNewIdReg(Register ValReg, unsigned Opcode, MachineRegisterInfo &MRI,
251  const SPIRVGlobalRegistry &GR) {
252  LLT NewT = LLT::scalar(32);
253  SPIRVType *SpvType = GR.getSPIRVTypeForVReg(ValReg);
254  assert(SpvType && "VReg is expected to have SPIRV type");
255  bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
256  bool IsVectorFloat =
257  SpvType->getOpcode() == SPIRV::OpTypeVector &&
258  GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())->getOpcode() ==
259  SPIRV::OpTypeFloat;
260  IsFloat |= IsVectorFloat;
261  auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
262  auto DstClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
263  if (MRI.getType(ValReg).isPointer()) {
264  NewT = LLT::pointer(0, 32);
265  GetIdOp = SPIRV::GET_pID;
266  DstClass = &SPIRV::pIDRegClass;
267  } else if (MRI.getType(ValReg).isVector()) {
268  NewT = LLT::fixed_vector(2, NewT);
269  GetIdOp = IsFloat ? SPIRV::GET_vfID : SPIRV::GET_vID;
270  DstClass = IsFloat ? &SPIRV::vfIDRegClass : &SPIRV::vIDRegClass;
271  }
273  MRI.setRegClass(IdReg, DstClass);
274  return {IdReg, GetIdOp};
275 }
276 
279  unsigned Opc = MI.getOpcode();
280  assert(MI.getNumDefs() > 0 && MRI.hasOneUse(MI.getOperand(0).getReg()));
281  MachineInstr &AssignTypeInst =
282  *(MRI.use_instr_begin(MI.getOperand(0).getReg()));
283  auto NewReg = createNewIdReg(MI.getOperand(0).getReg(), Opc, MRI, *GR).first;
284  AssignTypeInst.getOperand(1).setReg(NewReg);
285  MI.getOperand(0).setReg(NewReg);
286  MIB.setInsertPt(*MI.getParent(),
287  (MI.getNextNode() ? MI.getNextNode()->getIterator()
288  : MI.getParent()->end()));
289  for (auto &Op : MI.operands()) {
290  if (!Op.isReg() || Op.isDef())
291  continue;
292  auto IdOpInfo = createNewIdReg(Op.getReg(), Opc, MRI, *GR);
293  MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(Op.getReg());
294  Op.setReg(IdOpInfo.first);
295  }
296 }
297 
298 // Defined in SPIRVLegalizerInfo.cpp.
299 extern bool isTypeFoldingSupported(unsigned Opcode);
300 
303  MachineIRBuilder MIB) {
305  for (MachineBasicBlock &MBB : MF) {
306  for (MachineInstr &MI : MBB) {
307  if (isTypeFoldingSupported(MI.getOpcode()))
308  processInstr(MI, MIB, MRI, GR);
309  }
310  }
311 }
312 
314  MachineIRBuilder MIB) {
316  SwitchRegToMBB;
318  DenseSet<Register> SwitchRegs;
320  // Before IRTranslator pass, spv_switch calls are inserted before each
321  // switch instruction. IRTranslator lowers switches to ICMP+CBr+Br triples.
322  // A switch with two cases may be translated to this MIR sequesnce:
323  // intrinsic(@llvm.spv.switch), %CmpReg, %Const0, %Const1
324  // %Dst0 = G_ICMP intpred(eq), %CmpReg, %Const0
325  // G_BRCOND %Dst0, %bb.2
326  // G_BR %bb.5
327  // bb.5.entry:
328  // %Dst1 = G_ICMP intpred(eq), %CmpReg, %Const1
329  // G_BRCOND %Dst1, %bb.3
330  // G_BR %bb.4
331  // bb.2.sw.bb:
332  // ...
333  // bb.3.sw.bb1:
334  // ...
335  // bb.4.sw.epilog:
336  // ...
337  // Walk MIs and collect information about destination MBBs to update
338  // spv_switch call. We assume that all spv_switch precede corresponding ICMPs.
339  for (MachineBasicBlock &MBB : MF) {
340  for (MachineInstr &MI : MBB) {
341  if (isSpvIntrinsic(MI, Intrinsic::spv_switch)) {
342  assert(MI.getOperand(1).isReg());
343  Register Reg = MI.getOperand(1).getReg();
344  SwitchRegs.insert(Reg);
345  // Set the first successor as default MBB to support empty switches.
346  DefaultMBBs[Reg] = *MBB.succ_begin();
347  }
348  // Process only ICMPs that relate to spv_switches.
349  if (MI.getOpcode() == TargetOpcode::G_ICMP && MI.getOperand(2).isReg() &&
350  SwitchRegs.contains(MI.getOperand(2).getReg())) {
351  assert(MI.getOperand(0).isReg() && MI.getOperand(1).isPredicate() &&
352  MI.getOperand(3).isReg());
353  Register Dst = MI.getOperand(0).getReg();
354  // Set type info for destination register of switch's ICMP instruction.
355  if (GR->getSPIRVTypeForVReg(Dst) == nullptr) {
356  MIB.setInsertPt(*MI.getParent(), MI);
357  Type *LLVMTy = IntegerType::get(MF.getFunction().getContext(), 1);
358  SPIRVType *SpirvTy = GR->getOrCreateSPIRVType(LLVMTy, MIB);
359  MRI.setRegClass(Dst, &SPIRV::IDRegClass);
360  GR->assignSPIRVTypeToVReg(SpirvTy, Dst, MIB.getMF());
361  }
362  Register CmpReg = MI.getOperand(2).getReg();
363  MachineOperand &PredOp = MI.getOperand(1);
364  const auto CC = static_cast<CmpInst::Predicate>(PredOp.getPredicate());
365  assert(CC == CmpInst::ICMP_EQ && MRI.hasOneUse(Dst) &&
366  MRI.hasOneDef(CmpReg));
367  uint64_t Val = getIConstVal(MI.getOperand(3).getReg(), &MRI);
368  MachineInstr *CBr = MRI.use_begin(Dst)->getParent();
369  assert(CBr->getOpcode() == SPIRV::G_BRCOND &&
370  CBr->getOperand(1).isMBB());
371  SwitchRegToMBB[CmpReg][Val] = CBr->getOperand(1).getMBB();
372  // The next MI is always BR to either the next case or the default.
373  MachineInstr *NextMI = CBr->getNextNode();
374  assert(NextMI->getOpcode() == SPIRV::G_BR &&
375  NextMI->getOperand(0).isMBB());
376  MachineBasicBlock *NextMBB = NextMI->getOperand(0).getMBB();
377  assert(NextMBB != nullptr);
378  // The default MBB is not started by ICMP with switch's cmp register.
379  if (NextMBB->front().getOpcode() != SPIRV::G_ICMP ||
380  (NextMBB->front().getOperand(2).isReg() &&
381  NextMBB->front().getOperand(2).getReg() != CmpReg))
382  DefaultMBBs[CmpReg] = NextMBB;
383  }
384  }
385  }
386  // Modify spv_switch's operands by collected values. For the example above,
387  // the result will be like this:
388  // intrinsic(@llvm.spv.switch), %CmpReg, %bb.4, i32 0, %bb.2, i32 1, %bb.3
389  // Note that ICMP+CBr+Br sequences are not removed, but ModuleAnalysis marks
390  // them as skipped and AsmPrinter does not output them.
391  for (MachineBasicBlock &MBB : MF) {
392  for (MachineInstr &MI : MBB) {
393  if (!isSpvIntrinsic(MI, Intrinsic::spv_switch))
394  continue;
395  assert(MI.getOperand(1).isReg());
396  Register Reg = MI.getOperand(1).getReg();
397  unsigned NumOp = MI.getNumExplicitOperands();
400  for (unsigned i = 2; i < NumOp; i++) {
401  Register CReg = MI.getOperand(i).getReg();
402  uint64_t Val = getIConstVal(CReg, &MRI);
403  MachineInstr *ConstInstr = getDefInstrMaybeConstant(CReg, &MRI);
404  Vals.push_back(ConstInstr->getOperand(1).getCImm());
405  MBBs.push_back(SwitchRegToMBB[Reg][Val]);
406  }
407  for (unsigned i = MI.getNumExplicitOperands() - 1; i > 1; i--)
408  MI.removeOperand(i);
409  MI.addOperand(MachineOperand::CreateMBB(DefaultMBBs[Reg]));
410  for (unsigned i = 0; i < Vals.size(); i++) {
411  MI.addOperand(MachineOperand::CreateCImm(Vals[i]));
412  MI.addOperand(MachineOperand::CreateMBB(MBBs[i]));
413  }
414  }
415  }
416 }
417 
418 bool SPIRVPreLegalizer::runOnMachineFunction(MachineFunction &MF) {
419  // Initialize the type registry.
421  SPIRVGlobalRegistry *GR = ST.getSPIRVGlobalRegistry();
422  GR->setCurrentFunc(MF);
423  MachineIRBuilder MIB(MF);
425  insertBitcasts(MF, GR, MIB);
426  generateAssignInstrs(MF, GR, MIB);
427  processInstrsWithTypeFolding(MF, GR, MIB);
428  processSwitches(MF, GR, MIB);
429 
430  return true;
431 }
432 
433 INITIALIZE_PASS(SPIRVPreLegalizer, DEBUG_TYPE, "SPIRV pre legalizer", false,
434  false)
435 
436 char SPIRVPreLegalizer::ID = 0;
437 
439  return new SPIRVPreLegalizer();
440 }
i
i
Definition: README.txt:29
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::CmpInst::ICMP_EQ
@ ICMP_EQ
equal
Definition: InstrTypes.h:740
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::ConstantInt::getType
IntegerType * getType() const
getType - Specialize the getType() method to always return an IntegerType, which reduces the amount o...
Definition: Constants.h:173
DebugInfoMetadata.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::ilist_node_with_parent::getNextNode
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:289
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
DEBUG_TYPE
#define DEBUG_TYPE
Definition: SPIRVPreLegalizer.cpp:27
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
OptimizationRemarkEmitter.h
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::SPIRVGlobalRegistry::assignSPIRVTypeToVReg
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, MachineFunction &MF)
Definition: SPIRVGlobalRegistry.cpp:37
llvm::SPIRVSubtarget
Definition: SPIRVSubtarget.h:36
SPIRVSubtarget.h
isSpvIntrinsic
static bool isSpvIntrinsic(MachineInstr &MI, Intrinsic::ID IntrinsicID)
Definition: SPIRVPreLegalizer.cpp:42
llvm::detail::DenseSetImpl< ValueT, DenseMap< ValueT, detail::DenseSetEmpty, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::insert
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
llvm::SPIRVGlobalRegistry::getSPIRVTypeForVReg
SPIRVType * getSPIRVTypeForVReg(Register VReg) const
Definition: SPIRVGlobalRegistry.cpp:308
llvm::LLT::fixed_vector
static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:74
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
getDefInstrMaybeConstant
MachineInstr * getDefInstrMaybeConstant(Register &ConstReg, const MachineRegisterInfo *MRI)
Definition: SPIRVUtils.cpp:185
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
Constants.h
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:328
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:269
SPIRVUtils.h
generateAssignInstrs
static void generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR, MachineIRBuilder MIB)
Definition: SPIRVPreLegalizer.cpp:172
createNewIdReg
static std::pair< Register, unsigned > createNewIdReg(Register ValReg, unsigned Opcode, MachineRegisterInfo &MRI, const SPIRVGlobalRegistry &GR)
Definition: SPIRVPreLegalizer.cpp:250
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::MachineRegisterInfo::use_empty
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:514
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
processInstrsWithTypeFolding
static void processInstrsWithTypeFolding(MachineFunction &MF, SPIRVGlobalRegistry *GR, MachineIRBuilder MIB)
Definition: SPIRVPreLegalizer.cpp:301
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:49
llvm::DenseSet
Implements a dense probed hash-table based set.
Definition: DenseSet.h:268
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::MachineIRBuilder::setInsertPt
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
Definition: MachineIRBuilder.h:313
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:219
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:551
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
SPIRVGlobalRegistry.h
uint64_t
llvm::MachineOperand::CreateMBB
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
Definition: MachineOperand.h:825
propagateSPIRVType
static SPIRVType * propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR, MachineRegisterInfo &MRI, MachineIRBuilder &MIB)
Definition: SPIRVPreLegalizer.cpp:99
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::MachineRegisterInfo::use_instr_begin
use_instr_iterator use_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:485
llvm::MachineIRBuilder::buildBitcast
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
Definition: MachineIRBuilder.h:668
llvm::DenseMap
Definition: DenseMap.h:716
insertBitcasts
static void insertBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR, MachineIRBuilder MIB)
Definition: SPIRVPreLegalizer.cpp:74
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:122
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:556
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:597
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:659
SPIRV.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LLT::isPointer
bool isPointer() const
Definition: LowLevelTypeImpl.h:120
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:342
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:186
llvm::SPIRVGlobalRegistry
Definition: SPIRVGlobalRegistry.h:26
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineRegisterInfo::hasOneDef
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
Definition: MachineRegisterInfo.h:452
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::initializeSPIRVPreLegalizerPass
void initializeSPIRVPreLegalizerPass(PassRegistry &)
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:374
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::MachineRegisterInfo::use_begin
use_iterator use_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:472
llvm::detail::DenseSetImpl< ValueT, DenseMap< ValueT, detail::DenseSetEmpty, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::contains
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
Definition: DenseSet.h:185
llvm::MachineOperand::CreateCImm
static MachineOperand CreateCImm(const ConstantInt *CI)
Definition: MachineOperand.h:788
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:142
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::createSPIRVPreLegalizerPass
FunctionPass * createSPIRVPreLegalizerPass()
processInstr
static void processInstr(MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR)
Definition: SPIRVPreLegalizer.cpp:277
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::post_order
iterator_range< po_iterator< T > > post_order(const T &G)
Definition: PostOrderIterator.h:189
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:257
llvm::SPIRVGlobalRegistry::getSPIRVTypeID
Register getSPIRVTypeID(const SPIRVType *SpirvType) const
Definition: SPIRVGlobalRegistry.h:89
PostOrderIterator.h
llvm::MachineRegisterInfo::hasOneUse
bool hasOneUse(Register RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
Definition: MachineRegisterInfo.h:518
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:278
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
TargetIntrinsicInfo.h
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:53
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:250
foldConstantsIntoIntrinsics
static void foldConstantsIntoIntrinsics(MachineFunction &MF)
Definition: SPIRVPreLegalizer.cpp:49
llvm::IntegerType::get
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:311
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::SPIRVGlobalRegistry::getOrCreateSPIRVType
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
Definition: SPIRVGlobalRegistry.cpp:318
getIConstVal
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI)
Definition: SPIRVUtils.cpp:199
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::VectorType::get
static VectorType * get(Type *ElementType, ElementCount EC)
This static method is the primary way to construct an VectorType.
Definition: Type.cpp:668
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:280
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:56
insertAssignInstr
static Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy, SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB, MachineRegisterInfo &MRI)
Definition: SPIRVPreLegalizer.cpp:146
isTypeFoldingSupported
bool isTypeFoldingSupported(unsigned Opcode)
Definition: SPIRVLegalizerInfo.cpp:53
processSwitches
static void processSwitches(MachineFunction &MF, SPIRVGlobalRegistry *GR, MachineIRBuilder MIB)
Definition: SPIRVPreLegalizer.cpp:313
getMDOperandAsType
Type * getMDOperandAsType(const MDNode *N, unsigned I)
Definition: SPIRVUtils.cpp:205
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:39