41 TargetOpcode::G_CONSTANT,
42 TargetOpcode::G_FCONSTANT,
49 TargetOpcode::G_SELECT,
50 TargetOpcode::G_EXTRACT_VECTOR_ELT,
58 using namespace TargetOpcode;
61 GR = ST.getSPIRVGlobalRegistry();
99 const unsigned PSize = ST.getPointerSize();
108 auto allPtrsScalarsAndVectors = {
109 p0, p1, p2, p3, p4, p5, s1, s8, s16,
110 s32, s64, v2s1, v2s8, v2s16, v2s32, v2s64, v3s1, v3s8,
111 v3s16, v3s32, v3s64, v4s1, v4s8, v4s16, v4s32, v4s64, v8s1,
112 v8s8, v8s16, v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
114 auto allScalarsAndVectors = {
115 s1, s8, s16, s32, s64, v2s1, v2s8, v2s16, v2s32, v2s64,
116 v3s1, v3s8, v3s16, v3s32, v3s64, v4s1, v4s8, v4s16, v4s32, v4s64,
117 v8s1, v8s8, v8s16, v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
119 auto allIntScalarsAndVectors = {s8, s16, s32, s64, v2s8, v2s16,
120 v2s32, v2s64, v3s8, v3s16, v3s32, v3s64,
121 v4s8, v4s16, v4s32, v4s64, v8s8, v8s16,
122 v8s32, v8s64, v16s8, v16s16, v16s32, v16s64};
124 auto allBoolScalarsAndVectors = {s1, v2s1, v3s1, v4s1, v8s1, v16s1};
126 auto allIntScalars = {s8, s16, s32, s64};
128 auto allFloatScalarsAndVectors = {
129 s16, s32, s64, v2s16, v2s32, v2s64, v3s16, v3s32, v3s64,
130 v4s16, v4s32, v4s64, v8s16, v8s32, v8s64, v16s16, v16s32, v16s64};
132 auto allFloatAndIntScalars = allIntScalars;
134 auto allPtrs = {p0, p1, p2, p3, p4, p5};
135 auto allWritablePtrs = {p0, p1, p3, p4};
161 .legalForCartesianProduct(allIntScalarsAndVectors,
162 allFloatScalarsAndVectors);
165 .legalForCartesianProduct(allFloatScalarsAndVectors,
166 allScalarsAndVectors);
169 .legalFor(allIntScalarsAndVectors);
172 allIntScalarsAndVectors, allIntScalarsAndVectors);
180 return Query.
Types[0].getSizeInBits() == Query.
Types[1].getSizeInBits();
190 allPtrs, allIntScalars);
196 typeInSet(1, allPtrsScalarsAndVectors)));
200 typeInSet(1, allFloatScalarsAndVectors)));
203 G_ATOMICRMW_MAX, G_ATOMICRMW_MIN,
204 G_ATOMICRMW_SUB, G_ATOMICRMW_XOR,
205 G_ATOMICRMW_UMAX, G_ATOMICRMW_UMIN})
206 .legalForCartesianProduct(allIntScalars, allWritablePtrs);
220 .legalForCartesianProduct(allScalarsAndVectors);
224 .legalForCartesianProduct(allFloatScalarsAndVectors);
256 G_INTRINSIC_ROUNDEVEN})
257 .legalFor(allFloatScalarsAndVectors);
261 allFloatScalarsAndVectors);
264 allFloatScalarsAndVectors, allIntScalarsAndVectors);
266 if (ST.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
268 {G_CTTZ, G_CTTZ_ZERO_UNDEF, G_CTLZ, G_CTLZ_ZERO_UNDEF})
269 .legalForCartesianProduct(allIntScalarsAndVectors,
270 allIntScalarsAndVectors);
277 verify(*ST.getInstrInfo());
284 Register ConvReg =
MRI.createGenericVirtualRegister(ConvTy);
294 auto Opc =
MI.getOpcode();
297 assert(Opc == TargetOpcode::G_ICMP);
299 auto &Op0 =
MI.getOperand(2);
300 auto &Op1 =
MI.getOperand(3);
307 MRI.getType(Reg0).isPointer() &&
MRI.getType(Reg1).isPointer()) {
unsigned const MachineRegisterInfo * MRI
This file declares the MachineIRBuilder class.
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isTypeFoldingSupported(unsigned Opcode)
static const std::set< unsigned > TypeFoldingSupportingOpcs
static Register convertPtrToInt(Register Reg, LLT ConvTy, SPIRVType *SpirvType, LegalizerHelper &Helper, MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR)
bool isTypeFoldingSupported(unsigned Opcode)
static constexpr uint32_t Opcode
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
void computeTables()
Compute any ancillary tables needed to quickly decide how an operation should be handled.
LegalizeRuleSet & legalFor(std::initializer_list< LLT > Types)
The instruction is legal when type index 0 is any type in the given list.
LegalizeRuleSet & lower()
The instruction is lowered.
LegalizeRuleSet & custom()
Unconditionally custom lower.
LegalizeRuleSet & alwaysLegal()
LegalizeRuleSet & customIf(LegalityPredicate Predicate)
LegalizeRuleSet & legalForCartesianProduct(std::initializer_list< LLT > Types)
The instruction is legal when type indexes 0 and 1 are both in the given list.
LegalizeRuleSet & legalIf(LegalityPredicate Predicate)
The instruction is legal if predicate is true.
MachineIRBuilder & MIRBuilder
Expose MIRBuilder so clients can set their own RecordInsertInstruction functions.
LegalizeRuleSet & getActionDefinitionsBuilder(unsigned Opcode)
Get the action definition builder for the given opcode.
const LegacyLegalizerInfo & getLegacyLegalizerInfo() const
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
SPIRVType * getSPIRVTypeForVReg(Register VReg) const
SPIRVType * getOrCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AQ=SPIRV::AccessQualifier::ReadWrite, bool EmitIR=true)
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, MachineFunction &MF)
SPIRVLegalizerInfo(const SPIRVSubtarget &ST)
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override
Called for instructions with the Custom LegalizationAction.
unsigned getPointerSize() const
bool canDirectlyComparePointers() const
The instances of the Type class are immutable: once they are created, they are never changed.
LegalityPredicate typeInSet(unsigned TypeIdx, std::initializer_list< LLT > TypesInit)
True iff the given type index is one of the specified types.
Predicate all(Predicate P0, Predicate P1)
True iff P0 and P1 are true.
This is an optimization pass for GlobalISel generic memory operations.
std::function< bool(const LegalityQuery &)> LegalityPredicate
The LegalityQuery object bundles together all the information that's needed to decide whether a given...