LLVM  10.0.0svn
ARMCallLowering.cpp
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1 //===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARMCallLowering.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMISelLowering.h"
18 #include "ARMSubtarget.h"
19 #include "Utils/ARMBaseInfo.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Analysis.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/Support/Casting.h"
45 #include <algorithm>
46 #include <cassert>
47 #include <cstdint>
48 #include <utility>
49 
50 using namespace llvm;
51 
53  : CallLowering(&TLI) {}
54 
55 static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
56  Type *T) {
57  if (T->isArrayTy())
58  return isSupportedType(DL, TLI, T->getArrayElementType());
59 
60  if (T->isStructTy()) {
61  // For now we only allow homogeneous structs that we can manipulate with
62  // G_MERGE_VALUES and G_UNMERGE_VALUES
63  auto StructT = cast<StructType>(T);
64  for (unsigned i = 1, e = StructT->getNumElements(); i != e; ++i)
65  if (StructT->getElementType(i) != StructT->getElementType(0))
66  return false;
67  return isSupportedType(DL, TLI, StructT->getElementType(0));
68  }
69 
70  EVT VT = TLI.getValueType(DL, T, true);
71  if (!VT.isSimple() || VT.isVector() ||
72  !(VT.isInteger() || VT.isFloatingPoint()))
73  return false;
74 
75  unsigned VTSize = VT.getSimpleVT().getSizeInBits();
76 
77  if (VTSize == 64)
78  // FIXME: Support i64 too
79  return VT.isFloatingPoint();
80 
81  return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
82 }
83 
84 namespace {
85 
86 /// Helper class for values going out through an ABI boundary (used for handling
87 /// function return values and call parameters).
88 struct OutgoingValueHandler : public CallLowering::ValueHandler {
89  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
90  MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
91  : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
92 
93  bool isIncomingArgumentHandler() const override { return false; }
94 
95  Register getStackAddress(uint64_t Size, int64_t Offset,
96  MachinePointerInfo &MPO) override {
97  assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
98  "Unsupported size");
99 
100  LLT p0 = LLT::pointer(0, 32);
101  LLT s32 = LLT::scalar(32);
102  Register SPReg = MRI.createGenericVirtualRegister(p0);
103  MIRBuilder.buildCopy(SPReg, Register(ARM::SP));
104 
105  Register OffsetReg = MRI.createGenericVirtualRegister(s32);
106  MIRBuilder.buildConstant(OffsetReg, Offset);
107 
108  Register AddrReg = MRI.createGenericVirtualRegister(p0);
109  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
110 
111  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
112  return AddrReg;
113  }
114 
115  void assignValueToReg(Register ValVReg, Register PhysReg,
116  CCValAssign &VA) override {
117  assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
118  assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
119 
120  assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
121  assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
122 
123  Register ExtReg = extendRegister(ValVReg, VA);
124  MIRBuilder.buildCopy(PhysReg, ExtReg);
125  MIB.addUse(PhysReg, RegState::Implicit);
126  }
127 
128  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
129  MachinePointerInfo &MPO, CCValAssign &VA) override {
130  assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
131  "Unsupported size");
132 
133  Register ExtReg = extendRegister(ValVReg, VA);
134  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
136  /* Alignment */ 1);
137  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
138  }
139 
140  unsigned assignCustomValue(const CallLowering::ArgInfo &Arg,
141  ArrayRef<CCValAssign> VAs) override {
142  assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
143 
144  CCValAssign VA = VAs[0];
145  assert(VA.needsCustom() && "Value doesn't need custom handling");
146  assert(VA.getValVT() == MVT::f64 && "Unsupported type");
147 
148  CCValAssign NextVA = VAs[1];
149  assert(NextVA.needsCustom() && "Value doesn't need custom handling");
150  assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
151 
152  assert(VA.getValNo() == NextVA.getValNo() &&
153  "Values belong to different arguments");
154 
155  assert(VA.isRegLoc() && "Value should be in reg");
156  assert(NextVA.isRegLoc() && "Value should be in reg");
157 
158  Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
160  MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
161 
162  bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
163  if (!IsLittle)
164  std::swap(NewRegs[0], NewRegs[1]);
165 
166  assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
167  assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
168 
169  return 1;
170  }
171 
172  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
173  CCValAssign::LocInfo LocInfo,
175  CCState &State) override {
176  if (AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State))
177  return true;
178 
179  StackSize =
180  std::max(StackSize, static_cast<uint64_t>(State.getNextStackOffset()));
181  return false;
182  }
183 
184  MachineInstrBuilder &MIB;
185  uint64_t StackSize = 0;
186 };
187 
188 } // end anonymous namespace
189 
190 void ARMCallLowering::splitToValueTypes(const ArgInfo &OrigArg,
191  SmallVectorImpl<ArgInfo> &SplitArgs,
192  MachineFunction &MF) const {
193  const ARMTargetLowering &TLI = *getTLI<ARMTargetLowering>();
194  LLVMContext &Ctx = OrigArg.Ty->getContext();
195  const DataLayout &DL = MF.getDataLayout();
196  const Function &F = MF.getFunction();
197 
198  SmallVector<EVT, 4> SplitVTs;
199  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, nullptr, nullptr, 0);
200  assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
201 
202  if (SplitVTs.size() == 1) {
203  // Even if there is no splitting to do, we still want to replace the
204  // original type (e.g. pointer type -> integer).
205  auto Flags = OrigArg.Flags[0];
206  unsigned OriginalAlignment = DL.getABITypeAlignment(OrigArg.Ty);
207  Flags.setOrigAlign(OriginalAlignment);
208  SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
209  Flags, OrigArg.IsFixed);
210  return;
211  }
212 
213  // Create one ArgInfo for each virtual register.
214  for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) {
215  EVT SplitVT = SplitVTs[i];
216  Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
217  auto Flags = OrigArg.Flags[0];
218 
219  unsigned OriginalAlignment = DL.getABITypeAlignment(SplitTy);
220  Flags.setOrigAlign(OriginalAlignment);
221 
222  bool NeedsConsecutiveRegisters =
224  SplitTy, F.getCallingConv(), F.isVarArg());
225  if (NeedsConsecutiveRegisters) {
226  Flags.setInConsecutiveRegs();
227  if (i == e - 1)
228  Flags.setInConsecutiveRegsLast();
229  }
230 
231  // FIXME: We also want to split SplitTy further.
232  Register PartReg = OrigArg.Regs[i];
233  SplitArgs.emplace_back(PartReg, SplitTy, Flags, OrigArg.IsFixed);
234  }
235 }
236 
237 /// Lower the return value for the already existing \p Ret. This assumes that
238 /// \p MIRBuilder's insertion point is correct.
239 bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
240  const Value *Val, ArrayRef<Register> VRegs,
241  MachineInstrBuilder &Ret) const {
242  if (!Val)
243  // Nothing to do here.
244  return true;
245 
246  auto &MF = MIRBuilder.getMF();
247  const auto &F = MF.getFunction();
248 
249  auto DL = MF.getDataLayout();
250  auto &TLI = *getTLI<ARMTargetLowering>();
251  if (!isSupportedType(DL, TLI, Val->getType()))
252  return false;
253 
254  ArgInfo OrigRetInfo(VRegs, Val->getType());
255  setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
256 
257  SmallVector<ArgInfo, 4> SplitRetInfos;
258  splitToValueTypes(OrigRetInfo, SplitRetInfos, MF);
259 
260  CCAssignFn *AssignFn =
261  TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
262 
263  OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn);
264  return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler);
265 }
266 
268  const Value *Val,
269  ArrayRef<Register> VRegs) const {
270  assert(!Val == VRegs.empty() && "Return value without a vreg");
271 
272  auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
273  unsigned Opcode = ST.getReturnOpcode();
274  auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
275 
276  if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
277  return false;
278 
279  MIRBuilder.insertInstr(Ret);
280  return true;
281 }
282 
283 namespace {
284 
285 /// Helper class for values coming in through an ABI boundary (used for handling
286 /// formal arguments and call return values).
287 struct IncomingValueHandler : public CallLowering::ValueHandler {
288  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
289  CCAssignFn AssignFn)
290  : ValueHandler(MIRBuilder, MRI, AssignFn) {}
291 
292  bool isIncomingArgumentHandler() const override { return true; }
293 
294  Register getStackAddress(uint64_t Size, int64_t Offset,
295  MachinePointerInfo &MPO) override {
296  assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
297  "Unsupported size");
298 
299  auto &MFI = MIRBuilder.getMF().getFrameInfo();
300 
301  int FI = MFI.CreateFixedObject(Size, Offset, true);
302  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
303 
304  Register AddrReg =
306  MIRBuilder.buildFrameIndex(AddrReg, FI);
307 
308  return AddrReg;
309  }
310 
311  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
312  MachinePointerInfo &MPO, CCValAssign &VA) override {
313  assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
314  "Unsupported size");
315 
316  if (VA.getLocInfo() == CCValAssign::SExt ||
317  VA.getLocInfo() == CCValAssign::ZExt) {
318  // If the value is zero- or sign-extended, its size becomes 4 bytes, so
319  // that's what we should load.
320  Size = 4;
321  assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
322 
323  auto LoadVReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
324  buildLoad(LoadVReg, Addr, Size, /* Alignment */ 1, MPO);
325  MIRBuilder.buildTrunc(ValVReg, LoadVReg);
326  } else {
327  // If the value is not extended, a simple load will suffice.
328  buildLoad(ValVReg, Addr, Size, /* Alignment */ 1, MPO);
329  }
330  }
331 
332  void buildLoad(Register Val, Register Addr, uint64_t Size, unsigned Alignment,
333  MachinePointerInfo &MPO) {
334  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
335  MPO, MachineMemOperand::MOLoad, Size, Alignment);
336  MIRBuilder.buildLoad(Val, Addr, *MMO);
337  }
338 
339  void assignValueToReg(Register ValVReg, Register PhysReg,
340  CCValAssign &VA) override {
341  assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
342  assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
343 
344  auto ValSize = VA.getValVT().getSizeInBits();
345  auto LocSize = VA.getLocVT().getSizeInBits();
346 
347  assert(ValSize <= 64 && "Unsupported value size");
348  assert(LocSize <= 64 && "Unsupported location size");
349 
350  markPhysRegUsed(PhysReg);
351  if (ValSize == LocSize) {
352  MIRBuilder.buildCopy(ValVReg, PhysReg);
353  } else {
354  assert(ValSize < LocSize && "Extensions not supported");
355 
356  // We cannot create a truncating copy, nor a trunc of a physical register.
357  // Therefore, we need to copy the content of the physical register into a
358  // virtual one and then truncate that.
359  auto PhysRegToVReg =
361  MIRBuilder.buildCopy(PhysRegToVReg, PhysReg);
362  MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);
363  }
364  }
365 
366  unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg,
367  ArrayRef<CCValAssign> VAs) override {
368  assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
369 
370  CCValAssign VA = VAs[0];
371  assert(VA.needsCustom() && "Value doesn't need custom handling");
372  assert(VA.getValVT() == MVT::f64 && "Unsupported type");
373 
374  CCValAssign NextVA = VAs[1];
375  assert(NextVA.needsCustom() && "Value doesn't need custom handling");
376  assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
377 
378  assert(VA.getValNo() == NextVA.getValNo() &&
379  "Values belong to different arguments");
380 
381  assert(VA.isRegLoc() && "Value should be in reg");
382  assert(NextVA.isRegLoc() && "Value should be in reg");
383 
384  Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
386 
387  assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
388  assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
389 
390  bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
391  if (!IsLittle)
392  std::swap(NewRegs[0], NewRegs[1]);
393 
394  MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
395 
396  return 1;
397  }
398 
399  /// Marking a physical register as used is different between formal
400  /// parameters, where it's a basic block live-in, and call returns, where it's
401  /// an implicit-def of the call instruction.
402  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
403 };
404 
405 struct FormalArgHandler : public IncomingValueHandler {
406  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
407  CCAssignFn AssignFn)
408  : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
409 
410  void markPhysRegUsed(unsigned PhysReg) override {
411  MIRBuilder.getMRI()->addLiveIn(PhysReg);
412  MIRBuilder.getMBB().addLiveIn(PhysReg);
413  }
414 };
415 
416 } // end anonymous namespace
417 
419  MachineIRBuilder &MIRBuilder, const Function &F,
420  ArrayRef<ArrayRef<Register>> VRegs) const {
421  auto &TLI = *getTLI<ARMTargetLowering>();
422  auto Subtarget = TLI.getSubtarget();
423 
424  if (Subtarget->isThumb1Only())
425  return false;
426 
427  // Quick exit if there aren't any args
428  if (F.arg_empty())
429  return true;
430 
431  if (F.isVarArg())
432  return false;
433 
434  auto &MF = MIRBuilder.getMF();
435  auto &MBB = MIRBuilder.getMBB();
436  auto DL = MF.getDataLayout();
437 
438  for (auto &Arg : F.args()) {
439  if (!isSupportedType(DL, TLI, Arg.getType()))
440  return false;
441  if (Arg.hasByValOrInAllocaAttr())
442  return false;
443  }
444 
445  CCAssignFn *AssignFn =
446  TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
447 
448  FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
449  AssignFn);
450 
451  SmallVector<ArgInfo, 8> SplitArgInfos;
452  unsigned Idx = 0;
453  for (auto &Arg : F.args()) {
454  ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType());
455 
456  setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F);
457  splitToValueTypes(OrigArgInfo, SplitArgInfos, MF);
458 
459  Idx++;
460  }
461 
462  if (!MBB.empty())
463  MIRBuilder.setInstr(*MBB.begin());
464 
465  if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler))
466  return false;
467 
468  // Move back to the end of the basic block.
469  MIRBuilder.setMBB(MBB);
470  return true;
471 }
472 
473 namespace {
474 
475 struct CallReturnHandler : public IncomingValueHandler {
476  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
477  MachineInstrBuilder MIB, CCAssignFn *AssignFn)
478  : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
479 
480  void markPhysRegUsed(unsigned PhysReg) override {
481  MIB.addDef(PhysReg, RegState::Implicit);
482  }
483 
485 };
486 
487 // FIXME: This should move to the ARMSubtarget when it supports all the opcodes.
488 unsigned getCallOpcode(const ARMSubtarget &STI, bool isDirect) {
489  if (isDirect)
490  return STI.isThumb() ? ARM::tBL : ARM::BL;
491 
492  if (STI.isThumb())
493  return ARM::tBLXr;
494 
495  if (STI.hasV5TOps())
496  return ARM::BLX;
497 
498  if (STI.hasV4TOps())
499  return ARM::BX_CALL;
500 
501  return ARM::BMOVPCRX_CALL;
502 }
503 } // end anonymous namespace
504 
506  MachineFunction &MF = MIRBuilder.getMF();
507  const auto &TLI = *getTLI<ARMTargetLowering>();
508  const auto &DL = MF.getDataLayout();
509  const auto &STI = MF.getSubtarget<ARMSubtarget>();
510  const TargetRegisterInfo *TRI = STI.getRegisterInfo();
512 
513  if (STI.genLongCalls())
514  return false;
515 
516  if (STI.isThumb1Only())
517  return false;
518 
519  auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
520 
521  // Create the call instruction so we can add the implicit uses of arg
522  // registers, but don't insert it yet.
523  bool IsDirect = !Info.Callee.isReg();
524  auto CallOpcode = getCallOpcode(STI, IsDirect);
525  auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode);
526 
527  bool IsThumb = STI.isThumb();
528  if (IsThumb)
529  MIB.add(predOps(ARMCC::AL));
530 
531  MIB.add(Info.Callee);
532  if (!IsDirect) {
533  auto CalleeReg = Info.Callee.getReg();
534  if (CalleeReg && !Register::isPhysicalRegister(CalleeReg)) {
535  unsigned CalleeIdx = IsThumb ? 2 : 0;
536  MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
537  MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),
538  *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx));
539  }
540  }
541 
542  MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
543 
544  bool IsVarArg = false;
545  SmallVector<ArgInfo, 8> ArgInfos;
546  for (auto Arg : Info.OrigArgs) {
547  if (!isSupportedType(DL, TLI, Arg.Ty))
548  return false;
549 
550  if (!Arg.IsFixed)
551  IsVarArg = true;
552 
553  if (Arg.Flags[0].isByVal())
554  return false;
555 
556  splitToValueTypes(Arg, ArgInfos, MF);
557  }
558 
559  auto ArgAssignFn = TLI.CCAssignFnForCall(Info.CallConv, IsVarArg);
560  OutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
561  if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))
562  return false;
563 
564  // Now we can add the actual call instruction to the correct basic block.
565  MIRBuilder.insertInstr(MIB);
566 
567  if (!Info.OrigRet.Ty->isVoidTy()) {
568  if (!isSupportedType(DL, TLI, Info.OrigRet.Ty))
569  return false;
570 
571  ArgInfos.clear();
572  splitToValueTypes(Info.OrigRet, ArgInfos, MF);
573  auto RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, IsVarArg);
574  CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
575  if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler))
576  return false;
577  }
578 
579  // We now know the size of the stack - update the ADJCALLSTACKDOWN
580  // accordingly.
581  CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
582 
583  MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
584  .addImm(ArgHandler.StackSize)
585  .addImm(0)
586  .add(predOps(ARMCC::AL));
587 
588  return true;
589 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:112
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:641
MachineOperand Callee
Destination of the call.
Definition: CallLowering.h:77
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
bool isThumb() const
Definition: ARMSubtarget.h:753
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register getLocReg() const
bool hasV4TOps() const
Definition: ARMSubtarget.h:567
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
bool isScalar() const
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
bool handleAssignments(MachineIRBuilder &MIRBuilder, SmallVectorImpl< ArgInfo > &Args, ValueHandler &Handler) const
Invoke Handler::assignArg on each of the given Args and then use Callback to move them to the assigne...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
unsigned const TargetRegisterInfo * TRI
F(f)
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
static unsigned getCallOpcode(const Function &CallerF, bool IsIndirect, bool IsTailCall)
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:264
ARMCallLowering(const ARMTargetLowering &TLI)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
unsigned getSizeInBits() const
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:246
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
bool arg_empty() const
Definition: Function.h:729
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:119
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:141
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineRegisterInfo * getMRI()
Getter for MRI.
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Helper class to build MachineInstr.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
constexpr double e
Definition: MathExtras.h:57
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
MachineInstrBuilder buildGEP(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_GEP Op0, Op1.
Extended Value Type.
Definition: ValueTypes.h:33
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:112
This class contains a discriminated union of information about pointers in memory operands...
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
The memory access writes data.
SmallVector< ArgInfo, 8 > OrigArgs
List of descriptors of the arguments passed to the function.
Definition: CallLowering.h:83
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
CCState - This class holds information needed while lowering arguments and return values...
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:390
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
CCValAssign - Represent assignment of one arg/retval to a location.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:755
Promote Memory to Register
Definition: Mem2Reg.cpp:109
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This file declares the MachineIRBuilder class.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
unsigned getReturnOpcode() const
Returns the correct return opcode for the current feature set.
Definition: ARMSubtarget.h:845
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
CallingConv::ID CallConv
Calling convention to be used for the call.
Definition: CallLowering.h:73
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs...
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
uint32_t Size
Definition: Profile.cpp:46
static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI, Type *T)
bool hasV5TOps() const
Definition: ARMSubtarget.h:568
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
LLVM Value Representation.
Definition: Value.h:74
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:47
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Type * getArrayElementType() const
Definition: Type.h:368
This file describes how to lower LLVM calls to machine code calls.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Register getReg() const
getReg - Returns the register number.
ArgInfo OrigRet
Descriptor for the return type of the function.
Definition: CallLowering.h:80
iterator_range< arg_iterator > args()
Definition: Function.h:719
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isStructTy() const
True if this is an instance of StructType.
Definition: Type.h:218
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:221