LLVM  10.0.0svn
ARMCallLowering.cpp
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1 //===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARMCallLowering.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMISelLowering.h"
18 #include "ARMSubtarget.h"
19 #include "Utils/ARMBaseInfo.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Analysis.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/Support/Casting.h"
45 #include <algorithm>
46 #include <cassert>
47 #include <cstdint>
48 #include <utility>
49 
50 using namespace llvm;
51 
53  : CallLowering(&TLI) {}
54 
55 static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
56  Type *T) {
57  if (T->isArrayTy())
58  return isSupportedType(DL, TLI, T->getArrayElementType());
59 
60  if (T->isStructTy()) {
61  // For now we only allow homogeneous structs that we can manipulate with
62  // G_MERGE_VALUES and G_UNMERGE_VALUES
63  auto StructT = cast<StructType>(T);
64  for (unsigned i = 1, e = StructT->getNumElements(); i != e; ++i)
65  if (StructT->getElementType(i) != StructT->getElementType(0))
66  return false;
67  return isSupportedType(DL, TLI, StructT->getElementType(0));
68  }
69 
70  EVT VT = TLI.getValueType(DL, T, true);
71  if (!VT.isSimple() || VT.isVector() ||
72  !(VT.isInteger() || VT.isFloatingPoint()))
73  return false;
74 
75  unsigned VTSize = VT.getSimpleVT().getSizeInBits();
76 
77  if (VTSize == 64)
78  // FIXME: Support i64 too
79  return VT.isFloatingPoint();
80 
81  return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
82 }
83 
84 namespace {
85 
86 /// Helper class for values going out through an ABI boundary (used for handling
87 /// function return values and call parameters).
88 struct OutgoingValueHandler : public CallLowering::ValueHandler {
89  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
90  MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
91  : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
92 
93  Register getStackAddress(uint64_t Size, int64_t Offset,
94  MachinePointerInfo &MPO) override {
95  assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
96  "Unsupported size");
97 
98  LLT p0 = LLT::pointer(0, 32);
99  LLT s32 = LLT::scalar(32);
100  Register SPReg = MRI.createGenericVirtualRegister(p0);
101  MIRBuilder.buildCopy(SPReg, Register(ARM::SP));
102 
103  Register OffsetReg = MRI.createGenericVirtualRegister(s32);
104  MIRBuilder.buildConstant(OffsetReg, Offset);
105 
106  Register AddrReg = MRI.createGenericVirtualRegister(p0);
107  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
108 
109  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
110  return AddrReg;
111  }
112 
113  void assignValueToReg(Register ValVReg, Register PhysReg,
114  CCValAssign &VA) override {
115  assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
116  assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
117 
118  assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
119  assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
120 
121  Register ExtReg = extendRegister(ValVReg, VA);
122  MIRBuilder.buildCopy(PhysReg, ExtReg);
123  MIB.addUse(PhysReg, RegState::Implicit);
124  }
125 
126  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
127  MachinePointerInfo &MPO, CCValAssign &VA) override {
128  assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
129  "Unsupported size");
130 
131  Register ExtReg = extendRegister(ValVReg, VA);
132  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
134  /* Alignment */ 1);
135  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
136  }
137 
138  unsigned assignCustomValue(const CallLowering::ArgInfo &Arg,
139  ArrayRef<CCValAssign> VAs) override {
140  assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
141 
142  CCValAssign VA = VAs[0];
143  assert(VA.needsCustom() && "Value doesn't need custom handling");
144  assert(VA.getValVT() == MVT::f64 && "Unsupported type");
145 
146  CCValAssign NextVA = VAs[1];
147  assert(NextVA.needsCustom() && "Value doesn't need custom handling");
148  assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
149 
150  assert(VA.getValNo() == NextVA.getValNo() &&
151  "Values belong to different arguments");
152 
153  assert(VA.isRegLoc() && "Value should be in reg");
154  assert(NextVA.isRegLoc() && "Value should be in reg");
155 
156  Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
158  MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
159 
160  bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
161  if (!IsLittle)
162  std::swap(NewRegs[0], NewRegs[1]);
163 
164  assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
165  assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
166 
167  return 1;
168  }
169 
170  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
171  CCValAssign::LocInfo LocInfo,
172  const CallLowering::ArgInfo &Info, CCState &State) override {
173  if (AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State))
174  return true;
175 
176  StackSize =
177  std::max(StackSize, static_cast<uint64_t>(State.getNextStackOffset()));
178  return false;
179  }
180 
181  MachineInstrBuilder &MIB;
182  uint64_t StackSize = 0;
183 };
184 
185 } // end anonymous namespace
186 
187 void ARMCallLowering::splitToValueTypes(const ArgInfo &OrigArg,
188  SmallVectorImpl<ArgInfo> &SplitArgs,
189  MachineFunction &MF) const {
190  const ARMTargetLowering &TLI = *getTLI<ARMTargetLowering>();
191  LLVMContext &Ctx = OrigArg.Ty->getContext();
192  const DataLayout &DL = MF.getDataLayout();
193  const Function &F = MF.getFunction();
194 
195  SmallVector<EVT, 4> SplitVTs;
196  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, nullptr, nullptr, 0);
197  assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
198 
199  if (SplitVTs.size() == 1) {
200  // Even if there is no splitting to do, we still want to replace the
201  // original type (e.g. pointer type -> integer).
202  auto Flags = OrigArg.Flags;
203  unsigned OriginalAlignment = DL.getABITypeAlignment(OrigArg.Ty);
204  Flags.setOrigAlign(OriginalAlignment);
205  SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
206  Flags, OrigArg.IsFixed);
207  return;
208  }
209 
210  // Create one ArgInfo for each virtual register.
211  for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) {
212  EVT SplitVT = SplitVTs[i];
213  Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
214  auto Flags = OrigArg.Flags;
215 
216  unsigned OriginalAlignment = DL.getABITypeAlignment(SplitTy);
217  Flags.setOrigAlign(OriginalAlignment);
218 
219  bool NeedsConsecutiveRegisters =
221  SplitTy, F.getCallingConv(), F.isVarArg());
222  if (NeedsConsecutiveRegisters) {
223  Flags.setInConsecutiveRegs();
224  if (i == e - 1)
225  Flags.setInConsecutiveRegsLast();
226  }
227 
228  // FIXME: We also want to split SplitTy further.
229  Register PartReg = OrigArg.Regs[i];
230  SplitArgs.emplace_back(PartReg, SplitTy, Flags, OrigArg.IsFixed);
231  }
232 }
233 
234 /// Lower the return value for the already existing \p Ret. This assumes that
235 /// \p MIRBuilder's insertion point is correct.
236 bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
237  const Value *Val, ArrayRef<Register> VRegs,
238  MachineInstrBuilder &Ret) const {
239  if (!Val)
240  // Nothing to do here.
241  return true;
242 
243  auto &MF = MIRBuilder.getMF();
244  const auto &F = MF.getFunction();
245 
246  auto DL = MF.getDataLayout();
247  auto &TLI = *getTLI<ARMTargetLowering>();
248  if (!isSupportedType(DL, TLI, Val->getType()))
249  return false;
250 
251  ArgInfo OrigRetInfo(VRegs, Val->getType());
252  setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
253 
254  SmallVector<ArgInfo, 4> SplitRetInfos;
255  splitToValueTypes(OrigRetInfo, SplitRetInfos, MF);
256 
257  CCAssignFn *AssignFn =
258  TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
259 
260  OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn);
261  return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler);
262 }
263 
265  const Value *Val,
266  ArrayRef<Register> VRegs) const {
267  assert(!Val == VRegs.empty() && "Return value without a vreg");
268 
269  auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
270  unsigned Opcode = ST.getReturnOpcode();
271  auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
272 
273  if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
274  return false;
275 
276  MIRBuilder.insertInstr(Ret);
277  return true;
278 }
279 
280 namespace {
281 
282 /// Helper class for values coming in through an ABI boundary (used for handling
283 /// formal arguments and call return values).
284 struct IncomingValueHandler : public CallLowering::ValueHandler {
285  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
286  CCAssignFn AssignFn)
287  : ValueHandler(MIRBuilder, MRI, AssignFn) {}
288 
289  bool isIncomingArgumentHandler() const override { return true; }
290 
291  Register getStackAddress(uint64_t Size, int64_t Offset,
292  MachinePointerInfo &MPO) override {
293  assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
294  "Unsupported size");
295 
296  auto &MFI = MIRBuilder.getMF().getFrameInfo();
297 
298  int FI = MFI.CreateFixedObject(Size, Offset, true);
299  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
300 
301  Register AddrReg =
303  MIRBuilder.buildFrameIndex(AddrReg, FI);
304 
305  return AddrReg;
306  }
307 
308  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
309  MachinePointerInfo &MPO, CCValAssign &VA) override {
310  assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
311  "Unsupported size");
312 
313  if (VA.getLocInfo() == CCValAssign::SExt ||
314  VA.getLocInfo() == CCValAssign::ZExt) {
315  // If the value is zero- or sign-extended, its size becomes 4 bytes, so
316  // that's what we should load.
317  Size = 4;
318  assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
319 
320  auto LoadVReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
321  buildLoad(LoadVReg, Addr, Size, /* Alignment */ 1, MPO);
322  MIRBuilder.buildTrunc(ValVReg, LoadVReg);
323  } else {
324  // If the value is not extended, a simple load will suffice.
325  buildLoad(ValVReg, Addr, Size, /* Alignment */ 1, MPO);
326  }
327  }
328 
329  void buildLoad(Register Val, Register Addr, uint64_t Size, unsigned Alignment,
330  MachinePointerInfo &MPO) {
331  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
332  MPO, MachineMemOperand::MOLoad, Size, Alignment);
333  MIRBuilder.buildLoad(Val, Addr, *MMO);
334  }
335 
336  void assignValueToReg(Register ValVReg, Register PhysReg,
337  CCValAssign &VA) override {
338  assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
339  assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
340 
341  auto ValSize = VA.getValVT().getSizeInBits();
342  auto LocSize = VA.getLocVT().getSizeInBits();
343 
344  assert(ValSize <= 64 && "Unsupported value size");
345  assert(LocSize <= 64 && "Unsupported location size");
346 
347  markPhysRegUsed(PhysReg);
348  if (ValSize == LocSize) {
349  MIRBuilder.buildCopy(ValVReg, PhysReg);
350  } else {
351  assert(ValSize < LocSize && "Extensions not supported");
352 
353  // We cannot create a truncating copy, nor a trunc of a physical register.
354  // Therefore, we need to copy the content of the physical register into a
355  // virtual one and then truncate that.
356  auto PhysRegToVReg =
358  MIRBuilder.buildCopy(PhysRegToVReg, PhysReg);
359  MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);
360  }
361  }
362 
363  unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg,
364  ArrayRef<CCValAssign> VAs) override {
365  assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
366 
367  CCValAssign VA = VAs[0];
368  assert(VA.needsCustom() && "Value doesn't need custom handling");
369  assert(VA.getValVT() == MVT::f64 && "Unsupported type");
370 
371  CCValAssign NextVA = VAs[1];
372  assert(NextVA.needsCustom() && "Value doesn't need custom handling");
373  assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
374 
375  assert(VA.getValNo() == NextVA.getValNo() &&
376  "Values belong to different arguments");
377 
378  assert(VA.isRegLoc() && "Value should be in reg");
379  assert(NextVA.isRegLoc() && "Value should be in reg");
380 
381  Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
383 
384  assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
385  assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
386 
387  bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
388  if (!IsLittle)
389  std::swap(NewRegs[0], NewRegs[1]);
390 
391  MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
392 
393  return 1;
394  }
395 
396  /// Marking a physical register as used is different between formal
397  /// parameters, where it's a basic block live-in, and call returns, where it's
398  /// an implicit-def of the call instruction.
399  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
400 };
401 
402 struct FormalArgHandler : public IncomingValueHandler {
403  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
404  CCAssignFn AssignFn)
405  : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
406 
407  void markPhysRegUsed(unsigned PhysReg) override {
408  MIRBuilder.getMRI()->addLiveIn(PhysReg);
409  MIRBuilder.getMBB().addLiveIn(PhysReg);
410  }
411 };
412 
413 } // end anonymous namespace
414 
416  MachineIRBuilder &MIRBuilder, const Function &F,
417  ArrayRef<ArrayRef<Register>> VRegs) const {
418  auto &TLI = *getTLI<ARMTargetLowering>();
419  auto Subtarget = TLI.getSubtarget();
420 
421  if (Subtarget->isThumb1Only())
422  return false;
423 
424  // Quick exit if there aren't any args
425  if (F.arg_empty())
426  return true;
427 
428  if (F.isVarArg())
429  return false;
430 
431  auto &MF = MIRBuilder.getMF();
432  auto &MBB = MIRBuilder.getMBB();
433  auto DL = MF.getDataLayout();
434 
435  for (auto &Arg : F.args()) {
436  if (!isSupportedType(DL, TLI, Arg.getType()))
437  return false;
438  if (Arg.hasByValOrInAllocaAttr())
439  return false;
440  }
441 
442  CCAssignFn *AssignFn =
443  TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
444 
445  FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
446  AssignFn);
447 
448  SmallVector<ArgInfo, 8> SplitArgInfos;
449  unsigned Idx = 0;
450  for (auto &Arg : F.args()) {
451  ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType());
452 
453  setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F);
454  splitToValueTypes(OrigArgInfo, SplitArgInfos, MF);
455 
456  Idx++;
457  }
458 
459  if (!MBB.empty())
460  MIRBuilder.setInstr(*MBB.begin());
461 
462  if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler))
463  return false;
464 
465  // Move back to the end of the basic block.
466  MIRBuilder.setMBB(MBB);
467  return true;
468 }
469 
470 namespace {
471 
472 struct CallReturnHandler : public IncomingValueHandler {
473  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
474  MachineInstrBuilder MIB, CCAssignFn *AssignFn)
475  : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
476 
477  void markPhysRegUsed(unsigned PhysReg) override {
478  MIB.addDef(PhysReg, RegState::Implicit);
479  }
480 
482 };
483 
484 // FIXME: This should move to the ARMSubtarget when it supports all the opcodes.
485 unsigned getCallOpcode(const ARMSubtarget &STI, bool isDirect) {
486  if (isDirect)
487  return STI.isThumb() ? ARM::tBL : ARM::BL;
488 
489  if (STI.isThumb())
490  return ARM::tBLXr;
491 
492  if (STI.hasV5TOps())
493  return ARM::BLX;
494 
495  if (STI.hasV4TOps())
496  return ARM::BX_CALL;
497 
498  return ARM::BMOVPCRX_CALL;
499 }
500 } // end anonymous namespace
501 
503  MachineFunction &MF = MIRBuilder.getMF();
504  const auto &TLI = *getTLI<ARMTargetLowering>();
505  const auto &DL = MF.getDataLayout();
506  const auto &STI = MF.getSubtarget<ARMSubtarget>();
507  const TargetRegisterInfo *TRI = STI.getRegisterInfo();
509 
510  if (STI.genLongCalls())
511  return false;
512 
513  if (STI.isThumb1Only())
514  return false;
515 
516  auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
517 
518  // Create the call instruction so we can add the implicit uses of arg
519  // registers, but don't insert it yet.
520  bool IsDirect = !Info.Callee.isReg();
521  auto CallOpcode = getCallOpcode(STI, IsDirect);
522  auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode);
523 
524  bool IsThumb = STI.isThumb();
525  if (IsThumb)
526  MIB.add(predOps(ARMCC::AL));
527 
528  MIB.add(Info.Callee);
529  if (!IsDirect) {
530  auto CalleeReg = Info.Callee.getReg();
531  if (CalleeReg && !Register::isPhysicalRegister(CalleeReg)) {
532  unsigned CalleeIdx = IsThumb ? 2 : 0;
533  MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
534  MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),
535  *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx));
536  }
537  }
538 
539  MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
540 
541  bool IsVarArg = false;
542  SmallVector<ArgInfo, 8> ArgInfos;
543  for (auto Arg : Info.OrigArgs) {
544  if (!isSupportedType(DL, TLI, Arg.Ty))
545  return false;
546 
547  if (!Arg.IsFixed)
548  IsVarArg = true;
549 
550  if (Arg.Flags.isByVal())
551  return false;
552 
553  splitToValueTypes(Arg, ArgInfos, MF);
554  }
555 
556  auto ArgAssignFn = TLI.CCAssignFnForCall(Info.CallConv, IsVarArg);
557  OutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
558  if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))
559  return false;
560 
561  // Now we can add the actual call instruction to the correct basic block.
562  MIRBuilder.insertInstr(MIB);
563 
564  if (!Info.OrigRet.Ty->isVoidTy()) {
565  if (!isSupportedType(DL, TLI, Info.OrigRet.Ty))
566  return false;
567 
568  ArgInfos.clear();
569  splitToValueTypes(Info.OrigRet, ArgInfos, MF);
570  auto RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, IsVarArg);
571  CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
572  if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler))
573  return false;
574  }
575 
576  // We now know the size of the stack - update the ADJCALLSTACKDOWN
577  // accordingly.
578  CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
579 
580  MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
581  .addImm(ArgHandler.StackSize)
582  .addImm(0)
583  .add(predOps(ARMCC::AL));
584 
585  return true;
586 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:641
MachineOperand Callee
Destination of the call.
Definition: CallLowering.h:70
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
bool isThumb() const
Definition: ARMSubtarget.h:755
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register getLocReg() const
bool hasV4TOps() const
Definition: ARMSubtarget.h:569
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
bool isScalar() const
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
unsigned const TargetRegisterInfo * TRI
F(f)
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
bool handleAssignments(MachineIRBuilder &MIRBuilder, ArrayRef< ArgInfo > Args, ValueHandler &Handler) const
Invoke Handler::assignArg on each of the given Args and then use Callback to move them to the assigne...
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:261
ARMCallLowering(const ARMTargetLowering &TLI)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
unsigned getSizeInBits() const
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
bool arg_empty() const
Definition: Function.h:729
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:119
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:140
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineRegisterInfo * getMRI()
Getter for MRI.
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Helper class to build MachineInstr.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
MachineInstrBuilder buildGEP(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_GEP Op0, Op1.
Extended Value Type.
Definition: ValueTypes.h:33
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:91
This class contains a discriminated union of information about pointers in memory operands...
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
The memory access writes data.
SmallVector< ArgInfo, 8 > OrigArgs
List of descriptors of the arguments passed to the function.
Definition: CallLowering.h:76
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
CCState - This class holds information needed while lowering arguments and return values...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
CCValAssign - Represent assignment of one arg/retval to a location.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:752
Promote Memory to Register
Definition: Mem2Reg.cpp:109
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This file declares the MachineIRBuilder class.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
unsigned getReturnOpcode() const
Returns the correct return opcode for the current feature set.
Definition: ARMSubtarget.h:847
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
CallingConv::ID CallConv
Calling convention to be used for the call.
Definition: CallLowering.h:66
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs...
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
uint32_t Size
Definition: Profile.cpp:46
static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI, Type *T)
bool hasV5TOps() const
Definition: ARMSubtarget.h:570
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
LLVM Value Representation.
Definition: Value.h:73
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:47
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Type * getArrayElementType() const
Definition: Type.h:364
This file describes how to lower LLVM calls to machine code calls.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Register getReg() const
getReg - Returns the register number.
ArgInfo OrigRet
Descriptor for the return type of the function.
Definition: CallLowering.h:73
iterator_range< arg_iterator > args()
Definition: Function.h:719
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isStructTy() const
True if this is an instance of StructType.
Definition: Type.h:217
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:220