LLVM  9.0.0svn
LegalizeFloatTypes.cpp
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1 //===-------- LegalizeFloatTypes.cpp - Legalization of float types --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements float type expansion and softening for LegalizeTypes.
10 // Softening is the act of turning a computation in an illegal floating point
11 // type into a computation in an integer type of the same size; also known as
12 // "soft float". For example, turning f32 arithmetic into operations using i32.
13 // The resulting integer value is the same as what you would get by performing
14 // the floating point operation and bitcasting the result to the integer type.
15 // Expansion is the act of changing a computation in an illegal type to be a
16 // computation in two identical registers of a smaller type. For example,
17 // implementing ppcf128 arithmetic in two f64 registers.
18 //
19 //===----------------------------------------------------------------------===//
20 
21 #include "LegalizeTypes.h"
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "legalize-types"
27 
28 /// GetFPLibCall - Return the right libcall for the given floating point type.
30  RTLIB::Libcall Call_F32,
31  RTLIB::Libcall Call_F64,
32  RTLIB::Libcall Call_F80,
33  RTLIB::Libcall Call_F128,
34  RTLIB::Libcall Call_PPCF128) {
35  return
36  VT == MVT::f32 ? Call_F32 :
37  VT == MVT::f64 ? Call_F64 :
38  VT == MVT::f80 ? Call_F80 :
39  VT == MVT::f128 ? Call_F128 :
40  VT == MVT::ppcf128 ? Call_PPCF128 :
41  RTLIB::UNKNOWN_LIBCALL;
42 }
43 
44 //===----------------------------------------------------------------------===//
45 // Convert Float Results to Integer for Non-HW-supported Operations.
46 //===----------------------------------------------------------------------===//
47 
48 bool DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
49  LLVM_DEBUG(dbgs() << "Soften float result " << ResNo << ": "; N->dump(&DAG);
50  dbgs() << "\n");
51  SDValue R = SDValue();
52 
53  switch (N->getOpcode()) {
54  default:
55 #ifndef NDEBUG
56  dbgs() << "SoftenFloatResult #" << ResNo << ": ";
57  N->dump(&DAG); dbgs() << "\n";
58 #endif
59  llvm_unreachable("Do not know how to soften the result of this operator!");
60 
61  case ISD::Register:
62  case ISD::CopyFromReg:
63  case ISD::CopyToReg:
64  assert(isLegalInHWReg(N->getValueType(ResNo)) &&
65  "Unsupported SoftenFloatRes opcode!");
66  // Only when isLegalInHWReg, we can skip check of the operands.
67  R = SDValue(N, ResNo);
68  break;
69  case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
70  case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N, ResNo); break;
71  case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break;
72  case ISD::ConstantFP: R = SoftenFloatRes_ConstantFP(N, ResNo); break;
74  R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break;
75  case ISD::FABS: R = SoftenFloatRes_FABS(N, ResNo); break;
76  case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break;
77  case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break;
78  case ISD::FADD: R = SoftenFloatRes_FADD(N); break;
79  case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break;
80  case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N, ResNo); break;
81  case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break;
82  case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break;
83  case ISD::FEXP: R = SoftenFloatRes_FEXP(N); break;
84  case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break;
85  case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break;
86  case ISD::FLOG: R = SoftenFloatRes_FLOG(N); break;
87  case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break;
88  case ISD::FLOG10: R = SoftenFloatRes_FLOG10(N); break;
89  case ISD::FMA: R = SoftenFloatRes_FMA(N); break;
90  case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break;
91  case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break;
92  case ISD::FNEG: R = SoftenFloatRes_FNEG(N, ResNo); break;
93  case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break;
94  case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break;
95  case ISD::FP16_TO_FP: R = SoftenFloatRes_FP16_TO_FP(N); break;
96  case ISD::FPOW: R = SoftenFloatRes_FPOW(N); break;
97  case ISD::FPOWI: R = SoftenFloatRes_FPOWI(N); break;
98  case ISD::FREM: R = SoftenFloatRes_FREM(N); break;
99  case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break;
100  case ISD::FROUND: R = SoftenFloatRes_FROUND(N); break;
101  case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break;
102  case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break;
103  case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
104  case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break;
105  case ISD::LOAD: R = SoftenFloatRes_LOAD(N, ResNo); break;
106  case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break;
107  case ISD::SELECT: R = SoftenFloatRes_SELECT(N, ResNo); break;
108  case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N, ResNo); break;
109  case ISD::SINT_TO_FP:
110  case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break;
111  case ISD::UNDEF: R = SoftenFloatRes_UNDEF(N); break;
112  case ISD::VAARG: R = SoftenFloatRes_VAARG(N); break;
113  }
114 
115  if (R.getNode() && R.getNode() != N) {
116  SetSoftenedFloat(SDValue(N, ResNo), R);
117  // Return true only if the node is changed, assuming that the operands
118  // are also converted when necessary.
119  return true;
120  }
121 
122  // Otherwise, return false to tell caller to scan operands.
123  return false;
124 }
125 
126 SDValue DAGTypeLegalizer::SoftenFloatRes_BITCAST(SDNode *N, unsigned ResNo) {
127  if (isLegalInHWReg(N->getValueType(ResNo)))
128  return SDValue(N, ResNo);
129  return BitConvertToInteger(N->getOperand(0));
130 }
131 
132 SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(SDNode *N,
133  unsigned ResNo) {
134  SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
135  return BitConvertToInteger(Op);
136 }
137 
138 SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
139  // Convert the inputs to integers, and build a new pair out of them.
140  return DAG.getNode(ISD::BUILD_PAIR, SDLoc(N),
141  TLI.getTypeToTransformTo(*DAG.getContext(),
142  N->getValueType(0)),
143  BitConvertToInteger(N->getOperand(0)),
144  BitConvertToInteger(N->getOperand(1)));
145 }
146 
147 SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode *N, unsigned ResNo) {
148  // When LegalInHWReg, we can load better from the constant pool.
149  if (isLegalInHWReg(N->getValueType(ResNo)))
150  return SDValue(N, ResNo);
151  ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
152  // In ppcf128, the high 64 bits are always first in memory regardless
153  // of Endianness. LLVM's APFloat representation is not Endian sensitive,
154  // and so always converts into a 128-bit APInt in a non-Endian-sensitive
155  // way. However, APInt's are serialized in an Endian-sensitive fashion,
156  // so on big-Endian targets, the two doubles are output in the wrong
157  // order. Fix this by manually flipping the order of the high 64 bits
158  // and the low 64 bits here.
159  if (DAG.getDataLayout().isBigEndian() &&
161  uint64_t words[2] = { CN->getValueAPF().bitcastToAPInt().getRawData()[1],
162  CN->getValueAPF().bitcastToAPInt().getRawData()[0] };
163  APInt Val(128, words);
164  return DAG.getConstant(Val, SDLoc(CN),
165  TLI.getTypeToTransformTo(*DAG.getContext(),
166  CN->getValueType(0)));
167  } else {
168  return DAG.getConstant(CN->getValueAPF().bitcastToAPInt(), SDLoc(CN),
169  TLI.getTypeToTransformTo(*DAG.getContext(),
170  CN->getValueType(0)));
171  }
172 }
173 
174 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo) {
175  // When LegalInHWReg, keep the extracted value in register.
176  if (isLegalInHWReg(N->getValueType(ResNo)))
177  return SDValue(N, ResNo);
178  SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
179  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
181  NewOp, N->getOperand(1));
182 }
183 
184 SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N, unsigned ResNo) {
185  // When LegalInHWReg, FABS can be implemented as native bitwise operations.
186  if (isLegalInHWReg(N->getValueType(ResNo)))
187  return SDValue(N, ResNo);
188  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
189  unsigned Size = NVT.getSizeInBits();
190 
191  // Mask = ~(1 << (Size-1))
192  APInt API = APInt::getAllOnesValue(Size);
193  API.clearBit(Size - 1);
194  SDValue Mask = DAG.getConstant(API, SDLoc(N), NVT);
195  SDValue Op = GetSoftenedFloat(N->getOperand(0));
196  return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
197 }
198 
199 SDValue DAGTypeLegalizer::SoftenFloatRes_FMINNUM(SDNode *N) {
200  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
201  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
202  GetSoftenedFloat(N->getOperand(1)) };
203  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
204  RTLIB::FMIN_F32,
205  RTLIB::FMIN_F64,
206  RTLIB::FMIN_F80,
207  RTLIB::FMIN_F128,
208  RTLIB::FMIN_PPCF128),
209  NVT, Ops, false, SDLoc(N)).first;
210 }
211 
212 SDValue DAGTypeLegalizer::SoftenFloatRes_FMAXNUM(SDNode *N) {
213  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
214  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
215  GetSoftenedFloat(N->getOperand(1)) };
216  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
217  RTLIB::FMAX_F32,
218  RTLIB::FMAX_F64,
219  RTLIB::FMAX_F80,
220  RTLIB::FMAX_F128,
221  RTLIB::FMAX_PPCF128),
222  NVT, Ops, false, SDLoc(N)).first;
223 }
224 
225 SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
226  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
227  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
228  GetSoftenedFloat(N->getOperand(1)) };
229  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
230  RTLIB::ADD_F32,
231  RTLIB::ADD_F64,
232  RTLIB::ADD_F80,
233  RTLIB::ADD_F128,
234  RTLIB::ADD_PPCF128),
235  NVT, Ops, false, SDLoc(N)).first;
236 }
237 
238 SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) {
239  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
240  SDValue Op = GetSoftenedFloat(N->getOperand(0));
241  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
242  RTLIB::CEIL_F32,
243  RTLIB::CEIL_F64,
244  RTLIB::CEIL_F80,
245  RTLIB::CEIL_F128,
246  RTLIB::CEIL_PPCF128),
247  NVT, Op, false, SDLoc(N)).first;
248 }
249 
250 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N, unsigned ResNo) {
251  // When LegalInHWReg, FCOPYSIGN can be implemented as native bitwise operations.
252  if (isLegalInHWReg(N->getValueType(ResNo)))
253  return SDValue(N, ResNo);
254  SDValue LHS = GetSoftenedFloat(N->getOperand(0));
255  SDValue RHS = BitConvertToInteger(N->getOperand(1));
256  SDLoc dl(N);
257 
258  EVT LVT = LHS.getValueType();
259  EVT RVT = RHS.getValueType();
260 
261  unsigned LSize = LVT.getSizeInBits();
262  unsigned RSize = RVT.getSizeInBits();
263 
264  // First get the sign bit of second operand.
265  SDValue SignBit = DAG.getNode(
266  ISD::SHL, dl, RVT, DAG.getConstant(1, dl, RVT),
267  DAG.getConstant(RSize - 1, dl,
268  TLI.getShiftAmountTy(RVT, DAG.getDataLayout())));
269  SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit);
270 
271  // Shift right or sign-extend it if the two operands have different types.
272  int SizeDiff = RVT.getSizeInBits() - LVT.getSizeInBits();
273  if (SizeDiff > 0) {
274  SignBit =
275  DAG.getNode(ISD::SRL, dl, RVT, SignBit,
276  DAG.getConstant(SizeDiff, dl,
277  TLI.getShiftAmountTy(SignBit.getValueType(),
278  DAG.getDataLayout())));
279  SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit);
280  } else if (SizeDiff < 0) {
281  SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit);
282  SignBit =
283  DAG.getNode(ISD::SHL, dl, LVT, SignBit,
284  DAG.getConstant(-SizeDiff, dl,
285  TLI.getShiftAmountTy(SignBit.getValueType(),
286  DAG.getDataLayout())));
287  }
288 
289  // Clear the sign bit of the first operand.
290  SDValue Mask = DAG.getNode(
291  ISD::SHL, dl, LVT, DAG.getConstant(1, dl, LVT),
292  DAG.getConstant(LSize - 1, dl,
293  TLI.getShiftAmountTy(LVT, DAG.getDataLayout())));
294  Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, dl, LVT));
295  LHS = DAG.getNode(ISD::AND, dl, LVT, LHS, Mask);
296 
297  // Or the value with the sign bit.
298  return DAG.getNode(ISD::OR, dl, LVT, LHS, SignBit);
299 }
300 
301 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N) {
302  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
303  SDValue Op = GetSoftenedFloat(N->getOperand(0));
304  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
305  RTLIB::COS_F32,
306  RTLIB::COS_F64,
307  RTLIB::COS_F80,
308  RTLIB::COS_F128,
309  RTLIB::COS_PPCF128),
310  NVT, Op, false, SDLoc(N)).first;
311 }
312 
313 SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
314  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
315  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
316  GetSoftenedFloat(N->getOperand(1)) };
317  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
318  RTLIB::DIV_F32,
319  RTLIB::DIV_F64,
320  RTLIB::DIV_F80,
321  RTLIB::DIV_F128,
322  RTLIB::DIV_PPCF128),
323  NVT, Ops, false, SDLoc(N)).first;
324 }
325 
326 SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP(SDNode *N) {
327  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
328  SDValue Op = GetSoftenedFloat(N->getOperand(0));
329  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
330  RTLIB::EXP_F32,
331  RTLIB::EXP_F64,
332  RTLIB::EXP_F80,
333  RTLIB::EXP_F128,
334  RTLIB::EXP_PPCF128),
335  NVT, Op, false, SDLoc(N)).first;
336 }
337 
338 SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP2(SDNode *N) {
339  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
340  SDValue Op = GetSoftenedFloat(N->getOperand(0));
341  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
342  RTLIB::EXP2_F32,
343  RTLIB::EXP2_F64,
344  RTLIB::EXP2_F80,
345  RTLIB::EXP2_F128,
346  RTLIB::EXP2_PPCF128),
347  NVT, Op, false, SDLoc(N)).first;
348 }
349 
350 SDValue DAGTypeLegalizer::SoftenFloatRes_FFLOOR(SDNode *N) {
351  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
352  SDValue Op = GetSoftenedFloat(N->getOperand(0));
353  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
354  RTLIB::FLOOR_F32,
355  RTLIB::FLOOR_F64,
356  RTLIB::FLOOR_F80,
357  RTLIB::FLOOR_F128,
358  RTLIB::FLOOR_PPCF128),
359  NVT, Op, false, SDLoc(N)).first;
360 }
361 
362 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG(SDNode *N) {
363  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
364  SDValue Op = GetSoftenedFloat(N->getOperand(0));
365  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
366  RTLIB::LOG_F32,
367  RTLIB::LOG_F64,
368  RTLIB::LOG_F80,
369  RTLIB::LOG_F128,
370  RTLIB::LOG_PPCF128),
371  NVT, Op, false, SDLoc(N)).first;
372 }
373 
374 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG2(SDNode *N) {
375  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
376  SDValue Op = GetSoftenedFloat(N->getOperand(0));
377  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
378  RTLIB::LOG2_F32,
379  RTLIB::LOG2_F64,
380  RTLIB::LOG2_F80,
381  RTLIB::LOG2_F128,
382  RTLIB::LOG2_PPCF128),
383  NVT, Op, false, SDLoc(N)).first;
384 }
385 
386 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG10(SDNode *N) {
387  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
388  SDValue Op = GetSoftenedFloat(N->getOperand(0));
389  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
390  RTLIB::LOG10_F32,
391  RTLIB::LOG10_F64,
392  RTLIB::LOG10_F80,
393  RTLIB::LOG10_F128,
394  RTLIB::LOG10_PPCF128),
395  NVT, Op, false, SDLoc(N)).first;
396 }
397 
398 SDValue DAGTypeLegalizer::SoftenFloatRes_FMA(SDNode *N) {
399  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
400  SDValue Ops[3] = { GetSoftenedFloat(N->getOperand(0)),
401  GetSoftenedFloat(N->getOperand(1)),
402  GetSoftenedFloat(N->getOperand(2)) };
403  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
404  RTLIB::FMA_F32,
405  RTLIB::FMA_F64,
406  RTLIB::FMA_F80,
407  RTLIB::FMA_F128,
408  RTLIB::FMA_PPCF128),
409  NVT, Ops, false, SDLoc(N)).first;
410 }
411 
412 SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
413  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
414  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
415  GetSoftenedFloat(N->getOperand(1)) };
416  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
417  RTLIB::MUL_F32,
418  RTLIB::MUL_F64,
419  RTLIB::MUL_F80,
420  RTLIB::MUL_F128,
421  RTLIB::MUL_PPCF128),
422  NVT, Ops, false, SDLoc(N)).first;
423 }
424 
425 SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(SDNode *N) {
426  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
427  SDValue Op = GetSoftenedFloat(N->getOperand(0));
428  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
429  RTLIB::NEARBYINT_F32,
430  RTLIB::NEARBYINT_F64,
431  RTLIB::NEARBYINT_F80,
432  RTLIB::NEARBYINT_F128,
433  RTLIB::NEARBYINT_PPCF128),
434  NVT, Op, false, SDLoc(N)).first;
435 }
436 
437 SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N, unsigned ResNo) {
438  // When LegalInHWReg, FNEG can be implemented as native bitwise operations.
439  if (isLegalInHWReg(N->getValueType(ResNo)))
440  return SDValue(N, ResNo);
441  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
442  SDLoc dl(N);
443 
444  EVT FloatVT = N->getValueType(ResNo);
445  if (FloatVT == MVT::f32 || FloatVT == MVT::f64 || FloatVT == MVT::f128) {
446  // Expand Y = FNEG(X) -> Y = X ^ sign mask
447  APInt SignMask = APInt::getSignMask(NVT.getSizeInBits());
448  return DAG.getNode(ISD::XOR, dl, NVT, GetSoftenedFloat(N->getOperand(0)),
449  DAG.getConstant(SignMask, dl, NVT));
450  }
451 
452  // Expand Y = FNEG(X) -> Y = SUB -0.0, X
453  SDValue Ops[2] = { DAG.getConstantFP(-0.0, dl, N->getValueType(0)),
454  GetSoftenedFloat(N->getOperand(0)) };
455  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
456  RTLIB::SUB_F32,
457  RTLIB::SUB_F64,
458  RTLIB::SUB_F80,
459  RTLIB::SUB_F128,
460  RTLIB::SUB_PPCF128),
461  NVT, Ops, false, dl).first;
462 }
463 
464 SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
465  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
466  SDValue Op = N->getOperand(0);
467 
468  // There's only a libcall for f16 -> f32, so proceed in two stages. Also, it's
469  // entirely possible for both f16 and f32 to be legal, so use the fully
470  // hard-float FP_EXTEND rather than FP16_TO_FP.
471  if (Op.getValueType() == MVT::f16 && N->getValueType(0) != MVT::f32) {
472  Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op);
473  if (getTypeAction(MVT::f32) == TargetLowering::TypeSoftenFloat)
474  AddToWorklist(Op.getNode());
475  }
476 
477  if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat) {
478  Op = GetPromotedFloat(Op);
479  // If the promotion did the FP_EXTEND to the destination type for us,
480  // there's nothing left to do here.
481  if (Op.getValueType() == N->getValueType(0)) {
482  return BitConvertToInteger(Op);
483  }
484  }
485 
487  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
488  return TLI.makeLibCall(DAG, LC, NVT, Op, false, SDLoc(N)).first;
489 }
490 
491 // FIXME: Should we just use 'normal' FP_EXTEND / FP_TRUNC instead of special
492 // nodes?
493 SDValue DAGTypeLegalizer::SoftenFloatRes_FP16_TO_FP(SDNode *N) {
494  EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32);
495  SDValue Op = N->getOperand(0);
496  SDValue Res32 = TLI.makeLibCall(DAG, RTLIB::FPEXT_F16_F32, MidVT, Op,
497  false, SDLoc(N)).first;
498  if (N->getValueType(0) == MVT::f32)
499  return Res32;
500 
501  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
503  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
504  return TLI.makeLibCall(DAG, LC, NVT, Res32, false, SDLoc(N)).first;
505 }
506 
507 SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
508  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
509  SDValue Op = N->getOperand(0);
510  if (N->getValueType(0) == MVT::f16) {
511  // Semi-soften first, to FP_TO_FP16, so that targets which support f16 as a
512  // storage-only type get a chance to select things.
513  return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, Op);
514  }
515 
517  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
518  return TLI.makeLibCall(DAG, LC, NVT, Op, false, SDLoc(N)).first;
519 }
520 
521 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOW(SDNode *N) {
522  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
523  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
524  GetSoftenedFloat(N->getOperand(1)) };
525  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
526  RTLIB::POW_F32,
527  RTLIB::POW_F64,
528  RTLIB::POW_F80,
529  RTLIB::POW_F128,
530  RTLIB::POW_PPCF128),
531  NVT, Ops, false, SDLoc(N)).first;
532 }
533 
534 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
535  assert(N->getOperand(1).getValueType() == MVT::i32 &&
536  "Unsupported power type!");
537  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
538  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
539  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
540  RTLIB::POWI_F32,
541  RTLIB::POWI_F64,
542  RTLIB::POWI_F80,
543  RTLIB::POWI_F128,
544  RTLIB::POWI_PPCF128),
545  NVT, Ops, false, SDLoc(N)).first;
546 }
547 
548 SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) {
549  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
550  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
551  GetSoftenedFloat(N->getOperand(1)) };
552  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
553  RTLIB::REM_F32,
554  RTLIB::REM_F64,
555  RTLIB::REM_F80,
556  RTLIB::REM_F128,
557  RTLIB::REM_PPCF128),
558  NVT, Ops, false, SDLoc(N)).first;
559 }
560 
561 SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) {
562  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
563  SDValue Op = GetSoftenedFloat(N->getOperand(0));
564  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
565  RTLIB::RINT_F32,
566  RTLIB::RINT_F64,
567  RTLIB::RINT_F80,
568  RTLIB::RINT_F128,
569  RTLIB::RINT_PPCF128),
570  NVT, Op, false, SDLoc(N)).first;
571 }
572 
573 SDValue DAGTypeLegalizer::SoftenFloatRes_FROUND(SDNode *N) {
574  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
575  SDValue Op = GetSoftenedFloat(N->getOperand(0));
576  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
577  RTLIB::ROUND_F32,
578  RTLIB::ROUND_F64,
579  RTLIB::ROUND_F80,
580  RTLIB::ROUND_F128,
581  RTLIB::ROUND_PPCF128),
582  NVT, Op, false, SDLoc(N)).first;
583 }
584 
585 SDValue DAGTypeLegalizer::SoftenFloatRes_FSIN(SDNode *N) {
586  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
587  SDValue Op = GetSoftenedFloat(N->getOperand(0));
588  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
589  RTLIB::SIN_F32,
590  RTLIB::SIN_F64,
591  RTLIB::SIN_F80,
592  RTLIB::SIN_F128,
593  RTLIB::SIN_PPCF128),
594  NVT, Op, false, SDLoc(N)).first;
595 }
596 
597 SDValue DAGTypeLegalizer::SoftenFloatRes_FSQRT(SDNode *N) {
598  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
599  SDValue Op = GetSoftenedFloat(N->getOperand(0));
600  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
601  RTLIB::SQRT_F32,
602  RTLIB::SQRT_F64,
603  RTLIB::SQRT_F80,
604  RTLIB::SQRT_F128,
605  RTLIB::SQRT_PPCF128),
606  NVT, Op, false, SDLoc(N)).first;
607 }
608 
609 SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
610  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
611  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
612  GetSoftenedFloat(N->getOperand(1)) };
613  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
614  RTLIB::SUB_F32,
615  RTLIB::SUB_F64,
616  RTLIB::SUB_F80,
617  RTLIB::SUB_F128,
618  RTLIB::SUB_PPCF128),
619  NVT, Ops, false, SDLoc(N)).first;
620 }
621 
622 SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) {
623  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
624  if (N->getValueType(0) == MVT::f16)
625  return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, N->getOperand(0));
626 
627  SDValue Op = GetSoftenedFloat(N->getOperand(0));
628  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
629  RTLIB::TRUNC_F32,
630  RTLIB::TRUNC_F64,
631  RTLIB::TRUNC_F80,
632  RTLIB::TRUNC_F128,
633  RTLIB::TRUNC_PPCF128),
634  NVT, Op, false, SDLoc(N)).first;
635 }
636 
637 SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N, unsigned ResNo) {
638  bool LegalInHWReg = isLegalInHWReg(N->getValueType(ResNo));
639  LoadSDNode *L = cast<LoadSDNode>(N);
640  EVT VT = N->getValueType(0);
641  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
642  SDLoc dl(N);
643 
644  auto MMOFlags =
645  L->getMemOperand()->getFlags() &
647  SDValue NewL;
648  if (L->getExtensionType() == ISD::NON_EXTLOAD) {
649  NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), NVT, dl,
650  L->getChain(), L->getBasePtr(), L->getOffset(),
651  L->getPointerInfo(), NVT, L->getAlignment(), MMOFlags,
652  L->getAAInfo());
653  // Legalized the chain result - switch anything that used the old chain to
654  // use the new one.
655  if (N != NewL.getValue(1).getNode())
656  ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
657  return NewL;
658  }
659 
660  // Do a non-extending load followed by FP_EXTEND.
661  NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD, L->getMemoryVT(),
662  dl, L->getChain(), L->getBasePtr(), L->getOffset(),
663  L->getPointerInfo(), L->getMemoryVT(), L->getAlignment(),
664  MMOFlags, L->getAAInfo());
665  // Legalized the chain result - switch anything that used the old chain to
666  // use the new one.
667  ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
668  auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL);
669  if (LegalInHWReg)
670  return ExtendNode;
671  return BitConvertToInteger(ExtendNode);
672 }
673 
674 SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT(SDNode *N, unsigned ResNo) {
675  if (isLegalInHWReg(N->getValueType(ResNo)))
676  return SDValue(N, ResNo);
677  SDValue LHS = GetSoftenedFloat(N->getOperand(1));
678  SDValue RHS = GetSoftenedFloat(N->getOperand(2));
679  return DAG.getSelect(SDLoc(N),
680  LHS.getValueType(), N->getOperand(0), LHS, RHS);
681 }
682 
683 SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT_CC(SDNode *N, unsigned ResNo) {
684  if (isLegalInHWReg(N->getValueType(ResNo)))
685  return SDValue(N, ResNo);
686  SDValue LHS = GetSoftenedFloat(N->getOperand(2));
687  SDValue RHS = GetSoftenedFloat(N->getOperand(3));
688  return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
689  LHS.getValueType(), N->getOperand(0),
690  N->getOperand(1), LHS, RHS, N->getOperand(4));
691 }
692 
693 SDValue DAGTypeLegalizer::SoftenFloatRes_UNDEF(SDNode *N) {
694  return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
695  N->getValueType(0)));
696 }
697 
698 SDValue DAGTypeLegalizer::SoftenFloatRes_VAARG(SDNode *N) {
699  SDValue Chain = N->getOperand(0); // Get the chain.
700  SDValue Ptr = N->getOperand(1); // Get the pointer.
701  EVT VT = N->getValueType(0);
702  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
703  SDLoc dl(N);
704 
705  SDValue NewVAARG;
706  NewVAARG = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2),
707  N->getConstantOperandVal(3));
708 
709  // Legalized the chain result - switch anything that used the old chain to
710  // use the new one.
711  if (N != NewVAARG.getValue(1).getNode())
712  ReplaceValueWith(SDValue(N, 1), NewVAARG.getValue(1));
713  return NewVAARG;
714 }
715 
716 SDValue DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP(SDNode *N) {
717  bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
718  EVT SVT = N->getOperand(0).getValueType();
719  EVT RVT = N->getValueType(0);
720  EVT NVT = EVT();
721  SDLoc dl(N);
722 
723  // If the input is not legal, eg: i1 -> fp, then it needs to be promoted to
724  // a larger type, eg: i8 -> fp. Even if it is legal, no libcall may exactly
725  // match. Look for an appropriate libcall.
726  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
727  for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
728  t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
729  NVT = (MVT::SimpleValueType)t;
730  // The source needs to big enough to hold the operand.
731  if (NVT.bitsGE(SVT))
732  LC = Signed ? RTLIB::getSINTTOFP(NVT, RVT):RTLIB::getUINTTOFP (NVT, RVT);
733  }
734  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
735 
736  // Sign/zero extend the argument if the libcall takes a larger type.
737  SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
738  NVT, N->getOperand(0));
739  return TLI.makeLibCall(DAG, LC,
740  TLI.getTypeToTransformTo(*DAG.getContext(), RVT),
741  Op, Signed, dl).first;
742 }
743 
744 
745 //===----------------------------------------------------------------------===//
746 // Convert Float Operand to Integer for Non-HW-supported Operations.
747 //===----------------------------------------------------------------------===//
748 
749 bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
750  LLVM_DEBUG(dbgs() << "Soften float operand " << OpNo << ": "; N->dump(&DAG);
751  dbgs() << "\n");
752  SDValue Res = SDValue();
753 
754  switch (N->getOpcode()) {
755  default:
756  if (CanSkipSoftenFloatOperand(N, OpNo))
757  return false;
758 #ifndef NDEBUG
759  dbgs() << "SoftenFloatOperand Op #" << OpNo << ": ";
760  N->dump(&DAG); dbgs() << "\n";
761 #endif
762  llvm_unreachable("Do not know how to soften this operator's operand!");
763 
764  case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break;
765  case ISD::CopyToReg: Res = SoftenFloatOp_COPY_TO_REG(N); break;
766  case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break;
767  case ISD::FABS: Res = SoftenFloatOp_FABS(N); break;
768  case ISD::FCOPYSIGN: Res = SoftenFloatOp_FCOPYSIGN(N); break;
769  case ISD::FNEG: Res = SoftenFloatOp_FNEG(N); break;
770  case ISD::FP_EXTEND: Res = SoftenFloatOp_FP_EXTEND(N); break;
771  case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes
772  case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break;
773  case ISD::FP_TO_SINT:
774  case ISD::FP_TO_UINT: Res = SoftenFloatOp_FP_TO_XINT(N); break;
775  case ISD::LROUND: Res = SoftenFloatOp_LROUND(N); break;
776  case ISD::LLROUND: Res = SoftenFloatOp_LLROUND(N); break;
777  case ISD::LRINT: Res = SoftenFloatOp_LRINT(N); break;
778  case ISD::LLRINT: Res = SoftenFloatOp_LLRINT(N); break;
779  case ISD::SELECT: Res = SoftenFloatOp_SELECT(N); break;
780  case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break;
781  case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
782  case ISD::STORE:
783  Res = SoftenFloatOp_STORE(N, OpNo);
784  // Do not try to analyze or soften this node again if the value is
785  // or can be held in a register. In that case, Res.getNode() should
786  // be equal to N.
787  if (Res.getNode() == N &&
788  isLegalInHWReg(N->getOperand(OpNo).getValueType()))
789  return false;
790  // Otherwise, we need to reanalyze and lower the new Res nodes.
791  break;
792  }
793 
794  // If the result is null, the sub-method took care of registering results etc.
795  if (!Res.getNode()) return false;
796 
797  // If the result is N, the sub-method updated N in place. Tell the legalizer
798  // core about this to re-analyze.
799  if (Res.getNode() == N)
800  return true;
801 
802  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
803  "Invalid operand expansion");
804 
805  ReplaceValueWith(SDValue(N, 0), Res);
806  return false;
807 }
808 
809 bool DAGTypeLegalizer::CanSkipSoftenFloatOperand(SDNode *N, unsigned OpNo) {
810  if (!isLegalInHWReg(N->getOperand(OpNo).getValueType()))
811  return false;
812 
813  // When the operand type can be kept in registers there is nothing to do for
814  // the following opcodes.
815  switch (N->getOperand(OpNo).getOpcode()) {
816  case ISD::BITCAST:
817  case ISD::ConstantFP:
818  case ISD::CopyFromReg:
819  case ISD::CopyToReg:
820  case ISD::FABS:
821  case ISD::FCOPYSIGN:
822  case ISD::FNEG:
823  case ISD::Register:
824  case ISD::SELECT:
825  case ISD::SELECT_CC:
826  return true;
827  }
828 
829  switch (N->getOpcode()) {
830  case ISD::ConstantFP: // Leaf node.
831  case ISD::CopyFromReg: // Operand is a register that we know to be left
832  // unchanged by SoftenFloatResult().
833  case ISD::Register: // Leaf node.
834  return true;
835  }
836  return false;
837 }
838 
839 SDValue DAGTypeLegalizer::SoftenFloatOp_BITCAST(SDNode *N) {
840  return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
841  GetSoftenedFloat(N->getOperand(0)));
842 }
843 
844 SDValue DAGTypeLegalizer::SoftenFloatOp_COPY_TO_REG(SDNode *N) {
845  SDValue Op1 = GetSoftenedFloat(N->getOperand(1));
846  SDValue Op2 = GetSoftenedFloat(N->getOperand(2));
847 
848  if (Op1 == N->getOperand(1) && Op2 == N->getOperand(2))
849  return SDValue();
850 
851  if (N->getNumOperands() == 3)
852  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op1, Op2), 0);
853 
854  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op1, Op2,
855  N->getOperand(3)),
856  0);
857 }
858 
859 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_EXTEND(SDNode *N) {
860  // If we get here, the result must be legal but the source illegal.
861  EVT SVT = N->getOperand(0).getValueType();
862  EVT RVT = N->getValueType(0);
863  SDValue Op = GetSoftenedFloat(N->getOperand(0));
864 
865  if (SVT == MVT::f16)
866  return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), RVT, Op);
867 
868  RTLIB::Libcall LC = RTLIB::getFPEXT(SVT, RVT);
869  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND libcall");
870 
871  return TLI.makeLibCall(DAG, LC, RVT, Op, false, SDLoc(N)).first;
872 }
873 
874 
875 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_ROUND(SDNode *N) {
876  // We actually deal with the partially-softened FP_TO_FP16 node too, which
877  // returns an i16 so doesn't meet the constraints necessary for FP_ROUND.
879 
880  EVT SVT = N->getOperand(0).getValueType();
881  EVT RVT = N->getValueType(0);
882  EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT;
883 
884  RTLIB::Libcall LC = RTLIB::getFPROUND(SVT, FloatRVT);
885  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND libcall");
886 
887  SDValue Op = GetSoftenedFloat(N->getOperand(0));
888  return TLI.makeLibCall(DAG, LC, RVT, Op, false, SDLoc(N)).first;
889 }
890 
891 SDValue DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) {
892  SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
893  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
894 
895  EVT VT = NewLHS.getValueType();
896  NewLHS = GetSoftenedFloat(NewLHS);
897  NewRHS = GetSoftenedFloat(NewRHS);
898  TLI.softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, SDLoc(N));
899 
900  // If softenSetCCOperands returned a scalar, we need to compare the result
901  // against zero to select between true and false values.
902  if (!NewRHS.getNode()) {
903  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
904  CCCode = ISD::SETNE;
905  }
906 
907  // Update N to have the operands specified.
908  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
909  DAG.getCondCode(CCCode), NewLHS, NewRHS,
910  N->getOperand(4)),
911  0);
912 }
913 
914 SDValue DAGTypeLegalizer::SoftenFloatOp_FABS(SDNode *N) {
915  SDValue Op = GetSoftenedFloat(N->getOperand(0));
916 
917  if (Op == N->getOperand(0))
918  return SDValue();
919 
920  return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
921 }
922 
923 SDValue DAGTypeLegalizer::SoftenFloatOp_FCOPYSIGN(SDNode *N) {
924  SDValue Op0 = GetSoftenedFloat(N->getOperand(0));
925  SDValue Op1 = GetSoftenedFloat(N->getOperand(1));
926 
927  if (Op0 == N->getOperand(0) && Op1 == N->getOperand(1))
928  return SDValue();
929 
930  return SDValue(DAG.UpdateNodeOperands(N, Op0, Op1), 0);
931 }
932 
933 SDValue DAGTypeLegalizer::SoftenFloatOp_FNEG(SDNode *N) {
934  SDValue Op = GetSoftenedFloat(N->getOperand(0));
935 
936  if (Op == N->getOperand(0))
937  return SDValue();
938 
939  return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
940 }
941 
942 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_XINT(SDNode *N) {
943  bool Signed = N->getOpcode() == ISD::FP_TO_SINT;
944  EVT SVT = N->getOperand(0).getValueType();
945  EVT RVT = N->getValueType(0);
946  EVT NVT = EVT();
947  SDLoc dl(N);
948 
949  // If the result is not legal, eg: fp -> i1, then it needs to be promoted to
950  // a larger type, eg: fp -> i32. Even if it is legal, no libcall may exactly
951  // match, eg. we don't have fp -> i8 conversions.
952  // Look for an appropriate libcall.
953  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
954  for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE;
955  IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL;
956  ++IntVT) {
957  NVT = (MVT::SimpleValueType)IntVT;
958  // The type needs to big enough to hold the result.
959  if (NVT.bitsGE(RVT))
960  LC = Signed ? RTLIB::getFPTOSINT(SVT, NVT):RTLIB::getFPTOUINT(SVT, NVT);
961  }
962  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_XINT!");
963 
964  SDValue Op = GetSoftenedFloat(N->getOperand(0));
965  SDValue Res = TLI.makeLibCall(DAG, LC, NVT, Op, false, dl).first;
966 
967  // Truncate the result if the libcall returns a larger type.
968  return DAG.getNode(ISD::TRUNCATE, dl, RVT, Res);
969 }
970 
971 SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT(SDNode *N) {
972  SDValue Op1 = GetSoftenedFloat(N->getOperand(1));
973  SDValue Op2 = GetSoftenedFloat(N->getOperand(2));
974 
975  if (Op1 == N->getOperand(1) && Op2 == N->getOperand(2))
976  return SDValue();
977 
978  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op1, Op2),
979  0);
980 }
981 
982 SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(SDNode *N) {
983  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
984  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
985 
986  EVT VT = NewLHS.getValueType();
987  NewLHS = GetSoftenedFloat(NewLHS);
988  NewRHS = GetSoftenedFloat(NewRHS);
989  TLI.softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, SDLoc(N));
990 
991  // If softenSetCCOperands returned a scalar, we need to compare the result
992  // against zero to select between true and false values.
993  if (!NewRHS.getNode()) {
994  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
995  CCCode = ISD::SETNE;
996  }
997 
998  // Update N to have the operands specified.
999  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
1000  N->getOperand(2), N->getOperand(3),
1001  DAG.getCondCode(CCCode)),
1002  0);
1003 }
1004 
1005 SDValue DAGTypeLegalizer::SoftenFloatOp_SETCC(SDNode *N) {
1006  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1007  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1008 
1009  EVT VT = NewLHS.getValueType();
1010  NewLHS = GetSoftenedFloat(NewLHS);
1011  NewRHS = GetSoftenedFloat(NewRHS);
1012  TLI.softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, SDLoc(N));
1013 
1014  // If softenSetCCOperands returned a scalar, use it.
1015  if (!NewRHS.getNode()) {
1016  assert(NewLHS.getValueType() == N->getValueType(0) &&
1017  "Unexpected setcc expansion!");
1018  return NewLHS;
1019  }
1020 
1021  // Otherwise, update N to have the operands specified.
1022  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
1023  DAG.getCondCode(CCCode)),
1024  0);
1025 }
1026 
1027 SDValue DAGTypeLegalizer::SoftenFloatOp_STORE(SDNode *N, unsigned OpNo) {
1028  assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1029  assert(OpNo == 1 && "Can only soften the stored value!");
1030  StoreSDNode *ST = cast<StoreSDNode>(N);
1031  SDValue Val = ST->getValue();
1032  SDLoc dl(N);
1033 
1034  if (ST->isTruncatingStore())
1035  // Do an FP_ROUND followed by a non-truncating store.
1036  Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(),
1037  Val, DAG.getIntPtrConstant(0, dl)));
1038  else
1039  Val = GetSoftenedFloat(Val);
1040 
1041  return DAG.getStore(ST->getChain(), dl, Val, ST->getBasePtr(),
1042  ST->getMemOperand());
1043 }
1044 
1045 SDValue DAGTypeLegalizer::SoftenFloatOp_LROUND(SDNode *N) {
1046  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1047 
1048  SDValue Op = GetSoftenedFloat(N->getOperand(0));
1049  EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1050  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
1051  RTLIB::LROUND_F32,
1052  RTLIB::LROUND_F64,
1053  RTLIB::LROUND_F80,
1054  RTLIB::LROUND_F128,
1055  RTLIB::LROUND_PPCF128),
1056  NVT, Op, false, SDLoc(N)).first;
1057 }
1058 
1059 SDValue DAGTypeLegalizer::SoftenFloatOp_LLROUND(SDNode *N) {
1060  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1061 
1062  SDValue Op = GetSoftenedFloat(N->getOperand(0));
1063  EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1064  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
1065  RTLIB::LLROUND_F32,
1066  RTLIB::LLROUND_F64,
1067  RTLIB::LLROUND_F80,
1068  RTLIB::LLROUND_F128,
1069  RTLIB::LLROUND_PPCF128),
1070  NVT, Op, false, SDLoc(N)).first;
1071 }
1072 
1073 SDValue DAGTypeLegalizer::SoftenFloatOp_LRINT(SDNode *N) {
1074  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1075 
1076  SDValue Op = GetSoftenedFloat(N->getOperand(0));
1077  EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1078  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
1079  RTLIB::LRINT_F32,
1080  RTLIB::LRINT_F64,
1081  RTLIB::LRINT_F80,
1082  RTLIB::LRINT_F128,
1083  RTLIB::LRINT_PPCF128),
1084  NVT, Op, false, SDLoc(N)).first;
1085 }
1086 
1087 SDValue DAGTypeLegalizer::SoftenFloatOp_LLRINT(SDNode *N) {
1088  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1089 
1090  SDValue Op = GetSoftenedFloat(N->getOperand(0));
1091  EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1092  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
1093  RTLIB::LLRINT_F32,
1094  RTLIB::LLRINT_F64,
1095  RTLIB::LLRINT_F80,
1096  RTLIB::LLRINT_F128,
1097  RTLIB::LLRINT_PPCF128),
1098  NVT, Op, false, SDLoc(N)).first;
1099 }
1100 
1101 //===----------------------------------------------------------------------===//
1102 // Float Result Expansion
1103 //===----------------------------------------------------------------------===//
1104 
1105 /// ExpandFloatResult - This method is called when the specified result of the
1106 /// specified node is found to need expansion. At this point, the node may also
1107 /// have invalid operands or may have other results that need promotion, we just
1108 /// know that (at least) one result needs expansion.
1109 void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
1110  LLVM_DEBUG(dbgs() << "Expand float result: "; N->dump(&DAG); dbgs() << "\n");
1111  SDValue Lo, Hi;
1112  Lo = Hi = SDValue();
1113 
1114  // See if the target wants to custom expand this node.
1115  if (CustomLowerNode(N, N->getValueType(ResNo), true))
1116  return;
1117 
1118  switch (N->getOpcode()) {
1119  default:
1120 #ifndef NDEBUG
1121  dbgs() << "ExpandFloatResult #" << ResNo << ": ";
1122  N->dump(&DAG); dbgs() << "\n";
1123 #endif
1124  llvm_unreachable("Do not know how to expand the result of this operator!");
1125 
1126  case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1127  case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1128  case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1129 
1130  case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1131  case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1132  case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1133  case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1134  case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1135  case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1136 
1137  case ISD::ConstantFP: ExpandFloatRes_ConstantFP(N, Lo, Hi); break;
1138  case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break;
1139  case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break;
1140  case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break;
1141  case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break;
1142  case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break;
1143  case ISD::FCOPYSIGN: ExpandFloatRes_FCOPYSIGN(N, Lo, Hi); break;
1144  case ISD::FCOS: ExpandFloatRes_FCOS(N, Lo, Hi); break;
1145  case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break;
1146  case ISD::FEXP: ExpandFloatRes_FEXP(N, Lo, Hi); break;
1147  case ISD::FEXP2: ExpandFloatRes_FEXP2(N, Lo, Hi); break;
1148  case ISD::FFLOOR: ExpandFloatRes_FFLOOR(N, Lo, Hi); break;
1149  case ISD::FLOG: ExpandFloatRes_FLOG(N, Lo, Hi); break;
1150  case ISD::FLOG2: ExpandFloatRes_FLOG2(N, Lo, Hi); break;
1151  case ISD::FLOG10: ExpandFloatRes_FLOG10(N, Lo, Hi); break;
1152  case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi); break;
1153  case ISD::FMUL: ExpandFloatRes_FMUL(N, Lo, Hi); break;
1154  case ISD::FNEARBYINT: ExpandFloatRes_FNEARBYINT(N, Lo, Hi); break;
1155  case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break;
1156  case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break;
1157  case ISD::FPOW: ExpandFloatRes_FPOW(N, Lo, Hi); break;
1158  case ISD::FPOWI: ExpandFloatRes_FPOWI(N, Lo, Hi); break;
1159  case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break;
1160  case ISD::FROUND: ExpandFloatRes_FROUND(N, Lo, Hi); break;
1161  case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break;
1162  case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break;
1163  case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
1164  case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break;
1165  case ISD::LOAD: ExpandFloatRes_LOAD(N, Lo, Hi); break;
1166  case ISD::SINT_TO_FP:
1167  case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break;
1168  case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break;
1169  }
1170 
1171  // If Lo/Hi is null, the sub-method took care of registering results etc.
1172  if (Lo.getNode())
1173  SetExpandedFloat(SDValue(N, ResNo), Lo, Hi);
1174 }
1175 
1176 void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo,
1177  SDValue &Hi) {
1178  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1179  assert(NVT.getSizeInBits() == 64 &&
1180  "Do not know how to expand this float constant!");
1181  APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().bitcastToAPInt();
1182  SDLoc dl(N);
1183  Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1184  APInt(64, C.getRawData()[1])),
1185  dl, NVT);
1186  Hi = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1187  APInt(64, C.getRawData()[0])),
1188  dl, NVT);
1189 }
1190 
1191 void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
1192  SDValue &Hi) {
1193  assert(N->getValueType(0) == MVT::ppcf128 &&
1194  "Logic only correct for ppcf128!");
1195  SDLoc dl(N);
1196  SDValue Tmp;
1197  GetExpandedFloat(N->getOperand(0), Lo, Tmp);
1198  Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp);
1199  // Lo = Hi==fabs(Hi) ? Lo : -Lo;
1200  Lo = DAG.getSelectCC(dl, Tmp, Hi, Lo,
1201  DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo),
1202  ISD::SETEQ);
1203 }
1204 
1205 void DAGTypeLegalizer::ExpandFloatRes_FMINNUM(SDNode *N, SDValue &Lo,
1206  SDValue &Hi) {
1207  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1208  RTLIB::FMIN_F32, RTLIB::FMIN_F64,
1209  RTLIB::FMIN_F80, RTLIB::FMIN_F128,
1210  RTLIB::FMIN_PPCF128),
1211  N, false);
1212  GetPairElements(Call, Lo, Hi);
1213 }
1214 
1215 void DAGTypeLegalizer::ExpandFloatRes_FMAXNUM(SDNode *N, SDValue &Lo,
1216  SDValue &Hi) {
1217  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1218  RTLIB::FMAX_F32, RTLIB::FMAX_F64,
1219  RTLIB::FMAX_F80, RTLIB::FMAX_F128,
1220  RTLIB::FMAX_PPCF128),
1221  N, false);
1222  GetPairElements(Call, Lo, Hi);
1223 }
1224 
1225 void DAGTypeLegalizer::ExpandFloatRes_FADD(SDNode *N, SDValue &Lo,
1226  SDValue &Hi) {
1227  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1228  RTLIB::ADD_F32, RTLIB::ADD_F64,
1229  RTLIB::ADD_F80, RTLIB::ADD_F128,
1230  RTLIB::ADD_PPCF128),
1231  N, false);
1232  GetPairElements(Call, Lo, Hi);
1233 }
1234 
1235 void DAGTypeLegalizer::ExpandFloatRes_FCEIL(SDNode *N,
1236  SDValue &Lo, SDValue &Hi) {
1237  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1238  RTLIB::CEIL_F32, RTLIB::CEIL_F64,
1239  RTLIB::CEIL_F80, RTLIB::CEIL_F128,
1240  RTLIB::CEIL_PPCF128),
1241  N, false);
1242  GetPairElements(Call, Lo, Hi);
1243 }
1244 
1245 void DAGTypeLegalizer::ExpandFloatRes_FCOPYSIGN(SDNode *N,
1246  SDValue &Lo, SDValue &Hi) {
1247  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1248  RTLIB::COPYSIGN_F32,
1249  RTLIB::COPYSIGN_F64,
1250  RTLIB::COPYSIGN_F80,
1251  RTLIB::COPYSIGN_F128,
1252  RTLIB::COPYSIGN_PPCF128),
1253  N, false);
1254  GetPairElements(Call, Lo, Hi);
1255 }
1256 
1257 void DAGTypeLegalizer::ExpandFloatRes_FCOS(SDNode *N,
1258  SDValue &Lo, SDValue &Hi) {
1259  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1260  RTLIB::COS_F32, RTLIB::COS_F64,
1261  RTLIB::COS_F80, RTLIB::COS_F128,
1262  RTLIB::COS_PPCF128),
1263  N, false);
1264  GetPairElements(Call, Lo, Hi);
1265 }
1266 
1267 void DAGTypeLegalizer::ExpandFloatRes_FDIV(SDNode *N, SDValue &Lo,
1268  SDValue &Hi) {
1269  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1270  SDValue Call = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
1271  RTLIB::DIV_F32,
1272  RTLIB::DIV_F64,
1273  RTLIB::DIV_F80,
1274  RTLIB::DIV_F128,
1275  RTLIB::DIV_PPCF128),
1276  N->getValueType(0), Ops, false,
1277  SDLoc(N)).first;
1278  GetPairElements(Call, Lo, Hi);
1279 }
1280 
1281 void DAGTypeLegalizer::ExpandFloatRes_FEXP(SDNode *N,
1282  SDValue &Lo, SDValue &Hi) {
1283  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1284  RTLIB::EXP_F32, RTLIB::EXP_F64,
1285  RTLIB::EXP_F80, RTLIB::EXP_F128,
1286  RTLIB::EXP_PPCF128),
1287  N, false);
1288  GetPairElements(Call, Lo, Hi);
1289 }
1290 
1291 void DAGTypeLegalizer::ExpandFloatRes_FEXP2(SDNode *N,
1292  SDValue &Lo, SDValue &Hi) {
1293  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1294  RTLIB::EXP2_F32, RTLIB::EXP2_F64,
1295  RTLIB::EXP2_F80, RTLIB::EXP2_F128,
1296  RTLIB::EXP2_PPCF128),
1297  N, false);
1298  GetPairElements(Call, Lo, Hi);
1299 }
1300 
1301 void DAGTypeLegalizer::ExpandFloatRes_FFLOOR(SDNode *N,
1302  SDValue &Lo, SDValue &Hi) {
1303  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1304  RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
1305  RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
1306  RTLIB::FLOOR_PPCF128),
1307  N, false);
1308  GetPairElements(Call, Lo, Hi);
1309 }
1310 
1311 void DAGTypeLegalizer::ExpandFloatRes_FLOG(SDNode *N,
1312  SDValue &Lo, SDValue &Hi) {
1313  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1314  RTLIB::LOG_F32, RTLIB::LOG_F64,
1315  RTLIB::LOG_F80, RTLIB::LOG_F128,
1316  RTLIB::LOG_PPCF128),
1317  N, false);
1318  GetPairElements(Call, Lo, Hi);
1319 }
1320 
1321 void DAGTypeLegalizer::ExpandFloatRes_FLOG2(SDNode *N,
1322  SDValue &Lo, SDValue &Hi) {
1323  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1324  RTLIB::LOG2_F32, RTLIB::LOG2_F64,
1325  RTLIB::LOG2_F80, RTLIB::LOG2_F128,
1326  RTLIB::LOG2_PPCF128),
1327  N, false);
1328  GetPairElements(Call, Lo, Hi);
1329 }
1330 
1331 void DAGTypeLegalizer::ExpandFloatRes_FLOG10(SDNode *N,
1332  SDValue &Lo, SDValue &Hi) {
1333  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1334  RTLIB::LOG10_F32, RTLIB::LOG10_F64,
1335  RTLIB::LOG10_F80, RTLIB::LOG10_F128,
1336  RTLIB::LOG10_PPCF128),
1337  N, false);
1338  GetPairElements(Call, Lo, Hi);
1339 }
1340 
1341 void DAGTypeLegalizer::ExpandFloatRes_FMA(SDNode *N, SDValue &Lo,
1342  SDValue &Hi) {
1343  SDValue Ops[3] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
1344  SDValue Call = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
1345  RTLIB::FMA_F32,
1346  RTLIB::FMA_F64,
1347  RTLIB::FMA_F80,
1348  RTLIB::FMA_F128,
1349  RTLIB::FMA_PPCF128),
1350  N->getValueType(0), Ops, false,
1351  SDLoc(N)).first;
1352  GetPairElements(Call, Lo, Hi);
1353 }
1354 
1355 void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo,
1356  SDValue &Hi) {
1357  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1358  SDValue Call = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
1359  RTLIB::MUL_F32,
1360  RTLIB::MUL_F64,
1361  RTLIB::MUL_F80,
1362  RTLIB::MUL_F128,
1363  RTLIB::MUL_PPCF128),
1364  N->getValueType(0), Ops, false,
1365  SDLoc(N)).first;
1366  GetPairElements(Call, Lo, Hi);
1367 }
1368 
1369 void DAGTypeLegalizer::ExpandFloatRes_FNEARBYINT(SDNode *N,
1370  SDValue &Lo, SDValue &Hi) {
1371  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1372  RTLIB::NEARBYINT_F32,
1373  RTLIB::NEARBYINT_F64,
1374  RTLIB::NEARBYINT_F80,
1375  RTLIB::NEARBYINT_F128,
1376  RTLIB::NEARBYINT_PPCF128),
1377  N, false);
1378  GetPairElements(Call, Lo, Hi);
1379 }
1380 
1381 void DAGTypeLegalizer::ExpandFloatRes_FNEG(SDNode *N, SDValue &Lo,
1382  SDValue &Hi) {
1383  SDLoc dl(N);
1384  GetExpandedFloat(N->getOperand(0), Lo, Hi);
1385  Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo);
1386  Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi);
1387 }
1388 
1389 void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo,
1390  SDValue &Hi) {
1391  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1392  SDLoc dl(N);
1393  Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0));
1394  Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1395  APInt(NVT.getSizeInBits(), 0)), dl, NVT);
1396 }
1397 
1398 void DAGTypeLegalizer::ExpandFloatRes_FPOW(SDNode *N,
1399  SDValue &Lo, SDValue &Hi) {
1400  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1401  RTLIB::POW_F32, RTLIB::POW_F64,
1402  RTLIB::POW_F80, RTLIB::POW_F128,
1403  RTLIB::POW_PPCF128),
1404  N, false);
1405  GetPairElements(Call, Lo, Hi);
1406 }
1407 
1408 void DAGTypeLegalizer::ExpandFloatRes_FPOWI(SDNode *N,
1409  SDValue &Lo, SDValue &Hi) {
1410  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1411  RTLIB::POWI_F32, RTLIB::POWI_F64,
1412  RTLIB::POWI_F80, RTLIB::POWI_F128,
1413  RTLIB::POWI_PPCF128),
1414  N, false);
1415  GetPairElements(Call, Lo, Hi);
1416 }
1417 
1418 void DAGTypeLegalizer::ExpandFloatRes_FREM(SDNode *N,
1419  SDValue &Lo, SDValue &Hi) {
1420  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1421  RTLIB::REM_F32, RTLIB::REM_F64,
1422  RTLIB::REM_F80, RTLIB::REM_F128,
1423  RTLIB::REM_PPCF128),
1424  N, false);
1425  GetPairElements(Call, Lo, Hi);
1426 }
1427 
1428 void DAGTypeLegalizer::ExpandFloatRes_FRINT(SDNode *N,
1429  SDValue &Lo, SDValue &Hi) {
1430  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1431  RTLIB::RINT_F32, RTLIB::RINT_F64,
1432  RTLIB::RINT_F80, RTLIB::RINT_F128,
1433  RTLIB::RINT_PPCF128),
1434  N, false);
1435  GetPairElements(Call, Lo, Hi);
1436 }
1437 
1438 void DAGTypeLegalizer::ExpandFloatRes_FROUND(SDNode *N,
1439  SDValue &Lo, SDValue &Hi) {
1440  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1441  RTLIB::ROUND_F32,
1442  RTLIB::ROUND_F64,
1443  RTLIB::ROUND_F80,
1444  RTLIB::ROUND_F128,
1445  RTLIB::ROUND_PPCF128),
1446  N, false);
1447  GetPairElements(Call, Lo, Hi);
1448 }
1449 
1450 void DAGTypeLegalizer::ExpandFloatRes_FSIN(SDNode *N,
1451  SDValue &Lo, SDValue &Hi) {
1452  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1453  RTLIB::SIN_F32, RTLIB::SIN_F64,
1454  RTLIB::SIN_F80, RTLIB::SIN_F128,
1455  RTLIB::SIN_PPCF128),
1456  N, false);
1457  GetPairElements(Call, Lo, Hi);
1458 }
1459 
1460 void DAGTypeLegalizer::ExpandFloatRes_FSQRT(SDNode *N,
1461  SDValue &Lo, SDValue &Hi) {
1462  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1463  RTLIB::SQRT_F32, RTLIB::SQRT_F64,
1464  RTLIB::SQRT_F80, RTLIB::SQRT_F128,
1465  RTLIB::SQRT_PPCF128),
1466  N, false);
1467  GetPairElements(Call, Lo, Hi);
1468 }
1469 
1470 void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo,
1471  SDValue &Hi) {
1472  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1473  SDValue Call = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
1474  RTLIB::SUB_F32,
1475  RTLIB::SUB_F64,
1476  RTLIB::SUB_F80,
1477  RTLIB::SUB_F128,
1478  RTLIB::SUB_PPCF128),
1479  N->getValueType(0), Ops, false,
1480  SDLoc(N)).first;
1481  GetPairElements(Call, Lo, Hi);
1482 }
1483 
1484 void DAGTypeLegalizer::ExpandFloatRes_FTRUNC(SDNode *N,
1485  SDValue &Lo, SDValue &Hi) {
1486  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1487  RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
1488  RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
1489  RTLIB::TRUNC_PPCF128),
1490  N, false);
1491  GetPairElements(Call, Lo, Hi);
1492 }
1493 
1494 void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo,
1495  SDValue &Hi) {
1496  if (ISD::isNormalLoad(N)) {
1497  ExpandRes_NormalLoad(N, Lo, Hi);
1498  return;
1499  }
1500 
1501  assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1502  LoadSDNode *LD = cast<LoadSDNode>(N);
1503  SDValue Chain = LD->getChain();
1504  SDValue Ptr = LD->getBasePtr();
1505  SDLoc dl(N);
1506 
1507  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), LD->getValueType(0));
1508  assert(NVT.isByteSized() && "Expanded type not byte sized!");
1509  assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?");
1510 
1511  Hi = DAG.getExtLoad(LD->getExtensionType(), dl, NVT, Chain, Ptr,
1512  LD->getMemoryVT(), LD->getMemOperand());
1513 
1514  // Remember the chain.
1515  Chain = Hi.getValue(1);
1516 
1517  // The low part is zero.
1518  Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1519  APInt(NVT.getSizeInBits(), 0)), dl, NVT);
1520 
1521  // Modified the chain - switch anything that used the old chain to use the
1522  // new one.
1523  ReplaceValueWith(SDValue(LD, 1), Chain);
1524 }
1525 
1526 void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
1527  SDValue &Hi) {
1528  assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
1529  EVT VT = N->getValueType(0);
1530  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1531  SDValue Src = N->getOperand(0);
1532  EVT SrcVT = Src.getValueType();
1533  bool isSigned = N->getOpcode() == ISD::SINT_TO_FP;
1534  SDLoc dl(N);
1535 
1536  // First do an SINT_TO_FP, whether the original was signed or unsigned.
1537  // When promoting partial word types to i32 we must honor the signedness,
1538  // though.
1539  if (SrcVT.bitsLE(MVT::i32)) {
1540  // The integer can be represented exactly in an f64.
1541  Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1542  MVT::i32, Src);
1543  Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1544  APInt(NVT.getSizeInBits(), 0)), dl, NVT);
1545  Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src);
1546  } else {
1547  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1548  if (SrcVT.bitsLE(MVT::i64)) {
1549  Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1550  MVT::i64, Src);
1551  LC = RTLIB::SINTTOFP_I64_PPCF128;
1552  } else if (SrcVT.bitsLE(MVT::i128)) {
1553  Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
1554  LC = RTLIB::SINTTOFP_I128_PPCF128;
1555  }
1556  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
1557 
1558  Hi = TLI.makeLibCall(DAG, LC, VT, Src, true, dl).first;
1559  GetPairElements(Hi, Lo, Hi);
1560  }
1561 
1562  if (isSigned)
1563  return;
1564 
1565  // Unsigned - fix up the SINT_TO_FP value just calculated.
1566  Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
1567  SrcVT = Src.getValueType();
1568 
1569  // x>=0 ? (ppcf128)(iN)x : (ppcf128)(iN)x + 2^N; N=32,64,128.
1570  static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
1571  static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
1572  static const uint64_t TwoE128[] = { 0x47f0000000000000LL, 0 };
1573  ArrayRef<uint64_t> Parts;
1574 
1575  switch (SrcVT.getSimpleVT().SimpleTy) {
1576  default:
1577  llvm_unreachable("Unsupported UINT_TO_FP!");
1578  case MVT::i32:
1579  Parts = TwoE32;
1580  break;
1581  case MVT::i64:
1582  Parts = TwoE64;
1583  break;
1584  case MVT::i128:
1585  Parts = TwoE128;
1586  break;
1587  }
1588 
1589  // TODO: Are there fast-math-flags to propagate to this FADD?
1590  Lo = DAG.getNode(ISD::FADD, dl, VT, Hi,
1592  APInt(128, Parts)),
1593  dl, MVT::ppcf128));
1594  Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, dl, SrcVT),
1595  Lo, Hi, ISD::SETLT);
1596  GetPairElements(Lo, Lo, Hi);
1597 }
1598 
1599 
1600 //===----------------------------------------------------------------------===//
1601 // Float Operand Expansion
1602 //===----------------------------------------------------------------------===//
1603 
1604 /// ExpandFloatOperand - This method is called when the specified operand of the
1605 /// specified node is found to need expansion. At this point, all of the result
1606 /// types of the node are known to be legal, but other operands of the node may
1607 /// need promotion or expansion as well as the specified one.
1608 bool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) {
1609  LLVM_DEBUG(dbgs() << "Expand float operand: "; N->dump(&DAG); dbgs() << "\n");
1610  SDValue Res = SDValue();
1611 
1612  // See if the target wants to custom expand this node.
1613  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1614  return false;
1615 
1616  switch (N->getOpcode()) {
1617  default:
1618 #ifndef NDEBUG
1619  dbgs() << "ExpandFloatOperand Op #" << OpNo << ": ";
1620  N->dump(&DAG); dbgs() << "\n";
1621 #endif
1622  llvm_unreachable("Do not know how to expand this operator's operand!");
1623 
1624  case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
1625  case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1626  case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1627 
1628  case ISD::BR_CC: Res = ExpandFloatOp_BR_CC(N); break;
1629  case ISD::FCOPYSIGN: Res = ExpandFloatOp_FCOPYSIGN(N); break;
1630  case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break;
1631  case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break;
1632  case ISD::FP_TO_UINT: Res = ExpandFloatOp_FP_TO_UINT(N); break;
1633  case ISD::LROUND: Res = ExpandFloatOp_LROUND(N); break;
1634  case ISD::LLROUND: Res = ExpandFloatOp_LLROUND(N); break;
1635  case ISD::LRINT: Res = ExpandFloatOp_LRINT(N); break;
1636  case ISD::LLRINT: Res = ExpandFloatOp_LLRINT(N); break;
1637  case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break;
1638  case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break;
1639  case ISD::STORE: Res = ExpandFloatOp_STORE(cast<StoreSDNode>(N),
1640  OpNo); break;
1641  }
1642 
1643  // If the result is null, the sub-method took care of registering results etc.
1644  if (!Res.getNode()) return false;
1645 
1646  // If the result is N, the sub-method updated N in place. Tell the legalizer
1647  // core about this.
1648  if (Res.getNode() == N)
1649  return true;
1650 
1651  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1652  "Invalid operand expansion");
1653 
1654  ReplaceValueWith(SDValue(N, 0), Res);
1655  return false;
1656 }
1657 
1658 /// FloatExpandSetCCOperands - Expand the operands of a comparison. This code
1659 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1660 void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS,
1661  SDValue &NewRHS,
1662  ISD::CondCode &CCCode,
1663  const SDLoc &dl) {
1664  SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1665  GetExpandedFloat(NewLHS, LHSLo, LHSHi);
1666  GetExpandedFloat(NewRHS, RHSLo, RHSHi);
1667 
1668  assert(NewLHS.getValueType() == MVT::ppcf128 && "Unsupported setcc type!");
1669 
1670  // FIXME: This generated code sucks. We want to generate
1671  // FCMPU crN, hi1, hi2
1672  // BNE crN, L:
1673  // FCMPU crN, lo1, lo2
1674  // The following can be improved, but not that much.
1675  SDValue Tmp1, Tmp2, Tmp3;
1676  Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
1677  LHSHi, RHSHi, ISD::SETOEQ);
1678  Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
1679  LHSLo, RHSLo, CCCode);
1680  Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1681  Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
1682  LHSHi, RHSHi, ISD::SETUNE);
1683  Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
1684  LHSHi, RHSHi, CCCode);
1685  Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1686  NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
1687  NewRHS = SDValue(); // LHS is the result, not a compare.
1688 }
1689 
1690 SDValue DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) {
1691  SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1692  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1693  FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
1694 
1695  // If ExpandSetCCOperands returned a scalar, we need to compare the result
1696  // against zero to select between true and false values.
1697  if (!NewRHS.getNode()) {
1698  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
1699  CCCode = ISD::SETNE;
1700  }
1701 
1702  // Update N to have the operands specified.
1703  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1704  DAG.getCondCode(CCCode), NewLHS, NewRHS,
1705  N->getOperand(4)), 0);
1706 }
1707 
1708 SDValue DAGTypeLegalizer::ExpandFloatOp_FCOPYSIGN(SDNode *N) {
1710  "Logic only correct for ppcf128!");
1711  SDValue Lo, Hi;
1712  GetExpandedFloat(N->getOperand(1), Lo, Hi);
1713  // The ppcf128 value is providing only the sign; take it from the
1714  // higher-order double (which must have the larger magnitude).
1715  return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N),
1716  N->getValueType(0), N->getOperand(0), Hi);
1717 }
1718 
1719 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
1721  "Logic only correct for ppcf128!");
1722  SDValue Lo, Hi;
1723  GetExpandedFloat(N->getOperand(0), Lo, Hi);
1724  // Round it the rest of the way (e.g. to f32) if needed.
1725  return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
1726  N->getValueType(0), Hi, N->getOperand(1));
1727 }
1728 
1729 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
1730  EVT RVT = N->getValueType(0);
1731  SDLoc dl(N);
1732 
1734  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
1735  return TLI.makeLibCall(DAG, LC, RVT, N->getOperand(0), false, dl).first;
1736 }
1737 
1738 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
1739  EVT RVT = N->getValueType(0);
1740  SDLoc dl(N);
1741 
1743  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!");
1744  return TLI.makeLibCall(DAG, LC, N->getValueType(0), N->getOperand(0),
1745  false, dl).first;
1746 }
1747 
1748 SDValue DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(SDNode *N) {
1749  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1750  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
1751  FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
1752 
1753  // If ExpandSetCCOperands returned a scalar, we need to compare the result
1754  // against zero to select between true and false values.
1755  if (!NewRHS.getNode()) {
1756  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
1757  CCCode = ISD::SETNE;
1758  }
1759 
1760  // Update N to have the operands specified.
1761  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
1762  N->getOperand(2), N->getOperand(3),
1763  DAG.getCondCode(CCCode)), 0);
1764 }
1765 
1766 SDValue DAGTypeLegalizer::ExpandFloatOp_SETCC(SDNode *N) {
1767  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1768  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1769  FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
1770 
1771  // If ExpandSetCCOperands returned a scalar, use it.
1772  if (!NewRHS.getNode()) {
1773  assert(NewLHS.getValueType() == N->getValueType(0) &&
1774  "Unexpected setcc expansion!");
1775  return NewLHS;
1776  }
1777 
1778  // Otherwise, update N to have the operands specified.
1779  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
1780  DAG.getCondCode(CCCode)), 0);
1781 }
1782 
1783 SDValue DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) {
1784  if (ISD::isNormalStore(N))
1785  return ExpandOp_NormalStore(N, OpNo);
1786 
1787  assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1788  assert(OpNo == 1 && "Can only expand the stored value so far");
1789  StoreSDNode *ST = cast<StoreSDNode>(N);
1790 
1791  SDValue Chain = ST->getChain();
1792  SDValue Ptr = ST->getBasePtr();
1793 
1794  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(),
1795  ST->getValue().getValueType());
1796  assert(NVT.isByteSized() && "Expanded type not byte sized!");
1797  assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?");
1798  (void)NVT;
1799 
1800  SDValue Lo, Hi;
1801  GetExpandedOp(ST->getValue(), Lo, Hi);
1802 
1803  return DAG.getTruncStore(Chain, SDLoc(N), Hi, Ptr,
1804  ST->getMemoryVT(), ST->getMemOperand());
1805 }
1806 
1807 SDValue DAGTypeLegalizer::ExpandFloatOp_LROUND(SDNode *N) {
1808  EVT RVT = N->getValueType(0);
1809  EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1810  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
1811  RTLIB::LROUND_F32,
1812  RTLIB::LROUND_F64,
1813  RTLIB::LROUND_F80,
1814  RTLIB::LROUND_F128,
1815  RTLIB::LROUND_PPCF128),
1816  RVT, N->getOperand(0), false, SDLoc(N)).first;
1817 }
1818 
1819 SDValue DAGTypeLegalizer::ExpandFloatOp_LLROUND(SDNode *N) {
1820  EVT RVT = N->getValueType(0);
1821  EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1822  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
1823  RTLIB::LLROUND_F32,
1824  RTLIB::LLROUND_F64,
1825  RTLIB::LLROUND_F80,
1826  RTLIB::LLROUND_F128,
1827  RTLIB::LLROUND_PPCF128),
1828  RVT, N->getOperand(0), false, SDLoc(N)).first;
1829 }
1830 
1831 SDValue DAGTypeLegalizer::ExpandFloatOp_LRINT(SDNode *N) {
1832  EVT RVT = N->getValueType(0);
1833  EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1834  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
1835  RTLIB::LRINT_F32,
1836  RTLIB::LRINT_F64,
1837  RTLIB::LRINT_F80,
1838  RTLIB::LRINT_F128,
1839  RTLIB::LRINT_PPCF128),
1840  RVT, N->getOperand(0), false, SDLoc(N)).first;
1841 }
1842 
1843 SDValue DAGTypeLegalizer::ExpandFloatOp_LLRINT(SDNode *N) {
1844  EVT RVT = N->getValueType(0);
1845  EVT RetVT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
1846  return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
1847  RTLIB::LLRINT_F32,
1848  RTLIB::LLRINT_F64,
1849  RTLIB::LLRINT_F80,
1850  RTLIB::LLRINT_F128,
1851  RTLIB::LLRINT_PPCF128),
1852  RVT, N->getOperand(0), false, SDLoc(N)).first;
1853 }
1854 
1855 //===----------------------------------------------------------------------===//
1856 // Float Operand Promotion
1857 //===----------------------------------------------------------------------===//
1858 //
1859 
1861  if (OpVT == MVT::f16) {
1862  return ISD::FP16_TO_FP;
1863  } else if (RetVT == MVT::f16) {
1864  return ISD::FP_TO_FP16;
1865  }
1866 
1867  report_fatal_error("Attempt at an invalid promotion-related conversion");
1868 }
1869 
1870 bool DAGTypeLegalizer::PromoteFloatOperand(SDNode *N, unsigned OpNo) {
1871  LLVM_DEBUG(dbgs() << "Promote float operand " << OpNo << ": "; N->dump(&DAG);
1872  dbgs() << "\n");
1873  SDValue R = SDValue();
1874 
1875  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
1876  LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
1877  return false;
1878  }
1879 
1880  // Nodes that use a promotion-requiring floating point operand, but doesn't
1881  // produce a promotion-requiring floating point result, need to be legalized
1882  // to use the promoted float operand. Nodes that produce at least one
1883  // promotion-requiring floating point result have their operands legalized as
1884  // a part of PromoteFloatResult.
1885  switch (N->getOpcode()) {
1886  default:
1887  #ifndef NDEBUG
1888  dbgs() << "PromoteFloatOperand Op #" << OpNo << ": ";
1889  N->dump(&DAG); dbgs() << "\n";
1890  #endif
1891  llvm_unreachable("Do not know how to promote this operator's operand!");
1892 
1893  case ISD::BITCAST: R = PromoteFloatOp_BITCAST(N, OpNo); break;
1894  case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break;
1895  case ISD::FP_TO_SINT:
1896  case ISD::FP_TO_UINT: R = PromoteFloatOp_FP_TO_XINT(N, OpNo); break;
1897  case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break;
1898  case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break;
1899  case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break;
1900  case ISD::STORE: R = PromoteFloatOp_STORE(N, OpNo); break;
1901  }
1902 
1903  if (R.getNode())
1904  ReplaceValueWith(SDValue(N, 0), R);
1905  return false;
1906 }
1907 
1908 SDValue DAGTypeLegalizer::PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo) {
1909  SDValue Op = N->getOperand(0);
1910  EVT OpVT = Op->getValueType(0);
1911 
1912  SDValue Promoted = GetPromotedFloat(N->getOperand(0));
1913  EVT PromotedVT = Promoted->getValueType(0);
1914 
1915  // Convert the promoted float value to the desired IVT.
1916  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits());
1917  SDValue Convert = DAG.getNode(GetPromotionOpcode(PromotedVT, OpVT), SDLoc(N),
1918  IVT, Promoted);
1919  // The final result type might not be an scalar so we need a bitcast. The
1920  // bitcast will be further legalized if needed.
1921  return DAG.getBitcast(N->getValueType(0), Convert);
1922 }
1923 
1924 // Promote Operand 1 of FCOPYSIGN. Operand 0 ought to be handled by
1925 // PromoteFloatRes_FCOPYSIGN.
1926 SDValue DAGTypeLegalizer::PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo) {
1927  assert (OpNo == 1 && "Only Operand 1 must need promotion here");
1928  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
1929 
1930  return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
1931  N->getOperand(0), Op1);
1932 }
1933 
1934 // Convert the promoted float value to the desired integer type
1935 SDValue DAGTypeLegalizer::PromoteFloatOp_FP_TO_XINT(SDNode *N, unsigned OpNo) {
1936  SDValue Op = GetPromotedFloat(N->getOperand(0));
1937  return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), Op);
1938 }
1939 
1940 SDValue DAGTypeLegalizer::PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo) {
1941  SDValue Op = GetPromotedFloat(N->getOperand(0));
1942  EVT VT = N->getValueType(0);
1943 
1944  // Desired VT is same as promoted type. Use promoted float directly.
1945  if (VT == Op->getValueType(0))
1946  return Op;
1947 
1948  // Else, extend the promoted float value to the desired VT.
1949  return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op);
1950 }
1951 
1952 // Promote the float operands used for comparison. The true- and false-
1953 // operands have the same type as the result and are promoted, if needed, by
1954 // PromoteFloatRes_SELECT_CC
1955 SDValue DAGTypeLegalizer::PromoteFloatOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1956  SDValue LHS = GetPromotedFloat(N->getOperand(0));
1957  SDValue RHS = GetPromotedFloat(N->getOperand(1));
1958 
1959  return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1960  LHS, RHS, N->getOperand(2), N->getOperand(3),
1961  N->getOperand(4));
1962 }
1963 
1964 // Construct a SETCC that compares the promoted values and sets the conditional
1965 // code.
1966 SDValue DAGTypeLegalizer::PromoteFloatOp_SETCC(SDNode *N, unsigned OpNo) {
1967  EVT VT = N->getValueType(0);
1968  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1969  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
1970  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
1971  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1972 
1973  return DAG.getSetCC(SDLoc(N), NVT, Op0, Op1, CCCode);
1974 
1975 }
1976 
1977 // Lower the promoted Float down to the integer value of same size and construct
1978 // a STORE of the integer value.
1979 SDValue DAGTypeLegalizer::PromoteFloatOp_STORE(SDNode *N, unsigned OpNo) {
1980  StoreSDNode *ST = cast<StoreSDNode>(N);
1981  SDValue Val = ST->getValue();
1982  SDLoc DL(N);
1983 
1984  SDValue Promoted = GetPromotedFloat(Val);
1985  EVT VT = ST->getOperand(1).getValueType();
1986  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
1987 
1988  SDValue NewVal;
1989  NewVal = DAG.getNode(GetPromotionOpcode(Promoted.getValueType(), VT), DL,
1990  IVT, Promoted);
1991 
1992  return DAG.getStore(ST->getChain(), DL, NewVal, ST->getBasePtr(),
1993  ST->getMemOperand());
1994 }
1995 
1996 //===----------------------------------------------------------------------===//
1997 // Float Result Promotion
1998 //===----------------------------------------------------------------------===//
1999 
2000 void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
2001  LLVM_DEBUG(dbgs() << "Promote float result " << ResNo << ": "; N->dump(&DAG);
2002  dbgs() << "\n");
2003  SDValue R = SDValue();
2004 
2005  switch (N->getOpcode()) {
2006  // These opcodes cannot appear if promotion of FP16 is done in the backend
2007  // instead of Clang
2008  case ISD::FP16_TO_FP:
2009  case ISD::FP_TO_FP16:
2010  default:
2011 #ifndef NDEBUG
2012  dbgs() << "PromoteFloatResult #" << ResNo << ": ";
2013  N->dump(&DAG); dbgs() << "\n";
2014 #endif
2015  llvm_unreachable("Do not know how to promote this operator's result!");
2016 
2017  case ISD::BITCAST: R = PromoteFloatRes_BITCAST(N); break;
2018  case ISD::ConstantFP: R = PromoteFloatRes_ConstantFP(N); break;
2020  R = PromoteFloatRes_EXTRACT_VECTOR_ELT(N); break;
2021  case ISD::FCOPYSIGN: R = PromoteFloatRes_FCOPYSIGN(N); break;
2022 
2023  // Unary FP Operations
2024  case ISD::FABS:
2025  case ISD::FCEIL:
2026  case ISD::FCOS:
2027  case ISD::FEXP:
2028  case ISD::FEXP2:
2029  case ISD::FFLOOR:
2030  case ISD::FLOG:
2031  case ISD::FLOG2:
2032  case ISD::FLOG10:
2033  case ISD::FNEARBYINT:
2034  case ISD::FNEG:
2035  case ISD::FRINT:
2036  case ISD::FROUND:
2037  case ISD::FSIN:
2038  case ISD::FSQRT:
2039  case ISD::FTRUNC:
2040  case ISD::FCANONICALIZE: R = PromoteFloatRes_UnaryOp(N); break;
2041 
2042  // Binary FP Operations
2043  case ISD::FADD:
2044  case ISD::FDIV:
2045  case ISD::FMAXIMUM:
2046  case ISD::FMINIMUM:
2047  case ISD::FMAXNUM:
2048  case ISD::FMINNUM:
2049  case ISD::FMUL:
2050  case ISD::FPOW:
2051  case ISD::FREM:
2052  case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break;
2053 
2054  case ISD::FMA: // FMA is same as FMAD
2055  case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break;
2056 
2057  case ISD::FPOWI: R = PromoteFloatRes_FPOWI(N); break;
2058 
2059  case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break;
2060  case ISD::LOAD: R = PromoteFloatRes_LOAD(N); break;
2061  case ISD::SELECT: R = PromoteFloatRes_SELECT(N); break;
2062  case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break;
2063 
2064  case ISD::SINT_TO_FP:
2065  case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break;
2066  case ISD::UNDEF: R = PromoteFloatRes_UNDEF(N); break;
2067  case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break;
2068  }
2069 
2070  if (R.getNode())
2071  SetPromotedFloat(SDValue(N, ResNo), R);
2072 }
2073 
2074 // Bitcast from i16 to f16: convert the i16 to a f32 value instead.
2075 // At this point, it is not possible to determine if the bitcast value is
2076 // eventually stored to memory or promoted to f32 or promoted to a floating
2077 // point at a higher precision. Some of these cases are handled by FP_EXTEND,
2078 // STORE promotion handlers.
2079 SDValue DAGTypeLegalizer::PromoteFloatRes_BITCAST(SDNode *N) {
2080  EVT VT = N->getValueType(0);
2081  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2082  // Input type isn't guaranteed to be a scalar int so bitcast if not. The
2083  // bitcast will be legalized further if necessary.
2084  EVT IVT = EVT::getIntegerVT(*DAG.getContext(),
2086  SDValue Cast = DAG.getBitcast(IVT, N->getOperand(0));
2087  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, Cast);
2088 }
2089 
2090 SDValue DAGTypeLegalizer::PromoteFloatRes_ConstantFP(SDNode *N) {
2091  ConstantFPSDNode *CFPNode = cast<ConstantFPSDNode>(N);
2092  EVT VT = N->getValueType(0);
2093  SDLoc DL(N);
2094 
2095  // Get the (bit-cast) APInt of the APFloat and build an integer constant
2096  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
2097  SDValue C = DAG.getConstant(CFPNode->getValueAPF().bitcastToAPInt(), DL,
2098  IVT);
2099 
2100  // Convert the Constant to the desired FP type
2101  // FIXME We might be able to do the conversion during compilation and get rid
2102  // of it from the object code
2103  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2104  return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, C);
2105 }
2106 
2107 // If the Index operand is a constant, try to redirect the extract operation to
2108 // the correct legalized vector. If not, bit-convert the input vector to
2109 // equivalent integer vector. Extract the element as an (bit-cast) integer
2110 // value and convert it to the promoted type.
2111 SDValue DAGTypeLegalizer::PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
2112  SDLoc DL(N);
2113 
2114  // If the index is constant, try to extract the value from the legalized
2115  // vector type.
2116  if (isa<ConstantSDNode>(N->getOperand(1))) {
2117  SDValue Vec = N->getOperand(0);
2118  SDValue Idx = N->getOperand(1);
2119  EVT VecVT = Vec->getValueType(0);
2120  EVT EltVT = VecVT.getVectorElementType();
2121 
2122  uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2123 
2124  switch (getTypeAction(VecVT)) {
2125  default: break;
2127  SDValue Res = GetScalarizedVector(N->getOperand(0));
2128  ReplaceValueWith(SDValue(N, 0), Res);
2129  return SDValue();
2130  }
2132  Vec = GetWidenedVector(Vec);
2133  SDValue Res = DAG.getNode(N->getOpcode(), DL, EltVT, Vec, Idx);
2134  ReplaceValueWith(SDValue(N, 0), Res);
2135  return SDValue();
2136  }
2138  SDValue Lo, Hi;
2139  GetSplitVector(Vec, Lo, Hi);
2140 
2141  uint64_t LoElts = Lo.getValueType().getVectorNumElements();
2142  SDValue Res;
2143  if (IdxVal < LoElts)
2144  Res = DAG.getNode(N->getOpcode(), DL, EltVT, Lo, Idx);
2145  else
2146  Res = DAG.getNode(N->getOpcode(), DL, EltVT, Hi,
2147  DAG.getConstant(IdxVal - LoElts, DL,
2148  Idx.getValueType()));
2149  ReplaceValueWith(SDValue(N, 0), Res);
2150  return SDValue();
2151  }
2152 
2153  }
2154  }
2155 
2156  // Bit-convert the input vector to the equivalent integer vector
2157  SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
2158  EVT IVT = NewOp.getValueType().getVectorElementType();
2159 
2160  // Extract the element as an (bit-cast) integer value
2161  SDValue NewVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IVT,
2162  NewOp, N->getOperand(1));
2163 
2164  // Convert the element to the desired FP type
2165  EVT VT = N->getValueType(0);
2166  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2167  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, NewVal);
2168 }
2169 
2170 // FCOPYSIGN(X, Y) returns the value of X with the sign of Y. If the result
2171 // needs promotion, so does the argument X. Note that Y, if needed, will be
2172 // handled during operand promotion.
2173 SDValue DAGTypeLegalizer::PromoteFloatRes_FCOPYSIGN(SDNode *N) {
2174  EVT VT = N->getValueType(0);
2175  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2176  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2177 
2178  SDValue Op1 = N->getOperand(1);
2179 
2180  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1);
2181 }
2182 
2183 // Unary operation where the result and the operand have PromoteFloat type
2184 // action. Construct a new SDNode with the promoted float value of the old
2185 // operand.
2186 SDValue DAGTypeLegalizer::PromoteFloatRes_UnaryOp(SDNode *N) {
2187  EVT VT = N->getValueType(0);
2188  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2189  SDValue Op = GetPromotedFloat(N->getOperand(0));
2190 
2191  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op);
2192 }
2193 
2194 // Binary operations where the result and both operands have PromoteFloat type
2195 // action. Construct a new SDNode with the promoted float values of the old
2196 // operands.
2197 SDValue DAGTypeLegalizer::PromoteFloatRes_BinOp(SDNode *N) {
2198  EVT VT = N->getValueType(0);
2199  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2200  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2201  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
2202  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, N->getFlags());
2203 }
2204 
2205 SDValue DAGTypeLegalizer::PromoteFloatRes_FMAD(SDNode *N) {
2206  EVT VT = N->getValueType(0);
2207  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2208  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2209  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
2210  SDValue Op2 = GetPromotedFloat(N->getOperand(2));
2211 
2212  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, Op2);
2213 }
2214 
2215 // Promote the Float (first) operand and retain the Integer (second) operand
2216 SDValue DAGTypeLegalizer::PromoteFloatRes_FPOWI(SDNode *N) {
2217  EVT VT = N->getValueType(0);
2218  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2219  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2220  SDValue Op1 = N->getOperand(1);
2221 
2222  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1);
2223 }
2224 
2225 // Explicit operation to reduce precision. Reduce the value to half precision
2226 // and promote it back to the legal type.
2227 SDValue DAGTypeLegalizer::PromoteFloatRes_FP_ROUND(SDNode *N) {
2228  SDLoc DL(N);
2229 
2230  SDValue Op = N->getOperand(0);
2231  EVT VT = N->getValueType(0);
2232  EVT OpVT = Op->getValueType(0);
2233  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2234  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
2235 
2236  // Round promoted float to desired precision
2237  SDValue Round = DAG.getNode(GetPromotionOpcode(OpVT, VT), DL, IVT, Op);
2238  // Promote it back to the legal output type
2239  return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, Round);
2240 }
2241 
2242 SDValue DAGTypeLegalizer::PromoteFloatRes_LOAD(SDNode *N) {
2243  LoadSDNode *L = cast<LoadSDNode>(N);
2244  EVT VT = N->getValueType(0);
2245 
2246  // Load the value as an integer value with the same number of bits.
2247  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
2248  SDValue newL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), IVT,
2249  SDLoc(N), L->getChain(), L->getBasePtr(),
2250  L->getOffset(), L->getPointerInfo(), IVT,
2251  L->getAlignment(),
2252  L->getMemOperand()->getFlags(),
2253  L->getAAInfo());
2254  // Legalize the chain result by replacing uses of the old value chain with the
2255  // new one
2256  ReplaceValueWith(SDValue(N, 1), newL.getValue(1));
2257 
2258  // Convert the integer value to the desired FP type
2259  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2260  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, newL);
2261 }
2262 
2263 // Construct a new SELECT node with the promoted true- and false- values.
2264 SDValue DAGTypeLegalizer::PromoteFloatRes_SELECT(SDNode *N) {
2265  SDValue TrueVal = GetPromotedFloat(N->getOperand(1));
2266  SDValue FalseVal = GetPromotedFloat(N->getOperand(2));
2267 
2268  return DAG.getNode(ISD::SELECT, SDLoc(N), TrueVal->getValueType(0),
2269  N->getOperand(0), TrueVal, FalseVal);
2270 }
2271 
2272 // Construct a new SELECT_CC node with the promoted true- and false- values.
2273 // The operands used for comparison are promoted by PromoteFloatOp_SELECT_CC.
2274 SDValue DAGTypeLegalizer::PromoteFloatRes_SELECT_CC(SDNode *N) {
2275  SDValue TrueVal = GetPromotedFloat(N->getOperand(2));
2276  SDValue FalseVal = GetPromotedFloat(N->getOperand(3));
2277 
2278  return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2279  TrueVal.getNode()->getValueType(0), N->getOperand(0),
2280  N->getOperand(1), TrueVal, FalseVal, N->getOperand(4));
2281 }
2282 
2283 // Construct a SDNode that transforms the SINT or UINT operand to the promoted
2284 // float type.
2285 SDValue DAGTypeLegalizer::PromoteFloatRes_XINT_TO_FP(SDNode *N) {
2286  SDLoc DL(N);
2287  EVT VT = N->getValueType(0);
2288  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2289  SDValue NV = DAG.getNode(N->getOpcode(), DL, NVT, N->getOperand(0));
2290  // Round the value to the desired precision (that of the source type).
2291  return DAG.getNode(
2292  ISD::FP_EXTEND, DL, NVT,
2293  DAG.getNode(ISD::FP_ROUND, DL, VT, NV, DAG.getIntPtrConstant(0, DL)));
2294 }
2295 
2296 SDValue DAGTypeLegalizer::PromoteFloatRes_UNDEF(SDNode *N) {
2297  return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
2298  N->getValueType(0)));
2299 }
2300 
2301 SDValue DAGTypeLegalizer::BitcastToInt_ATOMIC_SWAP(SDNode *N) {
2302  EVT VT = N->getValueType(0);
2303  EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2304 
2305  AtomicSDNode *AM = cast<AtomicSDNode>(N);
2306  SDLoc SL(N);
2307 
2308  SDValue CastVal = BitConvertToInteger(AM->getVal());
2309  EVT CastVT = CastVal.getValueType();
2310 
2311  SDValue NewAtomic
2312  = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, CastVT,
2313  DAG.getVTList(CastVT, MVT::Other),
2314  { AM->getChain(), AM->getBasePtr(), CastVal },
2315  AM->getMemOperand());
2316 
2317  SDValue ResultCast = DAG.getNode(GetPromotionOpcode(VT, NFPVT), SL, NFPVT,
2318  NewAtomic);
2319  // Legalize the chain result by replacing uses of the old value chain with the
2320  // new one
2321  ReplaceValueWith(SDValue(N, 1), NewAtomic.getValue(1));
2322 
2323  return ResultCast;
2324 
2325 }
2326 
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:562
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:622
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOffset() const
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:183
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:561
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
DiagnosticInfoOptimizationBase::Argument NV
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:957
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:678
This class represents lattice values for constants.
Definition: AllocatorList.h:23
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:633
const SDValue & getVal() const
const SDValue & getBasePtr() const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const SDValue & getValue() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
const SDValue & getBasePtr() const
const SDValue & getChain() const
ISD::MemIndexedMode getAddressingMode() const
Return the addressing mode for this load or store: unindexed, pre-inc, pre-dec, post-inc, or post-dec.
static const fltSemantics & EVTToAPFloatSemantics(EVT VT)
Returns an APFloat semantics tag appropriate for the given type.
unsigned getAlignment() const
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select&#39;s if you just have operands and don&#39;t want to check...
Definition: SelectionDAG.h:970
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) const
Soften the operands of a comparison.
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:211
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:459
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
bool isTruncatingStore() const
Return true if the op does a truncation before store.
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Shift and rotation operations.
Definition: ISDOpcodes.h:434
bool isNormalStore(const SDNode *N)
Returns true if the specified node is a non-truncating and unindexed store.
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
CopyToReg - This node has three operands: a chain, a register number to set to this value...
Definition: ISDOpcodes.h:169
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
SimpleValueType SimpleTy
The memory access is dereferenceable (i.e., doesn&#39;t trap).
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:841
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:407
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
This is an SDNode representing atomic operations.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:502
bool isUNINDEXEDStore(const SDNode *N)
Returns true if the specified node is an unindexed store.
void clearBit(unsigned BitPosition)
Set a given bit to 0.
Definition: APInt.h:1461
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:872
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:995
static RTLIB::Libcall GetFPLibCall(EVT VT, RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128, RTLIB::Libcall Call_PPCF128)
GetFPLibCall - Return the right libcall for the given floating point type.
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true, bool isPostTypeLegalization=false) const
Returns a pair of (return value, chain).
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands...
UNDEF - An undefined node.
Definition: ISDOpcodes.h:177
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:548
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:351
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
const SDValue & getBasePtr() const
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
Definition: ValueTypes.h:234
bool isNormalLoad(const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:272
const SDValue & getOperand(unsigned Num) const
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
Definition: ValueTypes.h:246
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:750
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:580
Extended Value Type.
Definition: ValueTypes.h:33
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned first
bool isUNINDEXEDLoad(const SDNode *N)
Returns true if the specified node is an unindexed load.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
Definition: APInt.h:554
void dump() const
Dump this node, for debugging.
Returns platform specific canonical encoding of a floating point number.
Definition: ISDOpcodes.h:343
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:363
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:605
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
EVT getMemoryVT() const
Return the type of the in-memory value.
Class for arbitrary precision integers.
Definition: APInt.h:69
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:444
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:492
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:495
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:336
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:674
static const fltSemantics & PPCDoubleDouble() LLVM_READNONE
Definition: APFloat.cpp:170
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:411
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:642
#define N
Flags getFlags() const
Return the raw flags of the source value,.
The memory access always returns the same value (or traps).
uint32_t Size
Definition: Profile.cpp:46
unsigned getOpcode() const
SDValue getValue(unsigned R) const
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:174
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getCondCode(ISD::CondCode Cond)
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input...
const MachinePointerInfo & getPointerInfo() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:326
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC&#39;s if you just have an ISD::CondCode instead of an...
Definition: SelectionDAG.h:982
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
const APFloat & getValueAPF() const
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
Definition: ISDOpcodes.h:330
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:467
APInt bitcastToAPInt() const
Definition: APFloat.h:1104
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
Conversion operators.
Definition: ISDOpcodes.h:489
bool isBigEndian() const
Definition: DataLayout.h:233
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:498
#define LLVM_DEBUG(X)
Definition: Debug.h:122
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:610
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:63
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
static ISD::NodeType GetPromotionOpcode(EVT OpVT, EVT RetVT)
LLVMContext * getContext() const
Definition: SelectionDAG.h:414
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
This class is used to represent ISD::LOAD nodes.