LLVM  14.0.0git
LegalizeTypes.h
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1 //===-- LegalizeTypes.h - DAG Type Legalizer class definition ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the DAGTypeLegalizer class. This is a private interface
10 // shared between the code that implements the SelectionDAG::LegalizeTypes
11 // method.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_LEGALIZETYPES_H
16 #define LLVM_LIB_CODEGEN_SELECTIONDAG_LEGALIZETYPES_H
17 
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/TargetLowering.h"
21 #include "llvm/Support/Compiler.h"
22 #include "llvm/Support/Debug.h"
23 
24 namespace llvm {
25 
26 //===----------------------------------------------------------------------===//
27 /// This takes an arbitrary SelectionDAG as input and hacks on it until only
28 /// value types the target machine can handle are left. This involves promoting
29 /// small sizes to large sizes or splitting up large values into small values.
30 ///
31 class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
32  const TargetLowering &TLI;
33  SelectionDAG &DAG;
34 public:
35  /// This pass uses the NodeId on the SDNodes to hold information about the
36  /// state of the node. The enum has all the values.
37  enum NodeIdFlags {
38  /// All operands have been processed, so this node is ready to be handled.
39  ReadyToProcess = 0,
40 
41  /// This is a new node, not before seen, that was created in the process of
42  /// legalizing some other node.
43  NewNode = -1,
44 
45  /// This node's ID needs to be set to the number of its unprocessed
46  /// operands.
47  Unanalyzed = -2,
48 
49  /// This is a node that has already been processed.
50  Processed = -3
51 
52  // 1+ - This is a node which has this many unprocessed operands.
53  };
54 private:
55 
56  /// This is a bitvector that contains two bits for each simple value type,
57  /// where the two bits correspond to the LegalizeAction enum from
58  /// TargetLowering. This can be queried with "getTypeAction(VT)".
59  TargetLowering::ValueTypeActionImpl ValueTypeActions;
60 
61  /// Return how we should legalize values of this type.
62  TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const {
63  return TLI.getTypeAction(*DAG.getContext(), VT);
64  }
65 
66  /// Return true if this type is legal on this target.
67  bool isTypeLegal(EVT VT) const {
68  return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
69  }
70 
71  /// Return true if this is a simple legal type.
72  bool isSimpleLegalType(EVT VT) const {
73  return VT.isSimple() && TLI.isTypeLegal(VT);
74  }
75 
76  EVT getSetCCResultType(EVT VT) const {
77  return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
78  }
79 
80  /// Pretend all of this node's results are legal.
81  bool IgnoreNodeResults(SDNode *N) const {
82  return N->getOpcode() == ISD::TargetConstant ||
83  N->getOpcode() == ISD::Register;
84  }
85 
86  // Bijection from SDValue to unique id. As each created node gets a
87  // new id we do not need to worry about reuse expunging. Should we
88  // run out of ids, we can do a one time expensive compactifcation.
89  typedef unsigned TableId;
90 
91  TableId NextValueId = 1;
92 
93  SmallDenseMap<SDValue, TableId, 8> ValueToIdMap;
94  SmallDenseMap<TableId, SDValue, 8> IdToValueMap;
95 
96  /// For integer nodes that are below legal width, this map indicates what
97  /// promoted value to use.
98  SmallDenseMap<TableId, TableId, 8> PromotedIntegers;
99 
100  /// For integer nodes that need to be expanded this map indicates which
101  /// operands are the expanded version of the input.
102  SmallDenseMap<TableId, std::pair<TableId, TableId>, 8> ExpandedIntegers;
103 
104  /// For floating-point nodes converted to integers of the same size, this map
105  /// indicates the converted value to use.
106  SmallDenseMap<TableId, TableId, 8> SoftenedFloats;
107 
108  /// For floating-point nodes that have a smaller precision than the smallest
109  /// supported precision, this map indicates what promoted value to use.
110  SmallDenseMap<TableId, TableId, 8> PromotedFloats;
111 
112  /// For floating-point nodes that have a smaller precision than the smallest
113  /// supported precision, this map indicates the converted value to use.
114  SmallDenseMap<TableId, TableId, 8> SoftPromotedHalfs;
115 
116  /// For float nodes that need to be expanded this map indicates which operands
117  /// are the expanded version of the input.
118  SmallDenseMap<TableId, std::pair<TableId, TableId>, 8> ExpandedFloats;
119 
120  /// For nodes that are <1 x ty>, this map indicates the scalar value of type
121  /// 'ty' to use.
122  SmallDenseMap<TableId, TableId, 8> ScalarizedVectors;
123 
124  /// For nodes that need to be split this map indicates which operands are the
125  /// expanded version of the input.
126  SmallDenseMap<TableId, std::pair<TableId, TableId>, 8> SplitVectors;
127 
128  /// For vector nodes that need to be widened, indicates the widened value to
129  /// use.
130  SmallDenseMap<TableId, TableId, 8> WidenedVectors;
131 
132  /// For values that have been replaced with another, indicates the replacement
133  /// value to use.
134  SmallDenseMap<TableId, TableId, 8> ReplacedValues;
135 
136  /// This defines a worklist of nodes to process. In order to be pushed onto
137  /// this worklist, all operands of a node must have already been processed.
138  SmallVector<SDNode*, 128> Worklist;
139 
140  TableId getTableId(SDValue V) {
141  assert(V.getNode() && "Getting TableId on SDValue()");
142 
143  auto I = ValueToIdMap.find(V);
144  if (I != ValueToIdMap.end()) {
145  // replace if there's been a shift.
146  RemapId(I->second);
147  assert(I->second && "All Ids should be nonzero");
148  return I->second;
149  }
150  // Add if it's not there.
151  ValueToIdMap.insert(std::make_pair(V, NextValueId));
152  IdToValueMap.insert(std::make_pair(NextValueId, V));
153  ++NextValueId;
154  assert(NextValueId != 0 &&
155  "Ran out of Ids. Increase id type size or add compactification");
156  return NextValueId - 1;
157  }
158 
159  const SDValue &getSDValue(TableId &Id) {
160  RemapId(Id);
161  assert(Id && "TableId should be non-zero");
162  auto I = IdToValueMap.find(Id);
163  assert(I != IdToValueMap.end() && "cannot find Id in map");
164  return I->second;
165  }
166 
167 public:
168  explicit DAGTypeLegalizer(SelectionDAG &dag)
169  : TLI(dag.getTargetLoweringInfo()), DAG(dag),
170  ValueTypeActions(TLI.getValueTypeActions()) {
171  static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
172  "Too many value types for ValueTypeActions to hold!");
173  }
174 
175  /// This is the main entry point for the type legalizer. This does a
176  /// top-down traversal of the dag, legalizing types as it goes. Returns
177  /// "true" if it made any changes.
178  bool run();
179 
180  void NoteDeletion(SDNode *Old, SDNode *New) {
181  assert(Old != New && "node replaced with self");
182  for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
183  TableId NewId = getTableId(SDValue(New, i));
184  TableId OldId = getTableId(SDValue(Old, i));
185 
186  if (OldId != NewId) {
187  ReplacedValues[OldId] = NewId;
188 
189  // Delete Node from tables. We cannot do this when OldId == NewId,
190  // because NewId can still have table references to it in
191  // ReplacedValues.
192  IdToValueMap.erase(OldId);
193  PromotedIntegers.erase(OldId);
194  ExpandedIntegers.erase(OldId);
195  SoftenedFloats.erase(OldId);
196  PromotedFloats.erase(OldId);
197  SoftPromotedHalfs.erase(OldId);
198  ExpandedFloats.erase(OldId);
199  ScalarizedVectors.erase(OldId);
200  SplitVectors.erase(OldId);
201  WidenedVectors.erase(OldId);
202  }
203 
204  ValueToIdMap.erase(SDValue(Old, i));
205  }
206  }
207 
208  SelectionDAG &getDAG() const { return DAG; }
209 
210 private:
211  SDNode *AnalyzeNewNode(SDNode *N);
212  void AnalyzeNewValue(SDValue &Val);
213  void PerformExpensiveChecks();
214  void RemapId(TableId &Id);
215  void RemapValue(SDValue &V);
216 
217  // Common routines.
218  SDValue BitConvertToInteger(SDValue Op);
219  SDValue BitConvertVectorToIntegerVector(SDValue Op);
220  SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
221  bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult);
222  bool CustomWidenLowerNode(SDNode *N, EVT VT);
223 
224  /// Replace each result of the given MERGE_VALUES node with the corresponding
225  /// input operand, except for the result 'ResNo', for which the corresponding
226  /// input operand is returned.
227  SDValue DisintegrateMERGE_VALUES(SDNode *N, unsigned ResNo);
228 
229  SDValue JoinIntegers(SDValue Lo, SDValue Hi);
230 
231  std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
232 
233  SDValue PromoteTargetBoolean(SDValue Bool, EVT ValVT);
234 
235  void ReplaceValueWith(SDValue From, SDValue To);
236  void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
237  void SplitInteger(SDValue Op, EVT LoVT, EVT HiVT,
238  SDValue &Lo, SDValue &Hi);
239 
240  //===--------------------------------------------------------------------===//
241  // Integer Promotion Support: LegalizeIntegerTypes.cpp
242  //===--------------------------------------------------------------------===//
243 
244  /// Given a processed operand Op which was promoted to a larger integer type,
245  /// this returns the promoted value. The low bits of the promoted value
246  /// corresponding to the original type are exactly equal to Op.
247  /// The extra bits contain rubbish, so the promoted value may need to be zero-
248  /// or sign-extended from the original type before it is usable (the helpers
249  /// SExtPromotedInteger and ZExtPromotedInteger can do this for you).
250  /// For example, if Op is an i16 and was promoted to an i32, then this method
251  /// returns an i32, the lower 16 bits of which coincide with Op, and the upper
252  /// 16 bits of which contain rubbish.
253  SDValue GetPromotedInteger(SDValue Op) {
254  TableId &PromotedId = PromotedIntegers[getTableId(Op)];
255  SDValue PromotedOp = getSDValue(PromotedId);
256  assert(PromotedOp.getNode() && "Operand wasn't promoted?");
257  return PromotedOp;
258  }
259  void SetPromotedInteger(SDValue Op, SDValue Result);
260 
261  /// Get a promoted operand and sign extend it to the final size.
262  SDValue SExtPromotedInteger(SDValue Op) {
263  EVT OldVT = Op.getValueType();
264  SDLoc dl(Op);
265  Op = GetPromotedInteger(Op);
266  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
267  DAG.getValueType(OldVT));
268  }
269 
270  /// Get a promoted operand and zero extend it to the final size.
271  SDValue ZExtPromotedInteger(SDValue Op) {
272  EVT OldVT = Op.getValueType();
273  SDLoc dl(Op);
274  Op = GetPromotedInteger(Op);
275  return DAG.getZeroExtendInReg(Op, dl, OldVT);
276  }
277 
278  // Get a promoted operand and sign or zero extend it to the final size
279  // (depending on TargetLoweringInfo::isSExtCheaperThanZExt). For a given
280  // subtarget and type, the choice of sign or zero-extension will be
281  // consistent.
282  SDValue SExtOrZExtPromotedInteger(SDValue Op) {
283  EVT OldVT = Op.getValueType();
284  SDLoc DL(Op);
285  Op = GetPromotedInteger(Op);
286  if (TLI.isSExtCheaperThanZExt(OldVT, Op.getValueType()))
287  return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), Op,
288  DAG.getValueType(OldVT));
289  return DAG.getZeroExtendInReg(Op, DL, OldVT);
290  }
291 
292  // Promote the given operand V (vector or scalar) according to N's specific
293  // reduction kind. N must be an integer VECREDUCE_* or VP_REDUCE_*. Returns
294  // the nominal extension opcode (ISD::(ANY|ZERO|SIGN)_EXTEND) and the
295  // promoted value.
296  SDValue PromoteIntOpVectorReduction(SDNode *N, SDValue V);
297 
298  // Integer Result Promotion.
299  void PromoteIntegerResult(SDNode *N, unsigned ResNo);
300  SDValue PromoteIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
301  SDValue PromoteIntRes_AssertSext(SDNode *N);
302  SDValue PromoteIntRes_AssertZext(SDNode *N);
303  SDValue PromoteIntRes_Atomic0(AtomicSDNode *N);
304  SDValue PromoteIntRes_Atomic1(AtomicSDNode *N);
305  SDValue PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N, unsigned ResNo);
306  SDValue PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N);
307  SDValue PromoteIntRes_INSERT_SUBVECTOR(SDNode *N);
308  SDValue PromoteIntRes_VECTOR_REVERSE(SDNode *N);
309  SDValue PromoteIntRes_VECTOR_SHUFFLE(SDNode *N);
310  SDValue PromoteIntRes_VECTOR_SPLICE(SDNode *N);
311  SDValue PromoteIntRes_BUILD_VECTOR(SDNode *N);
312  SDValue PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N);
313  SDValue PromoteIntRes_SPLAT_VECTOR(SDNode *N);
314  SDValue PromoteIntRes_STEP_VECTOR(SDNode *N);
315  SDValue PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N);
316  SDValue PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N);
317  SDValue PromoteIntRes_CONCAT_VECTORS(SDNode *N);
318  SDValue PromoteIntRes_BITCAST(SDNode *N);
319  SDValue PromoteIntRes_BSWAP(SDNode *N);
320  SDValue PromoteIntRes_BITREVERSE(SDNode *N);
321  SDValue PromoteIntRes_BUILD_PAIR(SDNode *N);
322  SDValue PromoteIntRes_Constant(SDNode *N);
323  SDValue PromoteIntRes_CTLZ(SDNode *N);
324  SDValue PromoteIntRes_CTPOP_PARITY(SDNode *N);
325  SDValue PromoteIntRes_CTTZ(SDNode *N);
326  SDValue PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N);
327  SDValue PromoteIntRes_FP_TO_XINT(SDNode *N);
328  SDValue PromoteIntRes_FP_TO_XINT_SAT(SDNode *N);
329  SDValue PromoteIntRes_FP_TO_FP16(SDNode *N);
330  SDValue PromoteIntRes_FREEZE(SDNode *N);
331  SDValue PromoteIntRes_INT_EXTEND(SDNode *N);
332  SDValue PromoteIntRes_LOAD(LoadSDNode *N);
333  SDValue PromoteIntRes_MLOAD(MaskedLoadSDNode *N);
334  SDValue PromoteIntRes_MGATHER(MaskedGatherSDNode *N);
335  SDValue PromoteIntRes_Overflow(SDNode *N);
336  SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo);
337  SDValue PromoteIntRes_SELECT(SDNode *N);
338  SDValue PromoteIntRes_VSELECT(SDNode *N);
339  SDValue PromoteIntRes_SELECT_CC(SDNode *N);
340  SDValue PromoteIntRes_SETCC(SDNode *N);
341  SDValue PromoteIntRes_SHL(SDNode *N, bool IsVP);
342  SDValue PromoteIntRes_SimpleIntBinOp(SDNode *N, bool IsVP);
343  SDValue PromoteIntRes_ZExtIntBinOp(SDNode *N, bool IsVP);
344  SDValue PromoteIntRes_SExtIntBinOp(SDNode *N, bool IsVP);
345  SDValue PromoteIntRes_UMINUMAX(SDNode *N);
346  SDValue PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N);
347  SDValue PromoteIntRes_SRA(SDNode *N, bool IsVP);
348  SDValue PromoteIntRes_SRL(SDNode *N, bool IsVP);
349  SDValue PromoteIntRes_TRUNCATE(SDNode *N);
350  SDValue PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo);
351  SDValue PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo);
352  SDValue PromoteIntRes_SADDSUBO_CARRY(SDNode *N, unsigned ResNo);
353  SDValue PromoteIntRes_UNDEF(SDNode *N);
354  SDValue PromoteIntRes_VAARG(SDNode *N);
355  SDValue PromoteIntRes_VSCALE(SDNode *N);
356  SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
357  SDValue PromoteIntRes_ADDSUBSHLSAT(SDNode *N);
358  SDValue PromoteIntRes_MULFIX(SDNode *N);
359  SDValue PromoteIntRes_DIVFIX(SDNode *N);
360  SDValue PromoteIntRes_FLT_ROUNDS(SDNode *N);
361  SDValue PromoteIntRes_VECREDUCE(SDNode *N);
362  SDValue PromoteIntRes_VP_REDUCE(SDNode *N);
363  SDValue PromoteIntRes_ABS(SDNode *N);
364  SDValue PromoteIntRes_Rotate(SDNode *N);
365  SDValue PromoteIntRes_FunnelShift(SDNode *N);
366 
367  // Integer Operand Promotion.
368  bool PromoteIntegerOperand(SDNode *N, unsigned OpNo);
369  SDValue PromoteIntOp_ANY_EXTEND(SDNode *N);
370  SDValue PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N);
371  SDValue PromoteIntOp_BITCAST(SDNode *N);
372  SDValue PromoteIntOp_BUILD_PAIR(SDNode *N);
373  SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
374  SDValue PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo);
375  SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N);
376  SDValue PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo);
377  SDValue PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N);
378  SDValue PromoteIntOp_INSERT_SUBVECTOR(SDNode *N);
379  SDValue PromoteIntOp_CONCAT_VECTORS(SDNode *N);
380  SDValue PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N);
381  SDValue PromoteIntOp_SPLAT_VECTOR(SDNode *N);
382  SDValue PromoteIntOp_SELECT(SDNode *N, unsigned OpNo);
383  SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
384  SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
385  SDValue PromoteIntOp_Shift(SDNode *N);
386  SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
387  SDValue PromoteIntOp_SINT_TO_FP(SDNode *N);
388  SDValue PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N);
389  SDValue PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo);
390  SDValue PromoteIntOp_TRUNCATE(SDNode *N);
391  SDValue PromoteIntOp_UINT_TO_FP(SDNode *N);
392  SDValue PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N);
393  SDValue PromoteIntOp_ZERO_EXTEND(SDNode *N);
394  SDValue PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
395  SDValue PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo);
396  SDValue PromoteIntOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
397  SDValue PromoteIntOp_MGATHER(MaskedGatherSDNode *N, unsigned OpNo);
398  SDValue PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo);
399  SDValue PromoteIntOp_FRAMERETURNADDR(SDNode *N);
400  SDValue PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo);
401  SDValue PromoteIntOp_FIX(SDNode *N);
402  SDValue PromoteIntOp_FPOWI(SDNode *N);
403  SDValue PromoteIntOp_VECREDUCE(SDNode *N);
404  SDValue PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo);
405  SDValue PromoteIntOp_SET_ROUNDING(SDNode *N);
406 
407  void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
408 
409  //===--------------------------------------------------------------------===//
410  // Integer Expansion Support: LegalizeIntegerTypes.cpp
411  //===--------------------------------------------------------------------===//
412 
413  /// Given a processed operand Op which was expanded into two integers of half
414  /// the size, this returns the two halves. The low bits of Op are exactly
415  /// equal to the bits of Lo; the high bits exactly equal Hi.
416  /// For example, if Op is an i64 which was expanded into two i32's, then this
417  /// method returns the two i32's, with Lo being equal to the lower 32 bits of
418  /// Op, and Hi being equal to the upper 32 bits.
419  void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
420  void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi);
421 
422  // Integer Result Expansion.
423  void ExpandIntegerResult(SDNode *N, unsigned ResNo);
424  void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
425  void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi);
426  void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi);
427  void ExpandIntRes_Constant (SDNode *N, SDValue &Lo, SDValue &Hi);
428  void ExpandIntRes_ABS (SDNode *N, SDValue &Lo, SDValue &Hi);
429  void ExpandIntRes_CTLZ (SDNode *N, SDValue &Lo, SDValue &Hi);
430  void ExpandIntRes_CTPOP (SDNode *N, SDValue &Lo, SDValue &Hi);
431  void ExpandIntRes_CTTZ (SDNode *N, SDValue &Lo, SDValue &Hi);
432  void ExpandIntRes_LOAD (LoadSDNode *N, SDValue &Lo, SDValue &Hi);
433  void ExpandIntRes_READCYCLECOUNTER (SDNode *N, SDValue &Lo, SDValue &Hi);
434  void ExpandIntRes_SIGN_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
435  void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDValue &Lo, SDValue &Hi);
436  void ExpandIntRes_TRUNCATE (SDNode *N, SDValue &Lo, SDValue &Hi);
437  void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
438  void ExpandIntRes_FLT_ROUNDS (SDNode *N, SDValue &Lo, SDValue &Hi);
439  void ExpandIntRes_FP_TO_SINT (SDNode *N, SDValue &Lo, SDValue &Hi);
440  void ExpandIntRes_FP_TO_UINT (SDNode *N, SDValue &Lo, SDValue &Hi);
441  void ExpandIntRes_FP_TO_XINT_SAT (SDNode *N, SDValue &Lo, SDValue &Hi);
442  void ExpandIntRes_LLROUND_LLRINT (SDNode *N, SDValue &Lo, SDValue &Hi);
443 
444  void ExpandIntRes_Logical (SDNode *N, SDValue &Lo, SDValue &Hi);
445  void ExpandIntRes_ADDSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
446  void ExpandIntRes_ADDSUBC (SDNode *N, SDValue &Lo, SDValue &Hi);
447  void ExpandIntRes_ADDSUBE (SDNode *N, SDValue &Lo, SDValue &Hi);
448  void ExpandIntRes_ADDSUBCARRY (SDNode *N, SDValue &Lo, SDValue &Hi);
449  void ExpandIntRes_SADDSUBO_CARRY (SDNode *N, SDValue &Lo, SDValue &Hi);
450  void ExpandIntRes_BITREVERSE (SDNode *N, SDValue &Lo, SDValue &Hi);
451  void ExpandIntRes_BSWAP (SDNode *N, SDValue &Lo, SDValue &Hi);
452  void ExpandIntRes_PARITY (SDNode *N, SDValue &Lo, SDValue &Hi);
453  void ExpandIntRes_MUL (SDNode *N, SDValue &Lo, SDValue &Hi);
454  void ExpandIntRes_SDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
455  void ExpandIntRes_SREM (SDNode *N, SDValue &Lo, SDValue &Hi);
456  void ExpandIntRes_UDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
457  void ExpandIntRes_UREM (SDNode *N, SDValue &Lo, SDValue &Hi);
458  void ExpandIntRes_Shift (SDNode *N, SDValue &Lo, SDValue &Hi);
459 
460  void ExpandIntRes_MINMAX (SDNode *N, SDValue &Lo, SDValue &Hi);
461 
462  void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
463  void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
464  void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi);
465  void ExpandIntRes_ADDSUBSAT (SDNode *N, SDValue &Lo, SDValue &Hi);
466  void ExpandIntRes_SHLSAT (SDNode *N, SDValue &Lo, SDValue &Hi);
467  void ExpandIntRes_MULFIX (SDNode *N, SDValue &Lo, SDValue &Hi);
468  void ExpandIntRes_DIVFIX (SDNode *N, SDValue &Lo, SDValue &Hi);
469 
470  void ExpandIntRes_ATOMIC_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
471  void ExpandIntRes_VECREDUCE (SDNode *N, SDValue &Lo, SDValue &Hi);
472 
473  void ExpandIntRes_Rotate (SDNode *N, SDValue &Lo, SDValue &Hi);
474  void ExpandIntRes_FunnelShift (SDNode *N, SDValue &Lo, SDValue &Hi);
475 
476  void ExpandIntRes_VSCALE (SDNode *N, SDValue &Lo, SDValue &Hi);
477 
478  void ExpandShiftByConstant(SDNode *N, const APInt &Amt,
479  SDValue &Lo, SDValue &Hi);
480  bool ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
481  bool ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
482 
483  // Integer Operand Expansion.
484  bool ExpandIntegerOperand(SDNode *N, unsigned OpNo);
485  SDValue ExpandIntOp_BR_CC(SDNode *N);
486  SDValue ExpandIntOp_SELECT_CC(SDNode *N);
487  SDValue ExpandIntOp_SETCC(SDNode *N);
488  SDValue ExpandIntOp_SETCCCARRY(SDNode *N);
489  SDValue ExpandIntOp_Shift(SDNode *N);
490  SDValue ExpandIntOp_SINT_TO_FP(SDNode *N);
491  SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo);
492  SDValue ExpandIntOp_TRUNCATE(SDNode *N);
493  SDValue ExpandIntOp_UINT_TO_FP(SDNode *N);
494  SDValue ExpandIntOp_RETURNADDR(SDNode *N);
495  SDValue ExpandIntOp_ATOMIC_STORE(SDNode *N);
496  SDValue ExpandIntOp_SPLAT_VECTOR(SDNode *N);
497 
498  void IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
499  ISD::CondCode &CCCode, const SDLoc &dl);
500 
501  //===--------------------------------------------------------------------===//
502  // Float to Integer Conversion Support: LegalizeFloatTypes.cpp
503  //===--------------------------------------------------------------------===//
504 
505  /// GetSoftenedFloat - Given a processed operand Op which was converted to an
506  /// integer of the same size, this returns the integer. The integer contains
507  /// exactly the same bits as Op - only the type changed. For example, if Op
508  /// is an f32 which was softened to an i32, then this method returns an i32,
509  /// the bits of which coincide with those of Op
510  SDValue GetSoftenedFloat(SDValue Op) {
511  TableId Id = getTableId(Op);
512  auto Iter = SoftenedFloats.find(Id);
513  if (Iter == SoftenedFloats.end()) {
514  assert(isSimpleLegalType(Op.getValueType()) &&
515  "Operand wasn't converted to integer?");
516  return Op;
517  }
518  SDValue SoftenedOp = getSDValue(Iter->second);
519  assert(SoftenedOp.getNode() && "Unconverted op in SoftenedFloats?");
520  return SoftenedOp;
521  }
522  void SetSoftenedFloat(SDValue Op, SDValue Result);
523 
524  // Convert Float Results to Integer.
525  void SoftenFloatResult(SDNode *N, unsigned ResNo);
526  SDValue SoftenFloatRes_Unary(SDNode *N, RTLIB::Libcall LC);
527  SDValue SoftenFloatRes_Binary(SDNode *N, RTLIB::Libcall LC);
528  SDValue SoftenFloatRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
529  SDValue SoftenFloatRes_BITCAST(SDNode *N);
530  SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
531  SDValue SoftenFloatRes_ConstantFP(SDNode *N);
532  SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo);
533  SDValue SoftenFloatRes_FABS(SDNode *N);
534  SDValue SoftenFloatRes_FMINNUM(SDNode *N);
535  SDValue SoftenFloatRes_FMAXNUM(SDNode *N);
536  SDValue SoftenFloatRes_FADD(SDNode *N);
537  SDValue SoftenFloatRes_FCBRT(SDNode *N);
538  SDValue SoftenFloatRes_FCEIL(SDNode *N);
539  SDValue SoftenFloatRes_FCOPYSIGN(SDNode *N);
540  SDValue SoftenFloatRes_FCOS(SDNode *N);
541  SDValue SoftenFloatRes_FDIV(SDNode *N);
542  SDValue SoftenFloatRes_FEXP(SDNode *N);
543  SDValue SoftenFloatRes_FEXP2(SDNode *N);
544  SDValue SoftenFloatRes_FFLOOR(SDNode *N);
545  SDValue SoftenFloatRes_FLOG(SDNode *N);
546  SDValue SoftenFloatRes_FLOG2(SDNode *N);
547  SDValue SoftenFloatRes_FLOG10(SDNode *N);
548  SDValue SoftenFloatRes_FMA(SDNode *N);
549  SDValue SoftenFloatRes_FMUL(SDNode *N);
550  SDValue SoftenFloatRes_FNEARBYINT(SDNode *N);
551  SDValue SoftenFloatRes_FNEG(SDNode *N);
552  SDValue SoftenFloatRes_FP_EXTEND(SDNode *N);
553  SDValue SoftenFloatRes_FP16_TO_FP(SDNode *N);
554  SDValue SoftenFloatRes_FP_ROUND(SDNode *N);
555  SDValue SoftenFloatRes_FPOW(SDNode *N);
556  SDValue SoftenFloatRes_FPOWI(SDNode *N);
557  SDValue SoftenFloatRes_FREEZE(SDNode *N);
558  SDValue SoftenFloatRes_FREM(SDNode *N);
559  SDValue SoftenFloatRes_FRINT(SDNode *N);
560  SDValue SoftenFloatRes_FROUND(SDNode *N);
561  SDValue SoftenFloatRes_FROUNDEVEN(SDNode *N);
562  SDValue SoftenFloatRes_FSIN(SDNode *N);
563  SDValue SoftenFloatRes_FSQRT(SDNode *N);
564  SDValue SoftenFloatRes_FSUB(SDNode *N);
565  SDValue SoftenFloatRes_FTRUNC(SDNode *N);
566  SDValue SoftenFloatRes_LOAD(SDNode *N);
567  SDValue SoftenFloatRes_SELECT(SDNode *N);
568  SDValue SoftenFloatRes_SELECT_CC(SDNode *N);
569  SDValue SoftenFloatRes_UNDEF(SDNode *N);
570  SDValue SoftenFloatRes_VAARG(SDNode *N);
571  SDValue SoftenFloatRes_XINT_TO_FP(SDNode *N);
572  SDValue SoftenFloatRes_VECREDUCE(SDNode *N);
573  SDValue SoftenFloatRes_VECREDUCE_SEQ(SDNode *N);
574 
575  // Convert Float Operand to Integer.
576  bool SoftenFloatOperand(SDNode *N, unsigned OpNo);
577  SDValue SoftenFloatOp_Unary(SDNode *N, RTLIB::Libcall LC);
578  SDValue SoftenFloatOp_BITCAST(SDNode *N);
579  SDValue SoftenFloatOp_BR_CC(SDNode *N);
580  SDValue SoftenFloatOp_FP_ROUND(SDNode *N);
581  SDValue SoftenFloatOp_FP_TO_XINT(SDNode *N);
582  SDValue SoftenFloatOp_FP_TO_XINT_SAT(SDNode *N);
583  SDValue SoftenFloatOp_LROUND(SDNode *N);
584  SDValue SoftenFloatOp_LLROUND(SDNode *N);
585  SDValue SoftenFloatOp_LRINT(SDNode *N);
586  SDValue SoftenFloatOp_LLRINT(SDNode *N);
587  SDValue SoftenFloatOp_SELECT_CC(SDNode *N);
588  SDValue SoftenFloatOp_SETCC(SDNode *N);
589  SDValue SoftenFloatOp_STORE(SDNode *N, unsigned OpNo);
590  SDValue SoftenFloatOp_FCOPYSIGN(SDNode *N);
591 
592  //===--------------------------------------------------------------------===//
593  // Float Expansion Support: LegalizeFloatTypes.cpp
594  //===--------------------------------------------------------------------===//
595 
596  /// Given a processed operand Op which was expanded into two floating-point
597  /// values of half the size, this returns the two halves.
598  /// The low bits of Op are exactly equal to the bits of Lo; the high bits
599  /// exactly equal Hi. For example, if Op is a ppcf128 which was expanded
600  /// into two f64's, then this method returns the two f64's, with Lo being
601  /// equal to the lower 64 bits of Op, and Hi to the upper 64 bits.
602  void GetExpandedFloat(SDValue Op, SDValue &Lo, SDValue &Hi);
603  void SetExpandedFloat(SDValue Op, SDValue Lo, SDValue Hi);
604 
605  // Float Result Expansion.
606  void ExpandFloatResult(SDNode *N, unsigned ResNo);
607  void ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, SDValue &Hi);
608  void ExpandFloatRes_Unary(SDNode *N, RTLIB::Libcall LC,
609  SDValue &Lo, SDValue &Hi);
610  void ExpandFloatRes_Binary(SDNode *N, RTLIB::Libcall LC,
611  SDValue &Lo, SDValue &Hi);
612  void ExpandFloatRes_FABS (SDNode *N, SDValue &Lo, SDValue &Hi);
613  void ExpandFloatRes_FMINNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
614  void ExpandFloatRes_FMAXNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
615  void ExpandFloatRes_FADD (SDNode *N, SDValue &Lo, SDValue &Hi);
616  void ExpandFloatRes_FCBRT (SDNode *N, SDValue &Lo, SDValue &Hi);
617  void ExpandFloatRes_FCEIL (SDNode *N, SDValue &Lo, SDValue &Hi);
618  void ExpandFloatRes_FCOPYSIGN (SDNode *N, SDValue &Lo, SDValue &Hi);
619  void ExpandFloatRes_FCOS (SDNode *N, SDValue &Lo, SDValue &Hi);
620  void ExpandFloatRes_FDIV (SDNode *N, SDValue &Lo, SDValue &Hi);
621  void ExpandFloatRes_FEXP (SDNode *N, SDValue &Lo, SDValue &Hi);
622  void ExpandFloatRes_FEXP2 (SDNode *N, SDValue &Lo, SDValue &Hi);
623  void ExpandFloatRes_FFLOOR (SDNode *N, SDValue &Lo, SDValue &Hi);
624  void ExpandFloatRes_FLOG (SDNode *N, SDValue &Lo, SDValue &Hi);
625  void ExpandFloatRes_FLOG2 (SDNode *N, SDValue &Lo, SDValue &Hi);
626  void ExpandFloatRes_FLOG10 (SDNode *N, SDValue &Lo, SDValue &Hi);
627  void ExpandFloatRes_FMA (SDNode *N, SDValue &Lo, SDValue &Hi);
628  void ExpandFloatRes_FMUL (SDNode *N, SDValue &Lo, SDValue &Hi);
629  void ExpandFloatRes_FNEARBYINT(SDNode *N, SDValue &Lo, SDValue &Hi);
630  void ExpandFloatRes_FNEG (SDNode *N, SDValue &Lo, SDValue &Hi);
631  void ExpandFloatRes_FP_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
632  void ExpandFloatRes_FPOW (SDNode *N, SDValue &Lo, SDValue &Hi);
633  void ExpandFloatRes_FPOWI (SDNode *N, SDValue &Lo, SDValue &Hi);
634  void ExpandFloatRes_FREEZE (SDNode *N, SDValue &Lo, SDValue &Hi);
635  void ExpandFloatRes_FREM (SDNode *N, SDValue &Lo, SDValue &Hi);
636  void ExpandFloatRes_FRINT (SDNode *N, SDValue &Lo, SDValue &Hi);
637  void ExpandFloatRes_FROUND (SDNode *N, SDValue &Lo, SDValue &Hi);
638  void ExpandFloatRes_FROUNDEVEN(SDNode *N, SDValue &Lo, SDValue &Hi);
639  void ExpandFloatRes_FSIN (SDNode *N, SDValue &Lo, SDValue &Hi);
640  void ExpandFloatRes_FSQRT (SDNode *N, SDValue &Lo, SDValue &Hi);
641  void ExpandFloatRes_FSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
642  void ExpandFloatRes_FTRUNC (SDNode *N, SDValue &Lo, SDValue &Hi);
643  void ExpandFloatRes_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
644  void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);
645 
646  // Float Operand Expansion.
647  bool ExpandFloatOperand(SDNode *N, unsigned OpNo);
648  SDValue ExpandFloatOp_BR_CC(SDNode *N);
649  SDValue ExpandFloatOp_FCOPYSIGN(SDNode *N);
650  SDValue ExpandFloatOp_FP_ROUND(SDNode *N);
651  SDValue ExpandFloatOp_FP_TO_XINT(SDNode *N);
652  SDValue ExpandFloatOp_LROUND(SDNode *N);
653  SDValue ExpandFloatOp_LLROUND(SDNode *N);
654  SDValue ExpandFloatOp_LRINT(SDNode *N);
655  SDValue ExpandFloatOp_LLRINT(SDNode *N);
656  SDValue ExpandFloatOp_SELECT_CC(SDNode *N);
657  SDValue ExpandFloatOp_SETCC(SDNode *N);
658  SDValue ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
659 
660  void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
661  ISD::CondCode &CCCode, const SDLoc &dl,
662  SDValue &Chain, bool IsSignaling = false);
663 
664  //===--------------------------------------------------------------------===//
665  // Float promotion support: LegalizeFloatTypes.cpp
666  //===--------------------------------------------------------------------===//
667 
668  SDValue GetPromotedFloat(SDValue Op) {
669  TableId &PromotedId = PromotedFloats[getTableId(Op)];
670  SDValue PromotedOp = getSDValue(PromotedId);
671  assert(PromotedOp.getNode() && "Operand wasn't promoted?");
672  return PromotedOp;
673  }
674  void SetPromotedFloat(SDValue Op, SDValue Result);
675 
676  void PromoteFloatResult(SDNode *N, unsigned ResNo);
677  SDValue PromoteFloatRes_BITCAST(SDNode *N);
678  SDValue PromoteFloatRes_BinOp(SDNode *N);
679  SDValue PromoteFloatRes_ConstantFP(SDNode *N);
680  SDValue PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N);
681  SDValue PromoteFloatRes_FCOPYSIGN(SDNode *N);
682  SDValue PromoteFloatRes_FMAD(SDNode *N);
683  SDValue PromoteFloatRes_FPOWI(SDNode *N);
684  SDValue PromoteFloatRes_FP_ROUND(SDNode *N);
685  SDValue PromoteFloatRes_LOAD(SDNode *N);
686  SDValue PromoteFloatRes_SELECT(SDNode *N);
687  SDValue PromoteFloatRes_SELECT_CC(SDNode *N);
688  SDValue PromoteFloatRes_UnaryOp(SDNode *N);
689  SDValue PromoteFloatRes_UNDEF(SDNode *N);
690  SDValue BitcastToInt_ATOMIC_SWAP(SDNode *N);
691  SDValue PromoteFloatRes_XINT_TO_FP(SDNode *N);
692  SDValue PromoteFloatRes_VECREDUCE(SDNode *N);
693  SDValue PromoteFloatRes_VECREDUCE_SEQ(SDNode *N);
694 
695  bool PromoteFloatOperand(SDNode *N, unsigned OpNo);
696  SDValue PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo);
697  SDValue PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo);
698  SDValue PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo);
699  SDValue PromoteFloatOp_FP_TO_XINT(SDNode *N, unsigned OpNo);
700  SDValue PromoteFloatOp_FP_TO_XINT_SAT(SDNode *N, unsigned OpNo);
701  SDValue PromoteFloatOp_STORE(SDNode *N, unsigned OpNo);
702  SDValue PromoteFloatOp_SELECT_CC(SDNode *N, unsigned OpNo);
703  SDValue PromoteFloatOp_SETCC(SDNode *N, unsigned OpNo);
704 
705  //===--------------------------------------------------------------------===//
706  // Half soft promotion support: LegalizeFloatTypes.cpp
707  //===--------------------------------------------------------------------===//
708 
709  SDValue GetSoftPromotedHalf(SDValue Op) {
710  TableId &PromotedId = SoftPromotedHalfs[getTableId(Op)];
711  SDValue PromotedOp = getSDValue(PromotedId);
712  assert(PromotedOp.getNode() && "Operand wasn't promoted?");
713  return PromotedOp;
714  }
715  void SetSoftPromotedHalf(SDValue Op, SDValue Result);
716 
717  void SoftPromoteHalfResult(SDNode *N, unsigned ResNo);
718  SDValue SoftPromoteHalfRes_BinOp(SDNode *N);
719  SDValue SoftPromoteHalfRes_BITCAST(SDNode *N);
720  SDValue SoftPromoteHalfRes_ConstantFP(SDNode *N);
721  SDValue SoftPromoteHalfRes_EXTRACT_VECTOR_ELT(SDNode *N);
722  SDValue SoftPromoteHalfRes_FCOPYSIGN(SDNode *N);
723  SDValue SoftPromoteHalfRes_FMAD(SDNode *N);
724  SDValue SoftPromoteHalfRes_FPOWI(SDNode *N);
725  SDValue SoftPromoteHalfRes_FP_ROUND(SDNode *N);
726  SDValue SoftPromoteHalfRes_LOAD(SDNode *N);
727  SDValue SoftPromoteHalfRes_SELECT(SDNode *N);
728  SDValue SoftPromoteHalfRes_SELECT_CC(SDNode *N);
729  SDValue SoftPromoteHalfRes_UnaryOp(SDNode *N);
730  SDValue SoftPromoteHalfRes_XINT_TO_FP(SDNode *N);
731  SDValue SoftPromoteHalfRes_UNDEF(SDNode *N);
732  SDValue SoftPromoteHalfRes_VECREDUCE(SDNode *N);
733  SDValue SoftPromoteHalfRes_VECREDUCE_SEQ(SDNode *N);
734 
735  bool SoftPromoteHalfOperand(SDNode *N, unsigned OpNo);
736  SDValue SoftPromoteHalfOp_BITCAST(SDNode *N);
737  SDValue SoftPromoteHalfOp_FCOPYSIGN(SDNode *N, unsigned OpNo);
738  SDValue SoftPromoteHalfOp_FP_EXTEND(SDNode *N);
739  SDValue SoftPromoteHalfOp_FP_TO_XINT(SDNode *N);
740  SDValue SoftPromoteHalfOp_FP_TO_XINT_SAT(SDNode *N);
741  SDValue SoftPromoteHalfOp_SETCC(SDNode *N);
742  SDValue SoftPromoteHalfOp_SELECT_CC(SDNode *N, unsigned OpNo);
743  SDValue SoftPromoteHalfOp_STORE(SDNode *N, unsigned OpNo);
744 
745  //===--------------------------------------------------------------------===//
746  // Scalarization Support: LegalizeVectorTypes.cpp
747  //===--------------------------------------------------------------------===//
748 
749  /// Given a processed one-element vector Op which was scalarized to its
750  /// element type, this returns the element. For example, if Op is a v1i32,
751  /// Op = < i32 val >, this method returns val, an i32.
752  SDValue GetScalarizedVector(SDValue Op) {
753  TableId &ScalarizedId = ScalarizedVectors[getTableId(Op)];
754  SDValue ScalarizedOp = getSDValue(ScalarizedId);
755  assert(ScalarizedOp.getNode() && "Operand wasn't scalarized?");
756  return ScalarizedOp;
757  }
758  void SetScalarizedVector(SDValue Op, SDValue Result);
759 
760  // Vector Result Scalarization: <1 x ty> -> ty.
761  void ScalarizeVectorResult(SDNode *N, unsigned ResNo);
762  SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
763  SDValue ScalarizeVecRes_BinOp(SDNode *N);
764  SDValue ScalarizeVecRes_TernaryOp(SDNode *N);
765  SDValue ScalarizeVecRes_UnaryOp(SDNode *N);
766  SDValue ScalarizeVecRes_StrictFPOp(SDNode *N);
767  SDValue ScalarizeVecRes_OverflowOp(SDNode *N, unsigned ResNo);
768  SDValue ScalarizeVecRes_InregOp(SDNode *N);
769  SDValue ScalarizeVecRes_VecInregOp(SDNode *N);
770 
771  SDValue ScalarizeVecRes_BITCAST(SDNode *N);
772  SDValue ScalarizeVecRes_BUILD_VECTOR(SDNode *N);
773  SDValue ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N);
774  SDValue ScalarizeVecRes_FP_ROUND(SDNode *N);
775  SDValue ScalarizeVecRes_FPOWI(SDNode *N);
776  SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
777  SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
778  SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
779  SDValue ScalarizeVecRes_VSELECT(SDNode *N);
780  SDValue ScalarizeVecRes_SELECT(SDNode *N);
781  SDValue ScalarizeVecRes_SELECT_CC(SDNode *N);
782  SDValue ScalarizeVecRes_SETCC(SDNode *N);
783  SDValue ScalarizeVecRes_UNDEF(SDNode *N);
784  SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
785  SDValue ScalarizeVecRes_FP_TO_XINT_SAT(SDNode *N);
786 
787  SDValue ScalarizeVecRes_FIX(SDNode *N);
788 
789  // Vector Operand Scalarization: <1 x ty> -> ty.
790  bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
791  SDValue ScalarizeVecOp_BITCAST(SDNode *N);
792  SDValue ScalarizeVecOp_UnaryOp(SDNode *N);
793  SDValue ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N);
794  SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N);
795  SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
796  SDValue ScalarizeVecOp_VSELECT(SDNode *N);
797  SDValue ScalarizeVecOp_VSETCC(SDNode *N);
798  SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
799  SDValue ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo);
800  SDValue ScalarizeVecOp_STRICT_FP_ROUND(SDNode *N, unsigned OpNo);
801  SDValue ScalarizeVecOp_FP_EXTEND(SDNode *N);
802  SDValue ScalarizeVecOp_STRICT_FP_EXTEND(SDNode *N);
803  SDValue ScalarizeVecOp_VECREDUCE(SDNode *N);
804  SDValue ScalarizeVecOp_VECREDUCE_SEQ(SDNode *N);
805 
806  //===--------------------------------------------------------------------===//
807  // Vector Splitting Support: LegalizeVectorTypes.cpp
808  //===--------------------------------------------------------------------===//
809 
810  /// Given a processed vector Op which was split into vectors of half the size,
811  /// this method returns the halves. The first elements of Op coincide with the
812  /// elements of Lo; the remaining elements of Op coincide with the elements of
813  /// Hi: Op is what you would get by concatenating Lo and Hi.
814  /// For example, if Op is a v8i32 that was split into two v4i32's, then this
815  /// method returns the two v4i32's, with Lo corresponding to the first 4
816  /// elements of Op, and Hi to the last 4 elements.
817  void GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi);
818  void SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi);
819 
820  // Helper function for incrementing the pointer when splitting
821  // memory operations
822  void IncrementPointer(MemSDNode *N, EVT MemVT, MachinePointerInfo &MPI,
823  SDValue &Ptr, uint64_t *ScaledOffset = nullptr);
824 
825  // Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>.
826  void SplitVectorResult(SDNode *N, unsigned ResNo);
827  void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi, bool IsVP);
828  void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
829  void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
830  void SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo, SDValue &Hi);
831  void SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi);
832  void SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo, SDValue &Hi);
833  void SplitVecRes_StrictFPOp(SDNode *N, SDValue &Lo, SDValue &Hi);
834  void SplitVecRes_OverflowOp(SDNode *N, unsigned ResNo,
835  SDValue &Lo, SDValue &Hi);
836 
837  void SplitVecRes_FIX(SDNode *N, SDValue &Lo, SDValue &Hi);
838 
839  void SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi);
840  void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
841  void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi);
842  void SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
843  void SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
844  void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
845  void SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi);
846  void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
847  void SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi);
848  void SplitVecRes_MLOAD(MaskedLoadSDNode *MLD, SDValue &Lo, SDValue &Hi);
849  void SplitVecRes_MGATHER(MaskedGatherSDNode *MGT, SDValue &Lo, SDValue &Hi);
850  void SplitVecRes_ScalarOp(SDNode *N, SDValue &Lo, SDValue &Hi);
851  void SplitVecRes_STEP_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
852  void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
853  void SplitVecRes_VECTOR_REVERSE(SDNode *N, SDValue &Lo, SDValue &Hi);
854  void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
855  SDValue &Hi);
856  void SplitVecRes_VECTOR_SPLICE(SDNode *N, SDValue &Lo, SDValue &Hi);
857  void SplitVecRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi);
858  void SplitVecRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo, SDValue &Hi);
859 
860  // Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
861  bool SplitVectorOperand(SDNode *N, unsigned OpNo);
862  SDValue SplitVecOp_VSELECT(SDNode *N, unsigned OpNo);
863  SDValue SplitVecOp_VECREDUCE(SDNode *N, unsigned OpNo);
864  SDValue SplitVecOp_VECREDUCE_SEQ(SDNode *N);
865  SDValue SplitVecOp_UnaryOp(SDNode *N);
866  SDValue SplitVecOp_TruncateHelper(SDNode *N);
867 
868  SDValue SplitVecOp_BITCAST(SDNode *N);
869  SDValue SplitVecOp_INSERT_SUBVECTOR(SDNode *N, unsigned OpNo);
870  SDValue SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N);
871  SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
872  SDValue SplitVecOp_ExtVecInRegOp(SDNode *N);
873  SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
874  SDValue SplitVecOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
875  SDValue SplitVecOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
876  SDValue SplitVecOp_MGATHER(MaskedGatherSDNode *MGT, unsigned OpNo);
877  SDValue SplitVecOp_CONCAT_VECTORS(SDNode *N);
878  SDValue SplitVecOp_VSETCC(SDNode *N);
879  SDValue SplitVecOp_FP_ROUND(SDNode *N);
880  SDValue SplitVecOp_FCOPYSIGN(SDNode *N);
881  SDValue SplitVecOp_FP_TO_XINT_SAT(SDNode *N);
882 
883  //===--------------------------------------------------------------------===//
884  // Vector Widening Support: LegalizeVectorTypes.cpp
885  //===--------------------------------------------------------------------===//
886 
887  /// Given a processed vector Op which was widened into a larger vector, this
888  /// method returns the larger vector. The elements of the returned vector
889  /// consist of the elements of Op followed by elements containing rubbish.
890  /// For example, if Op is a v2i32 that was widened to a v4i32, then this
891  /// method returns a v4i32 for which the first two elements are the same as
892  /// those of Op, while the last two elements contain rubbish.
893  SDValue GetWidenedVector(SDValue Op) {
894  TableId &WidenedId = WidenedVectors[getTableId(Op)];
895  SDValue WidenedOp = getSDValue(WidenedId);
896  assert(WidenedOp.getNode() && "Operand wasn't widened?");
897  return WidenedOp;
898  }
899  void SetWidenedVector(SDValue Op, SDValue Result);
900 
901  // Widen Vector Result Promotion.
902  void WidenVectorResult(SDNode *N, unsigned ResNo);
903  SDValue WidenVecRes_MERGE_VALUES(SDNode* N, unsigned ResNo);
904  SDValue WidenVecRes_BITCAST(SDNode* N);
905  SDValue WidenVecRes_BUILD_VECTOR(SDNode* N);
906  SDValue WidenVecRes_CONCAT_VECTORS(SDNode* N);
907  SDValue WidenVecRes_EXTEND_VECTOR_INREG(SDNode* N);
908  SDValue WidenVecRes_EXTRACT_SUBVECTOR(SDNode* N);
909  SDValue WidenVecRes_INSERT_VECTOR_ELT(SDNode* N);
910  SDValue WidenVecRes_LOAD(SDNode* N);
911  SDValue WidenVecRes_MLOAD(MaskedLoadSDNode* N);
912  SDValue WidenVecRes_MGATHER(MaskedGatherSDNode* N);
913  SDValue WidenVecRes_ScalarOp(SDNode* N);
914  SDValue WidenVecRes_SELECT(SDNode* N);
915  SDValue WidenVSELECTMask(SDNode *N);
916  SDValue WidenVecRes_SELECT_CC(SDNode* N);
917  SDValue WidenVecRes_SETCC(SDNode* N);
918  SDValue WidenVecRes_STRICT_FSETCC(SDNode* N);
919  SDValue WidenVecRes_UNDEF(SDNode *N);
920  SDValue WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N);
921 
922  SDValue WidenVecRes_Ternary(SDNode *N);
923  SDValue WidenVecRes_Binary(SDNode *N, bool IsVP);
924  SDValue WidenVecRes_BinaryCanTrap(SDNode *N);
925  SDValue WidenVecRes_BinaryWithExtraScalarOp(SDNode *N);
926  SDValue WidenVecRes_StrictFP(SDNode *N);
927  SDValue WidenVecRes_OverflowOp(SDNode *N, unsigned ResNo);
928  SDValue WidenVecRes_Convert(SDNode *N);
929  SDValue WidenVecRes_Convert_StrictFP(SDNode *N);
930  SDValue WidenVecRes_FP_TO_XINT_SAT(SDNode *N);
931  SDValue WidenVecRes_FCOPYSIGN(SDNode *N);
932  SDValue WidenVecRes_POWI(SDNode *N);
933  SDValue WidenVecRes_Unary(SDNode *N);
934  SDValue WidenVecRes_InregOp(SDNode *N);
935 
936  // Widen Vector Operand.
937  bool WidenVectorOperand(SDNode *N, unsigned OpNo);
938  SDValue WidenVecOp_BITCAST(SDNode *N);
939  SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N);
940  SDValue WidenVecOp_EXTEND(SDNode *N);
941  SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
942  SDValue WidenVecOp_INSERT_SUBVECTOR(SDNode *N);
943  SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N);
944  SDValue WidenVecOp_STORE(SDNode* N);
945  SDValue WidenVecOp_MSTORE(SDNode* N, unsigned OpNo);
946  SDValue WidenVecOp_MGATHER(SDNode* N, unsigned OpNo);
947  SDValue WidenVecOp_MSCATTER(SDNode* N, unsigned OpNo);
948  SDValue WidenVecOp_SETCC(SDNode* N);
949  SDValue WidenVecOp_STRICT_FSETCC(SDNode* N);
950  SDValue WidenVecOp_VSELECT(SDNode *N);
951 
952  SDValue WidenVecOp_Convert(SDNode *N);
953  SDValue WidenVecOp_FP_TO_XINT_SAT(SDNode *N);
954  SDValue WidenVecOp_FCOPYSIGN(SDNode *N);
955  SDValue WidenVecOp_VECREDUCE(SDNode *N);
956  SDValue WidenVecOp_VECREDUCE_SEQ(SDNode *N);
957 
958  /// Helper function to generate a set of operations to perform
959  /// a vector operation for a wider type.
960  ///
961  SDValue UnrollVectorOp_StrictFP(SDNode *N, unsigned ResNE);
962 
963  //===--------------------------------------------------------------------===//
964  // Vector Widening Utilities Support: LegalizeVectorTypes.cpp
965  //===--------------------------------------------------------------------===//
966 
967  /// Helper function to generate a set of loads to load a vector with a
968  /// resulting wider type. It takes:
969  /// LdChain: list of chains for the load to be generated.
970  /// Ld: load to widen
971  SDValue GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
972  LoadSDNode *LD);
973 
974  /// Helper function to generate a set of extension loads to load a vector with
975  /// a resulting wider type. It takes:
976  /// LdChain: list of chains for the load to be generated.
977  /// Ld: load to widen
978  /// ExtType: extension element type
979  SDValue GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
980  LoadSDNode *LD, ISD::LoadExtType ExtType);
981 
982  /// Helper function to generate a set of stores to store a widen vector into
983  /// non-widen memory.
984  /// StChain: list of chains for the stores we have generated
985  /// ST: store of a widen value
986  void GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain, StoreSDNode *ST);
987 
988  /// Modifies a vector input (widen or narrows) to a vector of NVT. The
989  /// input vector must have the same element type as NVT.
990  /// When FillWithZeroes is "on" the vector will be widened with zeroes.
991  /// By default, the vector will be widened with undefined values.
992  SDValue ModifyToType(SDValue InOp, EVT NVT, bool FillWithZeroes = false);
993 
994  /// Return a mask of vector type MaskVT to replace InMask. Also adjust
995  /// MaskVT to ToMaskVT if needed with vector extension or truncation.
996  SDValue convertMask(SDValue InMask, EVT MaskVT, EVT ToMaskVT);
997 
998  //===--------------------------------------------------------------------===//
999  // Generic Splitting: LegalizeTypesGeneric.cpp
1000  //===--------------------------------------------------------------------===//
1001 
1002  // Legalization methods which only use that the illegal type is split into two
1003  // not necessarily identical types. As such they can be used for splitting
1004  // vectors and expanding integers and floats.
1005 
1006  void GetSplitOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
1007  if (Op.getValueType().isVector())
1008  GetSplitVector(Op, Lo, Hi);
1009  else if (Op.getValueType().isInteger())
1010  GetExpandedInteger(Op, Lo, Hi);
1011  else
1012  GetExpandedFloat(Op, Lo, Hi);
1013  }
1014 
1015  /// Use ISD::EXTRACT_ELEMENT nodes to extract the low and high parts of the
1016  /// given value.
1017  void GetPairElements(SDValue Pair, SDValue &Lo, SDValue &Hi);
1018 
1019  // Generic Result Splitting.
1020  void SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1021  SDValue &Lo, SDValue &Hi);
1022  void SplitRes_SELECT (SDNode *N, SDValue &Lo, SDValue &Hi);
1023  void SplitRes_SELECT_CC (SDNode *N, SDValue &Lo, SDValue &Hi);
1024  void SplitRes_UNDEF (SDNode *N, SDValue &Lo, SDValue &Hi);
1025  void SplitRes_FREEZE (SDNode *N, SDValue &Lo, SDValue &Hi);
1026 
1027  //===--------------------------------------------------------------------===//
1028  // Generic Expansion: LegalizeTypesGeneric.cpp
1029  //===--------------------------------------------------------------------===//
1030 
1031  // Legalization methods which only use that the illegal type is split into two
1032  // identical types of half the size, and that the Lo/Hi part is stored first
1033  // in memory on little/big-endian machines, followed by the Hi/Lo part. As
1034  // such they can be used for expanding integers and floats.
1035 
1036  void GetExpandedOp(SDValue Op, SDValue &Lo, SDValue &Hi) {
1037  if (Op.getValueType().isInteger())
1038  GetExpandedInteger(Op, Lo, Hi);
1039  else
1040  GetExpandedFloat(Op, Lo, Hi);
1041  }
1042 
1043 
1044  /// This function will split the integer \p Op into \p NumElements
1045  /// operations of type \p EltVT and store them in \p Ops.
1046  void IntegerToVector(SDValue Op, unsigned NumElements,
1047  SmallVectorImpl<SDValue> &Ops, EVT EltVT);
1048 
1049  // Generic Result Expansion.
1050  void ExpandRes_MERGE_VALUES (SDNode *N, unsigned ResNo,
1051  SDValue &Lo, SDValue &Hi);
1052  void ExpandRes_BITCAST (SDNode *N, SDValue &Lo, SDValue &Hi);
1053  void ExpandRes_BUILD_PAIR (SDNode *N, SDValue &Lo, SDValue &Hi);
1054  void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDValue &Lo, SDValue &Hi);
1055  void ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
1056  void ExpandRes_NormalLoad (SDNode *N, SDValue &Lo, SDValue &Hi);
1057  void ExpandRes_VAARG (SDNode *N, SDValue &Lo, SDValue &Hi);
1058 
1059  // Generic Operand Expansion.
1060  SDValue ExpandOp_BITCAST (SDNode *N);
1061  SDValue ExpandOp_BUILD_VECTOR (SDNode *N);
1062  SDValue ExpandOp_EXTRACT_ELEMENT (SDNode *N);
1063  SDValue ExpandOp_INSERT_VECTOR_ELT(SDNode *N);
1064  SDValue ExpandOp_SCALAR_TO_VECTOR (SDNode *N);
1065  SDValue ExpandOp_NormalStore (SDNode *N, unsigned OpNo);
1066 };
1067 
1068 } // end namespace llvm.
1069 
1070 #endif
i
i
Definition: README.txt:29
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:152
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1722
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
DenseMap.h
llvm::SelectionDAG::getZeroExtendInReg
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
Definition: SelectionDAG.cpp:1318
llvm::DAGTypeLegalizer::NodeIdFlags
NodeIdFlags
This pass uses the NodeId on the SDNodes to hold information about the state of the node.
Definition: LegalizeTypes.h:37
SelectionDAG.h
llvm::DAGTypeLegalizer::getDAG
SelectionDAG & getDAG() const
Definition: LegalizeTypes.h:208
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:447
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
llvm::DAGTypeLegalizer
This takes an arbitrary SelectionDAG as input and hacks on it until only value types the target machi...
Definition: LegalizeTypes.h:31
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1335
TargetLowering.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:747
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::DAGTypeLegalizer::NoteDeletion
void NoteDeletion(SDNode *Old, SDNode *New)
Definition: LegalizeTypes.h:180
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3189
llvm::TargetLoweringBase::ValueTypeActionImpl
Definition: TargetLowering.h:901
llvm::ISD::Register
@ Register
Definition: ISDOpcodes.h:74
llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction
LegalizeTypeAction getTypeAction(MVT VT) const
Definition: TargetLowering.h:912
uint64_t
llvm::MVT::MAX_ALLOWED_VALUETYPE
@ MAX_ALLOWED_VALUETYPE
Definition: MachineValueType.h:282
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8316
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1355
Compiler.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
LLVM_LIBRARY_VISIBILITY
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library,...
Definition: Compiler.h:131
Node
Definition: ItaniumDemangle.h:235
llvm::TargetLoweringBase::TypeLegal
@ TypeLegal
Definition: TargetLowering.h:207
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:440
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:206
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::ISD::TargetConstant
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
Definition: ISDOpcodes.h:158
llvm::SDNode::getNumValues
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Definition: SelectionDAGNodes.h:963
N
#define N
llvm::MVT::LAST_VALUETYPE
@ LAST_VALUETYPE
Definition: MachineValueType.h:276
llvm::DAGTypeLegalizer::DAGTypeLegalizer
DAGTypeLegalizer(SelectionDAG &dag)
Definition: LegalizeTypes.h:168
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:228
Debug.h
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