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24 AArch64::X3, AArch64::X4, AArch64::X5,
25 AArch64::X6, AArch64::X7};
27 AArch64::H3, AArch64::H4, AArch64::H5,
28 AArch64::H6, AArch64::H7};
30 AArch64::S3, AArch64::S4, AArch64::S5,
31 AArch64::S6, AArch64::S7};
33 AArch64::D3, AArch64::D4, AArch64::D5,
34 AArch64::D6, AArch64::D7};
36 AArch64::Q3, AArch64::Q4, AArch64::Q5,
37 AArch64::Q6, AArch64::Q7};
39 AArch64::Z3, AArch64::Z4, AArch64::Z5,
40 AArch64::Z6, AArch64::Z7};
62 bool RegsAllocated[8];
63 for (
int I = 0;
I < 8;
I++) {
68 auto &It = PendingMembers[0];
81 for (
int I = 0;
I < 8;
I++)
82 if (!RegsAllocated[
I])
86 PendingMembers.
clear();
91 for (
auto &It : PendingMembers) {
98 PendingMembers.clear();
111 PendingMembers.push_back(
154 PendingMembers.push_back(
162 unsigned EltsPerReg = (IsDarwinILP32 && LocVT.
SimpleTy ==
MVT::i32) ? 2 : 1;
164 RegList,
alignTo(PendingMembers.size(), EltsPerReg) / EltsPerReg);
165 if (RegResult && EltsPerReg == 1) {
166 for (
auto &It : PendingMembers) {
167 It.convertToReg(RegResult);
171 PendingMembers.clear();
173 }
else if (RegResult) {
174 assert(EltsPerReg == 2 &&
"unexpected ABI");
175 bool UseHigh =
false;
177 for (
auto &It : PendingMembers) {
185 PendingMembers.clear();
191 for (
auto Reg : RegList)
207 #include "AArch64GenCallingConv.inc"
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
This is an optimization pass for GlobalISel generic memory operations.
CCState - This class holds information needed while lowering arguments and return values.
static const MCPhysReg DRegList[]
bool isInConsecutiveRegsLast() const
void addLoc(const CCValAssign &V)
static bool finishStackBlock(SmallVectorImpl< CCValAssign > &PendingMembers, MVT LocVT, ISD::ArgFlagsTy &ArgFlags, CCState &State, Align SlotAlign)
Reg
All possible values of the reg field in the ModR/M byte.
bool isTargetDarwin() const
static const MCPhysReg QRegList[]
MachineFunction & getMachineFunction() const
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
MCPhysReg AllocateRegBlock(ArrayRef< MCPhysReg > Regs, unsigned RegsRequired)
AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive registers.
static const MCPhysReg XRegList[]
bool is32BitVector() const
Return true if this is a 32-bit vector type.
const AArch64TargetLowering * getTargetLowering() const override
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Align getNonZeroMemAlign() const
bool isTargetILP32() const
static const MCPhysReg ZRegList[]
static bool CC_AArch64_Custom_Stack_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
The Darwin variadic PCS places anonymous arguments in 8-byte stack slots.
Align getStackAlignment() const
Analysis containing CSE Info
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
CallingConv::ID getCallingConv() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
void setInConsecutiveRegs(bool Flag=true)
SmallVectorImpl< CCValAssign > & getPendingLocs()
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool is128BitVector() const
Return true if this is a 128-bit vector type.
static const MCPhysReg SRegList[]
bool is64BitVector() const
Return true if this is a 64-bit vector type.
static const MCPhysReg HRegList[]
static bool CC_AArch64_Custom_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Given an [N x Ty] block, it should be passed in a consecutive sequence of registers.
void DeallocateReg(MCPhysReg Reg)
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
bool isTargetMachO() const
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Align max(MaybeAlign Lhs, Align Rhs)
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void setInConsecutiveRegsLast(bool Flag=true)
bool isAllocated(MCRegister Reg) const
isAllocated - Return true if the specified register (or an alias) is allocated.