LLVM  15.0.0git
LegalizeIntegerTypes.cpp
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1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements integer type expansion and promotion for LegalizeTypes.
10 // Promotion is the act of changing a computation in an illegal type into a
11 // computation in a larger type. For example, implementing i8 arithmetic in an
12 // i32 register (often needed on powerpc).
13 // Expansion is the act of changing a computation in an illegal type into a
14 // computation in two identical registers of a smaller type. For example,
15 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16 // targets).
17 //
18 //===----------------------------------------------------------------------===//
19 
20 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/Support/KnownBits.h"
26 #include <algorithm>
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "legalize-types"
30 
31 //===----------------------------------------------------------------------===//
32 // Integer Result Promotion
33 //===----------------------------------------------------------------------===//
34 
35 /// PromoteIntegerResult - This method is called when a result of a node is
36 /// found to be in need of promotion to a larger type. At this point, the node
37 /// may also have invalid operands or may have other results that need
38 /// expansion, we just know that (at least) one result needs promotion.
39 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
40  LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG);
41  dbgs() << "\n");
42  SDValue Res = SDValue();
43 
44  // See if the target wants to custom expand this node.
45  if (CustomLowerNode(N, N->getValueType(ResNo), true)) {
46  LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n");
47  return;
48  }
49 
50  switch (N->getOpcode()) {
51  default:
52 #ifndef NDEBUG
53  dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
54  N->dump(&DAG); dbgs() << "\n";
55 #endif
56  llvm_unreachable("Do not know how to promote this operator!");
57  case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
58  case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
59  case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
60  case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
61  case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
62  case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
63  case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
64  case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
66  case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
67  case ISD::PARITY:
68  case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break;
70  case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
72  Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
73  case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
74  case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
75  break;
76  case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
77  break;
78  case ISD::SELECT:
79  case ISD::VSELECT:
80  case ISD::VP_SELECT:
81  case ISD::VP_MERGE:
82  Res = PromoteIntRes_Select(N);
83  break;
84  case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
85  case ISD::STRICT_FSETCC:
87  case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
88  case ISD::SMIN:
89  case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
90  case ISD::UMIN:
91  case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break;
92 
93  case ISD::SHL:
94  case ISD::VP_SHL: Res = PromoteIntRes_SHL(N); break;
96  Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
97  case ISD::SRA:
98  case ISD::VP_ASHR: Res = PromoteIntRes_SRA(N); break;
99  case ISD::SRL:
100  case ISD::VP_LSHR: Res = PromoteIntRes_SRL(N); break;
101  case ISD::VP_TRUNCATE:
102  case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
103  case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
104  case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
105  case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
106 
108  Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
110  Res = PromoteIntRes_INSERT_SUBVECTOR(N); break;
111  case ISD::VECTOR_REVERSE:
112  Res = PromoteIntRes_VECTOR_REVERSE(N); break;
113  case ISD::VECTOR_SHUFFLE:
114  Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
115  case ISD::VECTOR_SPLICE:
116  Res = PromoteIntRes_VECTOR_SPLICE(N); break;
118  Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
119  case ISD::BUILD_VECTOR:
120  Res = PromoteIntRes_BUILD_VECTOR(N); break;
122  Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
123  case ISD::SPLAT_VECTOR:
124  Res = PromoteIntRes_SPLAT_VECTOR(N); break;
125  case ISD::STEP_VECTOR: Res = PromoteIntRes_STEP_VECTOR(N); break;
126  case ISD::CONCAT_VECTORS:
127  Res = PromoteIntRes_CONCAT_VECTORS(N); break;
128 
132  Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
133 
134  case ISD::SIGN_EXTEND:
135  case ISD::ZERO_EXTEND:
136  case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
137 
140  case ISD::FP_TO_SINT:
141  case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
142 
143  case ISD::FP_TO_SINT_SAT:
144  case ISD::FP_TO_UINT_SAT:
145  Res = PromoteIntRes_FP_TO_XINT_SAT(N); break;
146 
147  case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
148 
149  case ISD::FLT_ROUNDS_: Res = PromoteIntRes_FLT_ROUNDS(N); break;
150 
151  case ISD::AND:
152  case ISD::OR:
153  case ISD::XOR:
154  case ISD::ADD:
155  case ISD::SUB:
156  case ISD::MUL:
157  case ISD::VP_AND:
158  case ISD::VP_OR:
159  case ISD::VP_XOR:
160  case ISD::VP_ADD:
161  case ISD::VP_SUB:
162  case ISD::VP_MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
163 
164  case ISD::SDIV:
165  case ISD::SREM:
166  case ISD::VP_SDIV:
167  case ISD::VP_SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
168 
169  case ISD::UDIV:
170  case ISD::UREM:
171  case ISD::VP_UDIV:
172  case ISD::VP_UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
173 
174  case ISD::SADDO:
175  case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
176  case ISD::UADDO:
177  case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
178  case ISD::SMULO:
179  case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
180 
181  case ISD::ADDE:
182  case ISD::SUBE:
183  case ISD::ADDCARRY:
184  case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
185 
186  case ISD::SADDO_CARRY:
187  case ISD::SSUBO_CARRY: Res = PromoteIntRes_SADDSUBO_CARRY(N, ResNo); break;
188 
189  case ISD::SADDSAT:
190  case ISD::UADDSAT:
191  case ISD::SSUBSAT:
192  case ISD::USUBSAT:
193  case ISD::SSHLSAT:
194  case ISD::USHLSAT: Res = PromoteIntRes_ADDSUBSHLSAT(N); break;
195 
196  case ISD::SMULFIX:
197  case ISD::SMULFIXSAT:
198  case ISD::UMULFIX:
199  case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
200 
201  case ISD::SDIVFIX:
202  case ISD::SDIVFIXSAT:
203  case ISD::UDIVFIX:
204  case ISD::UDIVFIXSAT: Res = PromoteIntRes_DIVFIX(N); break;
205 
206  case ISD::ABS: Res = PromoteIntRes_ABS(N); break;
207 
208  case ISD::ATOMIC_LOAD:
209  Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
210 
215  case ISD::ATOMIC_LOAD_OR:
222  case ISD::ATOMIC_SWAP:
223  Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
224 
227  Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
228  break;
229 
230  case ISD::VECREDUCE_ADD:
231  case ISD::VECREDUCE_MUL:
232  case ISD::VECREDUCE_AND:
233  case ISD::VECREDUCE_OR:
234  case ISD::VECREDUCE_XOR:
235  case ISD::VECREDUCE_SMAX:
236  case ISD::VECREDUCE_SMIN:
237  case ISD::VECREDUCE_UMAX:
238  case ISD::VECREDUCE_UMIN:
239  Res = PromoteIntRes_VECREDUCE(N);
240  break;
241 
242  case ISD::VP_REDUCE_ADD:
243  case ISD::VP_REDUCE_MUL:
244  case ISD::VP_REDUCE_AND:
245  case ISD::VP_REDUCE_OR:
246  case ISD::VP_REDUCE_XOR:
247  case ISD::VP_REDUCE_SMAX:
248  case ISD::VP_REDUCE_SMIN:
249  case ISD::VP_REDUCE_UMAX:
250  case ISD::VP_REDUCE_UMIN:
251  Res = PromoteIntRes_VP_REDUCE(N);
252  break;
253 
254  case ISD::FREEZE:
255  Res = PromoteIntRes_FREEZE(N);
256  break;
257 
258  case ISD::ROTL:
259  case ISD::ROTR:
260  Res = PromoteIntRes_Rotate(N);
261  break;
262 
263  case ISD::FSHL:
264  case ISD::FSHR:
265  Res = PromoteIntRes_FunnelShift(N);
266  break;
267 
268  case ISD::IS_FPCLASS:
269  Res = PromoteIntRes_IS_FPCLASS(N);
270  break;
271  }
272 
273  // If the result is null then the sub-method took care of registering it.
274  if (Res.getNode())
275  SetPromotedInteger(SDValue(N, ResNo), Res);
276 }
277 
278 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
279  unsigned ResNo) {
280  SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
281  return GetPromotedInteger(Op);
282 }
283 
284 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
285  // Sign-extend the new bits, and continue the assertion.
286  SDValue Op = SExtPromotedInteger(N->getOperand(0));
287  return DAG.getNode(ISD::AssertSext, SDLoc(N),
288  Op.getValueType(), Op, N->getOperand(1));
289 }
290 
291 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
292  // Zero the new bits, and continue the assertion.
293  SDValue Op = ZExtPromotedInteger(N->getOperand(0));
294  return DAG.getNode(ISD::AssertZext, SDLoc(N),
295  Op.getValueType(), Op, N->getOperand(1));
296 }
297 
298 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
299  EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
300  SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
301  N->getMemoryVT(), ResVT,
302  N->getChain(), N->getBasePtr(),
303  N->getMemOperand());
304  // Legalize the chain result - switch anything that used the old chain to
305  // use the new one.
306  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
307  return Res;
308 }
309 
310 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
311  SDValue Op2 = GetPromotedInteger(N->getOperand(2));
312  SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
313  N->getMemoryVT(),
314  N->getChain(), N->getBasePtr(),
315  Op2, N->getMemOperand());
316  // Legalize the chain result - switch anything that used the old chain to
317  // use the new one.
318  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
319  return Res;
320 }
321 
322 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
323  unsigned ResNo) {
324  if (ResNo == 1) {
325  assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
326  EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
327  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
328 
329  // Only use the result of getSetCCResultType if it is legal,
330  // otherwise just use the promoted result type (NVT).
331  if (!TLI.isTypeLegal(SVT))
332  SVT = NVT;
333 
334  SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
335  SDValue Res = DAG.getAtomicCmpSwap(
336  ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
337  N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
338  N->getMemOperand());
339  ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
340  ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
341  return Res.getValue(1);
342  }
343 
344  // Op2 is used for the comparison and thus must be extended according to the
345  // target's atomic operations. Op3 is merely stored and so can be left alone.
346  SDValue Op2 = N->getOperand(2);
347  SDValue Op3 = GetPromotedInteger(N->getOperand(3));
348  switch (TLI.getExtendForAtomicCmpSwapArg()) {
349  case ISD::SIGN_EXTEND:
350  Op2 = SExtPromotedInteger(Op2);
351  break;
352  case ISD::ZERO_EXTEND:
353  Op2 = ZExtPromotedInteger(Op2);
354  break;
355  case ISD::ANY_EXTEND:
356  Op2 = GetPromotedInteger(Op2);
357  break;
358  default:
359  llvm_unreachable("Invalid atomic op extension");
360  }
361 
362  SDVTList VTs =
363  DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
364  SDValue Res = DAG.getAtomicCmpSwap(
365  N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
366  N->getBasePtr(), Op2, Op3, N->getMemOperand());
367  // Update the use to N with the newly created Res.
368  for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
369  ReplaceValueWith(SDValue(N, i), Res.getValue(i));
370  return Res;
371 }
372 
373 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
374  SDValue InOp = N->getOperand(0);
375  EVT InVT = InOp.getValueType();
376  EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
377  EVT OutVT = N->getValueType(0);
378  EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
379  SDLoc dl(N);
380 
381  switch (getTypeAction(InVT)) {
383  break;
385  if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
386  // The input promotes to the same size. Convert the promoted value.
387  return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
388  break;
390  // Promote the integer operand by hand.
391  return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
393  // Promote the integer operand by hand.
394  return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftPromotedHalf(InOp));
396  // Convert the promoted float by hand.
397  if (!NOutVT.isVector())
398  return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp));
399  break;
400  }
403  break;
405  // Convert the element to an integer and promote it by hand.
406  if (!NOutVT.isVector())
407  return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
408  BitConvertToInteger(GetScalarizedVector(InOp)));
409  break;
411  report_fatal_error("Scalarization of scalable vectors is not supported.");
413  if (!NOutVT.isVector()) {
414  // For example, i32 = BITCAST v2i16 on alpha. Convert the split
415  // pieces of the input into integers and reassemble in the final type.
416  SDValue Lo, Hi;
417  GetSplitVector(N->getOperand(0), Lo, Hi);
418  Lo = BitConvertToInteger(Lo);
419  Hi = BitConvertToInteger(Hi);
420 
421  if (DAG.getDataLayout().isBigEndian())
422  std::swap(Lo, Hi);
423 
424  InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
426  NOutVT.getSizeInBits()),
427  JoinIntegers(Lo, Hi));
428  return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
429  }
430  break;
431  }
433  // The input is widened to the same size. Convert to the widened value.
434  // Make sure that the outgoing value is not a vector, because this would
435  // make us bitcast between two vectors which are legalized in different ways.
436  if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector()) {
437  SDValue Res =
438  DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
439 
440  // For big endian targets we need to shift the casted value or the
441  // interesting bits will end up at the wrong place.
442  if (DAG.getDataLayout().isBigEndian()) {
443  unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
444  assert(ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!");
445  Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res,
446  DAG.getShiftAmountConstant(ShiftAmt, NOutVT, dl));
447  }
448  return Res;
449  }
450  // If the output type is also a vector and widening it to the same size
451  // as the widened input type would be a legal type, we can widen the bitcast
452  // and handle the promotion after.
453  if (NOutVT.isVector()) {
454  unsigned WidenInSize = NInVT.getSizeInBits();
455  unsigned OutSize = OutVT.getSizeInBits();
456  if (WidenInSize % OutSize == 0) {
457  unsigned Scale = WidenInSize / OutSize;
458  EVT WideOutVT = EVT::getVectorVT(*DAG.getContext(),
459  OutVT.getVectorElementType(),
460  OutVT.getVectorNumElements() * Scale);
461  if (isTypeLegal(WideOutVT)) {
462  InOp = DAG.getBitcast(WideOutVT, GetWidenedVector(InOp));
463  InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp,
464  DAG.getVectorIdxConstant(0, dl));
465  return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp);
466  }
467  }
468  }
469  }
470 
471  return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
472  CreateStackStoreLoad(InOp, OutVT));
473 }
474 
475 SDValue DAGTypeLegalizer::PromoteIntRes_FREEZE(SDNode *N) {
476  SDValue V = GetPromotedInteger(N->getOperand(0));
477  return DAG.getNode(ISD::FREEZE, SDLoc(N),
478  V.getValueType(), V);
479 }
480 
481 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
482  SDValue Op = GetPromotedInteger(N->getOperand(0));
483  EVT OVT = N->getValueType(0);
484  EVT NVT = Op.getValueType();
485  SDLoc dl(N);
486 
487  // If the larger BSWAP isn't supported by the target, try to expand now.
488  // If we expand later we'll end up with more operations since we lost the
489  // original type. We only do this for scalars since we have a shuffle
490  // based lowering for vectors in LegalizeVectorOps.
491  if (!OVT.isVector() &&
493  if (SDValue Res = TLI.expandBSWAP(N, DAG))
494  return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res);
495  }
496 
497  unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
498  return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
499  DAG.getShiftAmountConstant(DiffBits, NVT, dl));
500 }
501 
502 SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
503  SDValue Op = GetPromotedInteger(N->getOperand(0));
504  EVT OVT = N->getValueType(0);
505  EVT NVT = Op.getValueType();
506  SDLoc dl(N);
507 
508  // If the larger BITREVERSE isn't supported by the target, try to expand now.
509  // If we expand later we'll end up with more operations since we lost the
510  // original type. We only do this for scalars since we have a shuffle
511  // based lowering for vectors in LegalizeVectorOps.
512  if (!OVT.isVector() && OVT.isSimple() &&
514  if (SDValue Res = TLI.expandBITREVERSE(N, DAG))
515  return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res);
516  }
517 
518  unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
519  return DAG.getNode(ISD::SRL, dl, NVT,
520  DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
521  DAG.getShiftAmountConstant(DiffBits, NVT, dl));
522 }
523 
524 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
525  // The pair element type may be legal, or may not promote to the same type as
526  // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
527  return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
528  TLI.getTypeToTransformTo(*DAG.getContext(),
529  N->getValueType(0)), JoinIntegers(N->getOperand(0),
530  N->getOperand(1)));
531 }
532 
533 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
534  EVT VT = N->getValueType(0);
535  // FIXME there is no actual debug info here
536  SDLoc dl(N);
537  // Zero extend things like i1, sign extend everything else. It shouldn't
538  // matter in theory which one we pick, but this tends to give better code?
539  unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
540  SDValue Result = DAG.getNode(Opc, dl,
541  TLI.getTypeToTransformTo(*DAG.getContext(), VT),
542  SDValue(N, 0));
543  assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
544  return Result;
545 }
546 
547 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
548  EVT OVT = N->getValueType(0);
549  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
550  SDLoc dl(N);
551 
552  // If the larger CTLZ isn't supported by the target, try to expand now.
553  // If we expand later we'll end up with more operations since we lost the
554  // original type.
555  if (!OVT.isVector() && TLI.isTypeLegal(NVT) &&
558  if (SDValue Result = TLI.expandCTLZ(N, DAG)) {
559  Result = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Result);
560  return Result;
561  }
562  }
563 
564  // Zero extend to the promoted type and do the count there.
565  SDValue Op = ZExtPromotedInteger(N->getOperand(0));
566  Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
567  // Subtract off the extra leading bits in the bigger type.
568  return DAG.getNode(
569  ISD::SUB, dl, NVT, Op,
571  NVT));
572 }
573 
574 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
575  EVT OVT = N->getValueType(0);
576  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
577 
578  // If the larger CTPOP isn't supported by the target, try to expand now.
579  // If we expand later we'll end up with more operations since we lost the
580  // original type.
581  // TODO: Expand ISD::PARITY. Need to move ExpandPARITY from LegalizeDAG to
582  // TargetLowering.
583  if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() && TLI.isTypeLegal(NVT) &&
585  if (SDValue Result = TLI.expandCTPOP(N, DAG)) {
586  Result = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), NVT, Result);
587  return Result;
588  }
589  }
590 
591  // Zero extend to the promoted type and do the count or parity there.
592  SDValue Op = ZExtPromotedInteger(N->getOperand(0));
593  return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op);
594 }
595 
596 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
597  SDValue Op = GetPromotedInteger(N->getOperand(0));
598  EVT OVT = N->getValueType(0);
599  EVT NVT = Op.getValueType();
600  SDLoc dl(N);
601 
602  // If the larger CTTZ isn't supported by the target, try to expand now.
603  // If we expand later we'll end up with more operations since we lost the
604  // original type. Don't expand if we can use CTPOP or CTLZ expansion on the
605  // larger type.
606  if (!OVT.isVector() && TLI.isTypeLegal(NVT) &&
609  !TLI.isOperationLegal(ISD::CTPOP, NVT) &&
610  !TLI.isOperationLegal(ISD::CTLZ, NVT)) {
611  if (SDValue Result = TLI.expandCTTZ(N, DAG)) {
612  Result = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Result);
613  return Result;
614  }
615  }
616 
617  if (N->getOpcode() == ISD::CTTZ) {
618  // The count is the same in the promoted type except if the original
619  // value was zero. This can be handled by setting the bit just off
620  // the top of the original type.
621  auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
622  OVT.getScalarSizeInBits());
623  Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
624  }
625  return DAG.getNode(N->getOpcode(), dl, NVT, Op);
626 }
627 
628 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
629  SDLoc dl(N);
630  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
631 
632  SDValue Op0 = N->getOperand(0);
633  SDValue Op1 = N->getOperand(1);
634 
635  // If the input also needs to be promoted, do that first so we can get a
636  // get a good idea for the output type.
637  if (TLI.getTypeAction(*DAG.getContext(), Op0.getValueType())
639  SDValue In = GetPromotedInteger(Op0);
640 
641  // If the new type is larger than NVT, use it. We probably won't need to
642  // promote it again.
643  EVT SVT = In.getValueType().getScalarType();
644  if (SVT.bitsGE(NVT)) {
645  SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1);
646  return DAG.getAnyExtOrTrunc(Ext, dl, NVT);
647  }
648  }
649 
650  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1);
651 }
652 
653 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
654  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
655  unsigned NewOpc = N->getOpcode();
656  SDLoc dl(N);
657 
658  // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
659  // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
660  // and SINT conversions are Custom, there is no way to tell which is
661  // preferable. We choose SINT because that's the right thing on PPC.)
662  if (N->getOpcode() == ISD::FP_TO_UINT &&
663  !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
665  NewOpc = ISD::FP_TO_SINT;
666 
667  if (N->getOpcode() == ISD::STRICT_FP_TO_UINT &&
670  NewOpc = ISD::STRICT_FP_TO_SINT;
671 
672  SDValue Res;
673  if (N->isStrictFPOpcode()) {
674  Res = DAG.getNode(NewOpc, dl, {NVT, MVT::Other},
675  {N->getOperand(0), N->getOperand(1)});
676  // Legalize the chain result - switch anything that used the old chain to
677  // use the new one.
678  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
679  } else
680  Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
681 
682  // Assert that the converted value fits in the original type. If it doesn't
683  // (eg: because the value being converted is too big), then the result of the
684  // original operation was undefined anyway, so the assert is still correct.
685  //
686  // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
687  // before legalization: fp-to-uint16, 65534. -> 0xfffe
688  // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
689  return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT ||
690  N->getOpcode() == ISD::STRICT_FP_TO_UINT) ?
691  ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
692  DAG.getValueType(N->getValueType(0).getScalarType()));
693 }
694 
695 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT_SAT(SDNode *N) {
696  // Promote the result type, while keeping the original width in Op1.
697  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
698  SDLoc dl(N);
699  return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0),
700  N->getOperand(1));
701 }
702 
703 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
704  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
705  SDLoc dl(N);
706 
707  return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
708 }
709 
710 SDValue DAGTypeLegalizer::PromoteIntRes_FLT_ROUNDS(SDNode *N) {
711  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
712  SDLoc dl(N);
713 
714  SDValue Res =
715  DAG.getNode(N->getOpcode(), dl, {NVT, MVT::Other}, N->getOperand(0));
716 
717  // Legalize the chain result - switch anything that used the old chain to
718  // use the new one.
719  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
720  return Res;
721 }
722 
723 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
724  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
725  SDLoc dl(N);
726 
727  if (getTypeAction(N->getOperand(0).getValueType())
729  SDValue Res = GetPromotedInteger(N->getOperand(0));
730  assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
731 
732  // If the result and operand types are the same after promotion, simplify
733  // to an in-register extension.
734  if (NVT == Res.getValueType()) {
735  // The high bits are not guaranteed to be anything. Insert an extend.
736  if (N->getOpcode() == ISD::SIGN_EXTEND)
737  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
738  DAG.getValueType(N->getOperand(0).getValueType()));
739  if (N->getOpcode() == ISD::ZERO_EXTEND)
740  return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
741  assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
742  return Res;
743  }
744  }
745 
746  // Otherwise, just extend the original operand all the way to the larger type.
747  return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
748 }
749 
750 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
751  assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
752  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
753  ISD::LoadExtType ExtType =
754  ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
755  SDLoc dl(N);
756  SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
757  N->getMemoryVT(), N->getMemOperand());
758 
759  // Legalize the chain result - switch anything that used the old chain to
760  // use the new one.
761  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
762  return Res;
763 }
764 
765 SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
766  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
767  SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
768 
769  ISD::LoadExtType ExtType = N->getExtensionType();
770  if (ExtType == ISD::NON_EXTLOAD)
771  ExtType = ISD::EXTLOAD;
772 
773  SDLoc dl(N);
774  SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
775  N->getOffset(), N->getMask(), ExtPassThru,
776  N->getMemoryVT(), N->getMemOperand(),
777  N->getAddressingMode(), ExtType,
778  N->isExpandingLoad());
779  // Legalize the chain result - switch anything that used the old chain to
780  // use the new one.
781  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
782  return Res;
783 }
784 
785 SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
786  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
787  SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
788  assert(NVT == ExtPassThru.getValueType() &&
789  "Gather result type and the passThru argument type should be the same");
790 
791  ISD::LoadExtType ExtType = N->getExtensionType();
792  if (ExtType == ISD::NON_EXTLOAD)
793  ExtType = ISD::EXTLOAD;
794 
795  SDLoc dl(N);
796  SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
797  N->getIndex(), N->getScale() };
798  SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other),
799  N->getMemoryVT(), dl, Ops,
800  N->getMemOperand(), N->getIndexType(),
801  ExtType);
802  // Legalize the chain result - switch anything that used the old chain to
803  // use the new one.
804  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
805  return Res;
806 }
807 
808 /// Promote the overflow flag of an overflowing arithmetic node.
809 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
810  // Change the return type of the boolean result while obeying
811  // getSetCCResultType.
812  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
813  EVT VT = N->getValueType(0);
814  EVT SVT = getSetCCResultType(VT);
815  SDValue Ops[3] = { N->getOperand(0), N->getOperand(1) };
816  unsigned NumOps = N->getNumOperands();
817  assert(NumOps <= 3 && "Too many operands");
818  if (NumOps == 3)
819  Ops[2] = N->getOperand(2);
820 
821  SDLoc dl(N);
822  SDValue Res = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(VT, SVT),
823  makeArrayRef(Ops, NumOps));
824 
825  // Modified the sum result - switch anything that used the old sum to use
826  // the new one.
827  ReplaceValueWith(SDValue(N, 0), Res);
828 
829  // Convert to the expected type.
830  return DAG.getBoolExtOrTrunc(Res.getValue(1), dl, NVT, VT);
831 }
832 
833 SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
834  // If the promoted type is legal, we can convert this to:
835  // 1. ANY_EXTEND iN to iM
836  // 2. SHL by M-N
837  // 3. [US][ADD|SUB|SHL]SAT
838  // 4. L/ASHR by M-N
839  // Else it is more efficient to convert this to a min and a max
840  // operation in the higher precision arithmetic.
841  SDLoc dl(N);
842  SDValue Op1 = N->getOperand(0);
843  SDValue Op2 = N->getOperand(1);
844  unsigned OldBits = Op1.getScalarValueSizeInBits();
845 
846  unsigned Opcode = N->getOpcode();
847  bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
848 
849  SDValue Op1Promoted, Op2Promoted;
850  if (IsShift) {
851  Op1Promoted = GetPromotedInteger(Op1);
852  Op2Promoted = ZExtPromotedInteger(Op2);
853  } else if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) {
854  Op1Promoted = ZExtPromotedInteger(Op1);
855  Op2Promoted = ZExtPromotedInteger(Op2);
856  } else {
857  Op1Promoted = SExtPromotedInteger(Op1);
858  Op2Promoted = SExtPromotedInteger(Op2);
859  }
860  EVT PromotedType = Op1Promoted.getValueType();
861  unsigned NewBits = PromotedType.getScalarSizeInBits();
862 
863  if (Opcode == ISD::UADDSAT) {
864  APInt MaxVal = APInt::getAllOnes(OldBits).zext(NewBits);
865  SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
866  SDValue Add =
867  DAG.getNode(ISD::ADD, dl, PromotedType, Op1Promoted, Op2Promoted);
868  return DAG.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax);
869  }
870 
871  // USUBSAT can always be promoted as long as we have zero-extended the args.
872  if (Opcode == ISD::USUBSAT)
873  return DAG.getNode(ISD::USUBSAT, dl, PromotedType, Op1Promoted,
874  Op2Promoted);
875 
876  // Shift cannot use a min/max expansion, we can't detect overflow if all of
877  // the bits have been shifted out.
878  if (IsShift || TLI.isOperationLegal(Opcode, PromotedType)) {
879  unsigned ShiftOp;
880  switch (Opcode) {
881  case ISD::SADDSAT:
882  case ISD::SSUBSAT:
883  case ISD::SSHLSAT:
884  ShiftOp = ISD::SRA;
885  break;
886  case ISD::USHLSAT:
887  ShiftOp = ISD::SRL;
888  break;
889  default:
890  llvm_unreachable("Expected opcode to be signed or unsigned saturation "
891  "addition, subtraction or left shift");
892  }
893 
894  unsigned SHLAmount = NewBits - OldBits;
895  SDValue ShiftAmount =
896  DAG.getShiftAmountConstant(SHLAmount, PromotedType, dl);
897  Op1Promoted =
898  DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
899  if (!IsShift)
900  Op2Promoted =
901  DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
902 
903  SDValue Result =
904  DAG.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted);
905  return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
906  }
907 
908  unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
909  APInt MinVal = APInt::getSignedMinValue(OldBits).sext(NewBits);
910  APInt MaxVal = APInt::getSignedMaxValue(OldBits).sext(NewBits);
911  SDValue SatMin = DAG.getConstant(MinVal, dl, PromotedType);
912  SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
913  SDValue Result =
914  DAG.getNode(AddOp, dl, PromotedType, Op1Promoted, Op2Promoted);
915  Result = DAG.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
916  Result = DAG.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
917  return Result;
918 }
919 
920 SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
921  // Can just promote the operands then continue with operation.
922  SDLoc dl(N);
923  SDValue Op1Promoted, Op2Promoted;
924  bool Signed =
925  N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
926  bool Saturating =
927  N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
928  if (Signed) {
929  Op1Promoted = SExtPromotedInteger(N->getOperand(0));
930  Op2Promoted = SExtPromotedInteger(N->getOperand(1));
931  } else {
932  Op1Promoted = ZExtPromotedInteger(N->getOperand(0));
933  Op2Promoted = ZExtPromotedInteger(N->getOperand(1));
934  }
935  EVT OldType = N->getOperand(0).getValueType();
936  EVT PromotedType = Op1Promoted.getValueType();
937  unsigned DiffSize =
938  PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
939 
940  if (Saturating) {
941  // Promoting the operand and result values changes the saturation width,
942  // which is extends the values that we clamp to on saturation. This could be
943  // resolved by shifting one of the operands the same amount, which would
944  // also shift the result we compare against, then shifting back.
945  Op1Promoted =
946  DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
947  DAG.getShiftAmountConstant(DiffSize, PromotedType, dl));
948  SDValue Result = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
949  Op2Promoted, N->getOperand(2));
950  unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
951  return DAG.getNode(ShiftOp, dl, PromotedType, Result,
952  DAG.getShiftAmountConstant(DiffSize, PromotedType, dl));
953  }
954  return DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted, Op2Promoted,
955  N->getOperand(2));
956 }
957 
959  unsigned SatW, bool Signed,
960  const TargetLowering &TLI,
961  SelectionDAG &DAG) {
962  EVT VT = V.getValueType();
963  unsigned VTW = VT.getScalarSizeInBits();
964 
965  if (!Signed) {
966  // Saturate to the unsigned maximum by getting the minimum of V and the
967  // maximum.
968  return DAG.getNode(ISD::UMIN, dl, VT, V,
969  DAG.getConstant(APInt::getLowBitsSet(VTW, SatW),
970  dl, VT));
971  }
972 
973  // Saturate to the signed maximum (the low SatW - 1 bits) by taking the
974  // signed minimum of it and V.
975  V = DAG.getNode(ISD::SMIN, dl, VT, V,
976  DAG.getConstant(APInt::getLowBitsSet(VTW, SatW - 1),
977  dl, VT));
978  // Saturate to the signed minimum (the high SatW + 1 bits) by taking the
979  // signed maximum of it and V.
980  V = DAG.getNode(ISD::SMAX, dl, VT, V,
981  DAG.getConstant(APInt::getHighBitsSet(VTW, VTW - SatW + 1),
982  dl, VT));
983  return V;
984 }
985 
987  unsigned Scale, const TargetLowering &TLI,
988  SelectionDAG &DAG, unsigned SatW = 0) {
989  EVT VT = LHS.getValueType();
990  unsigned VTSize = VT.getScalarSizeInBits();
991  bool Signed = N->getOpcode() == ISD::SDIVFIX ||
992  N->getOpcode() == ISD::SDIVFIXSAT;
993  bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
994  N->getOpcode() == ISD::UDIVFIXSAT;
995 
996  SDLoc dl(N);
997  // Widen the types by a factor of two. This is guaranteed to expand, since it
998  // will always have enough high bits in the LHS to shift into.
999  EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VTSize * 2);
1000  if (VT.isVector())
1001  WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
1002  VT.getVectorElementCount());
1003  if (Signed) {
1004  LHS = DAG.getSExtOrTrunc(LHS, dl, WideVT);
1005  RHS = DAG.getSExtOrTrunc(RHS, dl, WideVT);
1006  } else {
1007  LHS = DAG.getZExtOrTrunc(LHS, dl, WideVT);
1008  RHS = DAG.getZExtOrTrunc(RHS, dl, WideVT);
1009  }
1010 
1011  SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, LHS, RHS, Scale,
1012  DAG);
1013  assert(Res && "Expanding DIVFIX with wide type failed?");
1014  if (Saturating) {
1015  // If the caller has told us to saturate at something less, use that width
1016  // instead of the type before doubling. However, it cannot be more than
1017  // what we just widened!
1018  assert(SatW <= VTSize &&
1019  "Tried to saturate to more than the original type?");
1020  Res = SaturateWidenedDIVFIX(Res, dl, SatW == 0 ? VTSize : SatW, Signed,
1021  TLI, DAG);
1022  }
1023  return DAG.getZExtOrTrunc(Res, dl, VT);
1024 }
1025 
1026 SDValue DAGTypeLegalizer::PromoteIntRes_DIVFIX(SDNode *N) {
1027  SDLoc dl(N);
1028  SDValue Op1Promoted, Op2Promoted;
1029  bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1030  N->getOpcode() == ISD::SDIVFIXSAT;
1031  bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1032  N->getOpcode() == ISD::UDIVFIXSAT;
1033  if (Signed) {
1034  Op1Promoted = SExtPromotedInteger(N->getOperand(0));
1035  Op2Promoted = SExtPromotedInteger(N->getOperand(1));
1036  } else {
1037  Op1Promoted = ZExtPromotedInteger(N->getOperand(0));
1038  Op2Promoted = ZExtPromotedInteger(N->getOperand(1));
1039  }
1040  EVT PromotedType = Op1Promoted.getValueType();
1041  unsigned Scale = N->getConstantOperandVal(2);
1042 
1043  // If the type is already legal and the operation is legal in that type, we
1044  // should not early expand.
1045  if (TLI.isTypeLegal(PromotedType)) {
1047  TLI.getFixedPointOperationAction(N->getOpcode(), PromotedType, Scale);
1048  if (Action == TargetLowering::Legal || Action == TargetLowering::Custom) {
1049  unsigned Diff = PromotedType.getScalarSizeInBits() -
1050  N->getValueType(0).getScalarSizeInBits();
1051  if (Saturating)
1052  Op1Promoted =
1053  DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
1054  DAG.getShiftAmountConstant(Diff, PromotedType, dl));
1055  SDValue Res = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
1056  Op2Promoted, N->getOperand(2));
1057  if (Saturating)
1058  Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res,
1059  DAG.getShiftAmountConstant(Diff, PromotedType, dl));
1060  return Res;
1061  }
1062  }
1063 
1064  // See if we can perform the division in this type without expanding.
1065  if (SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, Op1Promoted,
1066  Op2Promoted, Scale, DAG)) {
1067  if (Saturating)
1068  Res = SaturateWidenedDIVFIX(Res, dl,
1069  N->getValueType(0).getScalarSizeInBits(),
1070  Signed, TLI, DAG);
1071  return Res;
1072  }
1073  // If we cannot, expand it to twice the type width. If we are saturating, give
1074  // it the original width as a saturating width so we don't need to emit
1075  // two saturations.
1076  return earlyExpandDIVFIX(N, Op1Promoted, Op2Promoted, Scale, TLI, DAG,
1077  N->getValueType(0).getScalarSizeInBits());
1078 }
1079 
1080 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
1081  if (ResNo == 1)
1082  return PromoteIntRes_Overflow(N);
1083 
1084  // The operation overflowed iff the result in the larger type is not the
1085  // sign extension of its truncation to the original type.
1086  SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1087  SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1088  EVT OVT = N->getOperand(0).getValueType();
1089  EVT NVT = LHS.getValueType();
1090  SDLoc dl(N);
1091 
1092  // Do the arithmetic in the larger type.
1093  unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
1094  SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
1095 
1096  // Calculate the overflow flag: sign extend the arithmetic result from
1097  // the original type.
1098  SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
1099  DAG.getValueType(OVT));
1100  // Overflowed if and only if this is not equal to Res.
1101  Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
1102 
1103  // Use the calculated overflow everywhere.
1104  ReplaceValueWith(SDValue(N, 1), Ofl);
1105 
1106  return Res;
1107 }
1108 
1109 SDValue DAGTypeLegalizer::PromoteIntRes_Select(SDNode *N) {
1110  SDValue Mask = N->getOperand(0);
1111 
1112  SDValue LHS = GetPromotedInteger(N->getOperand(1));
1113  SDValue RHS = GetPromotedInteger(N->getOperand(2));
1114 
1115  unsigned Opcode = N->getOpcode();
1116  if (Opcode == ISD::VP_SELECT || Opcode == ISD::VP_MERGE)
1117  return DAG.getNode(Opcode, SDLoc(N), LHS.getValueType(), Mask, LHS, RHS,
1118  N->getOperand(3));
1119  return DAG.getNode(Opcode, SDLoc(N), LHS.getValueType(), Mask, LHS, RHS);
1120 }
1121 
1122 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
1123  SDValue LHS = GetPromotedInteger(N->getOperand(2));
1124  SDValue RHS = GetPromotedInteger(N->getOperand(3));
1125  return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
1126  LHS.getValueType(), N->getOperand(0),
1127  N->getOperand(1), LHS, RHS, N->getOperand(4));
1128 }
1129 
1130 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
1131  unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
1132  EVT InVT = N->getOperand(OpNo).getValueType();
1133  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1134 
1135  EVT SVT = getSetCCResultType(InVT);
1136 
1137  // If we got back a type that needs to be promoted, this likely means the
1138  // the input type also needs to be promoted. So get the promoted type for
1139  // the input and try the query again.
1140  if (getTypeAction(SVT) == TargetLowering::TypePromoteInteger) {
1141  if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) {
1142  InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
1143  SVT = getSetCCResultType(InVT);
1144  } else {
1145  // Input type isn't promoted, just use the default promoted type.
1146  SVT = NVT;
1147  }
1148  }
1149 
1150  SDLoc dl(N);
1151  assert(SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() &&
1152  "Vector compare must return a vector result!");
1153 
1154  // Get the SETCC result using the canonical SETCC type.
1155  SDValue SetCC;
1156  if (N->isStrictFPOpcode()) {
1157  EVT VTs[] = {SVT, MVT::Other};
1158  SDValue Opers[] = {N->getOperand(0), N->getOperand(1),
1159  N->getOperand(2), N->getOperand(3)};
1160  SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers);
1161  // Legalize the chain result - switch anything that used the old chain to
1162  // use the new one.
1163  ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1));
1164  } else
1165  SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
1166  N->getOperand(1), N->getOperand(2));
1167 
1168  // Convert to the expected type.
1169  return DAG.getSExtOrTrunc(SetCC, dl, NVT);
1170 }
1171 
1172 SDValue DAGTypeLegalizer::PromoteIntRes_IS_FPCLASS(SDNode *N) {
1173  SDLoc DL(N);
1174  SDValue Arg = N->getOperand(0);
1175  SDValue Test = N->getOperand(1);
1176  EVT NResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1177  return DAG.getNode(ISD::IS_FPCLASS, DL, NResVT, Arg, Test);
1178 }
1179 
1180 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
1181  SDValue LHS = GetPromotedInteger(N->getOperand(0));
1182  SDValue RHS = N->getOperand(1);
1183  if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1184  RHS = ZExtPromotedInteger(RHS);
1185  if (N->getOpcode() != ISD::VP_SHL)
1186  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1187  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1188  N->getOperand(2), N->getOperand(3));
1189 }
1190 
1191 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
1192  SDValue Op = GetPromotedInteger(N->getOperand(0));
1193  return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
1194  Op.getValueType(), Op, N->getOperand(1));
1195 }
1196 
1197 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
1198  // The input may have strange things in the top bits of the registers, but
1199  // these operations don't care. They may have weird bits going out, but
1200  // that too is okay if they are integer operations.
1201  SDValue LHS = GetPromotedInteger(N->getOperand(0));
1202  SDValue RHS = GetPromotedInteger(N->getOperand(1));
1203  if (N->getNumOperands() == 2)
1204  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1205  assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1206  assert(N->isVPOpcode() && "Expected VP opcode");
1207  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1208  N->getOperand(2), N->getOperand(3));
1209 }
1210 
1211 SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
1212  // Sign extend the input.
1213  SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1214  SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1215  if (N->getNumOperands() == 2)
1216  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1217  assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1218  assert(N->isVPOpcode() && "Expected VP opcode");
1219  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1220  N->getOperand(2), N->getOperand(3));
1221 }
1222 
1223 SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
1224  // Zero extend the input.
1225  SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1226  SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1227  if (N->getNumOperands() == 2)
1228  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1229  assert(N->getNumOperands() == 4 && "Unexpected number of operands!");
1230  assert(N->isVPOpcode() && "Expected VP opcode");
1231  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1232  N->getOperand(2), N->getOperand(3));
1233 }
1234 
1235 SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
1236  // It doesn't matter if we sign extend or zero extend in the inputs. So do
1237  // whatever is best for the target.
1238  SDValue LHS = SExtOrZExtPromotedInteger(N->getOperand(0));
1239  SDValue RHS = SExtOrZExtPromotedInteger(N->getOperand(1));
1240  return DAG.getNode(N->getOpcode(), SDLoc(N),
1241  LHS.getValueType(), LHS, RHS);
1242 }
1243 
1244 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
1245  // The input value must be properly sign extended.
1246  SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1247  SDValue RHS = N->getOperand(1);
1248  if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1249  RHS = ZExtPromotedInteger(RHS);
1250  if (N->getOpcode() != ISD::VP_ASHR)
1251  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1252  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1253  N->getOperand(2), N->getOperand(3));
1254 }
1255 
1256 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
1257  // The input value must be properly zero extended.
1258  SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1259  SDValue RHS = N->getOperand(1);
1260  if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1261  RHS = ZExtPromotedInteger(RHS);
1262  if (N->getOpcode() != ISD::VP_LSHR)
1263  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1264  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1265  N->getOperand(2), N->getOperand(3));
1266 }
1267 
1268 SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
1269  // Lower the rotate to shifts and ORs which can be promoted.
1270  SDValue Res = TLI.expandROT(N, true /*AllowVectorOps*/, DAG);
1271  ReplaceValueWith(SDValue(N, 0), Res);
1272  return SDValue();
1273 }
1274 
1275 SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
1276  SDValue Hi = GetPromotedInteger(N->getOperand(0));
1277  SDValue Lo = GetPromotedInteger(N->getOperand(1));
1278  SDValue Amt = N->getOperand(2);
1279  if (getTypeAction(Amt.getValueType()) == TargetLowering::TypePromoteInteger)
1280  Amt = ZExtPromotedInteger(Amt);
1281  EVT AmtVT = Amt.getValueType();
1282 
1283  SDLoc DL(N);
1284  EVT OldVT = N->getOperand(0).getValueType();
1285  EVT VT = Lo.getValueType();
1286  unsigned Opcode = N->getOpcode();
1287  bool IsFSHR = Opcode == ISD::FSHR;
1288  unsigned OldBits = OldVT.getScalarSizeInBits();
1289  unsigned NewBits = VT.getScalarSizeInBits();
1290 
1291  // Amount has to be interpreted modulo the old bit width.
1292  Amt = DAG.getNode(ISD::UREM, DL, AmtVT, Amt,
1293  DAG.getConstant(OldBits, DL, AmtVT));
1294 
1295  // If the promoted type is twice the size (or more), then we use the
1296  // traditional funnel 'double' shift codegen. This isn't necessary if the
1297  // shift amount is constant.
1298  // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1299  // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1300  if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Amt) &&
1301  !TLI.isOperationLegalOrCustom(Opcode, VT)) {
1302  SDValue HiShift = DAG.getConstant(OldBits, DL, VT);
1303  Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, HiShift);
1304  Lo = DAG.getZeroExtendInReg(Lo, DL, OldVT);
1305  SDValue Res = DAG.getNode(ISD::OR, DL, VT, Hi, Lo);
1306  Res = DAG.getNode(IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, Res, Amt);
1307  if (!IsFSHR)
1308  Res = DAG.getNode(ISD::SRL, DL, VT, Res, HiShift);
1309  return Res;
1310  }
1311 
1312  // Shift Lo up to occupy the upper bits of the promoted type.
1313  SDValue ShiftOffset = DAG.getConstant(NewBits - OldBits, DL, AmtVT);
1314  Lo = DAG.getNode(ISD::SHL, DL, VT, Lo, ShiftOffset);
1315 
1316  // Increase Amount to shift the result into the lower bits of the promoted
1317  // type.
1318  if (IsFSHR)
1319  Amt = DAG.getNode(ISD::ADD, DL, AmtVT, Amt, ShiftOffset);
1320 
1321  return DAG.getNode(Opcode, DL, VT, Hi, Lo, Amt);
1322 }
1323 
1324 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
1325  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1326  SDValue Res;
1327  SDValue InOp = N->getOperand(0);
1328  SDLoc dl(N);
1329 
1330  switch (getTypeAction(InOp.getValueType())) {
1331  default: llvm_unreachable("Unknown type action!");
1334  Res = InOp;
1335  break;
1337  Res = GetPromotedInteger(InOp);
1338  break;
1340  EVT InVT = InOp.getValueType();
1341  assert(InVT.isVector() && "Cannot split scalar types");
1342  ElementCount NumElts = InVT.getVectorElementCount();
1343  assert(NumElts == NVT.getVectorElementCount() &&
1344  "Dst and Src must have the same number of elements");
1345  assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&
1346  "Promoted vector type must be a power of two");
1347 
1348  SDValue EOp1, EOp2;
1349  GetSplitVector(InOp, EOp1, EOp2);
1350 
1351  EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
1352  NumElts.divideCoefficientBy(2));
1353  if (N->getOpcode() == ISD::TRUNCATE) {
1354  EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
1355  EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
1356  } else {
1357  assert(N->getOpcode() == ISD::VP_TRUNCATE &&
1358  "Expected VP_TRUNCATE opcode");
1359  SDValue MaskLo, MaskHi, EVLLo, EVLHi;
1360  std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1));
1361  std::tie(EVLLo, EVLHi) =
1362  DAG.SplitEVL(N->getOperand(2), N->getValueType(0), dl);
1363  EOp1 = DAG.getNode(ISD::VP_TRUNCATE, dl, HalfNVT, EOp1, MaskLo, EVLLo);
1364  EOp2 = DAG.getNode(ISD::VP_TRUNCATE, dl, HalfNVT, EOp2, MaskHi, EVLHi);
1365  }
1366  return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
1367  }
1368  // TODO: VP_TRUNCATE need to handle when TypeWidenVector access to some
1369  // targets.
1371  SDValue WideInOp = GetWidenedVector(InOp);
1372 
1373  // Truncate widened InOp.
1374  unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
1375  EVT TruncVT = EVT::getVectorVT(*DAG.getContext(),
1376  N->getValueType(0).getScalarType(), NumElem);
1377  SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, WideInOp);
1378 
1379  // Zero extend so that the elements are of same type as those of NVT
1380  EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), NVT.getVectorElementType(),
1381  NumElem);
1382  SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc);
1383 
1384  // Extract the low NVT subvector.
1385  SDValue ZeroIdx = DAG.getVectorIdxConstant(0, dl);
1386  return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx);
1387  }
1388  }
1389 
1390  // Truncate to NVT instead of VT
1391  if (N->getOpcode() == ISD::VP_TRUNCATE)
1392  return DAG.getNode(ISD::VP_TRUNCATE, dl, NVT, Res, N->getOperand(1),
1393  N->getOperand(2));
1394  return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
1395 }
1396 
1397 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
1398  if (ResNo == 1)
1399  return PromoteIntRes_Overflow(N);
1400 
1401  // The operation overflowed iff the result in the larger type is not the
1402  // zero extension of its truncation to the original type.
1403  SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1404  SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1405  EVT OVT = N->getOperand(0).getValueType();
1406  EVT NVT = LHS.getValueType();
1407  SDLoc dl(N);
1408 
1409  // Do the arithmetic in the larger type.
1410  unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1411  SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
1412 
1413  // Calculate the overflow flag: zero extend the arithmetic result from
1414  // the original type.
1415  SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
1416  // Overflowed if and only if this is not equal to Res.
1417  Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
1418 
1419  // Use the calculated overflow everywhere.
1420  ReplaceValueWith(SDValue(N, 1), Ofl);
1421 
1422  return Res;
1423 }
1424 
1425 // Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
1426 // the third operand of ADDE/SUBE nodes is carry flag, which differs from
1427 // the ADDCARRY/SUBCARRY nodes in that the third operand is carry Boolean.
1428 SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
1429  if (ResNo == 1)
1430  return PromoteIntRes_Overflow(N);
1431 
1432  // We need to sign-extend the operands so the carry value computed by the
1433  // wide operation will be equivalent to the carry value computed by the
1434  // narrow operation.
1435  // An ADDCARRY can generate carry only if any of the operands has its
1436  // most significant bit set. Sign extension propagates the most significant
1437  // bit into the higher bits which means the extra bit that the narrow
1438  // addition would need (i.e. the carry) will be propagated through the higher
1439  // bits of the wide addition.
1440  // A SUBCARRY can generate borrow only if LHS < RHS and this property will be
1441  // preserved by sign extension.
1442  SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1443  SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1444 
1445  EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(1)};
1446 
1447  // Do the arithmetic in the wide type.
1448  SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), DAG.getVTList(ValueVTs),
1449  LHS, RHS, N->getOperand(2));
1450 
1451  // Update the users of the original carry/borrow value.
1452  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
1453 
1454  return SDValue(Res.getNode(), 0);
1455 }
1456 
1457 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO_CARRY(SDNode *N,
1458  unsigned ResNo) {
1459  assert(ResNo == 1 && "Don't know how to promote other results yet.");
1460  return PromoteIntRes_Overflow(N);
1461 }
1462 
1463 SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
1464  EVT OVT = N->getValueType(0);
1465  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
1466 
1467  // If a larger ABS or SMAX isn't supported by the target, try to expand now.
1468  // If we expand later we'll end up sign extending more than just the sra input
1469  // in sra+xor+sub expansion.
1470  if (!OVT.isVector() &&
1472  !TLI.isOperationLegal(ISD::SMAX, NVT)) {
1473  if (SDValue Res = TLI.expandABS(N, DAG))
1474  return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), NVT, Res);
1475  }
1476 
1477  SDValue Op0 = SExtPromotedInteger(N->getOperand(0));
1478  return DAG.getNode(ISD::ABS, SDLoc(N), Op0.getValueType(), Op0);
1479 }
1480 
1481 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
1482  // Promote the overflow bit trivially.
1483  if (ResNo == 1)
1484  return PromoteIntRes_Overflow(N);
1485 
1486  SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
1487  SDLoc DL(N);
1488  EVT SmallVT = LHS.getValueType();
1489 
1490  // To determine if the result overflowed in a larger type, we extend the
1491  // input to the larger type, do the multiply (checking if it overflows),
1492  // then also check the high bits of the result to see if overflow happened
1493  // there.
1494  if (N->getOpcode() == ISD::SMULO) {
1495  LHS = SExtPromotedInteger(LHS);
1496  RHS = SExtPromotedInteger(RHS);
1497  } else {
1498  LHS = ZExtPromotedInteger(LHS);
1499  RHS = ZExtPromotedInteger(RHS);
1500  }
1501  SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
1502  SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
1503 
1504  // Overflow occurred if it occurred in the larger type, or if the high part
1505  // of the result does not zero/sign-extend the low part. Check this second
1506  // possibility first.
1507  SDValue Overflow;
1508  if (N->getOpcode() == ISD::UMULO) {
1509  // Unsigned overflow occurred if the high part is non-zero.
1510  unsigned Shift = SmallVT.getScalarSizeInBits();
1511  SDValue Hi =
1512  DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
1513  DAG.getShiftAmountConstant(Shift, Mul.getValueType(), DL));
1514  Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
1515  DAG.getConstant(0, DL, Hi.getValueType()),
1516  ISD::SETNE);
1517  } else {
1518  // Signed overflow occurred if the high part does not sign extend the low.
1519  SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
1520  Mul, DAG.getValueType(SmallVT));
1521  Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
1522  }
1523 
1524  // The only other way for overflow to occur is if the multiplication in the
1525  // larger type itself overflowed.
1526  Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
1527  SDValue(Mul.getNode(), 1));
1528 
1529  // Use the calculated overflow everywhere.
1530  ReplaceValueWith(SDValue(N, 1), Overflow);
1531  return Mul;
1532 }
1533 
1534 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
1535  return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
1536  N->getValueType(0)));
1537 }
1538 
1539 SDValue DAGTypeLegalizer::PromoteIntRes_VSCALE(SDNode *N) {
1540  EVT VT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1541 
1542  APInt MulImm = cast<ConstantSDNode>(N->getOperand(0))->getAPIntValue();
1543  return DAG.getVScale(SDLoc(N), VT, MulImm.sext(VT.getSizeInBits()));
1544 }
1545 
1546 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
1547  SDValue Chain = N->getOperand(0); // Get the chain.
1548  SDValue Ptr = N->getOperand(1); // Get the pointer.
1549  EVT VT = N->getValueType(0);
1550  SDLoc dl(N);
1551 
1552  MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
1553  unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
1554  // The argument is passed as NumRegs registers of type RegVT.
1555 
1556  SmallVector<SDValue, 8> Parts(NumRegs);
1557  for (unsigned i = 0; i < NumRegs; ++i) {
1558  Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
1559  N->getConstantOperandVal(3));
1560  Chain = Parts[i].getValue(1);
1561  }
1562 
1563  // Handle endianness of the load.
1564  if (DAG.getDataLayout().isBigEndian())
1565  std::reverse(Parts.begin(), Parts.end());
1566 
1567  // Assemble the parts in the promoted type.
1568  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1569  SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
1570  for (unsigned i = 1; i < NumRegs; ++i) {
1571  SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
1572  // Shift it to the right position and "or" it in.
1573  Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
1574  DAG.getConstant(i * RegVT.getSizeInBits(), dl,
1575  TLI.getPointerTy(DAG.getDataLayout())));
1576  Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
1577  }
1578 
1579  // Modified the chain result - switch anything that used the old chain to
1580  // use the new one.
1581  ReplaceValueWith(SDValue(N, 1), Chain);
1582 
1583  return Res;
1584 }
1585 
1586 //===----------------------------------------------------------------------===//
1587 // Integer Operand Promotion
1588 //===----------------------------------------------------------------------===//
1589 
1590 /// PromoteIntegerOperand - This method is called when the specified operand of
1591 /// the specified node is found to need promotion. At this point, all of the
1592 /// result types of the node are known to be legal, but other operands of the
1593 /// node may need promotion or expansion as well as the specified one.
1594 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
1595  LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG);
1596  dbgs() << "\n");
1597  SDValue Res = SDValue();
1598  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
1599  LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
1600  return false;
1601  }
1602 
1603  switch (N->getOpcode()) {
1604  default:
1605  #ifndef NDEBUG
1606  dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
1607  N->dump(&DAG); dbgs() << "\n";
1608  #endif
1609  llvm_unreachable("Do not know how to promote this operator's operand!");
1610 
1611  case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
1612  case ISD::ATOMIC_STORE:
1613  Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
1614  break;
1615  case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
1616  case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
1617  case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
1618  case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
1619  case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
1620  case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
1621  case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
1623  Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
1624  case ISD::SCALAR_TO_VECTOR:
1625  Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
1626  case ISD::SPLAT_VECTOR:
1627  Res = PromoteIntOp_SPLAT_VECTOR(N); break;
1628  case ISD::VSELECT:
1629  case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
1630  case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
1631  case ISD::VP_SETCC:
1632  case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
1633  case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
1634  case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
1635  case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
1636  case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
1637  OpNo); break;
1638  case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
1639  OpNo); break;
1640  case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
1641  OpNo); break;
1642  case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
1643  OpNo); break;
1644  case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(cast<MaskedScatterSDNode>(N),
1645  OpNo); break;
1646  case ISD::VP_TRUNCATE:
1647  case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
1648  case ISD::FP16_TO_FP:
1649  case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
1650  case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
1651  case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
1652  case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
1653  case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break;
1654 
1655  case ISD::SHL:
1656  case ISD::SRA:
1657  case ISD::SRL:
1658  case ISD::ROTL:
1659  case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
1660 
1661  case ISD::FSHL:
1662  case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break;
1663 
1664  case ISD::SADDO_CARRY:
1665  case ISD::SSUBO_CARRY:
1666  case ISD::ADDCARRY:
1667  case ISD::SUBCARRY: Res = PromoteIntOp_ADDSUBCARRY(N, OpNo); break;
1668 
1669  case ISD::FRAMEADDR:
1670  case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
1671 
1672  case ISD::PREFETCH: Res = PromoteIntOp_PREFETCH(N, OpNo); break;
1673 
1674  case ISD::SMULFIX:
1675  case ISD::SMULFIXSAT:
1676  case ISD::UMULFIX:
1677  case ISD::UMULFIXSAT:
1678  case ISD::SDIVFIX:
1679  case ISD::SDIVFIXSAT:
1680  case ISD::UDIVFIX:
1681  case ISD::UDIVFIXSAT: Res = PromoteIntOp_FIX(N); break;
1682 
1683  case ISD::FPOWI:
1684  case ISD::STRICT_FPOWI: Res = PromoteIntOp_FPOWI(N); break;
1685 
1686  case ISD::VECREDUCE_ADD:
1687  case ISD::VECREDUCE_MUL:
1688  case ISD::VECREDUCE_AND:
1689  case ISD::VECREDUCE_OR:
1690  case ISD::VECREDUCE_XOR:
1691  case ISD::VECREDUCE_SMAX:
1692  case ISD::VECREDUCE_SMIN:
1693  case ISD::VECREDUCE_UMAX:
1694  case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
1695  case ISD::VP_REDUCE_ADD:
1696  case ISD::VP_REDUCE_MUL:
1697  case ISD::VP_REDUCE_AND:
1698  case ISD::VP_REDUCE_OR:
1699  case ISD::VP_REDUCE_XOR:
1700  case ISD::VP_REDUCE_SMAX:
1701  case ISD::VP_REDUCE_SMIN:
1702  case ISD::VP_REDUCE_UMAX:
1703  case ISD::VP_REDUCE_UMIN:
1704  Res = PromoteIntOp_VP_REDUCE(N, OpNo);
1705  break;
1706 
1707  case ISD::SET_ROUNDING: Res = PromoteIntOp_SET_ROUNDING(N); break;
1708  }
1709 
1710  // If the result is null, the sub-method took care of registering results etc.
1711  if (!Res.getNode()) return false;
1712 
1713  // If the result is N, the sub-method updated N in place. Tell the legalizer
1714  // core about this.
1715  if (Res.getNode() == N)
1716  return true;
1717 
1718  const bool IsStrictFp = N->isStrictFPOpcode();
1719  assert(Res.getValueType() == N->getValueType(0) &&
1720  N->getNumValues() == (IsStrictFp ? 2 : 1) &&
1721  "Invalid operand expansion");
1722  LLVM_DEBUG(dbgs() << "Replacing: "; N->dump(&DAG); dbgs() << " with: ";
1723  Res.dump());
1724 
1725  ReplaceValueWith(SDValue(N, 0), Res);
1726  if (IsStrictFp)
1727  ReplaceValueWith(SDValue(N, 1), SDValue(Res.getNode(), 1));
1728 
1729  return false;
1730 }
1731 
1732 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
1733 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
1734 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
1735  ISD::CondCode CCCode) {
1736  // We have to insert explicit sign or zero extends. Note that we could
1737  // insert sign extends for ALL conditions. For those operations where either
1738  // zero or sign extension would be valid, we ask the target which extension
1739  // it would prefer.
1740 
1741  // Signed comparisons always require sign extension.
1742  if (ISD::isSignedIntSetCC(CCCode)) {
1743  LHS = SExtPromotedInteger(LHS);
1744  RHS = SExtPromotedInteger(RHS);
1745  return;
1746  }
1747 
1749  "Unknown integer comparison!");
1750 
1751  SDValue OpL = GetPromotedInteger(LHS);
1752  SDValue OpR = GetPromotedInteger(RHS);
1753 
1754  if (TLI.isSExtCheaperThanZExt(LHS.getValueType(), OpL.getValueType())) {
1755  // The target would prefer to promote the comparison operand with sign
1756  // extension. Honor that unless the promoted values are already zero
1757  // extended.
1758  unsigned OpLEffectiveBits =
1760  unsigned OpREffectiveBits =
1762  if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
1763  OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
1764  LHS = OpL;
1765  RHS = OpR;
1766  return;
1767  }
1768 
1769  // The promoted values aren't zero extended, use a sext_inreg.
1770  LHS = SExtPromotedInteger(LHS);
1771  RHS = SExtPromotedInteger(RHS);
1772  return;
1773  }
1774 
1775  // Prefer to promote the comparison operand with zero extension.
1776 
1777  // If the width of OpL/OpR excluding the duplicated sign bits is no greater
1778  // than the width of LHS/RHS, we can avoid/ inserting a zext_inreg operation
1779  // that we might not be able to remove.
1780  unsigned OpLEffectiveBits = DAG.ComputeMaxSignificantBits(OpL);
1781  unsigned OpREffectiveBits = DAG.ComputeMaxSignificantBits(OpR);
1782  if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
1783  OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
1784  LHS = OpL;
1785  RHS = OpR;
1786  return;
1787  }
1788 
1789  // Otherwise, use zext_inreg.
1790  LHS = ZExtPromotedInteger(LHS);
1791  RHS = ZExtPromotedInteger(RHS);
1792 }
1793 
1794 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
1795  SDValue Op = GetPromotedInteger(N->getOperand(0));
1796  return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
1797 }
1798 
1799 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
1800  SDValue Op2 = GetPromotedInteger(N->getOperand(2));
1801  return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
1802  N->getChain(), N->getBasePtr(), Op2, N->getMemOperand());
1803 }
1804 
1805 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
1806  // This should only occur in unusual situations like bitcasting to an
1807  // x86_fp80, so just turn it into a store+load
1808  return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
1809 }
1810 
1811 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
1812  assert(OpNo == 2 && "Don't know how to promote this operand!");
1813 
1814  SDValue LHS = N->getOperand(2);
1815  SDValue RHS = N->getOperand(3);
1816  PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
1817 
1818  // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
1819  // legal types.
1820  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1821  N->getOperand(1), LHS, RHS, N->getOperand(4)),
1822  0);
1823 }
1824 
1825 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
1826  assert(OpNo == 1 && "only know how to promote condition");
1827 
1828  // Promote all the way up to the canonical SetCC type.
1829  SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
1830 
1831  // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1832  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1833  N->getOperand(2)), 0);
1834 }
1835 
1836 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1837  // Since the result type is legal, the operands must promote to it.
1838  EVT OVT = N->getOperand(0).getValueType();
1839  SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1840  SDValue Hi = GetPromotedInteger(N->getOperand(1));
1841  assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
1842  SDLoc dl(N);
1843 
1844  Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1845  DAG.getConstant(OVT.getSizeInBits(), dl,
1846  TLI.getPointerTy(DAG.getDataLayout())));
1847  return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1848 }
1849 
1850 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1851  // The vector type is legal but the element type is not. This implies
1852  // that the vector is a power-of-two in length and that the element
1853  // type does not have a strange size (eg: it is not i1).
1854  EVT VecVT = N->getValueType(0);
1855  unsigned NumElts = VecVT.getVectorNumElements();
1856  assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
1857  "Legal vector of one illegal element?");
1858 
1859  // Promote the inserted value. The type does not need to match the
1860  // vector element type. Check that any extra bits introduced will be
1861  // truncated away.
1862  assert(N->getOperand(0).getValueSizeInBits() >=
1863  N->getValueType(0).getScalarSizeInBits() &&
1864  "Type of inserted value narrower than vector element type!");
1865 
1866  SmallVector<SDValue, 16> NewOps;
1867  for (unsigned i = 0; i < NumElts; ++i)
1868  NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1869 
1870  return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1871 }
1872 
1873 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1874  unsigned OpNo) {
1875  if (OpNo == 1) {
1876  // Promote the inserted value. This is valid because the type does not
1877  // have to match the vector element type.
1878 
1879  // Check that any extra bits introduced will be truncated away.
1880  assert(N->getOperand(1).getValueSizeInBits() >=
1881  N->getValueType(0).getScalarSizeInBits() &&
1882  "Type of inserted value narrower than vector element type!");
1883  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1884  GetPromotedInteger(N->getOperand(1)),
1885  N->getOperand(2)),
1886  0);
1887  }
1888 
1889  assert(OpNo == 2 && "Different operand and result vector types?");
1890 
1891  // Promote the index.
1892  SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1893  TLI.getVectorIdxTy(DAG.getDataLayout()));
1894  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1895  N->getOperand(1), Idx), 0);
1896 }
1897 
1898 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1899  // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1900  // the operand in place.
1901  return SDValue(DAG.UpdateNodeOperands(N,
1902  GetPromotedInteger(N->getOperand(0))), 0);
1903 }
1904 
1905 SDValue DAGTypeLegalizer::PromoteIntOp_SPLAT_VECTOR(SDNode *N) {
1906  // Integer SPLAT_VECTOR operands are implicitly truncated, so just promote the
1907  // operand in place.
1908  return SDValue(
1909  DAG.UpdateNodeOperands(N, GetPromotedInteger(N->getOperand(0))), 0);
1910 }
1911 
1912 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1913  assert(OpNo == 0 && "Only know how to promote the condition!");
1914  SDValue Cond = N->getOperand(0);
1915  EVT OpTy = N->getOperand(1).getValueType();
1916 
1917  if (N->getOpcode() == ISD::VSELECT)
1918  if (SDValue Res = WidenVSELECTMask(N))
1919  return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
1920  Res, N->getOperand(1), N->getOperand(2));
1921 
1922  // Promote all the way up to the canonical SetCC type.
1923  EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1924  Cond = PromoteTargetBoolean(Cond, OpVT);
1925 
1926  return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1927  N->getOperand(2)), 0);
1928 }
1929 
1930 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1931  assert(OpNo == 0 && "Don't know how to promote this operand!");
1932 
1933  SDValue LHS = N->getOperand(0);
1934  SDValue RHS = N->getOperand(1);
1935  PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1936 
1937  // The CC (#4) and the possible return values (#2 and #3) have legal types.
1938  return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1939  N->getOperand(3), N->getOperand(4)), 0);
1940 }
1941 
1942 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1943  assert(OpNo == 0 && "Don't know how to promote this operand!");
1944 
1945  SDValue LHS = N->getOperand(0);
1946  SDValue RHS = N->getOperand(1);
1947  PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1948 
1949  // The CC (#2) is always legal.
1950  if (N->getNumOperands() == 3)
1951  return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1952 
1953  assert(N->getNumOperands() == 5 && "Unexpected number of operands!");
1954  assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
1955 
1956  return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1957  N->getOperand(3), N->getOperand(4)),
1958  0);
1959 }
1960 
1961 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1962  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1963  ZExtPromotedInteger(N->getOperand(1))), 0);
1964 }
1965 
1966 SDValue DAGTypeLegalizer::PromoteIntOp_FunnelShift(SDNode *N) {
1967  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
1968  ZExtPromotedInteger(N->getOperand(2))), 0);
1969 }
1970 
1971 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1972  SDValue Op = GetPromotedInteger(N->getOperand(0));
1973  SDLoc dl(N);
1974  Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1975  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1976  Op, DAG.getValueType(N->getOperand(0).getValueType()));
1977 }
1978 
1979 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1980  return SDValue(DAG.UpdateNodeOperands(N,
1981  SExtPromotedInteger(N->getOperand(0))), 0);
1982 }
1983 
1984 SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N) {
1985  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1986  SExtPromotedInteger(N->getOperand(1))), 0);
1987 }
1988 
1989 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1990  assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1991  SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1992  SDLoc dl(N);
1993 
1994  SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1995 
1996  // Truncate the value and store the result.
1997  return DAG.getTruncStore(Ch, dl, Val, Ptr,
1998  N->getMemoryVT(), N->getMemOperand());
1999 }
2000 
2001 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
2002  unsigned OpNo) {
2003  SDValue DataOp = N->getValue();
2004  SDValue Mask = N->getMask();
2005 
2006  if (OpNo == 4) {
2007  // The Mask. Update in place.
2008  EVT DataVT = DataOp.getValueType();
2009  Mask = PromoteTargetBoolean(Mask, DataVT);
2010  SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
2011  NewOps[4] = Mask;
2012  return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
2013  }
2014 
2015  assert(OpNo == 1 && "Unexpected operand for promotion");
2016  DataOp = GetPromotedInteger(DataOp);
2017 
2018  return DAG.getMaskedStore(N->getChain(), SDLoc(N), DataOp, N->getBasePtr(),
2019  N->getOffset(), Mask, N->getMemoryVT(),
2020  N->getMemOperand(), N->getAddressingMode(),
2021  /*IsTruncating*/ true, N->isCompressingStore());
2022 }
2023 
2024 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
2025  unsigned OpNo) {
2026  assert(OpNo == 3 && "Only know how to promote the mask!");
2027  EVT DataVT = N->getValueType(0);
2028  SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
2029  SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
2030  NewOps[OpNo] = Mask;
2031  SDNode *Res = DAG.UpdateNodeOperands(N, NewOps);
2032  if (Res == N)
2033  return SDValue(Res, 0);
2034 
2035  // Update triggered CSE, do our own replacement since caller can't.
2036  ReplaceValueWith(SDValue(N, 0), SDValue(Res, 0));
2037  ReplaceValueWith(SDValue(N, 1), SDValue(Res, 1));
2038  return SDValue();
2039 }
2040 
2041 SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
2042  unsigned OpNo) {
2043  SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
2044 
2045  if (OpNo == 2) {
2046  // The Mask
2047  EVT DataVT = N->getValueType(0);
2048  NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
2049  } else if (OpNo == 4) {
2050  // The Index
2051  if (N->isIndexSigned())
2052  // Need to sign extend the index since the bits will likely be used.
2053  NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
2054  else
2055  NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
2056  } else
2057  NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
2058 
2059  SDNode *Res = DAG.UpdateNodeOperands(N, NewOps);
2060  if (Res == N)
2061  return SDValue(Res, 0);
2062 
2063  // Update triggered CSE, do our own replacement since caller can't.
2064  ReplaceValueWith(SDValue(N, 0), SDValue(Res, 0));
2065  ReplaceValueWith(SDValue(N, 1), SDValue(Res, 1));
2066  return SDValue();
2067 }
2068 
2069 SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
2070  unsigned OpNo) {
2071  bool TruncateStore = N->isTruncatingStore();
2072  SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
2073 
2074  if (OpNo == 2) {
2075  // The Mask
2076  EVT DataVT = N->getValue().getValueType();
2077  NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
2078  } else if (OpNo == 4) {
2079  // The Index
2080  if (N->isIndexSigned())
2081  // Need to sign extend the index since the bits will likely be used.
2082  NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
2083  else
2084  NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
2085  } else {
2086  NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
2087  TruncateStore = true;
2088  }
2089 
2090  return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), N->getMemoryVT(),
2091  SDLoc(N), NewOps, N->getMemOperand(),
2092  N->getIndexType(), TruncateStore);
2093 }
2094 
2095 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
2096  SDValue Op = GetPromotedInteger(N->getOperand(0));
2097  if (N->getOpcode() == ISD::VP_TRUNCATE)
2098  return DAG.getNode(ISD::VP_TRUNCATE, SDLoc(N), N->getValueType(0), Op,
2099  N->getOperand(1), N->getOperand(2));
2100  return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
2101 }
2102 
2103 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
2104  return SDValue(DAG.UpdateNodeOperands(N,
2105  ZExtPromotedInteger(N->getOperand(0))), 0);
2106 }
2107 
2108 SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N) {
2109  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2110  ZExtPromotedInteger(N->getOperand(1))), 0);
2111 }
2112 
2113 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
2114  SDLoc dl(N);
2115  SDValue Op = GetPromotedInteger(N->getOperand(0));
2116  Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
2117  return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
2118 }
2119 
2120 SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo) {
2121  assert(OpNo == 2 && "Don't know how to promote this operand!");
2122 
2123  SDValue LHS = N->getOperand(0);
2124  SDValue RHS = N->getOperand(1);
2125  SDValue Carry = N->getOperand(2);
2126  SDLoc DL(N);
2127 
2128  Carry = PromoteTargetBoolean(Carry, LHS.getValueType());
2129 
2130  return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, Carry), 0);
2131 }
2132 
2133 SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
2134  SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
2135  return SDValue(
2136  DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), Op2), 0);
2137 }
2138 
2139 SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
2140  // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
2141  SDValue Op = ZExtPromotedInteger(N->getOperand(0));
2142  return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2143 }
2144 
2145 SDValue DAGTypeLegalizer::PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo) {
2146  assert(OpNo > 1 && "Don't know how to promote this operand!");
2147  // Promote the rw, locality, and cache type arguments to a supported integer
2148  // width.
2149  SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
2150  SDValue Op3 = ZExtPromotedInteger(N->getOperand(3));
2151  SDValue Op4 = ZExtPromotedInteger(N->getOperand(4));
2152  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
2153  Op2, Op3, Op4),
2154  0);
2155 }
2156 
2157 SDValue DAGTypeLegalizer::PromoteIntOp_FPOWI(SDNode *N) {
2158  bool IsStrict = N->isStrictFPOpcode();
2159  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
2160 
2161  // The integer operand is the last operand in FPOWI (so the result and
2162  // floating point operand is already type legalized).
2163 
2164  // We can't just promote the exponent type in FPOWI, since we want to lower
2165  // the node to a libcall and we if we promote to a type larger than
2166  // sizeof(int) the libcall might not be according to the targets ABI. Instead
2167  // we rewrite to a libcall here directly, letting makeLibCall handle promotion
2168  // if the target accepts it according to shouldSignExtendTypeInLibCall.
2169  RTLIB::Libcall LC = RTLIB::getPOWI(N->getValueType(0));
2170  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fpowi.");
2171  if (!TLI.getLibcallName(LC)) {
2172  // Some targets don't have a powi libcall; use pow instead.
2173  // FIXME: Implement this if some target needs it.
2174  DAG.getContext()->emitError("Don't know how to promote fpowi to fpow");
2175  return DAG.getUNDEF(N->getValueType(0));
2176  }
2177  unsigned OpOffset = IsStrict ? 1 : 0;
2178  // The exponent should fit in a sizeof(int) type for the libcall to be valid.
2179  assert(DAG.getLibInfo().getIntSize() ==
2180  N->getOperand(1 + OpOffset).getValueType().getSizeInBits() &&
2181  "POWI exponent should match with sizeof(int) when doing the libcall.");
2183  CallOptions.setSExt(true);
2184  SDValue Ops[2] = {N->getOperand(0 + OpOffset), N->getOperand(1 + OpOffset)};
2185  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
2186  DAG, LC, N->getValueType(0), Ops, CallOptions, SDLoc(N), Chain);
2187  ReplaceValueWith(SDValue(N, 0), Tmp.first);
2188  if (IsStrict)
2189  ReplaceValueWith(SDValue(N, 1), Tmp.second);
2190  return SDValue();
2191 }
2192 
2194  switch (N->getOpcode()) {
2195  default:
2196  llvm_unreachable("Expected integer vector reduction");
2197  case ISD::VECREDUCE_ADD:
2198  case ISD::VECREDUCE_MUL:
2199  case ISD::VECREDUCE_AND:
2200  case ISD::VECREDUCE_OR:
2201  case ISD::VECREDUCE_XOR:
2202  case ISD::VP_REDUCE_ADD:
2203  case ISD::VP_REDUCE_MUL:
2204  case ISD::VP_REDUCE_AND:
2205  case ISD::VP_REDUCE_OR:
2206  case ISD::VP_REDUCE_XOR:
2207  return ISD::ANY_EXTEND;
2208  case ISD::VECREDUCE_SMAX:
2209  case ISD::VECREDUCE_SMIN:
2210  case ISD::VP_REDUCE_SMAX:
2211  case ISD::VP_REDUCE_SMIN:
2212  return ISD::SIGN_EXTEND;
2213  case ISD::VECREDUCE_UMAX:
2214  case ISD::VECREDUCE_UMIN:
2215  case ISD::VP_REDUCE_UMAX:
2216  case ISD::VP_REDUCE_UMIN:
2217  return ISD::ZERO_EXTEND;
2218  }
2219 }
2220 
2221 SDValue DAGTypeLegalizer::PromoteIntOpVectorReduction(SDNode *N, SDValue V) {
2222  switch (getExtendForIntVecReduction(N)) {
2223  default:
2224  llvm_unreachable("Impossible extension kind for integer reduction");
2225  case ISD::ANY_EXTEND:
2226  return GetPromotedInteger(V);
2227  case ISD::SIGN_EXTEND:
2228  return SExtPromotedInteger(V);
2229  case ISD::ZERO_EXTEND:
2230  return ZExtPromotedInteger(V);
2231  }
2232 }
2233 
2234 SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
2235  SDLoc dl(N);
2236  SDValue Op = PromoteIntOpVectorReduction(N, N->getOperand(0));
2237 
2238  EVT EltVT = Op.getValueType().getVectorElementType();
2239  EVT VT = N->getValueType(0);
2240 
2241  if (VT.bitsGE(EltVT))
2242  return DAG.getNode(N->getOpcode(), SDLoc(N), VT, Op);
2243 
2244  // Result size must be >= element size. If this is not the case after
2245  // promotion, also promote the result type and then truncate.
2246  SDValue Reduce = DAG.getNode(N->getOpcode(), dl, EltVT, Op);
2247  return DAG.getNode(ISD::TRUNCATE, dl, VT, Reduce);
2248 }
2249 
2250 SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
2251  SDLoc DL(N);
2252  SDValue Op = N->getOperand(OpNo);
2253  SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
2254 
2255  if (OpNo == 2) { // Mask
2256  // Update in place.
2257  NewOps[2] = PromoteTargetBoolean(Op, N->getOperand(1).getValueType());
2258  return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
2259  }
2260 
2261  assert(OpNo == 1 && "Unexpected operand for promotion");
2262 
2263  Op = PromoteIntOpVectorReduction(N, Op);
2264 
2265  NewOps[OpNo] = Op;
2266 
2267  EVT VT = N->getValueType(0);
2268  EVT EltVT = Op.getValueType().getScalarType();
2269 
2270  if (VT.bitsGE(EltVT))
2271  return DAG.getNode(N->getOpcode(), SDLoc(N), VT, NewOps);
2272 
2273  // Result size must be >= element/start-value size. If this is not the case
2274  // after promotion, also promote both the start value and result type and
2275  // then truncate.
2276  NewOps[0] =
2277  DAG.getNode(getExtendForIntVecReduction(N), DL, EltVT, N->getOperand(0));
2278  SDValue Reduce = DAG.getNode(N->getOpcode(), DL, EltVT, NewOps);
2279  return DAG.getNode(ISD::TRUNCATE, DL, VT, Reduce);
2280 }
2281 
2282 SDValue DAGTypeLegalizer::PromoteIntOp_SET_ROUNDING(SDNode *N) {
2283  SDValue Op = ZExtPromotedInteger(N->getOperand(1));
2284  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op), 0);
2285 }
2286 
2287 //===----------------------------------------------------------------------===//
2288 // Integer Result Expansion
2289 //===----------------------------------------------------------------------===//
2290 
2291 /// ExpandIntegerResult - This method is called when the specified result of the
2292 /// specified node is found to need expansion. At this point, the node may also
2293 /// have invalid operands or may have other results that need promotion, we just
2294 /// know that (at least) one result needs expansion.
2295 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
2296  LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG);
2297  dbgs() << "\n");
2298  SDValue Lo, Hi;
2299  Lo = Hi = SDValue();
2300 
2301  // See if the target wants to custom expand this node.
2302  if (CustomLowerNode(N, N->getValueType(ResNo), true))
2303  return;
2304 
2305  switch (N->getOpcode()) {
2306  default:
2307 #ifndef NDEBUG
2308  dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
2309  N->dump(&DAG); dbgs() << "\n";
2310 #endif
2311  report_fatal_error("Do not know how to expand the result of this "
2312  "operator!");
2313 
2314  case ISD::ARITH_FENCE: SplitRes_ARITH_FENCE(N, Lo, Hi); break;
2315  case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
2316  case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break;
2317  case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
2318  case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
2319  case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break;
2320 
2321  case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
2322  case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
2323  case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
2324  case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
2325  case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
2326 
2327  case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
2328  case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
2329  case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
2330  case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
2331  case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
2332  case ISD::PARITY: ExpandIntRes_PARITY(N, Lo, Hi); break;
2333  case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
2334  case ISD::ABS: ExpandIntRes_ABS(N, Lo, Hi); break;
2335  case ISD::CTLZ_ZERO_UNDEF:
2336  case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
2337  case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
2338  case ISD::CTTZ_ZERO_UNDEF:
2339  case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
2340  case ISD::FLT_ROUNDS_: ExpandIntRes_FLT_ROUNDS(N, Lo, Hi); break;
2342  case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
2344  case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
2345  case ISD::FP_TO_SINT_SAT:
2346  case ISD::FP_TO_UINT_SAT: ExpandIntRes_FP_TO_XINT_SAT(N, Lo, Hi); break;
2347  case ISD::STRICT_LLROUND:
2348  case ISD::STRICT_LLRINT:
2349  case ISD::LLROUND:
2350  case ISD::LLRINT: ExpandIntRes_LLROUND_LLRINT(N, Lo, Hi); break;
2351  case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
2352  case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
2353  case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
2354  case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
2355  case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
2356  case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
2357  case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
2358  case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
2359  case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
2360  case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
2361  case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
2362  case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
2363 
2364  case ISD::ATOMIC_LOAD_ADD:
2365  case ISD::ATOMIC_LOAD_SUB:
2366  case ISD::ATOMIC_LOAD_AND:
2367  case ISD::ATOMIC_LOAD_CLR:
2368  case ISD::ATOMIC_LOAD_OR:
2369  case ISD::ATOMIC_LOAD_XOR:
2370  case ISD::ATOMIC_LOAD_NAND:
2371  case ISD::ATOMIC_LOAD_MIN:
2372  case ISD::ATOMIC_LOAD_MAX:
2373  case ISD::ATOMIC_LOAD_UMIN:
2374  case ISD::ATOMIC_LOAD_UMAX:
2375  case ISD::ATOMIC_SWAP:
2376  case ISD::ATOMIC_CMP_SWAP: {
2377  std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
2378  SplitInteger(Tmp.first, Lo, Hi);
2379  ReplaceValueWith(SDValue(N, 1), Tmp.second);
2380  break;
2381  }
2383  AtomicSDNode *AN = cast<AtomicSDNode>(N);
2384  SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
2385  SDValue Tmp = DAG.getAtomicCmpSwap(
2386  ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
2387  N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
2388  AN->getMemOperand());
2389 
2390  // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
2391  // success simply by comparing the loaded value against the ingoing
2392  // comparison.
2393  SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
2394  N->getOperand(2), ISD::SETEQ);
2395 
2396  SplitInteger(Tmp, Lo, Hi);
2397  ReplaceValueWith(SDValue(N, 1), Success);
2398  ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
2399  break;
2400  }
2401 
2402  case ISD::AND:
2403  case ISD::OR:
2404  case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
2405 
2406  case ISD::UMAX:
2407  case ISD::SMAX:
2408  case ISD::UMIN:
2409  case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
2410 
2411  case ISD::ADD:
2412  case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
2413 
2414  case ISD::ADDC:
2415  case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
2416 
2417  case ISD::ADDE:
2418  case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
2419 
2420  case ISD::ADDCARRY:
2421  case ISD::SUBCARRY: ExpandIntRes_ADDSUBCARRY(N, Lo, Hi); break;
2422 
2423  case ISD::SADDO_CARRY:
2424  case ISD::SSUBO_CARRY: ExpandIntRes_SADDSUBO_CARRY(N, Lo, Hi); break;
2425 
2426  case ISD::SHL:
2427  case ISD::SRA:
2428  case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
2429 
2430  case ISD::SADDO:
2431  case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
2432  case ISD::UADDO:
2433  case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
2434  case ISD::UMULO:
2435  case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
2436 
2437  case ISD::SADDSAT:
2438  case ISD::UADDSAT:
2439  case ISD::SSUBSAT:
2440  case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
2441 
2442  case ISD::SSHLSAT:
2443  case ISD::USHLSAT: ExpandIntRes_SHLSAT(N, Lo, Hi); break;
2444 
2445  case ISD::SMULFIX:
2446  case ISD::SMULFIXSAT:
2447  case ISD::UMULFIX:
2448  case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
2449 
2450  case ISD::SDIVFIX:
2451  case ISD::SDIVFIXSAT:
2452  case ISD::UDIVFIX:
2453  case ISD::UDIVFIXSAT: ExpandIntRes_DIVFIX(N, Lo, Hi); break;
2454 
2455  case ISD::VECREDUCE_ADD:
2456  case ISD::VECREDUCE_MUL:
2457  case ISD::VECREDUCE_AND:
2458  case ISD::VECREDUCE_OR:
2459  case ISD::VECREDUCE_XOR:
2460  case ISD::VECREDUCE_SMAX:
2461  case ISD::VECREDUCE_SMIN:
2462  case ISD::VECREDUCE_UMAX:
2463  case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
2464 
2465  case ISD::ROTL:
2466  case ISD::ROTR:
2467  ExpandIntRes_Rotate(N, Lo, Hi);
2468  break;
2469 
2470  case ISD::FSHL:
2471  case ISD::FSHR:
2472  ExpandIntRes_FunnelShift(N, Lo, Hi);
2473  break;
2474 
2475  case ISD::VSCALE:
2476  ExpandIntRes_VSCALE(N, Lo, Hi);
2477  break;
2478  }
2479 
2480  // If Lo/Hi is null, the sub-method took care of registering results etc.
2481  if (Lo.getNode())
2482  SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
2483 }
2484 
2485 /// Lower an atomic node to the appropriate builtin call.
2486 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
2487  unsigned Opc = Node->getOpcode();
2488  MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2489  AtomicOrdering order = cast<AtomicSDNode>(Node)->getMergedOrdering();
2490  // Lower to outline atomic libcall if outline atomics enabled,
2491  // or to sync libcall otherwise
2492  RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, order, VT);
2493  EVT RetVT = Node->getValueType(0);
2496  if (TLI.getLibcallName(LC)) {
2497  Ops.append(Node->op_begin() + 2, Node->op_end());
2498  Ops.push_back(Node->getOperand(1));
2499  } else {
2500  LC = RTLIB::getSYNC(Opc, VT);
2501  assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2502  "Unexpected atomic op or value type!");
2503  Ops.append(Node->op_begin() + 1, Node->op_end());
2504  }
2505  return TLI.makeLibCall(DAG, LC, RetVT, Ops, CallOptions, SDLoc(Node),
2506  Node->getOperand(0));
2507 }
2508 
2509 /// N is a shift by a value that needs to be expanded,
2510 /// and the shift amount is a constant 'Amt'. Expand the operation.
2511 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
2512  SDValue &Lo, SDValue &Hi) {
2513  SDLoc DL(N);
2514  // Expand the incoming operand to be shifted, so that we have its parts
2515  SDValue InL, InH;
2516  GetExpandedInteger(N->getOperand(0), InL, InH);
2517 
2518  // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
2519  // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
2520  if (!Amt) {
2521  Lo = InL;
2522  Hi = InH;
2523  return;
2524  }
2525 
2526  EVT NVT = InL.getValueType();
2527  unsigned VTBits = N->getValueType(0).getSizeInBits();
2528  unsigned NVTBits = NVT.getSizeInBits();
2529  EVT ShTy = N->getOperand(1).getValueType();
2530 
2531  if (N->getOpcode() == ISD::SHL) {
2532  if (Amt.uge(VTBits)) {
2533  Lo = Hi = DAG.getConstant(0, DL, NVT);
2534  } else if (Amt.ugt(NVTBits)) {
2535  Lo = DAG.getConstant(0, DL, NVT);
2536  Hi = DAG.getNode(ISD::SHL, DL,
2537  NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2538  } else if (Amt == NVTBits) {
2539  Lo = DAG.getConstant(0, DL, NVT);
2540  Hi = InL;
2541  } else {
2542  Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
2543  Hi = DAG.getNode(ISD::OR, DL, NVT,
2544  DAG.getNode(ISD::SHL, DL, NVT, InH,
2545  DAG.getConstant(Amt, DL, ShTy)),
2546  DAG.getNode(ISD::SRL, DL, NVT, InL,
2547  DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2548  }
2549  return;
2550  }
2551 
2552  if (N->getOpcode() == ISD::SRL) {
2553  if (Amt.uge(VTBits)) {
2554  Lo = Hi = DAG.getConstant(0, DL, NVT);
2555  } else if (Amt.ugt(NVTBits)) {
2556  Lo = DAG.getNode(ISD::SRL, DL,
2557  NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2558  Hi = DAG.getConstant(0, DL, NVT);
2559  } else if (Amt == NVTBits) {
2560  Lo = InH;
2561  Hi = DAG.getConstant(0, DL, NVT);
2562  } else {
2563  Lo = DAG.getNode(ISD::OR, DL, NVT,
2564  DAG.getNode(ISD::SRL, DL, NVT, InL,
2565  DAG.getConstant(Amt, DL, ShTy)),
2566  DAG.getNode(ISD::SHL, DL, NVT, InH,
2567  DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2568  Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2569  }
2570  return;
2571  }
2572 
2573  assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2574  if (Amt.uge(VTBits)) {
2575  Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2576  DAG.getConstant(NVTBits - 1, DL, ShTy));
2577  } else if (Amt.ugt(NVTBits)) {
2578  Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2579  DAG.getConstant(Amt - NVTBits, DL, ShTy));
2580  Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2581  DAG.getConstant(NVTBits - 1, DL, ShTy));
2582  } else if (Amt == NVTBits) {
2583  Lo = InH;
2584  Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2585  DAG.getConstant(NVTBits - 1, DL, ShTy));
2586  } else {
2587  Lo = DAG.getNode(ISD::OR, DL, NVT,
2588  DAG.getNode(ISD::SRL, DL, NVT, InL,
2589  DAG.getConstant(Amt, DL, ShTy)),
2590  DAG.getNode(ISD::SHL, DL, NVT, InH,
2591  DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2592  Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2593  }
2594 }
2595 
2596 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
2597 /// this shift based on knowledge of the high bit of the shift amount. If we
2598 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
2599 /// shift amount.
2600 bool DAGTypeLegalizer::
2601 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
2602  SDValue Amt = N->getOperand(1);
2603  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2604  EVT ShTy = Amt.getValueType();
2605  unsigned ShBits = ShTy.getScalarSizeInBits();
2606  unsigned NVTBits = NVT.getScalarSizeInBits();
2607  assert(isPowerOf2_32(NVTBits) &&
2608  "Expanded integer type size not a power of two!");
2609  SDLoc dl(N);
2610 
2611  APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
2612  KnownBits Known = DAG.computeKnownBits(N->getOperand(1));
2613 
2614  // If we don't know anything about the high bits, exit.
2615  if (((Known.Zero|Known.One) & HighBitMask) == 0)
2616  return false;
2617 
2618  // Get the incoming operand to be shifted.
2619  SDValue InL, InH;
2620  GetExpandedInteger(N->getOperand(0), InL, InH);
2621 
2622  // If we know that any of the high bits of the shift amount are one, then we
2623  // can do this as a couple of simple shifts.
2624  if (Known.One.intersects(HighBitMask)) {
2625  // Mask out the high bit, which we know is set.
2626  Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
2627  DAG.getConstant(~HighBitMask, dl, ShTy));
2628 
2629  switch (N->getOpcode()) {
2630  default: llvm_unreachable("Unknown shift");
2631  case ISD::SHL:
2632  Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
2633  Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
2634  return true;
2635  case ISD::SRL:
2636  Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
2637  Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
2638  return true;
2639  case ISD::SRA:
2640  Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
2641  DAG.getConstant(NVTBits - 1, dl, ShTy));
2642  Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
2643  return true;
2644  }
2645  }
2646 
2647  // If we know that all of the high bits of the shift amount are zero, then we
2648  // can do this as a couple of simple shifts.
2649  if (HighBitMask.isSubsetOf(Known.Zero)) {
2650  // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
2651  // shift if x is zero. We can use XOR here because x is known to be smaller
2652  // than 32.
2653  SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
2654  DAG.getConstant(NVTBits - 1, dl, ShTy));
2655 
2656  unsigned Op1, Op2;
2657  switch (N->getOpcode()) {
2658  default: llvm_unreachable("Unknown shift");
2659  case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
2660  case ISD::SRL:
2661  case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
2662  }
2663 
2664  // When shifting right the arithmetic for Lo and Hi is swapped.
2665  if (N->getOpcode() != ISD::SHL)
2666  std::swap(InL, InH);
2667 
2668  // Use a little trick to get the bits that move from Lo to Hi. First
2669  // shift by one bit.
2670  SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
2671  // Then compute the remaining shift with amount-1.
2672  SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
2673 
2674  Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
2675  Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
2676 
2677  if (N->getOpcode() != ISD::SHL)
2678  std::swap(Hi, Lo);
2679  return true;
2680  }
2681 
2682  return false;
2683 }
2684 
2685 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
2686 /// of any size.
2687 bool DAGTypeLegalizer::
2688 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
2689  SDValue Amt = N->getOperand(1);
2690  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2691  EVT ShTy = Amt.getValueType();
2692  unsigned NVTBits = NVT.getSizeInBits();
2693  assert(isPowerOf2_32(NVTBits) &&
2694  "Expanded integer type size not a power of two!");
2695  SDLoc dl(N);
2696 
2697  // Get the incoming operand to be shifted.
2698  SDValue InL, InH;
2699  GetExpandedInteger(N->getOperand(0), InL, InH);
2700 
2701  SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
2702  SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
2703  SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
2704  SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2705  Amt, NVBitsNode, ISD::SETULT);
2706  SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2707  Amt, DAG.getConstant(0, dl, ShTy),
2708  ISD::SETEQ);
2709 
2710  SDValue LoS, HiS, LoL, HiL;
2711  switch (N->getOpcode()) {
2712  default: llvm_unreachable("Unknown shift");
2713  case ISD::SHL:
2714  // Short: ShAmt < NVTBits
2715  LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
2716  HiS = DAG.getNode(ISD::OR, dl, NVT,
2717  DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
2718  DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
2719 
2720  // Long: ShAmt >= NVTBits
2721  LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
2722  HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
2723 
2724  Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
2725  Hi = DAG.getSelect(dl, NVT, isZero, InH,
2726  DAG.getSelect(dl, NVT, isShort, HiS, HiL));
2727  return true;
2728  case ISD::SRL:
2729  // Short: ShAmt < NVTBits
2730  HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
2731  LoS = DAG.getNode(ISD::OR, dl, NVT,
2732  DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2733  // FIXME: If Amt is zero, the following shift generates an undefined result
2734  // on some architectures.
2735  DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2736 
2737  // Long: ShAmt >= NVTBits
2738  HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
2739  LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2740 
2741  Lo = DAG.getSelect(dl, NVT, isZero, InL,
2742  DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2743  Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2744  return true;
2745  case ISD::SRA:
2746  // Short: ShAmt < NVTBits
2747  HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
2748  LoS = DAG.getNode(ISD::OR, dl, NVT,
2749  DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2750  DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2751 
2752  // Long: ShAmt >= NVTBits
2753  HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
2754  DAG.getConstant(NVTBits - 1, dl, ShTy));
2755  LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2756 
2757  Lo = DAG.getSelect(dl, NVT, isZero, InL,
2758  DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2759  Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2760  return true;
2761  }
2762 }
2763 
2764 static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
2765 
2766  switch (Op) {
2767  default: llvm_unreachable("invalid min/max opcode");
2768  case ISD::SMAX:
2769  return std::make_pair(ISD::SETGT, ISD::UMAX);
2770  case ISD::UMAX:
2771  return std::make_pair(ISD::SETUGT, ISD::UMAX);
2772  case ISD::SMIN:
2773  return std::make_pair(ISD::SETLT, ISD::UMIN);
2774  case ISD::UMIN:
2775  return std::make_pair(ISD::SETULT, ISD::UMIN);
2776  }
2777 }
2778 
2779 void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
2780  SDValue &Lo, SDValue &Hi) {
2781  SDLoc DL(N);
2782  ISD::NodeType LoOpc;
2783  ISD::CondCode CondC;
2784  std::tie(CondC, LoOpc) = getExpandedMinMaxOps(N->getOpcode());
2785 
2786  // Expand the subcomponents.
2787  SDValue LHSL, LHSH, RHSL, RHSH;
2788  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2789  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2790 
2791  // Value types
2792  EVT NVT = LHSL.getValueType();
2793  EVT CCT = getSetCCResultType(NVT);
2794 
2795  // Hi part is always the same op
2796  Hi = DAG.getNode(N->getOpcode(), DL, NVT, {LHSH, RHSH});
2797 
2798  // We need to know whether to select Lo part that corresponds to 'winning'
2799  // Hi part or if Hi parts are equal.
2800  SDValue IsHiLeft = DAG.getSetCC(DL, CCT, LHSH, RHSH, CondC);
2801  SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ);
2802 
2803  // Lo part corresponding to the 'winning' Hi part
2804  SDValue LoCmp = DAG.getSelect(DL, NVT, IsHiLeft, LHSL, RHSL);
2805 
2806  // Recursed Lo part if Hi parts are equal, this uses unsigned version
2807  SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL});
2808 
2809  Lo = DAG.getSelect(DL, NVT, IsHiEq, LoMinMax, LoCmp);
2810 }
2811 
2812 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
2813  SDValue &Lo, SDValue &Hi) {
2814  SDLoc dl(N);
2815  // Expand the subcomponents.
2816  SDValue LHSL, LHSH, RHSL, RHSH;
2817  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2818  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2819 
2820  EVT NVT = LHSL.getValueType();
2821  SDValue LoOps[2] = { LHSL, RHSL };
2822  SDValue HiOps[3] = { LHSH, RHSH };
2823 
2824  bool HasOpCarry = TLI.isOperationLegalOrCustom(
2825  N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
2826  TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2827  if (HasOpCarry) {
2828  SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
2829  if (N->getOpcode() == ISD::ADD) {
2830  Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2831  HiOps[2] = Lo.getValue(1);
2832  Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, HiOps);
2833  } else {
2834  Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2835  HiOps[2] = Lo.getValue(1);
2836  Hi = DAG.getNode(ISD::SUBCARRY, dl, VTList, HiOps);
2837  }
2838  return;
2839  }
2840 
2841  // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
2842  // them. TODO: Teach operation legalization how to expand unsupported
2843  // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
2844  // a carry of type MVT::Glue, but there doesn't seem to be any way to
2845  // generate a value of this type in the expanded code sequence.
2846  bool hasCarry =
2847  TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2848  ISD::ADDC : ISD::SUBC,
2849  TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2850 
2851  if (hasCarry) {
2852  SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
2853  if (N->getOpcode() == ISD::ADD) {
2854  Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2855  HiOps[2] = Lo.getValue(1);
2856  Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2857  } else {
2858  Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2859  HiOps[2] = Lo.getValue(1);
2860  Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2861  }
2862  return;
2863  }
2864 
2865  bool hasOVF =
2866  TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2868  TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2870 
2871  if (hasOVF) {
2872  EVT OvfVT = getSetCCResultType(NVT);
2873  SDVTList VTList = DAG.getVTList(NVT, OvfVT);
2874  int RevOpc;
2875  if (N->getOpcode() == ISD::ADD) {
2876  RevOpc = ISD::SUB;
2877  Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2878  Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2879  } else {
2880  RevOpc = ISD::ADD;
2881  Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2882  Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2883  }
2884  SDValue OVF = Lo.getValue(1);
2885 
2886  switch (BoolType) {
2888  OVF = DAG.getNode(ISD::AND, dl, OvfVT, DAG.getConstant(1, dl, OvfVT), OVF);
2891  OVF = DAG.getZExtOrTrunc(OVF, dl, NVT);
2892  Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
2893  break;
2895  OVF = DAG.getSExtOrTrunc(OVF, dl, NVT);
2896  Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
2897  }
2898  return;
2899  }
2900 
2901  if (N->getOpcode() == ISD::ADD) {
2902  Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
2903  Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2904  SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
2905  ISD::SETULT);
2906 
2908  SDValue Carry = DAG.getZExtOrTrunc(Cmp1, dl, NVT);
2909  Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry);
2910  return;
2911  }
2912 
2913  SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
2914  DAG.getConstant(1, dl, NVT),
2915  DAG.getConstant(0, dl, NVT));
2916  SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
2917  ISD::SETULT);
2918  SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
2919  DAG.getConstant(1, dl, NVT), Carry1);
2920  Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
2921  } else {
2922  Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
2923  Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2924  SDValue Cmp =
2925  DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
2926  LoOps[0], LoOps[1], ISD::SETULT);
2927 
2928  SDValue Borrow;
2930  Borrow = DAG.getZExtOrTrunc(Cmp, dl, NVT);
2931  else
2932  Borrow = DAG.getSelect(dl, NVT, Cmp, DAG.getConstant(1, dl, NVT),
2933  DAG.getConstant(0, dl, NVT));
2934 
2935  Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
2936  }
2937 }
2938 
2939 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
2940  SDValue &Lo, SDValue &Hi) {
2941  // Expand the subcomponents.
2942  SDValue LHSL, LHSH, RHSL, RHSH;
2943  SDLoc dl(N);
2944  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2945  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2946  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2947  SDValue LoOps[2] = { LHSL, RHSL };
2948  SDValue HiOps[3] = { LHSH, RHSH };
2949 
2950  if (N->getOpcode() == ISD::ADDC) {
2951  Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2952  HiOps[2] = Lo.getValue(1);
2953  Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2954  } else {
2955  Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2956  HiOps[2] = Lo.getValue(1);
2957  Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2958  }
2959 
2960  // Legalized the flag result - switch anything that used the old flag to
2961  // use the new one.
2962  ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2963 }
2964 
2965 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
2966  SDValue &Lo, SDValue &Hi) {
2967  // Expand the subcomponents.
2968  SDValue LHSL, LHSH, RHSL, RHSH;
2969  SDLoc dl(N);
2970  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2971  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2972  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2973  SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2974  SDValue HiOps[3] = { LHSH, RHSH };
2975 
2976  Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2977  HiOps[2] = Lo.getValue(1);
2978  Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2979 
2980  // Legalized the flag result - switch anything that used the old flag to
2981  // use the new one.
2982  ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2983 }
2984 
2985 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2986  SDValue &Lo, SDValue &Hi) {
2987  SDValue LHS = N->getOperand(0);
2988  SDValue RHS = N->getOperand(1);
2989  SDLoc dl(N);
2990 
2991  SDValue Ovf;
2992 
2993  unsigned CarryOp, NoCarryOp;
2995  switch(N->getOpcode()) {
2996  case ISD::UADDO:
2997  CarryOp = ISD::ADDCARRY;
2998  NoCarryOp = ISD::ADD;
2999  Cond = ISD::SETULT;
3000  break;
3001  case ISD::USUBO:
3002  CarryOp = ISD::SUBCARRY;
3003  NoCarryOp = ISD::SUB;
3004  Cond = ISD::SETUGT;
3005  break;
3006  default:
3007  llvm_unreachable("Node has unexpected Opcode");
3008  }
3009 
3010  bool HasCarryOp = TLI.isOperationLegalOrCustom(
3011  CarryOp, TLI.getTypeToExpandTo(*DAG.getContext(), LHS.getValueType()));
3012 
3013  if (HasCarryOp) {
3014  // Expand the subcomponents.
3015  SDValue LHSL, LHSH, RHSL, RHSH;
3016  GetExpandedInteger(LHS, LHSL, LHSH);
3017  GetExpandedInteger(RHS, RHSL, RHSH);
3018  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
3019  SDValue LoOps[2] = { LHSL, RHSL };
3020  SDValue HiOps[3] = { LHSH, RHSH };
3021 
3022  Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
3023  HiOps[2] = Lo.getValue(1);
3024  Hi = DAG.getNode(CarryOp, dl, VTList, HiOps);
3025 
3026  Ovf = Hi.getValue(1);
3027  } else {
3028  // Expand the result by simply replacing it with the equivalent
3029  // non-overflow-checking operation.
3030  SDValue Sum = DAG.getNode(NoCarryOp, dl, LHS.getValueType(), LHS, RHS);
3031  SplitInteger(Sum, Lo, Hi);
3032 
3033  // Calculate the overflow: addition overflows iff a + b < a, and subtraction
3034  // overflows iff a - b > a.
3035  Ovf = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, Cond);
3036  }
3037 
3038  // Legalized the flag result - switch anything that used the old flag to
3039  // use the new one.
3040  ReplaceValueWith(SDValue(N, 1), Ovf);
3041 }
3042 
3043 void DAGTypeLegalizer::ExpandIntRes_ADDSUBCARRY(SDNode *N,
3044  SDValue &Lo, SDValue &Hi) {
3045  // Expand the subcomponents.
3046  SDValue LHSL, LHSH, RHSL, RHSH;
3047  SDLoc dl(N);
3048  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
3049  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
3050  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
3051  SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
3052  SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
3053 
3054  Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
3055  HiOps[2] = Lo.getValue(1);
3056  Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
3057 
3058  // Legalized the flag result - switch anything that used the old flag to
3059  // use the new one.
3060  ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
3061 }
3062 
3063 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO_CARRY(SDNode *N,
3064  SDValue &Lo, SDValue &Hi) {
3065  // Expand the subcomponents.
3066  SDValue LHSL, LHSH, RHSL, RHSH;
3067  SDLoc dl(N);
3068  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
3069  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
3070  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
3071 
3072  // We need to use an unsigned carry op for the lo part.
3073  unsigned CarryOp = N->getOpcode() == ISD::SADDO_CARRY ? ISD::ADDCARRY
3074  : ISD::SUBCARRY;
3075  Lo = DAG.getNode(CarryOp, dl, VTList, { LHSL, RHSL, N->getOperand(2) });
3076  Hi = DAG.getNode(N->getOpcode(), dl, VTList, { LHSH, RHSH, Lo.getValue(1) });
3077 
3078  // Legalized the flag result - switch anything that used the old flag to
3079  // use the new one.
3080  ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
3081 }
3082 
3083 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
3084  SDValue &Lo, SDValue &Hi) {
3085  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3086  SDLoc dl(N);
3087  SDValue Op = N->getOperand(0);
3088  if (Op.getValueType().bitsLE(NVT)) {
3089  // The low part is any extension of the input (which degenerates to a copy).
3090  Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
3091  Hi = DAG.getUNDEF(NVT); // The high part is undefined.
3092  } else {
3093  // For example, extension of an i48 to an i64. The operand type necessarily
3094  // promotes to the result type, so will end up being expanded too.
3095  assert(getTypeAction(Op.getValueType()) ==
3097  "Only know how to promote this result!");
3098  SDValue Res = GetPromotedInteger(Op);
3099  assert(Res.getValueType() == N->getValueType(0) &&
3100  "Operand over promoted?");
3101  // Split the promoted operand. This will simplify when it is expanded.
3102  SplitInteger(Res, Lo, Hi);
3103  }
3104 }
3105 
3106 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
3107  SDValue &Lo, SDValue &Hi) {
3108  SDLoc dl(N);
3109  GetExpandedInteger(N->getOperand(0), Lo, Hi);
3110  EVT NVT = Lo.getValueType();
3111  EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3112  unsigned NVTBits = NVT.getSizeInBits();
3113  unsigned EVTBits = EVT.getSizeInBits();
3114 
3115  if (NVTBits < EVTBits) {
3116  Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
3118  EVTBits - NVTBits)));
3119  } else {
3120  Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
3121  // The high part replicates the sign bit of Lo, make it explicit.
3122  Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
3123  DAG.getConstant(NVTBits - 1, dl,
3124  TLI.getPointerTy(DAG.getDataLayout())));
3125  }
3126 }
3127 
3128 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
3129  SDValue &Lo, SDValue &Hi) {
3130  SDLoc dl(N);
3131  GetExpandedInteger(N->getOperand(0), Lo, Hi);
3132  EVT NVT = Lo.getValueType();
3133  EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3134  unsigned NVTBits = NVT.getSizeInBits();
3135  unsigned EVTBits = EVT.getSizeInBits();
3136 
3137  if (NVTBits < EVTBits) {
3138  Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
3140  EVTBits - NVTBits)));
3141  } else {
3142  Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
3143  // The high part must be zero, make it explicit.
3144  Hi = DAG.getConstant(0, dl, NVT);
3145  }
3146 }
3147 
3148 void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
3149  SDValue &Lo, SDValue &Hi) {
3150  SDLoc dl(N);
3151  GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
3152  Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
3153  Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
3154 }
3155 
3156 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
3157  SDValue &Lo, SDValue &Hi) {
3158  SDLoc dl(N);
3159  GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
3160  Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
3161  Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
3162 }
3163 
3164 void DAGTypeLegalizer::ExpandIntRes_PARITY(SDNode *N, SDValue &Lo,
3165  SDValue &Hi) {
3166  SDLoc dl(N);
3167  // parity(HiLo) -> parity(Lo^Hi)
3168  GetExpandedInteger(N->getOperand(0), Lo, Hi);
3169  EVT NVT = Lo.getValueType();
3170  Lo =
3171  DAG.getNode(ISD::PARITY, dl, NVT, DAG.getNode(ISD::XOR, dl, NVT, Lo, Hi));
3172  Hi = DAG.getConstant(0, dl, NVT);
3173 }
3174 
3175 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
3176  SDValue &Lo, SDValue &Hi) {
3177  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3178  unsigned NBitWidth = NVT.getSizeInBits();
3179  auto Constant = cast<ConstantSDNode>(N);
3180  const APInt &Cst = Constant->getAPIntValue();
3181  bool IsTarget = Constant->isTargetOpcode();
3182  bool IsOpaque = Constant->isOpaque();
3183  SDLoc dl(N);
3184  Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
3185  Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
3186  IsOpaque);
3187 }
3188 
3189 void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
3190  SDLoc dl(N);
3191 
3192  SDValue N0 = N->getOperand(0);
3193  GetExpandedInteger(N0, Lo, Hi);
3194  EVT NVT = Lo.getValueType();
3195 
3196  // If we have SUBCARRY, use the expanded form of the sra+xor+sub sequence we
3197  // use in LegalizeDAG. The SUB part of the expansion is based on
3198  // ExpandIntRes_ADDSUB which also uses SUBCARRY/USUBO after checking that
3199  // SUBCARRY is LegalOrCustom. Each of the pieces here can be further expanded
3200  // if needed. Shift expansion has a special case for filling with sign bits
3201  // so that we will only end up with one SRA.
3202  bool HasSubCarry = TLI.isOperationLegalOrCustom(
3203  ISD::SUBCARRY, TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
3204  if (HasSubCarry) {
3205  SDValue Sign = DAG.getNode(
3206  ISD::SRA, dl, NVT, Hi,
3207  DAG.getShiftAmountConstant(NVT.getSizeInBits() - 1, NVT, dl));
3208  SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
3209  Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Sign);
3210  Hi = DAG.getNode(ISD::XOR, dl, NVT, Hi, Sign);
3211  Lo = DAG.getNode(ISD::USUBO, dl, VTList, Lo, Sign);
3212  Hi = DAG.getNode(ISD::SUBCARRY, dl, VTList, Hi, Sign, Lo.getValue(1));
3213  return;
3214  }
3215 
3216  // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
3217  EVT VT = N->getValueType(0);
3218  SDValue Neg = DAG.getNode(ISD::SUB, dl, VT,
3219  DAG.getConstant(0, dl, VT), N0);
3220  SDValue NegLo, NegHi;
3221  SplitInteger(Neg, NegLo, NegHi);
3222 
3223  SDValue HiIsNeg = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
3224  DAG.getConstant(0, dl, NVT), ISD::SETLT);
3225  Lo = DAG.getSelect(dl, NVT, HiIsNeg, NegLo, Lo);
3226  Hi = DAG.getSelect(dl, NVT, HiIsNeg, NegHi, Hi);
3227 }
3228 
3229 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
3230  SDValue &Lo, SDValue &Hi) {
3231  SDLoc dl(N);
3232  // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
3233  GetExpandedInteger(N->getOperand(0), Lo, Hi);
3234  EVT NVT = Lo.getValueType();
3235 
3236  SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
3237  DAG.getConstant(0, dl, NVT), ISD::SETNE);
3238 
3239  SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
3240  SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
3241 
3242  Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
3243  DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
3244  DAG.getConstant(NVT.getSizeInBits(), dl,
3245  NVT)));
3246  Hi = DAG.getConstant(0, dl, NVT);
3247 }
3248 
3249 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
3250  SDValue &Lo, SDValue &Hi) {
3251  SDLoc dl(N);
3252  // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
3253  GetExpandedInteger(N->getOperand(0), Lo, Hi);
3254  EVT NVT = Lo.getValueType();
3255  Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
3256  DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
3257  Hi = DAG.getConstant(0, dl, NVT);
3258 }
3259 
3260 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
3261  SDValue &Lo, SDValue &Hi) {
3262  SDLoc dl(N);
3263  // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
3264  GetExpandedInteger(N->getOperand(0), Lo, Hi);
3265  EVT NVT = Lo.getValueType();
3266 
3267  SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
3268  DAG.getConstant(0, dl, NVT), ISD::SETNE);
3269 
3270  SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
3271  SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
3272 
3273  Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
3274  DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
3275  DAG.getConstant(NVT.getSizeInBits(), dl,
3276  NVT)));
3277  Hi = DAG.getConstant(0, dl, NVT);
3278 }
3279 
3280 void DAGTypeLegalizer::ExpandIntRes_FLT_ROUNDS(SDNode *N, SDValue &Lo,
3281  SDValue &Hi) {
3282  SDLoc dl(N);
3283  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3284  unsigned NBitWidth = NVT.getSizeInBits();
3285 
3286  Lo = DAG.getNode(ISD::FLT_ROUNDS_, dl, {NVT, MVT::Other}, N->getOperand(0));
3287  SDValue Chain = Lo.getValue(1);
3288  // The high part is the sign of Lo, as -1 is a valid value for FLT_ROUNDS
3289  Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
3290  DAG.getShiftAmountConstant(NBitWidth - 1, NVT, dl));
3291 
3292  // Legalize the chain result - switch anything that used the old chain to
3293  // use the new one.
3294  ReplaceValueWith(SDValue(N, 1), Chain);
3295 }
3296 
3297 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
3298  SDValue &Hi) {
3299  SDLoc dl(N);
3300  EVT VT = N->getValueType(0);
3301 
3302  bool IsStrict = N->isStrictFPOpcode();
3303  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
3304  SDValue Op = N->getOperand(IsStrict ? 1 : 0);
3305  if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
3306  Op = GetPromotedFloat(Op);
3307 
3308  if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
3309  EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
3310  Op = GetSoftPromotedHalf(Op);
3311  Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
3312  Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
3313  SplitInteger(Op, Lo, Hi);
3314  return;
3315  }
3316 
3317  RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
3318  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
3320  CallOptions.setSExt(true);
3321  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
3322  CallOptions, dl, Chain);
3323  SplitInteger(Tmp.first, Lo, Hi);
3324 
3325  if (IsStrict)
3326  ReplaceValueWith(SDValue(N, 1), Tmp.second);
3327 }
3328 
3329 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
3330  SDValue &Hi) {
3331  SDLoc dl(N);
3332  EVT VT = N->getValueType(0);
3333 
3334  bool IsStrict = N->isStrictFPOpcode();
3335  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
3336  SDValue Op = N->getOperand(IsStrict ? 1 : 0);
3337  if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
3338  Op = GetPromotedFloat(Op);
3339 
3340  if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
3341  EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
3342  Op = GetSoftPromotedHalf(Op);
3343  Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
3344  Op = DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op);
3345  SplitInteger(Op, Lo, Hi);
3346  return;
3347  }
3348 
3349  RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
3350  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
3352  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
3353  CallOptions, dl, Chain);
3354  SplitInteger(Tmp.first, Lo, Hi);
3355 
3356  if (IsStrict)
3357  ReplaceValueWith(SDValue(N, 1), Tmp.second);
3358 }
3359 
3360 void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo,
3361  SDValue &Hi) {
3362  SDValue Res = TLI.expandFP_TO_INT_SAT(N, DAG);
3363  SplitInteger(Res, Lo, Hi);
3364 }
3365 
3366 void DAGTypeLegalizer::ExpandIntRes_LLROUND_LLRINT(SDNode *N, SDValue &Lo,
3367  SDValue &Hi) {
3368  SDValue Op = N->getOperand(N->isStrictFPOpcode() ? 1 : 0);
3369 
3370  assert(getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat &&
3371  "Input type needs to be promoted!");
3372 
3373  EVT VT = Op.getValueType();
3374 
3375  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3376  if (N->getOpcode() == ISD::LLROUND ||
3377  N->getOpcode() == ISD::STRICT_LLROUND) {
3378  if (VT == MVT::f32)
3379  LC = RTLIB::LLROUND_F32;
3380  else if (VT == MVT::f64)
3381  LC = RTLIB::LLROUND_F64;
3382  else if (VT == MVT::f80)
3383  LC = RTLIB::LLROUND_F80;
3384  else if (VT == MVT::f128)
3385  LC = RTLIB::LLROUND_F128;
3386  else if (VT == MVT::ppcf128)
3387  LC = RTLIB::LLROUND_PPCF128;
3388  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!");
3389  } else if (N->getOpcode() == ISD::LLRINT ||
3390  N->getOpcode() == ISD::STRICT_LLRINT) {
3391  if (VT == MVT::f32)
3392  LC = RTLIB::LLRINT_F32;
3393  else if (VT == MVT::f64)
3394  LC = RTLIB::LLRINT_F64;
3395  else if (VT == MVT::f80)
3396  LC = RTLIB::LLRINT_F80;
3397  else if (VT == MVT::f128)
3398  LC = RTLIB::LLRINT_F128;
3399  else if (VT == MVT::ppcf128)
3400  LC = RTLIB::LLRINT_PPCF128;
3401  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!");
3402  } else
3403  llvm_unreachable("Unexpected opcode!");
3404 
3405  SDLoc dl(N);
3406  EVT RetVT = N->getValueType(0);
3407  SDValue Chain = N->isStrictFPOpcode() ? N->getOperand(0) : SDValue();
3408 
3410  CallOptions.setSExt(true);
3411  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
3412  Op, CallOptions, dl,
3413  Chain);
3414  SplitInteger(Tmp.first, Lo, Hi);
3415 
3416  if (N->isStrictFPOpcode())
3417  ReplaceValueWith(SDValue(N, 1), Tmp.second);
3418 }
3419 
3420 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
3421  SDValue &Lo, SDValue &Hi) {
3422  if (N->isAtomic()) {
3423  // It's typical to have larger CAS than atomic load instructions.
3424  SDLoc dl(N);
3425  EVT VT = N->getMemoryVT();
3426  SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
3427  SDValue Zero = DAG.getConstant(0, dl, VT);
3428  SDValue Swap = DAG.getAtomicCmpSwap(
3430  VT, VTs, N->getOperand(0),
3431  N->getOperand(1), Zero, Zero, N->getMemOperand());
3432  ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
3433  ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
3434  return;
3435  }
3436 
3437  if (ISD::isNormalLoad(N)) {
3438  ExpandRes_NormalLoad(N, Lo, Hi);
3439  return;
3440  }
3441 
3442  assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
3443 
3444  EVT VT = N->getValueType(0);
3445  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3446  SDValue Ch = N->getChain();
3447  SDValue Ptr = N->getBasePtr();
3448  ISD::LoadExtType ExtType = N->getExtensionType();
3449  MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
3450  AAMDNodes AAInfo = N->getAAInfo();
3451  SDLoc dl(N);
3452 
3453  assert(NVT.isByteSized() && "Expanded type not byte sized!");
3454 
3455  if (N->getMemoryVT().bitsLE(NVT)) {
3456  EVT MemVT = N->getMemoryVT();
3457 
3458  Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), MemVT,
3459  N->getOriginalAlign(), MMOFlags, AAInfo);
3460 
3461  // Remember the chain.
3462  Ch = Lo.getValue(1);
3463 
3464  if (ExtType == ISD::SEXTLOAD) {
3465  // The high part is obtained by SRA'ing all but one of the bits of the
3466  // lo part.
3467  unsigned LoSize = Lo.getValueSizeInBits();
3468  Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
3469  DAG.getConstant(LoSize - 1, dl,
3470  TLI.getPointerTy(DAG.getDataLayout())));
3471  } else if (ExtType == ISD::ZEXTLOAD) {
3472  // The high part is just a zero.
3473  Hi = DAG.getConstant(0, dl, NVT);
3474  } else {
3475  assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
3476  // The high part is undefined.
3477  Hi = DAG.getUNDEF(NVT);
3478  }
3479  } else if (DAG.getDataLayout().isLittleEndian()) {
3480  // Little-endian - low bits are at low addresses.
3481  Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
3482  N->getOriginalAlign(), MMOFlags, AAInfo);
3483 
3484  unsigned ExcessBits =
3485  N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
3486  EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
3487 
3488  // Increment the pointer to the other half.
3489  unsigned IncrementSize = NVT.getSizeInBits()/8;
3490  Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
3491  Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
3492  N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
3493  N->getOriginalAlign(), MMOFlags, AAInfo);
3494 
3495  // Build a factor node to remember that this load is independent of the
3496  // other one.
3497  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
3498  Hi.getValue(1));
3499  } else {
3500  // Big-endian - high bits are at low addresses. Favor aligned loads at
3501  // the cost of some bit-fiddling.
3502  EVT MemVT = N->getMemoryVT();
3503  unsigned EBytes = MemVT.getStoreSize();
3504  unsigned IncrementSize = NVT.getSizeInBits()/8;
3505  unsigned ExcessBits = (EBytes - IncrementSize)*8;
3506 
3507  // Load both the high bits and maybe some of the low bits.
3508  Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
3510  MemVT.getSizeInBits() - ExcessBits),
3511  N->getOriginalAlign(), MMOFlags, AAInfo);
3512 
3513  // Increment the pointer to the other half.
3514  Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
3515  // Load the rest of the low bits.
3516  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
3517  N->getPointerInfo().getWithOffset(IncrementSize),
3518  EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
3519  N->getOriginalAlign(), MMOFlags, AAInfo);
3520 
3521  // Build a factor node to remember that this load is independent of the
3522  // other one.
3523  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
3524  Hi.getValue(1));
3525 
3526  if (ExcessBits < NVT.getSizeInBits()) {
3527  // Transfer low bits from the bottom of Hi to the top of Lo.
3528  Lo = DAG.getNode(
3529  ISD::OR, dl, NVT, Lo,
3530  DAG.getNode(ISD::SHL, dl, NVT, Hi,
3531  DAG.getConstant(ExcessBits, dl,
3532  TLI.getPointerTy(DAG.getDataLayout()))));
3533  // Move high bits to the right position in Hi.
3534  Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
3535  Hi,
3536  DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
3537  TLI.getPointerTy(DAG.getDataLayout())));
3538  }
3539  }
3540 
3541  // Legalize the chain result - switch anything that used the old chain to
3542  // use the new one.
3543  ReplaceValueWith(SDValue(N, 1), Ch);
3544 }
3545 
3546 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
3547  SDValue &Lo, SDValue &Hi) {
3548  SDLoc dl(N);
3549  SDValue LL, LH, RL, RH;
3550  GetExpandedInteger(N->getOperand(0), LL, LH);
3551  GetExpandedInteger(N->getOperand(1), RL, RH);
3552  Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
3553  Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
3554 }
3555 
3556 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
3557  SDValue &Lo, SDValue &Hi) {
3558  EVT VT = N->getValueType(0);
3559  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3560  SDLoc dl(N);
3561 
3562  SDValue LL, LH, RL, RH;
3563  GetExpandedInteger(N->getOperand(0), LL, LH);
3564  GetExpandedInteger(N->getOperand(1), RL, RH);
3565 
3566  if (TLI.expandMUL(N, Lo, Hi, NVT, DAG,
3568  LL, LH, RL, RH))
3569  return;
3570 
3571  // If nothing else, we can make a libcall.
3572  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3573  if (VT == MVT::i16)
3574  LC = RTLIB::MUL_I16;
3575  else if (VT == MVT::i32)
3576  LC = RTLIB::MUL_I32;
3577  else if (VT == MVT::i64)
3578  LC = RTLIB::MUL_I64;
3579  else if (VT == MVT::i128)
3580  LC = RTLIB::MUL_I128;
3581 
3582  if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(LC)) {
3583  // We'll expand the multiplication by brute force because we have no other
3584  // options. This is a trivially-generalized version of the code from
3585  // Hacker's Delight (itself derived from Knuth's Algorithm M from section
3586  // 4.3.1).
3587  unsigned Bits = NVT.getSizeInBits();
3588  unsigned HalfBits = Bits >> 1;
3589  SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(Bits, HalfBits), dl,
3590  NVT);
3591  SDValue LLL = DAG.getNode(ISD::AND, dl, NVT, LL, Mask);
3592  SDValue RLL = DAG.getNode(ISD::AND, dl, NVT, RL, Mask);
3593 
3594  SDValue T = DAG.getNode(ISD::MUL, dl, NVT, LLL, RLL);
3595  SDValue TL = DAG.getNode(ISD::AND, dl, NVT, T, Mask);
3596 
3597  SDValue Shift = DAG.getShiftAmountConstant(HalfBits, NVT, dl);
3598  SDValue TH = DAG.getNode(ISD::SRL, dl, NVT, T, Shift);
3599  SDValue LLH = DAG.getNode(ISD::SRL, dl, NVT, LL, Shift);
3600  SDValue RLH = DAG.getNode(ISD::SRL, dl, NVT, RL, Shift);
3601 
3602  SDValue U = DAG.getNode(ISD::ADD, dl, NVT,
3603  DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TH);
3604  SDValue UL = DAG.getNode(ISD::AND, dl, NVT, U, Mask);
3605  SDValue UH = DAG.getNode(ISD::SRL, dl, NVT, U, Shift);
3606 
3607  SDValue V = DAG.getNode(ISD::ADD, dl, NVT,
3608  DAG.getNode(ISD::MUL, dl, NVT, LLL, RLH), UL);
3609  SDValue VH = DAG.getNode(ISD::SRL, dl, NVT, V, Shift);
3610 
3611  SDValue W = DAG.getNode(ISD::ADD, dl, NVT,
3612  DAG.getNode(ISD::MUL, dl, NVT, LLH, RLH),
3613  DAG.getNode(ISD::ADD, dl, NVT, UH, VH));
3614  Lo = DAG.getNode(ISD::ADD, dl, NVT, TL,
3615  DAG.getNode(ISD::SHL, dl, NVT, V, Shift));
3616 
3617  Hi = DAG.getNode(ISD::ADD, dl, NVT, W,
3618  DAG.getNode(ISD::ADD, dl, NVT,
3619  DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
3620  DAG.getNode(ISD::MUL, dl, NVT, RL, LH)));
3621  return;
3622  }
3623 
3624  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3626  CallOptions.setSExt(true);
3627  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first,
3628  Lo, Hi);
3629 }
3630 
3631 void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
3632  SDValue &Hi) {
3633  SDLoc DL(N);
3634  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3635  SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
3636  SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
3637  Lo = R.getValue(0);
3638  Hi = R.getValue(1);
3639  ReplaceValueWith(SDValue(N, 1), R.getValue(2));
3640 }
3641 
3642 void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
3643  SDValue &Hi) {
3644  SDValue Result = TLI.expandAddSubSat(N, DAG);
3645  SplitInteger(Result, Lo, Hi);
3646 }
3647 
3648 void DAGTypeLegalizer::ExpandIntRes_SHLSAT(SDNode *N, SDValue &Lo,
3649  SDValue &Hi) {
3650  SDValue Result = TLI.expandShlSat(N, DAG);
3651  SplitInteger(Result, Lo, Hi);
3652 }
3653 
3654 /// This performs an expansion of the integer result for a fixed point
3655 /// multiplication. The default expansion performs rounding down towards
3656 /// negative infinity, though targets that do care about rounding should specify
3657 /// a target hook for rounding and provide their own expansion or lowering of
3658 /// fixed point multiplication to be consistent with rounding.
3659 void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
3660  SDValue &Hi) {
3661  SDLoc dl(N);
3662  EVT VT = N->getValueType(0);
3663  unsigned VTSize = VT.getScalarSizeInBits();
3664  SDValue LHS = N->getOperand(0);
3665  SDValue RHS = N->getOperand(1);
3666  uint64_t Scale = N->getConstantOperandVal(2);
3667  bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
3668  N->getOpcode() == ISD::UMULFIXSAT);
3669  bool Signed = (N->getOpcode() == ISD::SMULFIX ||
3670  N->getOpcode() == ISD::SMULFIXSAT);
3671 
3672  // Handle special case when scale is equal to zero.
3673  if (!Scale) {
3674  SDValue Result;
3675  if (!Saturating) {
3676  Result = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3677  } else {
3678  EVT BoolVT = getSetCCResultType(VT);
3679  unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
3680  Result = DAG.getNode(MulOp, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
3681  SDValue Product = Result.getValue(0);
3682  SDValue Overflow = Result.getValue(1);
3683  if (Signed) {
3684  APInt MinVal = APInt::getSignedMinValue(VTSize);
3685  APInt MaxVal = APInt::getSignedMaxValue(VTSize);
3686  SDValue SatMin = DAG.getConstant(MinVal, dl, VT);
3687  SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
3688  SDValue Zero = DAG.getConstant(0, dl, VT);
3689  // Xor the inputs, if resulting sign bit is 0 the product will be
3690  // positive, else negative.
3691  SDValue Xor = DAG.getNode(ISD::XOR, dl, VT, LHS, RHS);
3692  SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Xor, Zero, ISD::SETLT);
3693  Result = DAG.getSelect(dl, VT, ProdNeg, SatMin, SatMax);
3694  Result = DAG.getSelect(dl, VT, Overflow, Result, Product);
3695  } else {
3696  // For unsigned multiplication, we only need to check the max since we
3697  // can't really overflow towards zero.
3698  APInt MaxVal = APInt::getMaxValue(VTSize);
3699  SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
3700  Result = DAG.getSelect(dl, VT, Overflow, SatMax, Product);
3701  }
3702  }
3703  SplitInteger(Result, Lo, Hi);
3704  return;
3705  }
3706 
3707  // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
3708  // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
3709  assert(Scale <= VTSize && "Scale can't be larger than the value type size.");
3710 
3711  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3712  SDValue LL, LH, RL, RH;
3713  GetExpandedInteger(LHS, LL, LH);
3714  GetExpandedInteger(RHS, RL, RH);
3716 
3717  unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
3718  if (!TLI.expandMUL_LOHI(LoHiOp, VT, dl, LHS, RHS, Result, NVT, DAG,
3720  LL, LH, RL, RH)) {
3721  report_fatal_error("Unable to expand MUL_FIX using MUL_LOHI.");
3722  return;
3723  }
3724 
3725  unsigned NVTSize = NVT.getScalarSizeInBits();
3726  assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "
3727  "the size of the current value type");
3728 
3729  // After getting the multiplication result in 4 parts, we need to perform a
3730  // shift right by the amount of the scale to get the result in that scale.
3731  //
3732  // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
3733  // 128 bits that are cut into 4 32-bit parts:
3734  //
3735  // HH HL LH LL
3736  // |---32---|---32---|---32---|---32---|
3737  // 128 96 64 32 0
3738  //
3739  // |------VTSize-----|
3740  //
3741  // |NVTSize-|
3742  //
3743  // The resulting Lo and Hi would normally be in LL and LH after the shift. But
3744  // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
3745  // amount and get Lo and Hi using two funnel shifts. Or for the special case
3746  // when Scale is a multiple of NVTSize we can just pick the result without
3747  // shifting.
3748  uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
3749  if (Scale % NVTSize) {
3750  SDValue ShiftAmount = DAG.getShiftAmountConstant(Scale % NVTSize, NVT, dl);
3751  Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0],
3752  ShiftAmount);
3753  Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1],
3754  ShiftAmount);
3755  } else {
3756  Lo = Result[Part0];
3757  Hi = Result[Part0 + 1];
3758  }
3759 
3760  // Unless saturation is requested we are done. The result is in <Hi,Lo>.
3761  if (!Saturating)
3762  return;
3763 
3764  // Can not overflow when there is no integer part.
3765  if (Scale == VTSize)
3766  return;
3767 
3768  // To handle saturation we must check for overflow in the multiplication.
3769  //
3770  // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
3771  // aren't all zeroes.
3772  //
3773  // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
3774  // aren't all ones or all zeroes.
3775  //
3776  // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
3777  // highest bit of HH determines saturation direction in the event of signed
3778  // saturation.
3779 
3780  SDValue ResultHL = Result[2];
3781  SDValue ResultHH = Result[3];
3782 
3783  SDValue SatMax, SatMin;
3784  SDValue NVTZero = DAG.getConstant(0, dl, NVT);
3785  SDValue NVTNeg1 = DAG.getConstant(-1, dl, NVT);
3786  EVT BoolNVT = getSetCCResultType(NVT);
3787 
3788  if (!Signed) {
3789  if (Scale < NVTSize) {
3790  // Overflow happened if ((HH | (HL >> Scale)) != 0).
3791  SDValue HLAdjusted =
3792  DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3793  DAG.getShiftAmountConstant(Scale, NVT, dl));
3794  SDValue Tmp = DAG.getNode(ISD::OR, dl, NVT, HLAdjusted, ResultHH);
3795  SatMax = DAG.getSetCC(dl, BoolNVT, Tmp, NVTZero, ISD::SETNE);
3796  } else if (Scale == NVTSize) {
3797  // Overflow happened if (HH != 0).
3798  SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETNE);
3799  } else if (Scale < VTSize) {
3800  // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
3801  SDValue HLAdjusted =
3802  DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3803  DAG.getShiftAmountConstant(Scale - NVTSize, NVT, dl));
3804  SatMax = DAG.getSetCC(dl, BoolNVT, HLAdjusted, NVTZero, ISD::SETNE);
3805  } else
3806  llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"
3807  "(and saturation can't happen with Scale==VTSize).");
3808 
3809  Hi = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Hi);
3810  Lo = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Lo);
3811  return;
3812  }
3813 
3814  if (Scale < NVTSize) {
3815  // The number of overflow bits we can check are VTSize - Scale + 1 (we
3816  // include the sign bit). If these top bits are > 0, then we overflowed past
3817  // the max value. If these top bits are < -1, then we overflowed past the
3818  // min value. Otherwise, we did not overflow.
3819  unsigned OverflowBits = VTSize - Scale + 1;
3820  assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&
3821  "Extent of overflow bits must start within HL");
3822  SDValue HLHiMask = DAG.getConstant(
3823  APInt::getHighBitsSet(NVTSize, OverflowBits - NVTSize), dl, NVT);
3824  SDValue HLLoMask = DAG.getConstant(
3825  APInt::getLowBitsSet(NVTSize, VTSize - OverflowBits), dl, NVT);
3826  // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
3827  SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3828  SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3829  SDValue HLUGT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLLoMask, ISD::SETUGT);
3830  SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3831  DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLUGT));
3832  // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
3833  SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3834  SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3835  SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT);
3836  SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3837  DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLULT));
3838  } else if (Scale == NVTSize) {
3839  // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
3840  SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3841  SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3842  SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT);
3843  SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3844  DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLNeg));
3845  // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
3846  SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3847  SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3848  SDValue HLPos = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETGE);
3849  SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3850  DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLPos));
3851  } else if (Scale < VTSize) {
3852  // This is similar to the case when we saturate if Scale < NVTSize, but we
3853  // only need to check HH.
3854  unsigned OverflowBits = VTSize - Scale + 1;
3855  SDValue HHHiMask = DAG.getConstant(
3856  APInt::getHighBitsSet(NVTSize, OverflowBits), dl, NVT);
3857  SDValue HHLoMask = DAG.getConstant(
3858  APInt::getLowBitsSet(NVTSize, NVTSize - OverflowBits), dl, NVT);
3859  SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, HHLoMask, ISD::SETGT);
3860  SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT);
3861  } else
3862  llvm_unreachable("Illegal scale for signed fixed point mul.");
3863 
3864  // Saturate to signed maximum.
3865  APInt MaxHi = APInt::getSignedMaxValue(NVTSize);
3866  APInt MaxLo = APInt::getAllOnes(NVTSize);
3867  Hi = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxHi, dl, NVT), Hi);
3868  Lo = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxLo, dl, NVT), Lo);
3869  // Saturate to signed minimum.
3870  APInt MinHi = APInt::getSignedMinValue(NVTSize);
3871  Hi = DAG.getSelect(dl, NVT, SatMin, DAG.getConstant(MinHi, dl, NVT), Hi);
3872  Lo = DAG.getSelect(dl, NVT, SatMin, NVTZero, Lo);
3873 }
3874 
3875 void DAGTypeLegalizer::ExpandIntRes_DIVFIX(SDNode *N, SDValue &Lo,
3876  SDValue &Hi) {
3877  SDLoc dl(N);
3878  // Try expanding in the existing type first.
3879  SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, N->getOperand(0),
3880  N->getOperand(1),
3881  N->getConstantOperandVal(2), DAG);
3882 
3883  if (!Res)
3884  Res = earlyExpandDIVFIX(N, N->getOperand(0), N->getOperand(1),
3885  N->getConstantOperandVal(2), TLI, DAG);
3886  SplitInteger(Res, Lo, Hi);
3887 }
3888 
3889 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
3890  SDValue &Lo, SDValue &Hi) {
3891  assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) &&
3892  "Node has unexpected Opcode");
3893  SDValue LHS = Node->getOperand(0);
3894  SDValue RHS = Node->getOperand(1);
3895  SDLoc dl(Node);
3896 
3897  SDValue Ovf;
3898 
3899  bool IsAdd = Node->getOpcode() == ISD::SADDO;
3900  unsigned CarryOp = IsAdd ? ISD::SADDO_CARRY : ISD::SSUBO_CARRY;
3901 
3902  bool HasCarryOp = TLI.isOperationLegalOrCustom(
3903  CarryOp, TLI.getTypeToExpandTo(*DAG.getContext(), LHS.getValueType()));
3904 
3905  if (HasCarryOp) {
3906  // Expand the subcomponents.
3907  SDValue LHSL, LHSH, RHSL, RHSH;
3908  GetExpandedInteger(LHS, LHSL, LHSH);
3909  GetExpandedInteger(RHS, RHSL, RHSH);
3910  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), Node->getValueType(1));
3911 
3912  Lo = DAG.getNode(IsAdd ? ISD::UADDO : ISD::USUBO, dl, VTList, {LHSL, RHSL});
3913  Hi = DAG.getNode(CarryOp, dl, VTList, { LHSH, RHSH, Lo.getValue(1) });
3914 
3915  Ovf = Hi.getValue(1);
3916  } else {
3917  // Expand the result by simply replacing it with the equivalent
3918  // non-overflow-checking operation.
3919  SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3920  ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3921  LHS, RHS);
3922  SplitInteger(Sum, Lo, Hi);
3923 
3924  // Compute the overflow.
3925  //
3926  // LHSSign -> LHS < 0
3927  // RHSSign -> RHS < 0
3928  // SumSign -> Sum < 0
3929  //
3930  // Add:
3931  // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3932  // Sub:
3933  // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3934  //
3935  // To get better codegen we can rewrite this by doing bitwise math on
3936  // the integers and extract the final sign bit at the end. So the
3937  // above becomes:
3938  //
3939  // Add:
3940  // Overflow -> (~(LHS ^ RHS) & (LHS ^ Sum)) < 0
3941  // Sub:
3942  // Overflow -> ((LHS ^ RHS) & (LHS ^ Sum)) < 0
3943  //
3944  // NOTE: This is different than the expansion we do in expandSADDSUBO
3945  // because it is more costly to determine the RHS is > 0 for SSUBO with the
3946  // integers split.
3947  EVT VT = LHS.getValueType();
3948  SDValue SignsMatch = DAG.getNode(ISD::XOR, dl, VT, LHS, RHS);
3949  if (IsAdd)
3950  SignsMatch = DAG.getNOT(dl, SignsMatch, VT);
3951 
3952  SDValue SumSignNE = DAG.getNode(ISD::XOR, dl, VT, LHS, Sum);
3953  Ovf = DAG.getNode(ISD::AND, dl, VT, SignsMatch, SumSignNE);
3954  EVT OType = Node->getValueType(1);
3955  Ovf = DAG.getSetCC(dl, OType, Ovf, DAG.getConstant(0, dl, VT), ISD::SETLT);
3956  }
3957 
3958  // Use the calculated overflow everywhere.
3959  ReplaceValueWith(SDValue(Node, 1), Ovf);
3960 }
3961 
3962 // Emit a call to __udivei4 and friends which require
3963 // the arguments be based on the stack
3964 // and extra argument that contains the number of bits of the operands.
3965 // Returns the result of the call operation.
3967  const RTLIB::Libcall &LC,
3968  SelectionDAG &DAG, SDNode *N,
3969  const SDLoc &DL, const EVT &VT) {
3970 
3971  SDValue InChain = DAG.getEntryNode();
3972 
3974  TargetLowering::ArgListEntry Entry;
3975 
3976  // The signature of __udivei4 is
3977  // void __udivei4(unsigned int *quo, unsigned int *a, unsigned int *b,
3978  // unsigned int bits)
3979  EVT ArgVT = N->op_begin()->getValueType();
3980  assert(ArgVT.isInteger() && ArgVT.getSizeInBits() > 128 &&
3981  "Unexpected argument type for lowering");
3982  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
3983 
3984  SDValue Output = DAG.CreateStackTemporary(ArgVT);
3985  Entry.Node = Output;
3986  Entry.Ty = ArgTy->getPointerTo();
3987  Entry.IsSExt = false;
3988  Entry.IsZExt = false;
3989  Args.push_back(Entry);
3990 
3991  for (const llvm::SDUse &Op : N->ops()) {
3992  SDValue StackPtr = DAG.CreateStackTemporary(ArgVT);
3993  InChain = DAG.getStore(InChain, DL, Op, StackPtr, MachinePointerInfo());
3994  Entry.Node = StackPtr;
3995  Entry.Ty = ArgTy->getPointerTo();
3996  Entry.IsSExt = false;
3997  Entry.IsZExt = false;
3998  Args.push_back(Entry);
3999  }
4000 
4001  int Bits = N->getOperand(0)
4002  .getValueType()
4003  .getTypeForEVT(*DAG.getContext())
4004  ->getIntegerBitWidth();
4005  Entry.Node = DAG.getConstant(Bits, DL, TLI.getPointerTy(DAG.getDataLayout()));
4006  Entry.Ty = Type::getInt32Ty(*DAG.getContext());
4007  Entry.IsSExt = false;
4008  Entry.IsZExt = true;
4009  Args.push_back(Entry);
4010 
4012  TLI.getPointerTy(DAG.getDataLayout()));
4013 
4015  CLI.setDebugLoc(DL)
4016  .setChain(InChain)
4019  .setDiscardResult();
4020 
4021  SDValue Chain = TLI.LowerCallTo(CLI).second;
4022 
4023  return DAG.getLoad(ArgVT, DL, Chain, Output, MachinePointerInfo());
4024 }
4025 
4026 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
4027  SDValue &Lo, SDValue &Hi) {
4028  EVT VT = N->getValueType(0);
4029  SDLoc dl(N);
4030  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
4031 
4033  SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
4034  SplitInteger(Res.getValue(0), Lo, Hi);
4035  return;
4036  }
4037 
4038  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4039  if (VT == MVT::i16)
4040  LC = RTLIB::SDIV_I16;
4041  else if (VT == MVT::i32)
4042  LC = RTLIB::SDIV_I32;
4043  else if (VT == MVT::i64)
4044  LC = RTLIB::SDIV_I64;
4045  else if (VT == MVT::i128)
4046  LC = RTLIB::SDIV_I128;
4047 
4048  else {
4049  SDValue Result =
4050  ExpandExtIntRes_DIVREM(TLI, RTLIB::SDIV_IEXT, DAG, N, dl, VT);
4051  SplitInteger(Result, Lo, Hi);
4052  return;
4053  }
4054 
4055  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
4056 
4058  CallOptions.setSExt(true);
4059  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
4060 }
4061 
4062 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
4063  SDValue &Lo, SDValue &Hi) {
4064  EVT VT = N->getValueType(0);
4065  SDLoc dl(N);
4066 
4067  // If we can emit an efficient shift operation, do so now. Check to see if
4068  // the RHS is a constant.
4069  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
4070  return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
4071 
4072  // If we can determine that the high bit of the shift is zero or one, even if
4073  // the low bits are variable, emit this shift in an optimized form.
4074  if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
4075  return;
4076 
4077  // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
4078  unsigned PartsOpc;
4079  if (N->getOpcode() == ISD::SHL) {
4080  PartsOpc = ISD::SHL_PARTS;
4081  } else if (N->getOpcode() == ISD::SRL) {
4082  PartsOpc = ISD::SRL_PARTS;
4083  } else {
4084  assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
4085  PartsOpc = ISD::SRA_PARTS;
4086  }
4087 
4088  // Next check to see if the target supports this SHL_PARTS operation or if it
4089  // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
4090  // size, but create a libcall instead.
4091  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
4092  TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
4093  const bool LegalOrCustom =
4094  (Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4095  Action == TargetLowering::Custom;
4096 
4097  if (LegalOrCustom && TLI.shouldExpandShift(DAG, N)) {
4098  // Expand the subcomponents.
4099  SDValue LHSL, LHSH;
4100  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
4101  EVT VT = LHSL.getValueType();
4102 
4103  // If the shift amount operand is coming from a vector legalization it may
4104  // have an illegal type. Fix that first by casting the operand, otherwise
4105  // the new SHL_PARTS operation would need further legalization.
4106  SDValue ShiftOp = N->getOperand(1);
4107  EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
4108  if (ShiftOp.getValueType() != ShiftTy)
4109  ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
4110 
4111  SDValue Ops[] = { LHSL, LHSH, ShiftOp };
4112  Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
4113  Hi = Lo.getValue(1);
4114  return;
4115  }
4116 
4117  // Otherwise, emit a libcall.
4118  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4119  bool isSigned;
4120  if (N->getOpcode() == ISD::SHL) {
4121  isSigned = false; /*sign irrelevant*/
4122  if (VT == MVT::i16)
4123  LC = RTLIB::SHL_I16;
4124  else if (VT == MVT::i32)
4125  LC = RTLIB::SHL_I32;
4126  else if (VT == MVT::i64)
4127  LC = RTLIB::SHL_I64;
4128  else if (VT == MVT::i128)
4129  LC = RTLIB::SHL_I128;
4130  } else if (N->getOpcode() == ISD::SRL) {
4131  isSigned = false;
4132  if (VT == MVT::i16)
4133  LC = RTLIB::SRL_I16;
4134  else if (VT == MVT::i32)
4135  LC = RTLIB::SRL_I32;
4136  else if (VT == MVT::i64)
4137  LC = RTLIB::SRL_I64;
4138  else if (VT == MVT::i128)
4139  LC = RTLIB::SRL_I128;
4140  } else {
4141  assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
4142  isSigned = true;
4143  if (VT == MVT::i16)
4144  LC = RTLIB::SRA_I16;
4145  else if (VT == MVT::i32)
4146  LC = RTLIB::SRA_I32;
4147  else if (VT == MVT::i64)
4148  LC = RTLIB::SRA_I64;
4149  else if (VT == MVT::i128)
4150  LC = RTLIB::SRA_I128;
4151  }
4152 
4153  if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
4154  EVT ShAmtTy =
4156  SDValue ShAmt = DAG.getZExtOrTrunc(N->getOperand(1), dl, ShAmtTy);
4157  SDValue Ops[2] = {N->getOperand(0), ShAmt};
4159  CallOptions.setSExt(isSigned);
4160  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
4161  return;
4162  }
4163 
4164  if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
4165  llvm_unreachable("Unsupported shift!");
4166 }
4167 
4168 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
4169  SDValue &Lo, SDValue &Hi) {
4170  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4171  SDLoc dl(N);
4172  SDValue Op = N->getOperand(0);
4173  if (Op.getValueType().bitsLE(NVT)) {
4174  // The low part is sign extension of the input (degenerates to a copy).
4175  Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
4176  // The high part is obtained by SRA'ing all but one of the bits of low part.
4177  unsigned LoSize = NVT.getSizeInBits();
4178  Hi = DAG.getNode(
4179  ISD::SRA, dl, NVT, Lo,
4180  DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
4181  } else {
4182  // For example, extension of an i48 to an i64. The operand type necessarily
4183  // promotes to the result type, so will end up being expanded too.
4184  assert(getTypeAction(Op.getValueType()) ==
4186  "Only know how to promote this result!");
4187  SDValue Res = GetPromotedInteger(Op);
4188  assert(Res.getValueType() == N->getValueType(0) &&
4189  "Operand over promoted?");
4190  // Split the promoted operand. This will simplify when it is expanded.
4191  SplitInteger(Res, Lo, Hi);
4192  unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
4193  Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
4195  ExcessBits)));
4196  }
4197 }
4198 
4199 void DAGTypeLegalizer::
4200 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
4201  SDLoc dl(N);
4202  GetExpandedInteger(N->getOperand(0), Lo, Hi);
4203  EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4204 
4205  if (EVT.bitsLE(Lo.getValueType())) {
4206  // sext_inreg the low part if needed.
4207  Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
4208  N->getOperand(1));
4209 
4210  // The high part gets the sign extension from the lo-part. This handles
4211  // things like sextinreg V:i64 from i8.
4212  Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
4213  DAG.getConstant(Hi.getValueSizeInBits() - 1, dl,
4214  TLI.getPointerTy(DAG.getDataLayout())));
4215  } else {
4216  // For example, extension of an i48 to an i64. Leave the low part alone,
4217  // sext_inreg the high part.
4218  unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
4219  Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
4221  ExcessBits)));
4222  }
4223 }
4224 
4225 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
4226  SDValue &Lo, SDValue &Hi) {
4227  EVT VT = N->getValueType(0);
4228  SDLoc dl(N);
4229  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
4230 
4232  SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
4233  SplitInteger(Res.getValue(1), Lo, Hi);
4234  return;
4235  }
4236 
4237  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4238  if (VT == MVT::i16)
4239  LC = RTLIB::SREM_I16;
4240  else if (VT == MVT::i32)
4241  LC = RTLIB::SREM_I32;
4242  else if (VT == MVT::i64)
4243  LC = RTLIB::SREM_I64;
4244  else if (VT == MVT::i128)
4245  LC = RTLIB::SREM_I128;
4246 
4247  else {
4248  SDValue Result =
4249  ExpandExtIntRes_DIVREM(TLI, RTLIB::SREM_IEXT, DAG, N, dl, VT);
4250  SplitInteger(Result, Lo, Hi);
4251  return;
4252  }
4253 
4254  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
4255 
4257  CallOptions.setSExt(true);
4258  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
4259 }
4260 
4261 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
4262  SDValue &Lo, SDValue &Hi) {
4263  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4264  SDLoc dl(N);
4265  Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
4266  Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
4267  N->getOperand(0),
4268  DAG.getConstant(NVT.getSizeInBits(), dl,
4269  TLI.getPointerTy(DAG.getDataLayout())));
4270  Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
4271 }
4272 
4273 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
4274