LLVM  14.0.0git
LegalizeIntegerTypes.cpp
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1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements integer type expansion and promotion for LegalizeTypes.
10 // Promotion is the act of changing a computation in an illegal type into a
11 // computation in a larger type. For example, implementing i8 arithmetic in an
12 // i32 register (often needed on powerpc).
13 // Expansion is the act of changing a computation in an illegal type into a
14 // computation in two identical registers of a smaller type. For example,
15 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16 // targets).
17 //
18 //===----------------------------------------------------------------------===//
19 
20 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/Support/KnownBits.h"
26 #include <algorithm>
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "legalize-types"
30 
31 //===----------------------------------------------------------------------===//
32 // Integer Result Promotion
33 //===----------------------------------------------------------------------===//
34 
35 /// PromoteIntegerResult - This method is called when a result of a node is
36 /// found to be in need of promotion to a larger type. At this point, the node
37 /// may also have invalid operands or may have other results that need
38 /// expansion, we just know that (at least) one result needs promotion.
39 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
40  LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG);
41  dbgs() << "\n");
42  SDValue Res = SDValue();
43 
44  // See if the target wants to custom expand this node.
45  if (CustomLowerNode(N, N->getValueType(ResNo), true)) {
46  LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n");
47  return;
48  }
49 
50  switch (N->getOpcode()) {
51  default:
52 #ifndef NDEBUG
53  dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
54  N->dump(&DAG); dbgs() << "\n";
55 #endif
56  llvm_unreachable("Do not know how to promote this operator!");
57  case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
58  case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
59  case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
60  case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
61  case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
62  case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
63  case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
64  case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
66  case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
67  case ISD::PARITY:
68  case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break;
70  case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
72  Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
73  case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
74  case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
75  break;
76  case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
77  break;
78  case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
79  case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
80  case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
81  case ISD::STRICT_FSETCC:
83  case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
84  case ISD::SMIN:
85  case ISD::SMAX:
86  Res = PromoteIntRes_SExtIntBinOp(N, /*IsVP*/ false);
87  break;
88  case ISD::UMIN:
89  case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break;
90 
91  case ISD::SHL:
92  Res = PromoteIntRes_SHL(N, /*IsVP*/ false);
93  break;
95  Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
96  case ISD::SRA:
97  Res = PromoteIntRes_SRA(N, /*IsVP*/ false);
98  break;
99  case ISD::SRL:
100  Res = PromoteIntRes_SRL(N, /*IsVP*/ false);
101  break;
102  case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
103  case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
104  case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
105  case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
106 
108  Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
110  Res = PromoteIntRes_INSERT_SUBVECTOR(N); break;
111  case ISD::VECTOR_REVERSE:
112  Res = PromoteIntRes_VECTOR_REVERSE(N); break;
113  case ISD::VECTOR_SHUFFLE:
114  Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
115  case ISD::VECTOR_SPLICE:
116  Res = PromoteIntRes_VECTOR_SPLICE(N); break;
118  Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
119  case ISD::BUILD_VECTOR:
120  Res = PromoteIntRes_BUILD_VECTOR(N); break;
122  Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
123  case ISD::SPLAT_VECTOR:
124  Res = PromoteIntRes_SPLAT_VECTOR(N); break;
125  case ISD::STEP_VECTOR: Res = PromoteIntRes_STEP_VECTOR(N); break;
126  case ISD::CONCAT_VECTORS:
127  Res = PromoteIntRes_CONCAT_VECTORS(N); break;
128 
132  Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
133 
134  case ISD::SIGN_EXTEND:
135  case ISD::ZERO_EXTEND:
136  case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
137 
140  case ISD::FP_TO_SINT:
141  case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
142 
143  case ISD::FP_TO_SINT_SAT:
144  case ISD::FP_TO_UINT_SAT:
145  Res = PromoteIntRes_FP_TO_XINT_SAT(N); break;
146 
147  case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
148 
149  case ISD::FLT_ROUNDS_: Res = PromoteIntRes_FLT_ROUNDS(N); break;
150 
151  case ISD::AND:
152  case ISD::OR:
153  case ISD::XOR:
154  case ISD::ADD:
155  case ISD::SUB:
156  case ISD::MUL:
157  Res = PromoteIntRes_SimpleIntBinOp(N, /*IsVP*/ false);
158  break;
159 
160  case ISD::SDIV:
161  case ISD::SREM:
162  Res = PromoteIntRes_SExtIntBinOp(N, /*IsVP*/ false);
163  break;
164 
165  case ISD::UDIV:
166  case ISD::UREM:
167  Res = PromoteIntRes_ZExtIntBinOp(N, /*IsVP*/ false);
168  break;
169 
170  case ISD::SADDO:
171  case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
172  case ISD::UADDO:
173  case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
174  case ISD::SMULO:
175  case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
176 
177  case ISD::ADDE:
178  case ISD::SUBE:
179  case ISD::ADDCARRY:
180  case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
181 
182  case ISD::SADDO_CARRY:
183  case ISD::SSUBO_CARRY: Res = PromoteIntRes_SADDSUBO_CARRY(N, ResNo); break;
184 
185  case ISD::SADDSAT:
186  case ISD::UADDSAT:
187  case ISD::SSUBSAT:
188  case ISD::USUBSAT:
189  case ISD::SSHLSAT:
190  case ISD::USHLSAT: Res = PromoteIntRes_ADDSUBSHLSAT(N); break;
191 
192  case ISD::SMULFIX:
193  case ISD::SMULFIXSAT:
194  case ISD::UMULFIX:
195  case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
196 
197  case ISD::SDIVFIX:
198  case ISD::SDIVFIXSAT:
199  case ISD::UDIVFIX:
200  case ISD::UDIVFIXSAT: Res = PromoteIntRes_DIVFIX(N); break;
201 
202  case ISD::ABS: Res = PromoteIntRes_ABS(N); break;
203 
204  case ISD::ATOMIC_LOAD:
205  Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
206 
211  case ISD::ATOMIC_LOAD_OR:
218  case ISD::ATOMIC_SWAP:
219  Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
220 
223  Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
224  break;
225 
226  case ISD::VECREDUCE_ADD:
227  case ISD::VECREDUCE_MUL:
228  case ISD::VECREDUCE_AND:
229  case ISD::VECREDUCE_OR:
230  case ISD::VECREDUCE_XOR:
231  case ISD::VECREDUCE_SMAX:
232  case ISD::VECREDUCE_SMIN:
233  case ISD::VECREDUCE_UMAX:
234  case ISD::VECREDUCE_UMIN:
235  Res = PromoteIntRes_VECREDUCE(N);
236  break;
237 
238  case ISD::VP_REDUCE_ADD:
239  case ISD::VP_REDUCE_MUL:
240  case ISD::VP_REDUCE_AND:
241  case ISD::VP_REDUCE_OR:
242  case ISD::VP_REDUCE_XOR:
243  case ISD::VP_REDUCE_SMAX:
244  case ISD::VP_REDUCE_SMIN:
245  case ISD::VP_REDUCE_UMAX:
246  case ISD::VP_REDUCE_UMIN:
247  Res = PromoteIntRes_VP_REDUCE(N);
248  break;
249 
250  case ISD::FREEZE:
251  Res = PromoteIntRes_FREEZE(N);
252  break;
253 
254  case ISD::ROTL:
255  case ISD::ROTR:
256  Res = PromoteIntRes_Rotate(N);
257  break;
258 
259  case ISD::FSHL:
260  case ISD::FSHR:
261  Res = PromoteIntRes_FunnelShift(N);
262  break;
263 
264  case ISD::VP_AND:
265  case ISD::VP_OR:
266  case ISD::VP_XOR:
267  case ISD::VP_ADD:
268  case ISD::VP_SUB:
269  case ISD::VP_MUL:
270  Res = PromoteIntRes_SimpleIntBinOp(N, /*IsVP*/ true);
271  break;
272  case ISD::VP_SDIV:
273  case ISD::VP_SREM:
274  Res = PromoteIntRes_SExtIntBinOp(N, /*IsVP*/ true);
275  break;
276  case ISD::VP_UDIV:
277  case ISD::VP_UREM:
278  Res = PromoteIntRes_ZExtIntBinOp(N, /*IsVP*/ true);
279  break;
280  case ISD::VP_SHL:
281  Res = PromoteIntRes_SHL(N, /*IsVP*/ true);
282  break;
283  case ISD::VP_ASHR:
284  Res = PromoteIntRes_SRA(N, /*IsVP*/ true);
285  break;
286  case ISD::VP_LSHR:
287  Res = PromoteIntRes_SRL(N, /*IsVP*/ true);
288  break;
289  }
290 
291  // If the result is null then the sub-method took care of registering it.
292  if (Res.getNode())
293  SetPromotedInteger(SDValue(N, ResNo), Res);
294 }
295 
296 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
297  unsigned ResNo) {
298  SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
299  return GetPromotedInteger(Op);
300 }
301 
302 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
303  // Sign-extend the new bits, and continue the assertion.
304  SDValue Op = SExtPromotedInteger(N->getOperand(0));
305  return DAG.getNode(ISD::AssertSext, SDLoc(N),
306  Op.getValueType(), Op, N->getOperand(1));
307 }
308 
309 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
310  // Zero the new bits, and continue the assertion.
311  SDValue Op = ZExtPromotedInteger(N->getOperand(0));
312  return DAG.getNode(ISD::AssertZext, SDLoc(N),
313  Op.getValueType(), Op, N->getOperand(1));
314 }
315 
316 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
317  EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
318  SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
319  N->getMemoryVT(), ResVT,
320  N->getChain(), N->getBasePtr(),
321  N->getMemOperand());
322  // Legalize the chain result - switch anything that used the old chain to
323  // use the new one.
324  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
325  return Res;
326 }
327 
328 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
329  SDValue Op2 = GetPromotedInteger(N->getOperand(2));
330  SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
331  N->getMemoryVT(),
332  N->getChain(), N->getBasePtr(),
333  Op2, N->getMemOperand());
334  // Legalize the chain result - switch anything that used the old chain to
335  // use the new one.
336  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
337  return Res;
338 }
339 
340 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
341  unsigned ResNo) {
342  if (ResNo == 1) {
343  assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
344  EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
345  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
346 
347  // Only use the result of getSetCCResultType if it is legal,
348  // otherwise just use the promoted result type (NVT).
349  if (!TLI.isTypeLegal(SVT))
350  SVT = NVT;
351 
352  SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
353  SDValue Res = DAG.getAtomicCmpSwap(
354  ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
355  N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
356  N->getMemOperand());
357  ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
358  ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
359  return Res.getValue(1);
360  }
361 
362  // Op2 is used for the comparison and thus must be extended according to the
363  // target's atomic operations. Op3 is merely stored and so can be left alone.
364  SDValue Op2 = N->getOperand(2);
365  SDValue Op3 = GetPromotedInteger(N->getOperand(3));
366  switch (TLI.getExtendForAtomicCmpSwapArg()) {
367  case ISD::SIGN_EXTEND:
368  Op2 = SExtPromotedInteger(Op2);
369  break;
370  case ISD::ZERO_EXTEND:
371  Op2 = ZExtPromotedInteger(Op2);
372  break;
373  case ISD::ANY_EXTEND:
374  Op2 = GetPromotedInteger(Op2);
375  break;
376  default:
377  llvm_unreachable("Invalid atomic op extension");
378  }
379 
380  SDVTList VTs =
381  DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
382  SDValue Res = DAG.getAtomicCmpSwap(
383  N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
384  N->getBasePtr(), Op2, Op3, N->getMemOperand());
385  // Update the use to N with the newly created Res.
386  for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
387  ReplaceValueWith(SDValue(N, i), Res.getValue(i));
388  return Res;
389 }
390 
391 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
392  SDValue InOp = N->getOperand(0);
393  EVT InVT = InOp.getValueType();
394  EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
395  EVT OutVT = N->getValueType(0);
396  EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
397  SDLoc dl(N);
398 
399  switch (getTypeAction(InVT)) {
401  break;
403  if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
404  // The input promotes to the same size. Convert the promoted value.
405  return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
406  break;
408  // Promote the integer operand by hand.
409  return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
411  // Promote the integer operand by hand.
412  return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftPromotedHalf(InOp));
414  // Convert the promoted float by hand.
415  if (!NOutVT.isVector())
416  return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp));
417  break;
418  }
421  break;
423  // Convert the element to an integer and promote it by hand.
424  if (!NOutVT.isVector())
425  return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
426  BitConvertToInteger(GetScalarizedVector(InOp)));
427  break;
429  report_fatal_error("Scalarization of scalable vectors is not supported.");
431  if (!NOutVT.isVector()) {
432  // For example, i32 = BITCAST v2i16 on alpha. Convert the split
433  // pieces of the input into integers and reassemble in the final type.
434  SDValue Lo, Hi;
435  GetSplitVector(N->getOperand(0), Lo, Hi);
436  Lo = BitConvertToInteger(Lo);
437  Hi = BitConvertToInteger(Hi);
438 
439  if (DAG.getDataLayout().isBigEndian())
440  std::swap(Lo, Hi);
441 
442  InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
444  NOutVT.getSizeInBits()),
445  JoinIntegers(Lo, Hi));
446  return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
447  }
448  break;
449  }
451  // The input is widened to the same size. Convert to the widened value.
452  // Make sure that the outgoing value is not a vector, because this would
453  // make us bitcast between two vectors which are legalized in different ways.
454  if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector()) {
455  SDValue Res =
456  DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
457 
458  // For big endian targets we need to shift the casted value or the
459  // interesting bits will end up at the wrong place.
460  if (DAG.getDataLayout().isBigEndian()) {
461  unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
462  EVT ShiftAmtTy = TLI.getShiftAmountTy(NOutVT, DAG.getDataLayout());
463  assert(ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!");
464  Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res,
465  DAG.getConstant(ShiftAmt, dl, ShiftAmtTy));
466  }
467  return Res;
468  }
469  // If the output type is also a vector and widening it to the same size
470  // as the widened input type would be a legal type, we can widen the bitcast
471  // and handle the promotion after.
472  if (NOutVT.isVector()) {
473  unsigned WidenInSize = NInVT.getSizeInBits();
474  unsigned OutSize = OutVT.getSizeInBits();
475  if (WidenInSize % OutSize == 0) {
476  unsigned Scale = WidenInSize / OutSize;
477  EVT WideOutVT = EVT::getVectorVT(*DAG.getContext(),
478  OutVT.getVectorElementType(),
479  OutVT.getVectorNumElements() * Scale);
480  if (isTypeLegal(WideOutVT)) {
481  InOp = DAG.getBitcast(WideOutVT, GetWidenedVector(InOp));
482  InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp,
483  DAG.getVectorIdxConstant(0, dl));
484  return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp);
485  }
486  }
487  }
488  }
489 
490  return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
491  CreateStackStoreLoad(InOp, OutVT));
492 }
493 
494 SDValue DAGTypeLegalizer::PromoteIntRes_FREEZE(SDNode *N) {
495  SDValue V = GetPromotedInteger(N->getOperand(0));
496  return DAG.getNode(ISD::FREEZE, SDLoc(N),
497  V.getValueType(), V);
498 }
499 
500 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
501  SDValue Op = GetPromotedInteger(N->getOperand(0));
502  EVT OVT = N->getValueType(0);
503  EVT NVT = Op.getValueType();
504  SDLoc dl(N);
505 
506  // If the larger BSWAP isn't supported by the target, try to expand now.
507  // If we expand later we'll end up with more operations since we lost the
508  // original type. We only do this for scalars since we have a shuffle
509  // based lowering for vectors in LegalizeVectorOps.
510  if (!OVT.isVector() &&
512  if (SDValue Res = TLI.expandBSWAP(N, DAG))
513  return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res);
514  }
515 
516  unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
517  EVT ShiftVT = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
518  return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
519  DAG.getConstant(DiffBits, dl, ShiftVT));
520 }
521 
522 SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
523  SDValue Op = GetPromotedInteger(N->getOperand(0));
524  EVT OVT = N->getValueType(0);
525  EVT NVT = Op.getValueType();
526  SDLoc dl(N);
527 
528  // If the larger BITREVERSE isn't supported by the target, try to expand now.
529  // If we expand later we'll end up with more operations since we lost the
530  // original type. We only do this for scalars since we have a shuffle
531  // based lowering for vectors in LegalizeVectorOps.
532  if (!OVT.isVector() && OVT.isSimple() &&
534  if (SDValue Res = TLI.expandBITREVERSE(N, DAG))
535  return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res);
536  }
537 
538  unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
539  EVT ShiftVT = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
540  return DAG.getNode(ISD::SRL, dl, NVT,
541  DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
542  DAG.getConstant(DiffBits, dl, ShiftVT));
543 }
544 
545 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
546  // The pair element type may be legal, or may not promote to the same type as
547  // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
548  return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
549  TLI.getTypeToTransformTo(*DAG.getContext(),
550  N->getValueType(0)), JoinIntegers(N->getOperand(0),
551  N->getOperand(1)));
552 }
553 
554 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
555  EVT VT = N->getValueType(0);
556  // FIXME there is no actual debug info here
557  SDLoc dl(N);
558  // Zero extend things like i1, sign extend everything else. It shouldn't
559  // matter in theory which one we pick, but this tends to give better code?
560  unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
561  SDValue Result = DAG.getNode(Opc, dl,
562  TLI.getTypeToTransformTo(*DAG.getContext(), VT),
563  SDValue(N, 0));
564  assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
565  return Result;
566 }
567 
568 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
569  EVT OVT = N->getValueType(0);
570  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
571  SDLoc dl(N);
572 
573  // If the larger CTLZ isn't supported by the target, try to expand now.
574  // If we expand later we'll end up with more operations since we lost the
575  // original type.
576  if (!OVT.isVector() && TLI.isTypeLegal(NVT) &&
579  if (SDValue Result = TLI.expandCTLZ(N, DAG)) {
580  Result = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Result);
581  return Result;
582  }
583  }
584 
585  // Zero extend to the promoted type and do the count there.
586  SDValue Op = ZExtPromotedInteger(N->getOperand(0));
587  Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
588  // Subtract off the extra leading bits in the bigger type.
589  return DAG.getNode(
590  ISD::SUB, dl, NVT, Op,
592  NVT));
593 }
594 
595 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
596  EVT OVT = N->getValueType(0);
597  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
598 
599  // If the larger CTPOP isn't supported by the target, try to expand now.
600  // If we expand later we'll end up with more operations since we lost the
601  // original type.
602  // TODO: Expand ISD::PARITY. Need to move ExpandPARITY from LegalizeDAG to
603  // TargetLowering.
604  if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() && TLI.isTypeLegal(NVT) &&
606  if (SDValue Result = TLI.expandCTPOP(N, DAG)) {
607  Result = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), NVT, Result);
608  return Result;
609  }
610  }
611 
612  // Zero extend to the promoted type and do the count or parity there.
613  SDValue Op = ZExtPromotedInteger(N->getOperand(0));
614  return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op);
615 }
616 
617 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
618  SDValue Op = GetPromotedInteger(N->getOperand(0));
619  EVT OVT = N->getValueType(0);
620  EVT NVT = Op.getValueType();
621  SDLoc dl(N);
622 
623  // If the larger CTTZ isn't supported by the target, try to expand now.
624  // If we expand later we'll end up with more operations since we lost the
625  // original type. Don't expand if we can use CTPOP or CTLZ expansion on the
626  // larger type.
627  if (!OVT.isVector() && TLI.isTypeLegal(NVT) &&
630  !TLI.isOperationLegal(ISD::CTPOP, NVT) &&
631  !TLI.isOperationLegal(ISD::CTLZ, NVT)) {
632  if (SDValue Result = TLI.expandCTTZ(N, DAG)) {
633  Result = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Result);
634  return Result;
635  }
636  }
637 
638  if (N->getOpcode() == ISD::CTTZ) {
639  // The count is the same in the promoted type except if the original
640  // value was zero. This can be handled by setting the bit just off
641  // the top of the original type.
642  auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
643  OVT.getScalarSizeInBits());
644  Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
645  }
646  return DAG.getNode(N->getOpcode(), dl, NVT, Op);
647 }
648 
649 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
650  SDLoc dl(N);
651  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
652 
653  SDValue Op0 = N->getOperand(0);
654  SDValue Op1 = N->getOperand(1);
655 
656  // If the input also needs to be promoted, do that first so we can get a
657  // get a good idea for the output type.
658  if (TLI.getTypeAction(*DAG.getContext(), Op0.getValueType())
660  SDValue In = GetPromotedInteger(Op0);
661 
662  // If the new type is larger than NVT, use it. We probably won't need to
663  // promote it again.
664  EVT SVT = In.getValueType().getScalarType();
665  if (SVT.bitsGE(NVT)) {
666  SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1);
667  return DAG.getAnyExtOrTrunc(Ext, dl, NVT);
668  }
669  }
670 
671  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1);
672 }
673 
674 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
675  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
676  unsigned NewOpc = N->getOpcode();
677  SDLoc dl(N);
678 
679  // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
680  // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
681  // and SINT conversions are Custom, there is no way to tell which is
682  // preferable. We choose SINT because that's the right thing on PPC.)
683  if (N->getOpcode() == ISD::FP_TO_UINT &&
684  !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
686  NewOpc = ISD::FP_TO_SINT;
687 
688  if (N->getOpcode() == ISD::STRICT_FP_TO_UINT &&
691  NewOpc = ISD::STRICT_FP_TO_SINT;
692 
693  SDValue Res;
694  if (N->isStrictFPOpcode()) {
695  Res = DAG.getNode(NewOpc, dl, {NVT, MVT::Other},
696  {N->getOperand(0), N->getOperand(1)});
697  // Legalize the chain result - switch anything that used the old chain to
698  // use the new one.
699  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
700  } else
701  Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
702 
703  // Assert that the converted value fits in the original type. If it doesn't
704  // (eg: because the value being converted is too big), then the result of the
705  // original operation was undefined anyway, so the assert is still correct.
706  //
707  // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
708  // before legalization: fp-to-uint16, 65534. -> 0xfffe
709  // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
710  return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT ||
711  N->getOpcode() == ISD::STRICT_FP_TO_UINT) ?
712  ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
713  DAG.getValueType(N->getValueType(0).getScalarType()));
714 }
715 
716 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT_SAT(SDNode *N) {
717  // Promote the result type, while keeping the original width in Op1.
718  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
719  SDLoc dl(N);
720  return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0),
721  N->getOperand(1));
722 }
723 
724 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
725  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
726  SDLoc dl(N);
727 
728  return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
729 }
730 
731 SDValue DAGTypeLegalizer::PromoteIntRes_FLT_ROUNDS(SDNode *N) {
732  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
733  SDLoc dl(N);
734 
735  SDValue Res =
736  DAG.getNode(N->getOpcode(), dl, {NVT, MVT::Other}, N->getOperand(0));
737 
738  // Legalize the chain result - switch anything that used the old chain to
739  // use the new one.
740  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
741  return Res;
742 }
743 
744 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
745  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
746  SDLoc dl(N);
747 
748  if (getTypeAction(N->getOperand(0).getValueType())
750  SDValue Res = GetPromotedInteger(N->getOperand(0));
751  assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
752 
753  // If the result and operand types are the same after promotion, simplify
754  // to an in-register extension.
755  if (NVT == Res.getValueType()) {
756  // The high bits are not guaranteed to be anything. Insert an extend.
757  if (N->getOpcode() == ISD::SIGN_EXTEND)
758  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
759  DAG.getValueType(N->getOperand(0).getValueType()));
760  if (N->getOpcode() == ISD::ZERO_EXTEND)
761  return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
762  assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
763  return Res;
764  }
765  }
766 
767  // Otherwise, just extend the original operand all the way to the larger type.
768  return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
769 }
770 
771 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
772  assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
773  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
774  ISD::LoadExtType ExtType =
775  ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
776  SDLoc dl(N);
777  SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
778  N->getMemoryVT(), N->getMemOperand());
779 
780  // Legalize the chain result - switch anything that used the old chain to
781  // use the new one.
782  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
783  return Res;
784 }
785 
786 SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
787  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
788  SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
789 
790  ISD::LoadExtType ExtType = N->getExtensionType();
791  if (ExtType == ISD::NON_EXTLOAD)
792  ExtType = ISD::EXTLOAD;
793 
794  SDLoc dl(N);
795  SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
796  N->getOffset(), N->getMask(), ExtPassThru,
797  N->getMemoryVT(), N->getMemOperand(),
798  N->getAddressingMode(), ExtType,
799  N->isExpandingLoad());
800  // Legalize the chain result - switch anything that used the old chain to
801  // use the new one.
802  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
803  return Res;
804 }
805 
806 SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
807  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
808  SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
809  assert(NVT == ExtPassThru.getValueType() &&
810  "Gather result type and the passThru argument type should be the same");
811 
812  ISD::LoadExtType ExtType = N->getExtensionType();
813  if (ExtType == ISD::NON_EXTLOAD)
814  ExtType = ISD::EXTLOAD;
815 
816  SDLoc dl(N);
817  SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
818  N->getIndex(), N->getScale() };
819  SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other),
820  N->getMemoryVT(), dl, Ops,
821  N->getMemOperand(), N->getIndexType(),
822  ExtType);
823  // Legalize the chain result - switch anything that used the old chain to
824  // use the new one.
825  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
826  return Res;
827 }
828 
829 /// Promote the overflow flag of an overflowing arithmetic node.
830 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
831  // Change the return type of the boolean result while obeying
832  // getSetCCResultType.
833  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
834  EVT VT = N->getValueType(0);
835  EVT SVT = getSetCCResultType(VT);
836  SDValue Ops[3] = { N->getOperand(0), N->getOperand(1) };
837  unsigned NumOps = N->getNumOperands();
838  assert(NumOps <= 3 && "Too many operands");
839  if (NumOps == 3)
840  Ops[2] = N->getOperand(2);
841 
842  SDLoc dl(N);
843  SDValue Res = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(VT, SVT),
844  makeArrayRef(Ops, NumOps));
845 
846  // Modified the sum result - switch anything that used the old sum to use
847  // the new one.
848  ReplaceValueWith(SDValue(N, 0), Res);
849 
850  // Convert to the expected type.
851  return DAG.getBoolExtOrTrunc(Res.getValue(1), dl, NVT, VT);
852 }
853 
854 SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
855  // If the promoted type is legal, we can convert this to:
856  // 1. ANY_EXTEND iN to iM
857  // 2. SHL by M-N
858  // 3. [US][ADD|SUB|SHL]SAT
859  // 4. L/ASHR by M-N
860  // Else it is more efficient to convert this to a min and a max
861  // operation in the higher precision arithmetic.
862  SDLoc dl(N);
863  SDValue Op1 = N->getOperand(0);
864  SDValue Op2 = N->getOperand(1);
865  unsigned OldBits = Op1.getScalarValueSizeInBits();
866 
867  unsigned Opcode = N->getOpcode();
868  bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
869 
870  SDValue Op1Promoted, Op2Promoted;
871  if (IsShift) {
872  Op1Promoted = GetPromotedInteger(Op1);
873  Op2Promoted = ZExtPromotedInteger(Op2);
874  } else if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) {
875  Op1Promoted = ZExtPromotedInteger(Op1);
876  Op2Promoted = ZExtPromotedInteger(Op2);
877  } else {
878  Op1Promoted = SExtPromotedInteger(Op1);
879  Op2Promoted = SExtPromotedInteger(Op2);
880  }
881  EVT PromotedType = Op1Promoted.getValueType();
882  unsigned NewBits = PromotedType.getScalarSizeInBits();
883 
884  if (Opcode == ISD::UADDSAT) {
885  APInt MaxVal = APInt::getAllOnes(OldBits).zext(NewBits);
886  SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
887  SDValue Add =
888  DAG.getNode(ISD::ADD, dl, PromotedType, Op1Promoted, Op2Promoted);
889  return DAG.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax);
890  }
891 
892  // USUBSAT can always be promoted as long as we have zero-extended the args.
893  if (Opcode == ISD::USUBSAT)
894  return DAG.getNode(ISD::USUBSAT, dl, PromotedType, Op1Promoted,
895  Op2Promoted);
896 
897  // Shift cannot use a min/max expansion, we can't detect overflow if all of
898  // the bits have been shifted out.
899  if (IsShift || TLI.isOperationLegal(Opcode, PromotedType)) {
900  unsigned ShiftOp;
901  switch (Opcode) {
902  case ISD::SADDSAT:
903  case ISD::SSUBSAT:
904  case ISD::SSHLSAT:
905  ShiftOp = ISD::SRA;
906  break;
907  case ISD::USHLSAT:
908  ShiftOp = ISD::SRL;
909  break;
910  default:
911  llvm_unreachable("Expected opcode to be signed or unsigned saturation "
912  "addition, subtraction or left shift");
913  }
914 
915  unsigned SHLAmount = NewBits - OldBits;
916  EVT SHVT = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
917  SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT);
918  Op1Promoted =
919  DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
920  if (!IsShift)
921  Op2Promoted =
922  DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
923 
924  SDValue Result =
925  DAG.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted);
926  return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
927  }
928 
929  unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
930  APInt MinVal = APInt::getSignedMinValue(OldBits).sext(NewBits);
931  APInt MaxVal = APInt::getSignedMaxValue(OldBits).sext(NewBits);
932  SDValue SatMin = DAG.getConstant(MinVal, dl, PromotedType);
933  SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
934  SDValue Result =
935  DAG.getNode(AddOp, dl, PromotedType, Op1Promoted, Op2Promoted);
936  Result = DAG.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
937  Result = DAG.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
938  return Result;
939 }
940 
941 SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
942  // Can just promote the operands then continue with operation.
943  SDLoc dl(N);
944  SDValue Op1Promoted, Op2Promoted;
945  bool Signed =
946  N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
947  bool Saturating =
948  N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
949  if (Signed) {
950  Op1Promoted = SExtPromotedInteger(N->getOperand(0));
951  Op2Promoted = SExtPromotedInteger(N->getOperand(1));
952  } else {
953  Op1Promoted = ZExtPromotedInteger(N->getOperand(0));
954  Op2Promoted = ZExtPromotedInteger(N->getOperand(1));
955  }
956  EVT OldType = N->getOperand(0).getValueType();
957  EVT PromotedType = Op1Promoted.getValueType();
958  unsigned DiffSize =
959  PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
960 
961  if (Saturating) {
962  // Promoting the operand and result values changes the saturation width,
963  // which is extends the values that we clamp to on saturation. This could be
964  // resolved by shifting one of the operands the same amount, which would
965  // also shift the result we compare against, then shifting back.
966  EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
967  Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
968  DAG.getConstant(DiffSize, dl, ShiftTy));
969  SDValue Result = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
970  Op2Promoted, N->getOperand(2));
971  unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
972  return DAG.getNode(ShiftOp, dl, PromotedType, Result,
973  DAG.getConstant(DiffSize, dl, ShiftTy));
974  }
975  return DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted, Op2Promoted,
976  N->getOperand(2));
977 }
978 
980  unsigned SatW, bool Signed,
981  const TargetLowering &TLI,
982  SelectionDAG &DAG) {
983  EVT VT = V.getValueType();
984  unsigned VTW = VT.getScalarSizeInBits();
985 
986  if (!Signed) {
987  // Saturate to the unsigned maximum by getting the minimum of V and the
988  // maximum.
989  return DAG.getNode(ISD::UMIN, dl, VT, V,
990  DAG.getConstant(APInt::getLowBitsSet(VTW, SatW),
991  dl, VT));
992  }
993 
994  // Saturate to the signed maximum (the low SatW - 1 bits) by taking the
995  // signed minimum of it and V.
996  V = DAG.getNode(ISD::SMIN, dl, VT, V,
997  DAG.getConstant(APInt::getLowBitsSet(VTW, SatW - 1),
998  dl, VT));
999  // Saturate to the signed minimum (the high SatW + 1 bits) by taking the
1000  // signed maximum of it and V.
1001  V = DAG.getNode(ISD::SMAX, dl, VT, V,
1002  DAG.getConstant(APInt::getHighBitsSet(VTW, VTW - SatW + 1),
1003  dl, VT));
1004  return V;
1005 }
1006 
1008  unsigned Scale, const TargetLowering &TLI,
1009  SelectionDAG &DAG, unsigned SatW = 0) {
1010  EVT VT = LHS.getValueType();
1011  unsigned VTSize = VT.getScalarSizeInBits();
1012  bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1013  N->getOpcode() == ISD::SDIVFIXSAT;
1014  bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1015  N->getOpcode() == ISD::UDIVFIXSAT;
1016 
1017  SDLoc dl(N);
1018  // Widen the types by a factor of two. This is guaranteed to expand, since it
1019  // will always have enough high bits in the LHS to shift into.
1020  EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VTSize * 2);
1021  if (VT.isVector())
1022  WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
1023  VT.getVectorElementCount());
1024  if (Signed) {
1025  LHS = DAG.getSExtOrTrunc(LHS, dl, WideVT);
1026  RHS = DAG.getSExtOrTrunc(RHS, dl, WideVT);
1027  } else {
1028  LHS = DAG.getZExtOrTrunc(LHS, dl, WideVT);
1029  RHS = DAG.getZExtOrTrunc(RHS, dl, WideVT);
1030  }
1031 
1032  SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, LHS, RHS, Scale,
1033  DAG);
1034  assert(Res && "Expanding DIVFIX with wide type failed?");
1035  if (Saturating) {
1036  // If the caller has told us to saturate at something less, use that width
1037  // instead of the type before doubling. However, it cannot be more than
1038  // what we just widened!
1039  assert(SatW <= VTSize &&
1040  "Tried to saturate to more than the original type?");
1041  Res = SaturateWidenedDIVFIX(Res, dl, SatW == 0 ? VTSize : SatW, Signed,
1042  TLI, DAG);
1043  }
1044  return DAG.getZExtOrTrunc(Res, dl, VT);
1045 }
1046 
1047 SDValue DAGTypeLegalizer::PromoteIntRes_DIVFIX(SDNode *N) {
1048  SDLoc dl(N);
1049  SDValue Op1Promoted, Op2Promoted;
1050  bool Signed = N->getOpcode() == ISD::SDIVFIX ||
1051  N->getOpcode() == ISD::SDIVFIXSAT;
1052  bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
1053  N->getOpcode() == ISD::UDIVFIXSAT;
1054  if (Signed) {
1055  Op1Promoted = SExtPromotedInteger(N->getOperand(0));
1056  Op2Promoted = SExtPromotedInteger(N->getOperand(1));
1057  } else {
1058  Op1Promoted = ZExtPromotedInteger(N->getOperand(0));
1059  Op2Promoted = ZExtPromotedInteger(N->getOperand(1));
1060  }
1061  EVT PromotedType = Op1Promoted.getValueType();
1062  unsigned Scale = N->getConstantOperandVal(2);
1063 
1064  // If the type is already legal and the operation is legal in that type, we
1065  // should not early expand.
1066  if (TLI.isTypeLegal(PromotedType)) {
1068  TLI.getFixedPointOperationAction(N->getOpcode(), PromotedType, Scale);
1069  if (Action == TargetLowering::Legal || Action == TargetLowering::Custom) {
1070  EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
1071  unsigned Diff = PromotedType.getScalarSizeInBits() -
1072  N->getValueType(0).getScalarSizeInBits();
1073  if (Saturating)
1074  Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
1075  DAG.getConstant(Diff, dl, ShiftTy));
1076  SDValue Res = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
1077  Op2Promoted, N->getOperand(2));
1078  if (Saturating)
1079  Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res,
1080  DAG.getConstant(Diff, dl, ShiftTy));
1081  return Res;
1082  }
1083  }
1084 
1085  // See if we can perform the division in this type without expanding.
1086  if (SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, Op1Promoted,
1087  Op2Promoted, Scale, DAG)) {
1088  if (Saturating)
1089  Res = SaturateWidenedDIVFIX(Res, dl,
1090  N->getValueType(0).getScalarSizeInBits(),
1091  Signed, TLI, DAG);
1092  return Res;
1093  }
1094  // If we cannot, expand it to twice the type width. If we are saturating, give
1095  // it the original width as a saturating width so we don't need to emit
1096  // two saturations.
1097  return earlyExpandDIVFIX(N, Op1Promoted, Op2Promoted, Scale, TLI, DAG,
1098  N->getValueType(0).getScalarSizeInBits());
1099 }
1100 
1101 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
1102  if (ResNo == 1)
1103  return PromoteIntRes_Overflow(N);
1104 
1105  // The operation overflowed iff the result in the larger type is not the
1106  // sign extension of its truncation to the original type.
1107  SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1108  SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1109  EVT OVT = N->getOperand(0).getValueType();
1110  EVT NVT = LHS.getValueType();
1111  SDLoc dl(N);
1112 
1113  // Do the arithmetic in the larger type.
1114  unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
1115  SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
1116 
1117  // Calculate the overflow flag: sign extend the arithmetic result from
1118  // the original type.
1119  SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
1120  DAG.getValueType(OVT));
1121  // Overflowed if and only if this is not equal to Res.
1122  Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
1123 
1124  // Use the calculated overflow everywhere.
1125  ReplaceValueWith(SDValue(N, 1), Ofl);
1126 
1127  return Res;
1128 }
1129 
1130 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
1131  SDValue LHS = GetPromotedInteger(N->getOperand(1));
1132  SDValue RHS = GetPromotedInteger(N->getOperand(2));
1133  return DAG.getSelect(SDLoc(N),
1134  LHS.getValueType(), N->getOperand(0), LHS, RHS);
1135 }
1136 
1137 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
1138  SDValue Mask = N->getOperand(0);
1139 
1140  SDValue LHS = GetPromotedInteger(N->getOperand(1));
1141  SDValue RHS = GetPromotedInteger(N->getOperand(2));
1142  return DAG.getNode(ISD::VSELECT, SDLoc(N),
1143  LHS.getValueType(), Mask, LHS, RHS);
1144 }
1145 
1146 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
1147  SDValue LHS = GetPromotedInteger(N->getOperand(2));
1148  SDValue RHS = GetPromotedInteger(N->getOperand(3));
1149  return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
1150  LHS.getValueType(), N->getOperand(0),
1151  N->getOperand(1), LHS, RHS, N->getOperand(4));
1152 }
1153 
1154 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
1155  unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
1156  EVT InVT = N->getOperand(OpNo).getValueType();
1157  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1158 
1159  EVT SVT = getSetCCResultType(InVT);
1160 
1161  // If we got back a type that needs to be promoted, this likely means the
1162  // the input type also needs to be promoted. So get the promoted type for
1163  // the input and try the query again.
1164  if (getTypeAction(SVT) == TargetLowering::TypePromoteInteger) {
1165  if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) {
1166  InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
1167  SVT = getSetCCResultType(InVT);
1168  } else {
1169  // Input type isn't promoted, just use the default promoted type.
1170  SVT = NVT;
1171  }
1172  }
1173 
1174  SDLoc dl(N);
1175  assert(SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() &&
1176  "Vector compare must return a vector result!");
1177 
1178  // Get the SETCC result using the canonical SETCC type.
1179  SDValue SetCC;
1180  if (N->isStrictFPOpcode()) {
1181  EVT VTs[] = {SVT, MVT::Other};
1182  SDValue Opers[] = {N->getOperand(0), N->getOperand(1),
1183  N->getOperand(2), N->getOperand(3)};
1184  SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers);
1185  // Legalize the chain result - switch anything that used the old chain to
1186  // use the new one.
1187  ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1));
1188  } else
1189  SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
1190  N->getOperand(1), N->getOperand(2));
1191 
1192  // Convert to the expected type.
1193  return DAG.getSExtOrTrunc(SetCC, dl, NVT);
1194 }
1195 
1196 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N, bool IsVP) {
1197  SDValue LHS = GetPromotedInteger(N->getOperand(0));
1198  SDValue RHS = N->getOperand(1);
1199  if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1200  RHS = ZExtPromotedInteger(RHS);
1201  if (!IsVP)
1202  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1203  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1204  N->getOperand(2), N->getOperand(3));
1205 }
1206 
1207 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
1208  SDValue Op = GetPromotedInteger(N->getOperand(0));
1209  return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
1210  Op.getValueType(), Op, N->getOperand(1));
1211 }
1212 
1213 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N, bool IsVP) {
1214  // The input may have strange things in the top bits of the registers, but
1215  // these operations don't care. They may have weird bits going out, but
1216  // that too is okay if they are integer operations.
1217  SDValue LHS = GetPromotedInteger(N->getOperand(0));
1218  SDValue RHS = GetPromotedInteger(N->getOperand(1));
1219  if (!IsVP)
1220  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1221  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1222  N->getOperand(2), N->getOperand(3));
1223 }
1224 
1225 SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N, bool IsVP) {
1226  // Sign extend the input.
1227  SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1228  SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1229  if (!IsVP)
1230  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1231  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1232  N->getOperand(2), N->getOperand(3));
1233 }
1234 
1235 SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N, bool IsVP) {
1236  // Zero extend the input.
1237  SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1238  SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1239  if (!IsVP)
1240  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1241  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1242  N->getOperand(2), N->getOperand(3));
1243 }
1244 
1245 SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
1246  // It doesn't matter if we sign extend or zero extend in the inputs. So do
1247  // whatever is best for the target.
1248  SDValue LHS = SExtOrZExtPromotedInteger(N->getOperand(0));
1249  SDValue RHS = SExtOrZExtPromotedInteger(N->getOperand(1));
1250  return DAG.getNode(N->getOpcode(), SDLoc(N),
1251  LHS.getValueType(), LHS, RHS);
1252 }
1253 
1254 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N, bool IsVP) {
1255  // The input value must be properly sign extended.
1256  SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1257  SDValue RHS = N->getOperand(1);
1258  if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1259  RHS = ZExtPromotedInteger(RHS);
1260  if (!IsVP)
1261  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1262  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1263  N->getOperand(2), N->getOperand(3));
1264 }
1265 
1266 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N, bool IsVP) {
1267  // The input value must be properly zero extended.
1268  SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1269  SDValue RHS = N->getOperand(1);
1270  if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1271  RHS = ZExtPromotedInteger(RHS);
1272  if (!IsVP)
1273  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
1274  return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
1275  N->getOperand(2), N->getOperand(3));
1276 }
1277 
1278 SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
1279  // Lower the rotate to shifts and ORs which can be promoted.
1280  SDValue Res;
1281  TLI.expandROT(N, true /*AllowVectorOps*/, Res, DAG);
1282  ReplaceValueWith(SDValue(N, 0), Res);
1283  return SDValue();
1284 }
1285 
1286 SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
1287  SDValue Hi = GetPromotedInteger(N->getOperand(0));
1288  SDValue Lo = GetPromotedInteger(N->getOperand(1));
1289  SDValue Amt = GetPromotedInteger(N->getOperand(2));
1290 
1291  SDLoc DL(N);
1292  EVT OldVT = N->getOperand(0).getValueType();
1293  EVT VT = Lo.getValueType();
1294  unsigned Opcode = N->getOpcode();
1295  bool IsFSHR = Opcode == ISD::FSHR;
1296  unsigned OldBits = OldVT.getScalarSizeInBits();
1297  unsigned NewBits = VT.getScalarSizeInBits();
1298 
1299  // Amount has to be interpreted modulo the old bit width.
1300  Amt = DAG.getNode(ISD::UREM, DL, VT, Amt, DAG.getConstant(OldBits, DL, VT));
1301 
1302  // If the promoted type is twice the size (or more), then we use the
1303  // traditional funnel 'double' shift codegen. This isn't necessary if the
1304  // shift amount is constant.
1305  // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1306  // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1307  if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Amt) &&
1308  !TLI.isOperationLegalOrCustom(Opcode, VT)) {
1309  SDValue HiShift = DAG.getConstant(OldBits, DL, VT);
1310  Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, HiShift);
1311  Lo = DAG.getZeroExtendInReg(Lo, DL, OldVT);
1312  SDValue Res = DAG.getNode(ISD::OR, DL, VT, Hi, Lo);
1313  Res = DAG.getNode(IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, Res, Amt);
1314  if (!IsFSHR)
1315  Res = DAG.getNode(ISD::SRL, DL, VT, Res, HiShift);
1316  return Res;
1317  }
1318 
1319  // Shift Lo up to occupy the upper bits of the promoted type.
1320  SDValue ShiftOffset = DAG.getConstant(NewBits - OldBits, DL, VT);
1321  Lo = DAG.getNode(ISD::SHL, DL, VT, Lo, ShiftOffset);
1322 
1323  // Increase Amount to shift the result into the lower bits of the promoted
1324  // type.
1325  if (IsFSHR)
1326  Amt = DAG.getNode(ISD::ADD, DL, VT, Amt, ShiftOffset);
1327 
1328  return DAG.getNode(Opcode, DL, VT, Hi, Lo, Amt);
1329 }
1330 
1331 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
1332  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1333  SDValue Res;
1334  SDValue InOp = N->getOperand(0);
1335  SDLoc dl(N);
1336 
1337  switch (getTypeAction(InOp.getValueType())) {
1338  default: llvm_unreachable("Unknown type action!");
1341  Res = InOp;
1342  break;
1344  Res = GetPromotedInteger(InOp);
1345  break;
1347  EVT InVT = InOp.getValueType();
1348  assert(InVT.isVector() && "Cannot split scalar types");
1349  ElementCount NumElts = InVT.getVectorElementCount();
1350  assert(NumElts == NVT.getVectorElementCount() &&
1351  "Dst and Src must have the same number of elements");
1352  assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&
1353  "Promoted vector type must be a power of two");
1354 
1355  SDValue EOp1, EOp2;
1356  GetSplitVector(InOp, EOp1, EOp2);
1357 
1358  EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
1359  NumElts.divideCoefficientBy(2));
1360  EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
1361  EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
1362 
1363  return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
1364  }
1366  SDValue WideInOp = GetWidenedVector(InOp);
1367 
1368  // Truncate widened InOp.
1369  unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
1370  EVT TruncVT = EVT::getVectorVT(*DAG.getContext(),
1371  N->getValueType(0).getScalarType(), NumElem);
1372  SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, WideInOp);
1373 
1374  // Zero extend so that the elements are of same type as those of NVT
1375  EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), NVT.getVectorElementType(),
1376  NumElem);
1377  SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc);
1378 
1379  // Extract the low NVT subvector.
1380  SDValue ZeroIdx = DAG.getVectorIdxConstant(0, dl);
1381  return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx);
1382  }
1383  }
1384 
1385  // Truncate to NVT instead of VT
1386  return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
1387 }
1388 
1389 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
1390  if (ResNo == 1)
1391  return PromoteIntRes_Overflow(N);
1392 
1393  // The operation overflowed iff the result in the larger type is not the
1394  // zero extension of its truncation to the original type.
1395  SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1396  SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1397  EVT OVT = N->getOperand(0).getValueType();
1398  EVT NVT = LHS.getValueType();
1399  SDLoc dl(N);
1400 
1401  // Do the arithmetic in the larger type.
1402  unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1403  SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
1404 
1405  // Calculate the overflow flag: zero extend the arithmetic result from
1406  // the original type.
1407  SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
1408  // Overflowed if and only if this is not equal to Res.
1409  Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
1410 
1411  // Use the calculated overflow everywhere.
1412  ReplaceValueWith(SDValue(N, 1), Ofl);
1413 
1414  return Res;
1415 }
1416 
1417 // Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
1418 // the third operand of ADDE/SUBE nodes is carry flag, which differs from
1419 // the ADDCARRY/SUBCARRY nodes in that the third operand is carry Boolean.
1420 SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
1421  if (ResNo == 1)
1422  return PromoteIntRes_Overflow(N);
1423 
1424  // We need to sign-extend the operands so the carry value computed by the
1425  // wide operation will be equivalent to the carry value computed by the
1426  // narrow operation.
1427  // An ADDCARRY can generate carry only if any of the operands has its
1428  // most significant bit set. Sign extension propagates the most significant
1429  // bit into the higher bits which means the extra bit that the narrow
1430  // addition would need (i.e. the carry) will be propagated through the higher
1431  // bits of the wide addition.
1432  // A SUBCARRY can generate borrow only if LHS < RHS and this property will be
1433  // preserved by sign extension.
1434  SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1435  SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1436 
1437  EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(1)};
1438 
1439  // Do the arithmetic in the wide type.
1440  SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), DAG.getVTList(ValueVTs),
1441  LHS, RHS, N->getOperand(2));
1442 
1443  // Update the users of the original carry/borrow value.
1444  ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
1445 
1446  return SDValue(Res.getNode(), 0);
1447 }
1448 
1449 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO_CARRY(SDNode *N,
1450  unsigned ResNo) {
1451  assert(ResNo == 1 && "Don't know how to promote other results yet.");
1452  return PromoteIntRes_Overflow(N);
1453 }
1454 
1455 SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
1456  SDValue Op0 = SExtPromotedInteger(N->getOperand(0));
1457  return DAG.getNode(ISD::ABS, SDLoc(N), Op0.getValueType(), Op0);
1458 }
1459 
1460 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
1461  // Promote the overflow bit trivially.
1462  if (ResNo == 1)
1463  return PromoteIntRes_Overflow(N);
1464 
1465  SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
1466  SDLoc DL(N);
1467  EVT SmallVT = LHS.getValueType();
1468 
1469  // To determine if the result overflowed in a larger type, we extend the
1470  // input to the larger type, do the multiply (checking if it overflows),
1471  // then also check the high bits of the result to see if overflow happened
1472  // there.
1473  if (N->getOpcode() == ISD::SMULO) {
1474  LHS = SExtPromotedInteger(LHS);
1475  RHS = SExtPromotedInteger(RHS);
1476  } else {
1477  LHS = ZExtPromotedInteger(LHS);
1478  RHS = ZExtPromotedInteger(RHS);
1479  }
1480  SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
1481  SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
1482 
1483  // Overflow occurred if it occurred in the larger type, or if the high part
1484  // of the result does not zero/sign-extend the low part. Check this second
1485  // possibility first.
1486  SDValue Overflow;
1487  if (N->getOpcode() == ISD::UMULO) {
1488  // Unsigned overflow occurred if the high part is non-zero.
1489  unsigned Shift = SmallVT.getScalarSizeInBits();
1490  EVT ShiftTy = TLI.getShiftAmountTy(Mul.getValueType(), DAG.getDataLayout());
1491  SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
1492  DAG.getConstant(Shift, DL, ShiftTy));
1493  Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
1494  DAG.getConstant(0, DL, Hi.getValueType()),
1495  ISD::SETNE);
1496  } else {
1497  // Signed overflow occurred if the high part does not sign extend the low.
1498  SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
1499  Mul, DAG.getValueType(SmallVT));
1500  Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
1501  }
1502 
1503  // The only other way for overflow to occur is if the multiplication in the
1504  // larger type itself overflowed.
1505  Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
1506  SDValue(Mul.getNode(), 1));
1507 
1508  // Use the calculated overflow everywhere.
1509  ReplaceValueWith(SDValue(N, 1), Overflow);
1510  return Mul;
1511 }
1512 
1513 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
1514  return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
1515  N->getValueType(0)));
1516 }
1517 
1518 SDValue DAGTypeLegalizer::PromoteIntRes_VSCALE(SDNode *N) {
1519  EVT VT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1520 
1521  APInt MulImm = cast<ConstantSDNode>(N->getOperand(0))->getAPIntValue();
1522  return DAG.getVScale(SDLoc(N), VT, MulImm.sextOrSelf(VT.getSizeInBits()));
1523 }
1524 
1525 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
1526  SDValue Chain = N->getOperand(0); // Get the chain.
1527  SDValue Ptr = N->getOperand(1); // Get the pointer.
1528  EVT VT = N->getValueType(0);
1529  SDLoc dl(N);
1530 
1531  MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
1532  unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
1533  // The argument is passed as NumRegs registers of type RegVT.
1534 
1535  SmallVector<SDValue, 8> Parts(NumRegs);
1536  for (unsigned i = 0; i < NumRegs; ++i) {
1537  Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
1538  N->getConstantOperandVal(3));
1539  Chain = Parts[i].getValue(1);
1540  }
1541 
1542  // Handle endianness of the load.
1543  if (DAG.getDataLayout().isBigEndian())
1544  std::reverse(Parts.begin(), Parts.end());
1545 
1546  // Assemble the parts in the promoted type.
1547  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1548  SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
1549  for (unsigned i = 1; i < NumRegs; ++i) {
1550  SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
1551  // Shift it to the right position and "or" it in.
1552  Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
1553  DAG.getConstant(i * RegVT.getSizeInBits(), dl,
1554  TLI.getPointerTy(DAG.getDataLayout())));
1555  Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
1556  }
1557 
1558  // Modified the chain result - switch anything that used the old chain to
1559  // use the new one.
1560  ReplaceValueWith(SDValue(N, 1), Chain);
1561 
1562  return Res;
1563 }
1564 
1565 //===----------------------------------------------------------------------===//
1566 // Integer Operand Promotion
1567 //===----------------------------------------------------------------------===//
1568 
1569 /// PromoteIntegerOperand - This method is called when the specified operand of
1570 /// the specified node is found to need promotion. At this point, all of the
1571 /// result types of the node are known to be legal, but other operands of the
1572 /// node may need promotion or expansion as well as the specified one.
1573 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
1574  LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG);
1575  dbgs() << "\n");
1576  SDValue Res = SDValue();
1577  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
1578  LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
1579  return false;
1580  }
1581 
1582  switch (N->getOpcode()) {
1583  default:
1584  #ifndef NDEBUG
1585  dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
1586  N->dump(&DAG); dbgs() << "\n";
1587  #endif
1588  llvm_unreachable("Do not know how to promote this operator's operand!");
1589 
1590  case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
1591  case ISD::ATOMIC_STORE:
1592  Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
1593  break;
1594  case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
1595  case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
1596  case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
1597  case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
1598  case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
1599  case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
1600  case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
1602  Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
1603  case ISD::SCALAR_TO_VECTOR:
1604  Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
1605  case ISD::SPLAT_VECTOR:
1606  Res = PromoteIntOp_SPLAT_VECTOR(N); break;
1607  case ISD::VSELECT:
1608  case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
1609  case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
1610  case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
1611  case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
1612  case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
1613  case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
1614  case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
1615  OpNo); break;
1616  case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
1617  OpNo); break;
1618  case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
1619  OpNo); break;
1620  case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
1621  OpNo); break;
1622  case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(cast<MaskedScatterSDNode>(N),
1623  OpNo); break;
1624  case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
1625  case ISD::FP16_TO_FP:
1626  case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
1627  case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
1628  case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
1629  case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
1630  case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break;
1631 
1632  case ISD::SHL:
1633  case ISD::SRA:
1634  case ISD::SRL:
1635  case ISD::ROTL:
1636  case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
1637 
1638  case ISD::SADDO_CARRY:
1639  case ISD::SSUBO_CARRY:
1640  case ISD::ADDCARRY:
1641  case ISD::SUBCARRY: Res = PromoteIntOp_ADDSUBCARRY(N, OpNo); break;
1642 
1643  case ISD::FRAMEADDR:
1644  case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
1645 
1646  case ISD::PREFETCH: Res = PromoteIntOp_PREFETCH(N, OpNo); break;
1647 
1648  case ISD::SMULFIX:
1649  case ISD::SMULFIXSAT:
1650  case ISD::UMULFIX:
1651  case ISD::UMULFIXSAT:
1652  case ISD::SDIVFIX:
1653  case ISD::SDIVFIXSAT:
1654  case ISD::UDIVFIX:
1655  case ISD::UDIVFIXSAT: Res = PromoteIntOp_FIX(N); break;
1656 
1657  case ISD::FPOWI: Res = PromoteIntOp_FPOWI(N); break;
1658 
1659  case ISD::VECREDUCE_ADD:
1660  case ISD::VECREDUCE_MUL:
1661  case ISD::VECREDUCE_AND:
1662  case ISD::VECREDUCE_OR:
1663  case ISD::VECREDUCE_XOR:
1664  case ISD::VECREDUCE_SMAX:
1665  case ISD::VECREDUCE_SMIN:
1666  case ISD::VECREDUCE_UMAX:
1667  case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
1668  case ISD::VP_REDUCE_ADD:
1669  case ISD::VP_REDUCE_MUL:
1670  case ISD::VP_REDUCE_AND:
1671  case ISD::VP_REDUCE_OR:
1672  case ISD::VP_REDUCE_XOR:
1673  case ISD::VP_REDUCE_SMAX:
1674  case ISD::VP_REDUCE_SMIN:
1675  case ISD::VP_REDUCE_UMAX:
1676  case ISD::VP_REDUCE_UMIN:
1677  Res = PromoteIntOp_VP_REDUCE(N, OpNo);
1678  break;
1679 
1680  case ISD::SET_ROUNDING: Res = PromoteIntOp_SET_ROUNDING(N); break;
1681  }
1682 
1683  // If the result is null, the sub-method took care of registering results etc.
1684  if (!Res.getNode()) return false;
1685 
1686  // If the result is N, the sub-method updated N in place. Tell the legalizer
1687  // core about this.
1688  if (Res.getNode() == N)
1689  return true;
1690 
1691  const bool IsStrictFp = N->isStrictFPOpcode();
1692  assert(Res.getValueType() == N->getValueType(0) &&
1693  N->getNumValues() == (IsStrictFp ? 2 : 1) &&
1694  "Invalid operand expansion");
1695  LLVM_DEBUG(dbgs() << "Replacing: "; N->dump(&DAG); dbgs() << " with: ";
1696  Res.dump());
1697 
1698  ReplaceValueWith(SDValue(N, 0), Res);
1699  if (IsStrictFp)
1700  ReplaceValueWith(SDValue(N, 1), SDValue(Res.getNode(), 1));
1701 
1702  return false;
1703 }
1704 
1705 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
1706 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
1707 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
1708  ISD::CondCode CCCode) {
1709  // We have to insert explicit sign or zero extends. Note that we could
1710  // insert sign extends for ALL conditions. For those operations where either
1711  // zero or sign extension would be valid, use SExtOrZExtPromotedInteger
1712  // which will choose the cheapest for the target.
1713  switch (CCCode) {
1714  default: llvm_unreachable("Unknown integer comparison!");
1715  case ISD::SETEQ:
1716  case ISD::SETNE: {
1717  SDValue OpL = GetPromotedInteger(NewLHS);
1718  SDValue OpR = GetPromotedInteger(NewRHS);
1719 
1720  // We would prefer to promote the comparison operand with sign extension.
1721  // If the width of OpL/OpR excluding the duplicated sign bits is no greater
1722  // than the width of NewLHS/NewRH, we can avoid inserting real truncate
1723  // instruction, which is redundant eventually.
1724  unsigned OpLEffectiveBits = DAG.ComputeMinSignedBits(OpL);
1725  unsigned OpREffectiveBits = DAG.ComputeMinSignedBits(OpR);
1726  if (OpLEffectiveBits <= NewLHS.getScalarValueSizeInBits() &&
1727  OpREffectiveBits <= NewRHS.getScalarValueSizeInBits()) {
1728  NewLHS = OpL;
1729  NewRHS = OpR;
1730  } else {
1731  NewLHS = SExtOrZExtPromotedInteger(NewLHS);
1732  NewRHS = SExtOrZExtPromotedInteger(NewRHS);
1733  }
1734  break;
1735  }
1736  case ISD::SETUGE:
1737  case ISD::SETUGT:
1738  case ISD::SETULE:
1739  case ISD::SETULT:
1740  NewLHS = SExtOrZExtPromotedInteger(NewLHS);
1741  NewRHS = SExtOrZExtPromotedInteger(NewRHS);
1742  break;
1743  case ISD::SETGE:
1744  case ISD::SETGT:
1745  case ISD::SETLT:
1746  case ISD::SETLE:
1747  NewLHS = SExtPromotedInteger(NewLHS);
1748  NewRHS = SExtPromotedInteger(NewRHS);
1749  break;
1750  }
1751 }
1752 
1753 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
1754  SDValue Op = GetPromotedInteger(N->getOperand(0));
1755  return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
1756 }
1757 
1758 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
1759  SDValue Op2 = GetPromotedInteger(N->getOperand(2));
1760  return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
1761  N->getChain(), N->getBasePtr(), Op2, N->getMemOperand());
1762 }
1763 
1764 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
1765  // This should only occur in unusual situations like bitcasting to an
1766  // x86_fp80, so just turn it into a store+load
1767  return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
1768 }
1769 
1770 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
1771  assert(OpNo == 2 && "Don't know how to promote this operand!");
1772 
1773  SDValue LHS = N->getOperand(2);
1774  SDValue RHS = N->getOperand(3);
1775  PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
1776 
1777  // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
1778  // legal types.
1779  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1780  N->getOperand(1), LHS, RHS, N->getOperand(4)),
1781  0);
1782 }
1783 
1784 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
1785  assert(OpNo == 1 && "only know how to promote condition");
1786 
1787  // Promote all the way up to the canonical SetCC type.
1788  SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
1789 
1790  // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1791  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1792  N->getOperand(2)), 0);
1793 }
1794 
1795 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1796  // Since the result type is legal, the operands must promote to it.
1797  EVT OVT = N->getOperand(0).getValueType();
1798  SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1799  SDValue Hi = GetPromotedInteger(N->getOperand(1));
1800  assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
1801  SDLoc dl(N);
1802 
1803  Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1804  DAG.getConstant(OVT.getSizeInBits(), dl,
1805  TLI.getPointerTy(DAG.getDataLayout())));
1806  return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1807 }
1808 
1809 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1810  // The vector type is legal but the element type is not. This implies
1811  // that the vector is a power-of-two in length and that the element
1812  // type does not have a strange size (eg: it is not i1).
1813  EVT VecVT = N->getValueType(0);
1814  unsigned NumElts = VecVT.getVectorNumElements();
1815  assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
1816  "Legal vector of one illegal element?");
1817 
1818  // Promote the inserted value. The type does not need to match the
1819  // vector element type. Check that any extra bits introduced will be
1820  // truncated away.
1821  assert(N->getOperand(0).getValueSizeInBits() >=
1822  N->getValueType(0).getScalarSizeInBits() &&
1823  "Type of inserted value narrower than vector element type!");
1824 
1825  SmallVector<SDValue, 16> NewOps;
1826  for (unsigned i = 0; i < NumElts; ++i)
1827  NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1828 
1829  return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1830 }
1831 
1832 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1833  unsigned OpNo) {
1834  if (OpNo == 1) {
1835  // Promote the inserted value. This is valid because the type does not
1836  // have to match the vector element type.
1837 
1838  // Check that any extra bits introduced will be truncated away.
1839  assert(N->getOperand(1).getValueSizeInBits() >=
1840  N->getValueType(0).getScalarSizeInBits() &&
1841  "Type of inserted value narrower than vector element type!");
1842  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1843  GetPromotedInteger(N->getOperand(1)),
1844  N->getOperand(2)),
1845  0);
1846  }
1847 
1848  assert(OpNo == 2 && "Different operand and result vector types?");
1849 
1850  // Promote the index.
1851  SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1852  TLI.getVectorIdxTy(DAG.getDataLayout()));
1853  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1854  N->getOperand(1), Idx), 0);
1855 }
1856 
1857 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1858  // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1859  // the operand in place.
1860  return SDValue(DAG.UpdateNodeOperands(N,
1861  GetPromotedInteger(N->getOperand(0))), 0);
1862 }
1863 
1864 SDValue DAGTypeLegalizer::PromoteIntOp_SPLAT_VECTOR(SDNode *N) {
1865  // Integer SPLAT_VECTOR operands are implicitly truncated, so just promote the
1866  // operand in place.
1867  return SDValue(
1868  DAG.UpdateNodeOperands(N, GetPromotedInteger(N->getOperand(0))), 0);
1869 }
1870 
1871 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1872  assert(OpNo == 0 && "Only know how to promote the condition!");
1873  SDValue Cond = N->getOperand(0);
1874  EVT OpTy = N->getOperand(1).getValueType();
1875 
1876  if (N->getOpcode() == ISD::VSELECT)
1877  if (SDValue Res = WidenVSELECTMask(N))
1878  return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
1879  Res, N->getOperand(1), N->getOperand(2));
1880 
1881  // Promote all the way up to the canonical SetCC type.
1882  EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1883  Cond = PromoteTargetBoolean(Cond, OpVT);
1884 
1885  return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1886  N->getOperand(2)), 0);
1887 }
1888 
1889 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1890  assert(OpNo == 0 && "Don't know how to promote this operand!");
1891 
1892  SDValue LHS = N->getOperand(0);
1893  SDValue RHS = N->getOperand(1);
1894  PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1895 
1896  // The CC (#4) and the possible return values (#2 and #3) have legal types.
1897  return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1898  N->getOperand(3), N->getOperand(4)), 0);
1899 }
1900 
1901 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1902  assert(OpNo == 0 && "Don't know how to promote this operand!");
1903 
1904  SDValue LHS = N->getOperand(0);
1905  SDValue RHS = N->getOperand(1);
1906  PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1907 
1908  // The CC (#2) is always legal.
1909  return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1910 }
1911 
1912 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1913  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1914  ZExtPromotedInteger(N->getOperand(1))), 0);
1915 }
1916 
1917 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1918  SDValue Op = GetPromotedInteger(N->getOperand(0));
1919  SDLoc dl(N);
1920  Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1921  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1922  Op, DAG.getValueType(N->getOperand(0).getValueType()));
1923 }
1924 
1925 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1926  return SDValue(DAG.UpdateNodeOperands(N,
1927  SExtPromotedInteger(N->getOperand(0))), 0);
1928 }
1929 
1930 SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N) {
1931  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1932  SExtPromotedInteger(N->getOperand(1))), 0);
1933 }
1934 
1935 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1936  assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1937  SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1938  SDLoc dl(N);
1939 
1940  SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1941 
1942  // Truncate the value and store the result.
1943  return DAG.getTruncStore(Ch, dl, Val, Ptr,
1944  N->getMemoryVT(), N->getMemOperand());
1945 }
1946 
1947 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
1948  unsigned OpNo) {
1949  SDValue DataOp = N->getValue();
1950  SDValue Mask = N->getMask();
1951 
1952  if (OpNo == 4) {
1953  // The Mask. Update in place.
1954  EVT DataVT = DataOp.getValueType();
1955  Mask = PromoteTargetBoolean(Mask, DataVT);
1956  SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1957  NewOps[4] = Mask;
1958  return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1959  }
1960 
1961  assert(OpNo == 1 && "Unexpected operand for promotion");
1962  DataOp = GetPromotedInteger(DataOp);
1963 
1964  return DAG.getMaskedStore(N->getChain(), SDLoc(N), DataOp, N->getBasePtr(),
1965  N->getOffset(), Mask, N->getMemoryVT(),
1966  N->getMemOperand(), N->getAddressingMode(),
1967  /*IsTruncating*/ true, N->isCompressingStore());
1968 }
1969 
1970 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
1971  unsigned OpNo) {
1972  assert(OpNo == 3 && "Only know how to promote the mask!");
1973  EVT DataVT = N->getValueType(0);
1974  SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1975  SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1976  NewOps[OpNo] = Mask;
1977  SDNode *Res = DAG.UpdateNodeOperands(N, NewOps);
1978  if (Res == N)
1979  return SDValue(Res, 0);
1980 
1981  // Update triggered CSE, do our own replacement since caller can't.
1982  ReplaceValueWith(SDValue(N, 0), SDValue(Res, 0));
1983  ReplaceValueWith(SDValue(N, 1), SDValue(Res, 1));
1984  return SDValue();
1985 }
1986 
1987 SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
1988  unsigned OpNo) {
1989 
1990  SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1991  if (OpNo == 2) {
1992  // The Mask
1993  EVT DataVT = N->getValueType(0);
1994  NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1995  } else if (OpNo == 4) {
1996  // The Index
1997  if (N->isIndexSigned())
1998  // Need to sign extend the index since the bits will likely be used.
1999  NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
2000  else
2001  NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
2002  } else
2003  NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
2004 
2005  SDNode *Res = DAG.UpdateNodeOperands(N, NewOps);
2006  if (Res == N)
2007  return SDValue(Res, 0);
2008 
2009  // Update triggered CSE, do our own replacement since caller can't.
2010  ReplaceValueWith(SDValue(N, 0), SDValue(Res, 0));
2011  ReplaceValueWith(SDValue(N, 1), SDValue(Res, 1));
2012  return SDValue();
2013 }
2014 
2015 SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
2016  unsigned OpNo) {
2017  bool TruncateStore = N->isTruncatingStore();
2018  SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
2019  if (OpNo == 2) {
2020  // The Mask
2021  EVT DataVT = N->getValue().getValueType();
2022  NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
2023  } else if (OpNo == 4) {
2024  // The Index
2025  if (N->isIndexSigned())
2026  // Need to sign extend the index since the bits will likely be used.
2027  NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
2028  else
2029  NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
2030 
2031  N->setIndexType(TLI.getCanonicalIndexType(N->getIndexType(),
2032  N->getMemoryVT(), NewOps[OpNo]));
2033  } else {
2034  NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
2035  TruncateStore = true;
2036  }
2037 
2038  return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), N->getMemoryVT(),
2039  SDLoc(N), NewOps, N->getMemOperand(),
2040  N->getIndexType(), TruncateStore);
2041 }
2042 
2043 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
2044  SDValue Op = GetPromotedInteger(N->getOperand(0));
2045  return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
2046 }
2047 
2048 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
2049  return SDValue(DAG.UpdateNodeOperands(N,
2050  ZExtPromotedInteger(N->getOperand(0))), 0);
2051 }
2052 
2053 SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N) {
2054  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2055  ZExtPromotedInteger(N->getOperand(1))), 0);
2056 }
2057 
2058 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
2059  SDLoc dl(N);
2060  SDValue Op = GetPromotedInteger(N->getOperand(0));
2061  Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
2062  return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
2063 }
2064 
2065 SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo) {
2066  assert(OpNo == 2 && "Don't know how to promote this operand!");
2067 
2068  SDValue LHS = N->getOperand(0);
2069  SDValue RHS = N->getOperand(1);
2070  SDValue Carry = N->getOperand(2);
2071  SDLoc DL(N);
2072 
2073  Carry = PromoteTargetBoolean(Carry, LHS.getValueType());
2074 
2075  return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, Carry), 0);
2076 }
2077 
2078 SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
2079  SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
2080  return SDValue(
2081  DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), Op2), 0);
2082 }
2083 
2084 SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
2085  // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
2086  SDValue Op = ZExtPromotedInteger(N->getOperand(0));
2087  return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
2088 }
2089 
2090 SDValue DAGTypeLegalizer::PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo) {
2091  assert(OpNo > 1 && "Don't know how to promote this operand!");
2092  // Promote the rw, locality, and cache type arguments to a supported integer
2093  // width.
2094  SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
2095  SDValue Op3 = ZExtPromotedInteger(N->getOperand(3));
2096  SDValue Op4 = ZExtPromotedInteger(N->getOperand(4));
2097  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
2098  Op2, Op3, Op4),
2099  0);
2100 }
2101 
2102 SDValue DAGTypeLegalizer::PromoteIntOp_FPOWI(SDNode *N) {
2103  // FIXME: Support for promotion of STRICT_FPOWI is not implemented yet.
2104  assert(N->getOpcode() == ISD::FPOWI && "No STRICT_FPOWI support here yet.");
2105 
2106  // The integer operand is the last operand in FPOWI (so the result and
2107  // floating point operand is already type legalized).
2108 
2109  // We can't just promote the exponent type in FPOWI, since we want to lower
2110  // the node to a libcall and we if we promote to a type larger than
2111  // sizeof(int) the libcall might not be according to the targets ABI. Instead
2112  // we rewrite to a libcall here directly, letting makeLibCall handle promotion
2113  // if the target accepts it according to shouldSignExtendTypeInLibCall.
2114  RTLIB::Libcall LC = RTLIB::getPOWI(N->getValueType(0));
2115  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fpowi.");
2116  if (!TLI.getLibcallName(LC)) {
2117  // Some targets don't have a powi libcall; use pow instead.
2118  // FIXME: Implement this if some target needs it.
2119  DAG.getContext()->emitError("Don't know how to promote fpowi to fpow");
2120  return DAG.getUNDEF(N->getValueType(0));
2121  }
2122  // The exponent should fit in a sizeof(int) type for the libcall to be valid.
2123  assert(DAG.getLibInfo().getIntSize() ==
2124  N->getOperand(1).getValueType().getSizeInBits() &&
2125  "POWI exponent should match with sizeof(int) when doing the libcall.");
2127  CallOptions.setSExt(true);
2128  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2129  std::pair<SDValue, SDValue> Tmp =
2130  TLI.makeLibCall(DAG, LC, N->getValueType(0), Ops,
2131  CallOptions, SDLoc(N), SDValue());
2132  ReplaceValueWith(SDValue(N, 0), Tmp.first);
2133  return SDValue();
2134 }
2135 
2137  switch (N->getOpcode()) {
2138  default:
2139  llvm_unreachable("Expected integer vector reduction");
2140  case ISD::VECREDUCE_ADD:
2141  case ISD::VECREDUCE_MUL:
2142  case ISD::VECREDUCE_AND:
2143  case ISD::VECREDUCE_OR:
2144  case ISD::VECREDUCE_XOR:
2145  case ISD::VP_REDUCE_ADD:
2146  case ISD::VP_REDUCE_MUL:
2147  case ISD::VP_REDUCE_AND:
2148  case ISD::VP_REDUCE_OR:
2149  case ISD::VP_REDUCE_XOR:
2150  return ISD::ANY_EXTEND;
2151  case ISD::VECREDUCE_SMAX:
2152  case ISD::VECREDUCE_SMIN:
2153  case ISD::VP_REDUCE_SMAX:
2154  case ISD::VP_REDUCE_SMIN:
2155  return ISD::SIGN_EXTEND;
2156  case ISD::VECREDUCE_UMAX:
2157  case ISD::VECREDUCE_UMIN:
2158  case ISD::VP_REDUCE_UMAX:
2159  case ISD::VP_REDUCE_UMIN:
2160  return ISD::ZERO_EXTEND;
2161  }
2162 }
2163 
2164 SDValue DAGTypeLegalizer::PromoteIntOpVectorReduction(SDNode *N, SDValue V) {
2165  switch (getExtendForIntVecReduction(N)) {
2166  default:
2167  llvm_unreachable("Impossible extension kind for integer reduction");
2168  case ISD::ANY_EXTEND:
2169  return GetPromotedInteger(V);
2170  case ISD::SIGN_EXTEND:
2171  return SExtPromotedInteger(V);
2172  case ISD::ZERO_EXTEND:
2173  return ZExtPromotedInteger(V);
2174  }
2175 }
2176 
2177 SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
2178  SDLoc dl(N);
2179  SDValue Op = PromoteIntOpVectorReduction(N, N->getOperand(0));
2180 
2181  EVT EltVT = Op.getValueType().getVectorElementType();
2182  EVT VT = N->getValueType(0);
2183 
2184  if (VT.bitsGE(EltVT))
2185  return DAG.getNode(N->getOpcode(), SDLoc(N), VT, Op);
2186 
2187  // Result size must be >= element size. If this is not the case after
2188  // promotion, also promote the result type and then truncate.
2189  SDValue Reduce = DAG.getNode(N->getOpcode(), dl, EltVT, Op);
2190  return DAG.getNode(ISD::TRUNCATE, dl, VT, Reduce);
2191 }
2192 
2193 SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
2194  SDLoc DL(N);
2195  SDValue Op = N->getOperand(OpNo);
2196  SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
2197 
2198  if (OpNo == 2) { // Mask
2199  // Update in place.
2200  NewOps[2] = PromoteTargetBoolean(Op, N->getOperand(1).getValueType());
2201  return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
2202  }
2203 
2204  assert(OpNo == 1 && "Unexpected operand for promotion");
2205 
2206  Op = PromoteIntOpVectorReduction(N, Op);
2207 
2208  NewOps[OpNo] = Op;
2209 
2210  EVT VT = N->getValueType(0);
2211  EVT EltVT = Op.getValueType().getScalarType();
2212 
2213  if (VT.bitsGE(EltVT))
2214  return DAG.getNode(N->getOpcode(), SDLoc(N), VT, NewOps);
2215 
2216  // Result size must be >= element/start-value size. If this is not the case
2217  // after promotion, also promote both the start value and result type and
2218  // then truncate.
2219  NewOps[0] =
2220  DAG.getNode(getExtendForIntVecReduction(N), DL, EltVT, N->getOperand(0));
2221  SDValue Reduce = DAG.getNode(N->getOpcode(), DL, EltVT, NewOps);
2222  return DAG.getNode(ISD::TRUNCATE, DL, VT, Reduce);
2223 }
2224 
2225 SDValue DAGTypeLegalizer::PromoteIntOp_SET_ROUNDING(SDNode *N) {
2226  SDValue Op = ZExtPromotedInteger(N->getOperand(1));
2227  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op), 0);
2228 }
2229 
2230 //===----------------------------------------------------------------------===//
2231 // Integer Result Expansion
2232 //===----------------------------------------------------------------------===//
2233 
2234 /// ExpandIntegerResult - This method is called when the specified result of the
2235 /// specified node is found to need expansion. At this point, the node may also
2236 /// have invalid operands or may have other results that need promotion, we just
2237 /// know that (at least) one result needs expansion.
2238 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
2239  LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG);
2240  dbgs() << "\n");
2241  SDValue Lo, Hi;
2242  Lo = Hi = SDValue();
2243 
2244  // See if the target wants to custom expand this node.
2245  if (CustomLowerNode(N, N->getValueType(ResNo), true))
2246  return;
2247 
2248  switch (N->getOpcode()) {
2249  default:
2250 #ifndef NDEBUG
2251  dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
2252  N->dump(&DAG); dbgs() << "\n";
2253 #endif
2254  report_fatal_error("Do not know how to expand the result of this "
2255  "operator!");
2256 
2257  case ISD::ARITH_FENCE: SplitRes_ARITH_FENCE(N, Lo, Hi); break;
2258  case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
2259  case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
2260  case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
2261  case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
2262  case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break;
2263 
2264  case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
2265  case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
2266  case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
2267  case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
2268  case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
2269 
2270  case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
2271  case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
2272  case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
2273  case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
2274  case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
2275  case ISD::PARITY: ExpandIntRes_PARITY(N, Lo, Hi); break;
2276  case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
2277  case ISD::ABS: ExpandIntRes_ABS(N, Lo, Hi); break;
2278  case ISD::CTLZ_ZERO_UNDEF:
2279  case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
2280  case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
2281  case ISD::CTTZ_ZERO_UNDEF:
2282  case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
2283  case ISD::FLT_ROUNDS_: ExpandIntRes_FLT_ROUNDS(N, Lo, Hi); break;
2285  case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
2287  case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
2288  case ISD::FP_TO_SINT_SAT:
2289  case ISD::FP_TO_UINT_SAT: ExpandIntRes_FP_TO_XINT_SAT(N, Lo, Hi); break;
2290  case ISD::STRICT_LLROUND:
2291  case ISD::STRICT_LLRINT:
2292  case ISD::LLROUND:
2293  case ISD::LLRINT: ExpandIntRes_LLROUND_LLRINT(N, Lo, Hi); break;
2294  case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
2295  case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
2296  case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
2297  case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
2298  case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
2299  case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
2300  case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
2301  case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
2302  case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
2303  case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
2304  case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
2305  case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
2306 
2307  case ISD::ATOMIC_LOAD_ADD:
2308  case ISD::ATOMIC_LOAD_SUB:
2309  case ISD::ATOMIC_LOAD_AND:
2310  case ISD::ATOMIC_LOAD_CLR:
2311  case ISD::ATOMIC_LOAD_OR:
2312  case ISD::ATOMIC_LOAD_XOR:
2313  case ISD::ATOMIC_LOAD_NAND:
2314  case ISD::ATOMIC_LOAD_MIN:
2315  case ISD::ATOMIC_LOAD_MAX:
2316  case ISD::ATOMIC_LOAD_UMIN:
2317  case ISD::ATOMIC_LOAD_UMAX:
2318  case ISD::ATOMIC_SWAP:
2319  case ISD::ATOMIC_CMP_SWAP: {
2320  std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
2321  SplitInteger(Tmp.first, Lo, Hi);
2322  ReplaceValueWith(SDValue(N, 1), Tmp.second);
2323  break;
2324  }
2326  AtomicSDNode *AN = cast<AtomicSDNode>(N);
2327  SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
2328  SDValue Tmp = DAG.getAtomicCmpSwap(
2329  ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
2330  N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
2331  AN->getMemOperand());
2332 
2333  // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
2334  // success simply by comparing the loaded value against the ingoing
2335  // comparison.
2336  SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
2337  N->getOperand(2), ISD::SETEQ);
2338 
2339  SplitInteger(Tmp, Lo, Hi);
2340  ReplaceValueWith(SDValue(N, 1), Success);
2341  ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
2342  break;
2343  }
2344 
2345  case ISD::AND:
2346  case ISD::OR:
2347  case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
2348 
2349  case ISD::UMAX:
2350  case ISD::SMAX:
2351  case ISD::UMIN:
2352  case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
2353 
2354  case ISD::ADD:
2355  case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
2356 
2357  case ISD::ADDC:
2358  case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
2359 
2360  case ISD::ADDE:
2361  case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
2362 
2363  case ISD::ADDCARRY:
2364  case ISD::SUBCARRY: ExpandIntRes_ADDSUBCARRY(N, Lo, Hi); break;
2365 
2366  case ISD::SADDO_CARRY:
2367  case ISD::SSUBO_CARRY: ExpandIntRes_SADDSUBO_CARRY(N, Lo, Hi); break;
2368 
2369  case ISD::SHL:
2370  case ISD::SRA:
2371  case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
2372 
2373  case ISD::SADDO:
2374  case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
2375  case ISD::UADDO:
2376  case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
2377  case ISD::UMULO:
2378  case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
2379 
2380  case ISD::SADDSAT:
2381  case ISD::UADDSAT:
2382  case ISD::SSUBSAT:
2383  case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
2384 
2385  case ISD::SSHLSAT:
2386  case ISD::USHLSAT: ExpandIntRes_SHLSAT(N, Lo, Hi); break;
2387 
2388  case ISD::SMULFIX:
2389  case ISD::SMULFIXSAT:
2390  case ISD::UMULFIX:
2391  case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
2392 
2393  case ISD::SDIVFIX:
2394  case ISD::SDIVFIXSAT:
2395  case ISD::UDIVFIX:
2396  case ISD::UDIVFIXSAT: ExpandIntRes_DIVFIX(N, Lo, Hi); break;
2397 
2398  case ISD::VECREDUCE_ADD:
2399  case ISD::VECREDUCE_MUL:
2400  case ISD::VECREDUCE_AND:
2401  case ISD::VECREDUCE_OR:
2402  case ISD::VECREDUCE_XOR:
2403  case ISD::VECREDUCE_SMAX:
2404  case ISD::VECREDUCE_SMIN:
2405  case ISD::VECREDUCE_UMAX:
2406  case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
2407 
2408  case ISD::ROTL:
2409  case ISD::ROTR:
2410  ExpandIntRes_Rotate(N, Lo, Hi);
2411  break;
2412 
2413  case ISD::FSHL:
2414  case ISD::FSHR:
2415  ExpandIntRes_FunnelShift(N, Lo, Hi);
2416  break;
2417 
2418  case ISD::VSCALE:
2419  ExpandIntRes_VSCALE(N, Lo, Hi);
2420  break;
2421  }
2422 
2423  // If Lo/Hi is null, the sub-method took care of registering results etc.
2424  if (Lo.getNode())
2425  SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
2426 }
2427 
2428 /// Lower an atomic node to the appropriate builtin call.
2429 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
2430  unsigned Opc = Node->getOpcode();
2431  MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2432  AtomicOrdering order = cast<AtomicSDNode>(Node)->getMergedOrdering();
2433  // Lower to outline atomic libcall if outline atomics enabled,
2434  // or to sync libcall otherwise
2435  RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, order, VT);
2436  EVT RetVT = Node->getValueType(0);
2439  if (TLI.getLibcallName(LC)) {
2440  Ops.append(Node->op_begin() + 2, Node->op_end());
2441  Ops.push_back(Node->getOperand(1));
2442  } else {
2443  LC = RTLIB::getSYNC(Opc, VT);
2444  assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2445  "Unexpected atomic op or value type!");
2446  Ops.append(Node->op_begin() + 1, Node->op_end());
2447  }
2448  return TLI.makeLibCall(DAG, LC, RetVT, Ops, CallOptions, SDLoc(Node),
2449  Node->getOperand(0));
2450 }
2451 
2452 /// N is a shift by a value that needs to be expanded,
2453 /// and the shift amount is a constant 'Amt'. Expand the operation.
2454 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
2455  SDValue &Lo, SDValue &Hi) {
2456  SDLoc DL(N);
2457  // Expand the incoming operand to be shifted, so that we have its parts
2458  SDValue InL, InH;
2459  GetExpandedInteger(N->getOperand(0), InL, InH);
2460 
2461  // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
2462  // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
2463  if (!Amt) {
2464  Lo = InL;
2465  Hi = InH;
2466  return;
2467  }
2468 
2469  EVT NVT = InL.getValueType();
2470  unsigned VTBits = N->getValueType(0).getSizeInBits();
2471  unsigned NVTBits = NVT.getSizeInBits();
2472  EVT ShTy = N->getOperand(1).getValueType();
2473 
2474  if (N->getOpcode() == ISD::SHL) {
2475  if (Amt.ugt(VTBits)) {
2476  Lo = Hi = DAG.getConstant(0, DL, NVT);
2477  } else if (Amt.ugt(NVTBits)) {
2478  Lo = DAG.getConstant(0, DL, NVT);
2479  Hi = DAG.getNode(ISD::SHL, DL,
2480  NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2481  } else if (Amt == NVTBits) {
2482  Lo = DAG.getConstant(0, DL, NVT);
2483  Hi = InL;
2484  } else {
2485  Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
2486  Hi = DAG.getNode(ISD::OR, DL, NVT,
2487  DAG.getNode(ISD::SHL, DL, NVT, InH,
2488  DAG.getConstant(Amt, DL, ShTy)),
2489  DAG.getNode(ISD::SRL, DL, NVT, InL,
2490  DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2491  }
2492  return;
2493  }
2494 
2495  if (N->getOpcode() == ISD::SRL) {
2496  if (Amt.ugt(VTBits)) {
2497  Lo = Hi = DAG.getConstant(0, DL, NVT);
2498  } else if (Amt.ugt(NVTBits)) {
2499  Lo = DAG.getNode(ISD::SRL, DL,
2500  NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2501  Hi = DAG.getConstant(0, DL, NVT);
2502  } else if (Amt == NVTBits) {
2503  Lo = InH;
2504  Hi = DAG.getConstant(0, DL, NVT);
2505  } else {
2506  Lo = DAG.getNode(ISD::OR, DL, NVT,
2507  DAG.getNode(ISD::SRL, DL, NVT, InL,
2508  DAG.getConstant(Amt, DL, ShTy)),
2509  DAG.getNode(ISD::SHL, DL, NVT, InH,
2510  DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2511  Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2512  }
2513  return;
2514  }
2515 
2516  assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2517  if (Amt.ugt(VTBits)) {
2518  Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2519  DAG.getConstant(NVTBits - 1, DL, ShTy));
2520  } else if (Amt.ugt(NVTBits)) {
2521  Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2522  DAG.getConstant(Amt - NVTBits, DL, ShTy));
2523  Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2524  DAG.getConstant(NVTBits - 1, DL, ShTy));
2525  } else if (Amt == NVTBits) {
2526  Lo = InH;
2527  Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2528  DAG.getConstant(NVTBits - 1, DL, ShTy));
2529  } else {
2530  Lo = DAG.getNode(ISD::OR, DL, NVT,
2531  DAG.getNode(ISD::SRL, DL, NVT, InL,
2532  DAG.getConstant(Amt, DL, ShTy)),
2533  DAG.getNode(ISD::SHL, DL, NVT, InH,
2534  DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2535  Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2536  }
2537 }
2538 
2539 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
2540 /// this shift based on knowledge of the high bit of the shift amount. If we
2541 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
2542 /// shift amount.
2543 bool DAGTypeLegalizer::
2544 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
2545  SDValue Amt = N->getOperand(1);
2546  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2547  EVT ShTy = Amt.getValueType();
2548  unsigned ShBits = ShTy.getScalarSizeInBits();
2549  unsigned NVTBits = NVT.getScalarSizeInBits();
2550  assert(isPowerOf2_32(NVTBits) &&
2551  "Expanded integer type size not a power of two!");
2552  SDLoc dl(N);
2553 
2554  APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
2555  KnownBits Known = DAG.computeKnownBits(N->getOperand(1));
2556 
2557  // If we don't know anything about the high bits, exit.
2558  if (((Known.Zero|Known.One) & HighBitMask) == 0)
2559  return false;
2560 
2561  // Get the incoming operand to be shifted.
2562  SDValue InL, InH;
2563  GetExpandedInteger(N->getOperand(0), InL, InH);
2564 
2565  // If we know that any of the high bits of the shift amount are one, then we
2566  // can do this as a couple of simple shifts.
2567  if (Known.One.intersects(HighBitMask)) {
2568  // Mask out the high bit, which we know is set.
2569  Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
2570  DAG.getConstant(~HighBitMask, dl, ShTy));
2571 
2572  switch (N->getOpcode()) {
2573  default: llvm_unreachable("Unknown shift");
2574  case ISD::SHL:
2575  Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
2576  Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
2577  return true;
2578  case ISD::SRL:
2579  Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
2580  Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
2581  return true;
2582  case ISD::SRA:
2583  Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
2584  DAG.getConstant(NVTBits - 1, dl, ShTy));
2585  Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
2586  return true;
2587  }
2588  }
2589 
2590  // If we know that all of the high bits of the shift amount are zero, then we
2591  // can do this as a couple of simple shifts.
2592  if (HighBitMask.isSubsetOf(Known.Zero)) {
2593  // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
2594  // shift if x is zero. We can use XOR here because x is known to be smaller
2595  // than 32.
2596  SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
2597  DAG.getConstant(NVTBits - 1, dl, ShTy));
2598 
2599  unsigned Op1, Op2;
2600  switch (N->getOpcode()) {
2601  default: llvm_unreachable("Unknown shift");
2602  case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
2603  case ISD::SRL:
2604  case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
2605  }
2606 
2607  // When shifting right the arithmetic for Lo and Hi is swapped.
2608  if (N->getOpcode() != ISD::SHL)
2609  std::swap(InL, InH);
2610 
2611  // Use a little trick to get the bits that move from Lo to Hi. First
2612  // shift by one bit.
2613  SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
2614  // Then compute the remaining shift with amount-1.
2615  SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
2616 
2617  Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
2618  Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
2619 
2620  if (N->getOpcode() != ISD::SHL)
2621  std::swap(Hi, Lo);
2622  return true;
2623  }
2624 
2625  return false;
2626 }
2627 
2628 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
2629 /// of any size.
2630 bool DAGTypeLegalizer::
2631 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
2632  SDValue Amt = N->getOperand(1);
2633  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2634  EVT ShTy = Amt.getValueType();
2635  unsigned NVTBits = NVT.getSizeInBits();
2636  assert(isPowerOf2_32(NVTBits) &&
2637  "Expanded integer type size not a power of two!");
2638  SDLoc dl(N);
2639 
2640  // Get the incoming operand to be shifted.
2641  SDValue InL, InH;
2642  GetExpandedInteger(N->getOperand(0), InL, InH);
2643 
2644  SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
2645  SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
2646  SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
2647  SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2648  Amt, NVBitsNode, ISD::SETULT);
2649  SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2650  Amt, DAG.getConstant(0, dl, ShTy),
2651  ISD::SETEQ);
2652 
2653  SDValue LoS, HiS, LoL, HiL;
2654  switch (N->getOpcode()) {
2655  default: llvm_unreachable("Unknown shift");
2656  case ISD::SHL:
2657  // Short: ShAmt < NVTBits
2658  LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
2659  HiS = DAG.getNode(ISD::OR, dl, NVT,
2660  DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
2661  DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
2662 
2663  // Long: ShAmt >= NVTBits
2664  LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
2665  HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
2666 
2667  Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
2668  Hi = DAG.getSelect(dl, NVT, isZero, InH,
2669  DAG.getSelect(dl, NVT, isShort, HiS, HiL));
2670  return true;
2671  case ISD::SRL:
2672  // Short: ShAmt < NVTBits
2673  HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
2674  LoS = DAG.getNode(ISD::OR, dl, NVT,
2675  DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2676  // FIXME: If Amt is zero, the following shift generates an undefined result
2677  // on some architectures.
2678  DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2679 
2680  // Long: ShAmt >= NVTBits
2681  HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
2682  LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2683 
2684  Lo = DAG.getSelect(dl, NVT, isZero, InL,
2685  DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2686  Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2687  return true;
2688  case ISD::SRA:
2689  // Short: ShAmt < NVTBits
2690  HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
2691  LoS = DAG.getNode(ISD::OR, dl, NVT,
2692  DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2693  DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2694 
2695  // Long: ShAmt >= NVTBits
2696  HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
2697  DAG.getConstant(NVTBits - 1, dl, ShTy));
2698  LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2699 
2700  Lo = DAG.getSelect(dl, NVT, isZero, InL,
2701  DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2702  Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2703  return true;
2704  }
2705 }
2706 
2707 static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
2708 
2709  switch (Op) {
2710  default: llvm_unreachable("invalid min/max opcode");
2711  case ISD::SMAX:
2712  return std::make_pair(ISD::SETGT, ISD::UMAX);
2713  case ISD::UMAX:
2714  return std::make_pair(ISD::SETUGT, ISD::UMAX);
2715  case ISD::SMIN:
2716  return std::make_pair(ISD::SETLT, ISD::UMIN);
2717  case ISD::UMIN:
2718  return std::make_pair(ISD::SETULT, ISD::UMIN);
2719  }
2720 }
2721 
2722 void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
2723  SDValue &Lo, SDValue &Hi) {
2724  SDLoc DL(N);
2725  ISD::NodeType LoOpc;
2726  ISD::CondCode CondC;
2727  std::tie(CondC, LoOpc) = getExpandedMinMaxOps(N->getOpcode());
2728 
2729  // Expand the subcomponents.
2730  SDValue LHSL, LHSH, RHSL, RHSH;
2731  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2732  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2733 
2734  // Value types
2735  EVT NVT = LHSL.getValueType();
2736  EVT CCT = getSetCCResultType(NVT);
2737 
2738  // Hi part is always the same op
2739  Hi = DAG.getNode(N->getOpcode(), DL, NVT, {LHSH, RHSH});
2740 
2741  // We need to know whether to select Lo part that corresponds to 'winning'
2742  // Hi part or if Hi parts are equal.
2743  SDValue IsHiLeft = DAG.getSetCC(DL, CCT, LHSH, RHSH, CondC);
2744  SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ);
2745 
2746  // Lo part corresponding to the 'winning' Hi part
2747  SDValue LoCmp = DAG.getSelect(DL, NVT, IsHiLeft, LHSL, RHSL);
2748 
2749  // Recursed Lo part if Hi parts are equal, this uses unsigned version
2750  SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL});
2751 
2752  Lo = DAG.getSelect(DL, NVT, IsHiEq, LoMinMax, LoCmp);
2753 }
2754 
2755 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
2756  SDValue &Lo, SDValue &Hi) {
2757  SDLoc dl(N);
2758  // Expand the subcomponents.
2759  SDValue LHSL, LHSH, RHSL, RHSH;
2760  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2761  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2762 
2763  EVT NVT = LHSL.getValueType();
2764  SDValue LoOps[2] = { LHSL, RHSL };
2765  SDValue HiOps[3] = { LHSH, RHSH };
2766 
2767  bool HasOpCarry = TLI.isOperationLegalOrCustom(
2768  N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
2769  TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2770  if (HasOpCarry) {
2771  SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
2772  if (N->getOpcode() == ISD::ADD) {
2773  Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2774  HiOps[2] = Lo.getValue(1);
2775  Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, HiOps);
2776  } else {
2777  Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2778  HiOps[2] = Lo.getValue(1);
2779  Hi = DAG.getNode(ISD::SUBCARRY, dl, VTList, HiOps);
2780  }
2781  return;
2782  }
2783 
2784  // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
2785  // them. TODO: Teach operation legalization how to expand unsupported
2786  // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
2787  // a carry of type MVT::Glue, but there doesn't seem to be any way to
2788  // generate a value of this type in the expanded code sequence.
2789  bool hasCarry =
2790  TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2791  ISD::ADDC : ISD::SUBC,
2792  TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2793 
2794  if (hasCarry) {
2795  SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
2796  if (N->getOpcode() == ISD::ADD) {
2797  Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2798  HiOps[2] = Lo.getValue(1);
2799  Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2800  } else {
2801  Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2802  HiOps[2] = Lo.getValue(1);
2803  Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2804  }
2805  return;
2806  }
2807 
2808  bool hasOVF =
2809  TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2811  TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2813 
2814  if (hasOVF) {
2815  EVT OvfVT = getSetCCResultType(NVT);
2816  SDVTList VTList = DAG.getVTList(NVT, OvfVT);
2817  int RevOpc;
2818  if (N->getOpcode() == ISD::ADD) {
2819  RevOpc = ISD::SUB;
2820  Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2821  Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2822  } else {
2823  RevOpc = ISD::ADD;
2824  Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2825  Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2826  }
2827  SDValue OVF = Lo.getValue(1);
2828 
2829  switch (BoolType) {
2831  OVF = DAG.getNode(ISD::AND, dl, OvfVT, DAG.getConstant(1, dl, OvfVT), OVF);
2834  OVF = DAG.getZExtOrTrunc(OVF, dl, NVT);
2835  Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
2836  break;
2838  OVF = DAG.getSExtOrTrunc(OVF, dl, NVT);
2839  Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
2840  }
2841  return;
2842  }
2843 
2844  if (N->getOpcode() == ISD::ADD) {
2845  Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
2846  Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2847  SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
2848  ISD::SETULT);
2849 
2851  SDValue Carry = DAG.getZExtOrTrunc(Cmp1, dl, NVT);
2852  Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry);
2853  return;
2854  }
2855 
2856  SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
2857  DAG.getConstant(1, dl, NVT),
2858  DAG.getConstant(0, dl, NVT));
2859  SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
2860  ISD::SETULT);
2861  SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
2862  DAG.getConstant(1, dl, NVT), Carry1);
2863  Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
2864  } else {
2865  Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
2866  Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2867  SDValue Cmp =
2868  DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
2869  LoOps[0], LoOps[1], ISD::SETULT);
2870 
2871  SDValue Borrow;
2873  Borrow = DAG.getZExtOrTrunc(Cmp, dl, NVT);
2874  else
2875  Borrow = DAG.getSelect(dl, NVT, Cmp, DAG.getConstant(1, dl, NVT),
2876  DAG.getConstant(0, dl, NVT));
2877 
2878  Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
2879  }
2880 }
2881 
2882 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
2883  SDValue &Lo, SDValue &Hi) {
2884  // Expand the subcomponents.
2885  SDValue LHSL, LHSH, RHSL, RHSH;
2886  SDLoc dl(N);
2887  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2888  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2889  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2890  SDValue LoOps[2] = { LHSL, RHSL };
2891  SDValue HiOps[3] = { LHSH, RHSH };
2892 
2893  if (N->getOpcode() == ISD::ADDC) {
2894  Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2895  HiOps[2] = Lo.getValue(1);
2896  Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2897  } else {
2898  Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2899  HiOps[2] = Lo.getValue(1);
2900  Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2901  }
2902 
2903  // Legalized the flag result - switch anything that used the old flag to
2904  // use the new one.
2905  ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2906 }
2907 
2908 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
2909  SDValue &Lo, SDValue &Hi) {
2910  // Expand the subcomponents.
2911  SDValue LHSL, LHSH, RHSL, RHSH;
2912  SDLoc dl(N);
2913  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2914  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2915  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2916  SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2917  SDValue HiOps[3] = { LHSH, RHSH };
2918 
2919  Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2920  HiOps[2] = Lo.getValue(1);
2921  Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2922 
2923  // Legalized the flag result - switch anything that used the old flag to
2924  // use the new one.
2925  ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2926 }
2927 
2928 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2929  SDValue &Lo, SDValue &Hi) {
2930  SDValue LHS = N->getOperand(0);
2931  SDValue RHS = N->getOperand(1);
2932  SDLoc dl(N);
2933 
2934  SDValue Ovf;
2935 
2936  unsigned CarryOp, NoCarryOp;
2938  switch(N->getOpcode()) {
2939  case ISD::UADDO:
2940  CarryOp = ISD::ADDCARRY;
2941  NoCarryOp = ISD::ADD;
2942  Cond = ISD::SETULT;
2943  break;
2944  case ISD::USUBO:
2945  CarryOp = ISD::SUBCARRY;
2946  NoCarryOp = ISD::SUB;
2947  Cond = ISD::SETUGT;
2948  break;
2949  default:
2950  llvm_unreachable("Node has unexpected Opcode");
2951  }
2952 
2953  bool HasCarryOp = TLI.isOperationLegalOrCustom(
2954  CarryOp, TLI.getTypeToExpandTo(*DAG.getContext(), LHS.getValueType()));
2955 
2956  if (HasCarryOp) {
2957  // Expand the subcomponents.
2958  SDValue LHSL, LHSH, RHSL, RHSH;
2959  GetExpandedInteger(LHS, LHSL, LHSH);
2960  GetExpandedInteger(RHS, RHSL, RHSH);
2961  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2962  SDValue LoOps[2] = { LHSL, RHSL };
2963  SDValue HiOps[3] = { LHSH, RHSH };
2964 
2965  Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2966  HiOps[2] = Lo.getValue(1);
2967  Hi = DAG.getNode(CarryOp, dl, VTList, HiOps);
2968 
2969  Ovf = Hi.getValue(1);
2970  } else {
2971  // Expand the result by simply replacing it with the equivalent
2972  // non-overflow-checking operation.
2973  SDValue Sum = DAG.getNode(NoCarryOp, dl, LHS.getValueType(), LHS, RHS);
2974  SplitInteger(Sum, Lo, Hi);
2975 
2976  // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2977  // overflows iff a - b > a.
2978  Ovf = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, Cond);
2979  }
2980 
2981  // Legalized the flag result - switch anything that used the old flag to
2982  // use the new one.
2983  ReplaceValueWith(SDValue(N, 1), Ovf);
2984 }
2985 
2986 void DAGTypeLegalizer::ExpandIntRes_ADDSUBCARRY(SDNode *N,
2987  SDValue &Lo, SDValue &Hi) {
2988  // Expand the subcomponents.
2989  SDValue LHSL, LHSH, RHSL, RHSH;
2990  SDLoc dl(N);
2991  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2992  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2993  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2994  SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2995  SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
2996 
2997  Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2998  HiOps[2] = Lo.getValue(1);
2999  Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
3000 
3001  // Legalized the flag result - switch anything that used the old flag to
3002  // use the new one.
3003  ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
3004 }
3005 
3006 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO_CARRY(SDNode *N,
3007  SDValue &Lo, SDValue &Hi) {
3008  // Expand the subcomponents.
3009  SDValue LHSL, LHSH, RHSL, RHSH;
3010  SDLoc dl(N);
3011  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
3012  GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
3013  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
3014 
3015  // We need to use an unsigned carry op for the lo part.
3016  unsigned CarryOp = N->getOpcode() == ISD::SADDO_CARRY ? ISD::ADDCARRY
3017  : ISD::SUBCARRY;
3018  Lo = DAG.getNode(CarryOp, dl, VTList, { LHSL, RHSL, N->getOperand(2) });
3019  Hi = DAG.getNode(N->getOpcode(), dl, VTList, { LHSH, RHSH, Lo.getValue(1) });
3020 
3021  // Legalized the flag result - switch anything that used the old flag to
3022  // use the new one.
3023  ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
3024 }
3025 
3026 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
3027  SDValue &Lo, SDValue &Hi) {
3028  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3029  SDLoc dl(N);
3030  SDValue Op = N->getOperand(0);
3031  if (Op.getValueType().bitsLE(NVT)) {
3032  // The low part is any extension of the input (which degenerates to a copy).
3033  Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
3034  Hi = DAG.getUNDEF(NVT); // The high part is undefined.
3035  } else {
3036  // For example, extension of an i48 to an i64. The operand type necessarily
3037  // promotes to the result type, so will end up being expanded too.
3038  assert(getTypeAction(Op.getValueType()) ==
3040  "Only know how to promote this result!");
3041  SDValue Res = GetPromotedInteger(Op);
3042  assert(Res.getValueType() == N->getValueType(0) &&
3043  "Operand over promoted?");
3044  // Split the promoted operand. This will simplify when it is expanded.
3045  SplitInteger(Res, Lo, Hi);
3046  }
3047 }
3048 
3049 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
3050  SDValue &Lo, SDValue &Hi) {
3051  SDLoc dl(N);
3052  GetExpandedInteger(N->getOperand(0), Lo, Hi);
3053  EVT NVT = Lo.getValueType();
3054  EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3055  unsigned NVTBits = NVT.getSizeInBits();
3056  unsigned EVTBits = EVT.getSizeInBits();
3057 
3058  if (NVTBits < EVTBits) {
3059  Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
3061  EVTBits - NVTBits)));
3062  } else {
3063  Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
3064  // The high part replicates the sign bit of Lo, make it explicit.
3065  Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
3066  DAG.getConstant(NVTBits - 1, dl,
3067  TLI.getPointerTy(DAG.getDataLayout())));
3068  }
3069 }
3070 
3071 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
3072  SDValue &Lo, SDValue &Hi) {
3073  SDLoc dl(N);
3074  GetExpandedInteger(N->getOperand(0), Lo, Hi);
3075  EVT NVT = Lo.getValueType();
3076  EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3077  unsigned NVTBits = NVT.getSizeInBits();
3078  unsigned EVTBits = EVT.getSizeInBits();
3079 
3080  if (NVTBits < EVTBits) {
3081  Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
3083  EVTBits - NVTBits)));
3084  } else {
3085  Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
3086  // The high part must be zero, make it explicit.
3087  Hi = DAG.getConstant(0, dl, NVT);
3088  }
3089 }
3090 
3091 void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
3092  SDValue &Lo, SDValue &Hi) {
3093  SDLoc dl(N);
3094  GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
3095  Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
3096  Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
3097 }
3098 
3099 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
3100  SDValue &Lo, SDValue &Hi) {
3101  SDLoc dl(N);
3102  GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
3103  Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
3104  Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
3105 }
3106 
3107 void DAGTypeLegalizer::ExpandIntRes_PARITY(SDNode *N, SDValue &Lo,
3108  SDValue &Hi) {
3109  SDLoc dl(N);
3110  // parity(HiLo) -> parity(Lo^Hi)
3111  GetExpandedInteger(N->getOperand(0), Lo, Hi);
3112  EVT NVT = Lo.getValueType();
3113  Lo =
3114  DAG.getNode(ISD::PARITY, dl, NVT, DAG.getNode(ISD::XOR, dl, NVT, Lo, Hi));
3115  Hi = DAG.getConstant(0, dl, NVT);
3116 }
3117 
3118 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
3119  SDValue &Lo, SDValue &Hi) {
3120  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3121  unsigned NBitWidth = NVT.getSizeInBits();
3122  auto Constant = cast<ConstantSDNode>(N);
3123  const APInt &Cst = Constant->getAPIntValue();
3124  bool IsTarget = Constant->isTargetOpcode();
3125  bool IsOpaque = Constant->isOpaque();
3126  SDLoc dl(N);
3127  Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
3128  Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
3129  IsOpaque);
3130 }
3131 
3132 void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
3133  SDLoc dl(N);
3134 
3135  SDValue N0 = N->getOperand(0);
3136  GetExpandedInteger(N0, Lo, Hi);
3137  EVT NVT = Lo.getValueType();
3138 
3139  // If we have ADDCARRY, use the expanded form of the sra+add+xor sequence we
3140  // use in LegalizeDAG. The ADD part of the expansion is based on
3141  // ExpandIntRes_ADDSUB which also uses ADDCARRY/UADDO after checking that
3142  // ADDCARRY is LegalOrCustom. Each of the pieces here can be further expanded
3143  // if needed. Shift expansion has a special case for filling with sign bits
3144  // so that we will only end up with one SRA.
3145  bool HasAddCarry = TLI.isOperationLegalOrCustom(
3146  ISD::ADDCARRY, TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
3147  if (HasAddCarry) {
3148  EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3149  SDValue Sign =
3150  DAG.getNode(ISD::SRA, dl, NVT, Hi,
3151  DAG.getConstant(NVT.getSizeInBits() - 1, dl, ShiftAmtTy));
3152  SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
3153  Lo = DAG.getNode(ISD::UADDO, dl, VTList, Lo, Sign);
3154  Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, Hi, Sign, Lo.getValue(1));
3155  Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Sign);
3156  Hi = DAG.getNode(ISD::XOR, dl, NVT, Hi, Sign);
3157  return;
3158  }
3159 
3160  // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
3161  EVT VT = N->getValueType(0);
3162  SDValue Neg = DAG.getNode(ISD::SUB, dl, VT,
3163  DAG.getConstant(0, dl, VT), N0);
3164  SDValue NegLo, NegHi;
3165  SplitInteger(Neg, NegLo, NegHi);
3166 
3167  SDValue HiIsNeg = DAG.getSetCC(dl, getSetCCResultType(NVT),
3168  DAG.getConstant(0, dl, NVT), Hi, ISD::SETGT);
3169  Lo = DAG.getSelect(dl, NVT, HiIsNeg, NegLo, Lo);
3170  Hi = DAG.getSelect(dl, NVT, HiIsNeg, NegHi, Hi);
3171 }
3172 
3173 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
3174  SDValue &Lo, SDValue &Hi) {
3175  SDLoc dl(N);
3176  // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
3177  GetExpandedInteger(N->getOperand(0), Lo, Hi);
3178  EVT NVT = Lo.getValueType();
3179 
3180  SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
3181  DAG.getConstant(0, dl, NVT), ISD::SETNE);
3182 
3183  SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
3184  SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
3185 
3186  Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
3187  DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
3188  DAG.getConstant(NVT.getSizeInBits(), dl,
3189  NVT)));
3190  Hi = DAG.getConstant(0, dl, NVT);
3191 }
3192 
3193 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
3194  SDValue &Lo, SDValue &Hi) {
3195  SDLoc dl(N);
3196  // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
3197  GetExpandedInteger(N->getOperand(0), Lo, Hi);
3198  EVT NVT = Lo.getValueType();
3199  Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
3200  DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
3201  Hi = DAG.getConstant(0, dl, NVT);
3202 }
3203 
3204 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
3205  SDValue &Lo, SDValue &Hi) {
3206  SDLoc dl(N);
3207  // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
3208  GetExpandedInteger(N->getOperand(0), Lo, Hi);
3209  EVT NVT = Lo.getValueType();
3210 
3211  SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
3212  DAG.getConstant(0, dl, NVT), ISD::SETNE);
3213 
3214  SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
3215  SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
3216 
3217  Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
3218  DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
3219  DAG.getConstant(NVT.getSizeInBits(), dl,
3220  NVT)));
3221  Hi = DAG.getConstant(0, dl, NVT);
3222 }
3223 
3224 void DAGTypeLegalizer::ExpandIntRes_FLT_ROUNDS(SDNode *N, SDValue &Lo,
3225  SDValue &Hi) {
3226  SDLoc dl(N);
3227  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3228  unsigned NBitWidth = NVT.getSizeInBits();
3229 
3230  EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3231  Lo = DAG.getNode(ISD::FLT_ROUNDS_, dl, {NVT, MVT::Other}, N->getOperand(0));
3232  SDValue Chain = Lo.getValue(1);
3233  // The high part is the sign of Lo, as -1 is a valid value for FLT_ROUNDS
3234  Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
3235  DAG.getConstant(NBitWidth - 1, dl, ShiftAmtTy));
3236 
3237  // Legalize the chain result - switch anything that used the old chain to
3238  // use the new one.
3239  ReplaceValueWith(SDValue(N, 1), Chain);
3240 }
3241 
3242 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
3243  SDValue &Hi) {
3244  SDLoc dl(N);
3245  EVT VT = N->getValueType(0);
3246 
3247  bool IsStrict = N->isStrictFPOpcode();
3248  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
3249  SDValue Op = N->getOperand(IsStrict ? 1 : 0);
3250  if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
3251  Op = GetPromotedFloat(Op);
3252 
3253  if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
3254  EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
3255  Op = GetSoftPromotedHalf(Op);
3256  Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
3257  Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
3258  SplitInteger(Op, Lo, Hi);
3259  return;
3260  }
3261 
3262  RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
3263  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
3265  CallOptions.setSExt(true);
3266  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
3267  CallOptions, dl, Chain);
3268  SplitInteger(Tmp.first, Lo, Hi);
3269 
3270  if (IsStrict)
3271  ReplaceValueWith(SDValue(N, 1), Tmp.second);
3272 }
3273 
3274 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
3275  SDValue &Hi) {
3276  SDLoc dl(N);
3277  EVT VT = N->getValueType(0);
3278 
3279  bool IsStrict = N->isStrictFPOpcode();
3280  SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
3281  SDValue Op = N->getOperand(IsStrict ? 1 : 0);
3282  if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
3283  Op = GetPromotedFloat(Op);
3284 
3285  if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
3286  EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
3287  Op = GetSoftPromotedHalf(Op);
3288  Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
3289  Op = DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op);
3290  SplitInteger(Op, Lo, Hi);
3291  return;
3292  }
3293 
3294  RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
3295  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
3297  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
3298  CallOptions, dl, Chain);
3299  SplitInteger(Tmp.first, Lo, Hi);
3300 
3301  if (IsStrict)
3302  ReplaceValueWith(SDValue(N, 1), Tmp.second);
3303 }
3304 
3305 void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo,
3306  SDValue &Hi) {
3307  SDValue Res = TLI.expandFP_TO_INT_SAT(N, DAG);
3308  SplitInteger(Res, Lo, Hi);
3309 }
3310 
3311 void DAGTypeLegalizer::ExpandIntRes_LLROUND_LLRINT(SDNode *N, SDValue &Lo,
3312  SDValue &Hi) {
3313  SDValue Op = N->getOperand(N->isStrictFPOpcode() ? 1 : 0);
3314 
3315  assert(getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat &&
3316  "Input type needs to be promoted!");
3317 
3318  EVT VT = Op.getValueType();
3319 
3320  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3321  if (N->getOpcode() == ISD::LLROUND ||
3322  N->getOpcode() == ISD::STRICT_LLROUND) {
3323  if (VT == MVT::f32)
3324  LC = RTLIB::LLROUND_F32;
3325  else if (VT == MVT::f64)
3326  LC = RTLIB::LLROUND_F64;
3327  else if (VT == MVT::f80)
3328  LC = RTLIB::LLROUND_F80;
3329  else if (VT == MVT::f128)
3330  LC = RTLIB::LLROUND_F128;
3331  else if (VT == MVT::ppcf128)
3332  LC = RTLIB::LLROUND_PPCF128;
3333  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!");
3334  } else if (N->getOpcode() == ISD::LLRINT ||
3335  N->getOpcode() == ISD::STRICT_LLRINT) {
3336  if (VT == MVT::f32)
3337  LC = RTLIB::LLRINT_F32;
3338  else if (VT == MVT::f64)
3339  LC = RTLIB::LLRINT_F64;
3340  else if (VT == MVT::f80)
3341  LC = RTLIB::LLRINT_F80;
3342  else if (VT == MVT::f128)
3343  LC = RTLIB::LLRINT_F128;
3344  else if (VT == MVT::ppcf128)
3345  LC = RTLIB::LLRINT_PPCF128;
3346  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!");
3347  } else
3348  llvm_unreachable("Unexpected opcode!");
3349 
3350  SDLoc dl(N);
3351  EVT RetVT = N->getValueType(0);
3352  SDValue Chain = N->isStrictFPOpcode() ? N->getOperand(0) : SDValue();
3353 
3355  CallOptions.setSExt(true);
3356  std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
3357  Op, CallOptions, dl,
3358  Chain);
3359  SplitInteger(Tmp.first, Lo, Hi);
3360 
3361  if (N->isStrictFPOpcode())
3362  ReplaceValueWith(SDValue(N, 1), Tmp.second);
3363 }
3364 
3365 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
3366  SDValue &Lo, SDValue &Hi) {
3367  if (N->isAtomic()) {
3368  // It's typical to have larger CAS than atomic load instructions.
3369  SDLoc dl(N);
3370  EVT VT = N->getMemoryVT();
3371  SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
3372  SDValue Zero = DAG.getConstant(0, dl, VT);
3373  SDValue Swap = DAG.getAtomicCmpSwap(
3375  VT, VTs, N->getOperand(0),
3376  N->getOperand(1), Zero, Zero, N->getMemOperand());
3377  ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
3378  ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
3379  return;
3380  }
3381 
3382  if (ISD::isNormalLoad(N)) {
3383  ExpandRes_NormalLoad(N, Lo, Hi);
3384  return;
3385  }
3386 
3387  assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
3388 
3389  EVT VT = N->getValueType(0);
3390  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3391  SDValue Ch = N->getChain();
3392  SDValue Ptr = N->getBasePtr();
3393  ISD::LoadExtType ExtType = N->getExtensionType();
3394  MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
3395  AAMDNodes AAInfo = N->getAAInfo();
3396  SDLoc dl(N);
3397 
3398  assert(NVT.isByteSized() && "Expanded type not byte sized!");
3399 
3400  if (N->getMemoryVT().bitsLE(NVT)) {
3401  EVT MemVT = N->getMemoryVT();
3402 
3403  Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), MemVT,
3404  N->getOriginalAlign(), MMOFlags, AAInfo);
3405 
3406  // Remember the chain.
3407  Ch = Lo.getValue(1);
3408 
3409  if (ExtType == ISD::SEXTLOAD) {
3410  // The high part is obtained by SRA'ing all but one of the bits of the
3411  // lo part.
3412  unsigned LoSize = Lo.getValueSizeInBits();
3413  Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
3414  DAG.getConstant(LoSize - 1, dl,
3415  TLI.getPointerTy(DAG.getDataLayout())));
3416  } else if (ExtType == ISD::ZEXTLOAD) {
3417  // The high part is just a zero.
3418  Hi = DAG.getConstant(0, dl, NVT);
3419  } else {
3420  assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
3421  // The high part is undefined.
3422  Hi = DAG.getUNDEF(NVT);
3423  }
3424  } else if (DAG.getDataLayout().isLittleEndian()) {
3425  // Little-endian - low bits are at low addresses.
3426  Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
3427  N->getOriginalAlign(), MMOFlags, AAInfo);
3428 
3429  unsigned ExcessBits =
3430  N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
3431  EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
3432 
3433  // Increment the pointer to the other half.
3434  unsigned IncrementSize = NVT.getSizeInBits()/8;
3435  Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
3436  Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
3437  N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
3438  N->getOriginalAlign(), MMOFlags, AAInfo);
3439 
3440  // Build a factor node to remember that this load is independent of the
3441  // other one.
3442  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
3443  Hi.getValue(1));
3444  } else {
3445  // Big-endian - high bits are at low addresses. Favor aligned loads at
3446  // the cost of some bit-fiddling.
3447  EVT MemVT = N->getMemoryVT();
3448  unsigned EBytes = MemVT.getStoreSize();
3449  unsigned IncrementSize = NVT.getSizeInBits()/8;
3450  unsigned ExcessBits = (EBytes - IncrementSize)*8;
3451 
3452  // Load both the high bits and maybe some of the low bits.
3453  Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
3455  MemVT.getSizeInBits() - ExcessBits),
3456  N->getOriginalAlign(), MMOFlags, AAInfo);
3457 
3458  // Increment the pointer to the other half.
3459  Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
3460  // Load the rest of the low bits.
3461  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
3462  N->getPointerInfo().getWithOffset(IncrementSize),
3463  EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
3464  N->getOriginalAlign(), MMOFlags, AAInfo);
3465 
3466  // Build a factor node to remember that this load is independent of the
3467  // other one.
3468  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
3469  Hi.getValue(1));
3470 
3471  if (ExcessBits < NVT.getSizeInBits()) {
3472  // Transfer low bits from the bottom of Hi to the top of Lo.
3473  Lo = DAG.getNode(
3474  ISD::OR, dl, NVT, Lo,
3475  DAG.getNode(ISD::SHL, dl, NVT, Hi,
3476  DAG.getConstant(ExcessBits, dl,
3477  TLI.getPointerTy(DAG.getDataLayout()))));
3478  // Move high bits to the right position in Hi.
3479  Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
3480  Hi,
3481  DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
3482  TLI.getPointerTy(DAG.getDataLayout())));
3483  }
3484  }
3485 
3486  // Legalize the chain result - switch anything that used the old chain to
3487  // use the new one.
3488  ReplaceValueWith(SDValue(N, 1), Ch);
3489 }
3490 
3491 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
3492  SDValue &Lo, SDValue &Hi) {
3493  SDLoc dl(N);
3494  SDValue LL, LH, RL, RH;
3495  GetExpandedInteger(N->getOperand(0), LL, LH);
3496  GetExpandedInteger(N->getOperand(1), RL, RH);
3497  Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
3498  Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
3499 }
3500 
3501 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
3502  SDValue &Lo, SDValue &Hi) {
3503  EVT VT = N->getValueType(0);
3504  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3505  SDLoc dl(N);
3506 
3507  SDValue LL, LH, RL, RH;
3508  GetExpandedInteger(N->getOperand(0), LL, LH);
3509  GetExpandedInteger(N->getOperand(1), RL, RH);
3510 
3511  if (TLI.expandMUL(N, Lo, Hi, NVT, DAG,
3513  LL, LH, RL, RH))
3514  return;
3515 
3516  // If nothing else, we can make a libcall.
3517  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3518  if (VT == MVT::i16)
3519  LC = RTLIB::MUL_I16;
3520  else if (VT == MVT::i32)
3521  LC = RTLIB::MUL_I32;
3522  else if (VT == MVT::i64)
3523  LC = RTLIB::MUL_I64;
3524  else if (VT == MVT::i128)
3525  LC = RTLIB::MUL_I128;
3526 
3527  if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(LC)) {
3528  // We'll expand the multiplication by brute force because we have no other
3529  // options. This is a trivially-generalized version of the code from
3530  // Hacker's Delight (itself derived from Knuth's Algorithm M from section
3531  // 4.3.1).
3532  unsigned Bits = NVT.getSizeInBits();
3533  unsigned HalfBits = Bits >> 1;
3534  SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(Bits, HalfBits), dl,
3535  NVT);
3536  SDValue LLL = DAG.getNode(ISD::AND, dl, NVT, LL, Mask);
3537  SDValue RLL = DAG.getNode(ISD::AND, dl, NVT, RL, Mask);
3538 
3539  SDValue T = DAG.getNode(ISD::MUL, dl, NVT, LLL, RLL);
3540  SDValue TL = DAG.getNode(ISD::AND, dl, NVT, T, Mask);
3541 
3542  EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3543  SDValue Shift = DAG.getConstant(HalfBits, dl, ShiftAmtTy);
3544  SDValue TH = DAG.getNode(ISD::SRL, dl, NVT, T, Shift);
3545  SDValue LLH = DAG.getNode(ISD::SRL, dl, NVT, LL, Shift);
3546  SDValue RLH = DAG.getNode(ISD::SRL, dl, NVT, RL, Shift);
3547 
3548  SDValue U = DAG.getNode(ISD::ADD, dl, NVT,
3549  DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TH);
3550  SDValue UL = DAG.getNode(ISD::AND, dl, NVT, U, Mask);
3551  SDValue UH = DAG.getNode(ISD::SRL, dl, NVT, U, Shift);
3552 
3553  SDValue V = DAG.getNode(ISD::ADD, dl, NVT,
3554  DAG.getNode(ISD::MUL, dl, NVT, LLL, RLH), UL);
3555  SDValue VH = DAG.getNode(ISD::SRL, dl, NVT, V, Shift);
3556 
3557  SDValue W = DAG.getNode(ISD::ADD, dl, NVT,
3558  DAG.getNode(ISD::MUL, dl, NVT, LLH, RLH),
3559  DAG.getNode(ISD::ADD, dl, NVT, UH, VH));
3560  Lo = DAG.getNode(ISD::ADD, dl, NVT, TL,
3561  DAG.getNode(ISD::SHL, dl, NVT, V, Shift));
3562 
3563  Hi = DAG.getNode(ISD::ADD, dl, NVT, W,
3564  DAG.getNode(ISD::ADD, dl, NVT,
3565  DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
3566  DAG.getNode(ISD::MUL, dl, NVT, RL, LH)));
3567  return;
3568  }
3569 
3570  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3572  CallOptions.setSExt(true);
3573  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first,
3574  Lo, Hi);
3575 }
3576 
3577 void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
3578  SDValue &Hi) {
3579  SDLoc DL(N);
3580  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3581  SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
3582  SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
3583  Lo = R.getValue(0);
3584  Hi = R.getValue(1);
3585  ReplaceValueWith(SDValue(N, 1), R.getValue(2));
3586 }
3587 
3588 void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
3589  SDValue &Hi) {
3590  SDValue Result = TLI.expandAddSubSat(N, DAG);
3591  SplitInteger(Result, Lo, Hi);
3592 }
3593 
3594 void DAGTypeLegalizer::ExpandIntRes_SHLSAT(SDNode *N, SDValue &Lo,
3595  SDValue &Hi) {
3596  SDValue Result = TLI.expandShlSat(N, DAG);
3597  SplitInteger(Result, Lo, Hi);
3598 }
3599 
3600 /// This performs an expansion of the integer result for a fixed point
3601 /// multiplication. The default expansion performs rounding down towards
3602 /// negative infinity, though targets that do care about rounding should specify
3603 /// a target hook for rounding and provide their own expansion or lowering of
3604 /// fixed point multiplication to be consistent with rounding.
3605 void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
3606  SDValue &Hi) {
3607  SDLoc dl(N);
3608  EVT VT = N->getValueType(0);
3609  unsigned VTSize = VT.getScalarSizeInBits();
3610  SDValue LHS = N->getOperand(0);
3611  SDValue RHS = N->getOperand(1);
3612  uint64_t Scale = N->getConstantOperandVal(2);
3613  bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
3614  N->getOpcode() == ISD::UMULFIXSAT);
3615  bool Signed = (N->getOpcode() == ISD::SMULFIX ||
3616  N->getOpcode() == ISD::SMULFIXSAT);
3617 
3618  // Handle special case when scale is equal to zero.
3619  if (!Scale) {
3620  SDValue Result;
3621  if (!Saturating) {
3622  Result = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3623  } else {
3624  EVT BoolVT = getSetCCResultType(VT);
3625  unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
3626  Result = DAG.getNode(MulOp, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
3627  SDValue Product = Result.getValue(0);
3628  SDValue Overflow = Result.getValue(1);
3629  if (Signed) {
3630  APInt MinVal = APInt::getSignedMinValue(VTSize);
3631  APInt MaxVal = APInt::getSignedMaxValue(VTSize);
3632  SDValue SatMin = DAG.getConstant(MinVal, dl, VT);
3633  SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
3634  SDValue Zero = DAG.getConstant(0, dl, VT);
3635  // Xor the inputs, if resulting sign bit is 0 the product will be
3636  // positive, else negative.
3637  SDValue Xor = DAG.getNode(ISD::XOR, dl, VT, LHS, RHS);
3638  SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Xor, Zero, ISD::SETLT);
3639  Result = DAG.getSelect(dl, VT, ProdNeg, SatMin, SatMax);
3640  Result = DAG.getSelect(dl, VT, Overflow, Result, Product);
3641  } else {
3642  // For unsigned multiplication, we only need to check the max since we
3643  // can't really overflow towards zero.
3644  APInt MaxVal = APInt::getMaxValue(VTSize);
3645  SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
3646  Result = DAG.getSelect(dl, VT, Overflow, SatMax, Product);
3647  }
3648  }
3649  SplitInteger(Result, Lo, Hi);
3650  return;
3651  }
3652 
3653  // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
3654  // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
3655  assert(Scale <= VTSize && "Scale can't be larger than the value type size.");
3656 
3657  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3658  SDValue LL, LH, RL, RH;
3659  GetExpandedInteger(LHS, LL, LH);
3660  GetExpandedInteger(RHS, RL, RH);
3662 
3663  unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
3664  if (!TLI.expandMUL_LOHI(LoHiOp, VT, dl, LHS, RHS, Result, NVT, DAG,
3666  LL, LH, RL, RH)) {
3667  report_fatal_error("Unable to expand MUL_FIX using MUL_LOHI.");
3668  return;
3669  }
3670 
3671  unsigned NVTSize = NVT.getScalarSizeInBits();
3672  assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "
3673  "the size of the current value type");
3674  EVT ShiftTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3675 
3676  // After getting the multiplication result in 4 parts, we need to perform a
3677  // shift right by the amount of the scale to get the result in that scale.
3678  //
3679  // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
3680  // 128 bits that are cut into 4 32-bit parts:
3681  //
3682  // HH HL LH LL
3683  // |---32---|---32---|---32---|---32---|
3684  // 128 96 64 32 0
3685  //
3686  // |------VTSize-----|
3687  //
3688  // |NVTSize-|
3689  //
3690  // The resulting Lo and Hi would normally be in LL and LH after the shift. But
3691  // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
3692  // amount and get Lo and Hi using two funnel shifts. Or for the special case
3693  // when Scale is a multiple of NVTSize we can just pick the result without
3694  // shifting.
3695  uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
3696  if (Scale % NVTSize) {
3697  SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy);
3698  Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0],
3699  ShiftAmount);
3700  Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1],
3701  ShiftAmount);
3702  } else {
3703  Lo = Result[Part0];
3704  Hi = Result[Part0 + 1];
3705  }
3706 
3707  // Unless saturation is requested we are done. The result is in <Hi,Lo>.
3708  if (!Saturating)
3709  return;
3710 
3711  // Can not overflow when there is no integer part.
3712  if (Scale == VTSize)
3713  return;
3714 
3715  // To handle saturation we must check for overflow in the multiplication.
3716  //
3717  // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
3718  // aren't all zeroes.
3719  //
3720  // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
3721  // aren't all ones or all zeroes.
3722  //
3723  // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
3724  // highest bit of HH determines saturation direction in the event of signed
3725  // saturation.
3726 
3727  SDValue ResultHL = Result[2];
3728  SDValue ResultHH = Result[3];
3729 
3730  SDValue SatMax, SatMin;
3731  SDValue NVTZero = DAG.getConstant(0, dl, NVT);
3732  SDValue NVTNeg1 = DAG.getConstant(-1, dl, NVT);
3733  EVT BoolNVT = getSetCCResultType(NVT);
3734 
3735  if (!Signed) {
3736  if (Scale < NVTSize) {
3737  // Overflow happened if ((HH | (HL >> Scale)) != 0).
3738  SDValue HLAdjusted = DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3739  DAG.getConstant(Scale, dl, ShiftTy));
3740  SDValue Tmp = DAG.getNode(ISD::OR, dl, NVT, HLAdjusted, ResultHH);
3741  SatMax = DAG.getSetCC(dl, BoolNVT, Tmp, NVTZero, ISD::SETNE);
3742  } else if (Scale == NVTSize) {
3743  // Overflow happened if (HH != 0).
3744  SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETNE);
3745  } else if (Scale < VTSize) {
3746  // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
3747  SDValue HLAdjusted = DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3748  DAG.getConstant(Scale - NVTSize, dl,
3749  ShiftTy));
3750  SatMax = DAG.getSetCC(dl, BoolNVT, HLAdjusted, NVTZero, ISD::SETNE);
3751  } else
3752  llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"
3753  "(and saturation can't happen with Scale==VTSize).");
3754 
3755  Hi = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Hi);
3756  Lo = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Lo);
3757  return;
3758  }
3759 
3760  if (Scale < NVTSize) {
3761  // The number of overflow bits we can check are VTSize - Scale + 1 (we
3762  // include the sign bit). If these top bits are > 0, then we overflowed past
3763  // the max value. If these top bits are < -1, then we overflowed past the
3764  // min value. Otherwise, we did not overflow.
3765  unsigned OverflowBits = VTSize - Scale + 1;
3766  assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&
3767  "Extent of overflow bits must start within HL");
3768  SDValue HLHiMask = DAG.getConstant(
3769  APInt::getHighBitsSet(NVTSize, OverflowBits - NVTSize), dl, NVT);
3770  SDValue HLLoMask = DAG.getConstant(
3771  APInt::getLowBitsSet(NVTSize, VTSize - OverflowBits), dl, NVT);
3772  // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
3773  SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3774  SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3775  SDValue HLUGT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLLoMask, ISD::SETUGT);
3776  SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3777  DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLUGT));
3778  // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
3779  SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3780  SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3781  SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT);
3782  SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3783  DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLULT));
3784  } else if (Scale == NVTSize) {
3785  // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
3786  SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3787  SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3788  SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT);
3789  SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3790  DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLNeg));
3791  // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
3792  SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3793  SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3794  SDValue HLPos = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETGE);
3795  SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3796  DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLPos));
3797  } else if (Scale < VTSize) {
3798  // This is similar to the case when we saturate if Scale < NVTSize, but we
3799  // only need to check HH.
3800  unsigned OverflowBits = VTSize - Scale + 1;
3801  SDValue HHHiMask = DAG.getConstant(
3802  APInt::getHighBitsSet(NVTSize, OverflowBits), dl, NVT);
3803  SDValue HHLoMask = DAG.getConstant(
3804  APInt::getLowBitsSet(NVTSize, NVTSize - OverflowBits), dl, NVT);
3805  SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, HHLoMask, ISD::SETGT);
3806  SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT);
3807  } else
3808  llvm_unreachable("Illegal scale for signed fixed point mul.");
3809 
3810  // Saturate to signed maximum.
3811  APInt MaxHi = APInt::getSignedMaxValue(NVTSize);
3812  APInt MaxLo = APInt::getAllOnes(NVTSize);
3813  Hi = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxHi, dl, NVT), Hi);
3814  Lo = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxLo, dl, NVT), Lo);
3815  // Saturate to signed minimum.
3816  APInt MinHi = APInt::getSignedMinValue(NVTSize);
3817  Hi = DAG.getSelect(dl, NVT, SatMin, DAG.getConstant(MinHi, dl, NVT), Hi);
3818  Lo = DAG.getSelect(dl, NVT, SatMin, NVTZero, Lo);
3819 }
3820 
3821 void DAGTypeLegalizer::ExpandIntRes_DIVFIX(SDNode *N, SDValue &Lo,
3822  SDValue &Hi) {
3823  SDLoc dl(N);
3824  // Try expanding in the existing type first.
3825  SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, N->getOperand(0),
3826  N->getOperand(1),
3827  N->getConstantOperandVal(2), DAG);
3828 
3829  if (!Res)
3830  Res = earlyExpandDIVFIX(N, N->getOperand(0), N->getOperand(1),
3831  N->getConstantOperandVal(2), TLI, DAG);
3832  SplitInteger(Res, Lo, Hi);
3833 }
3834 
3835 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
3836  SDValue &Lo, SDValue &Hi) {
3837  assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) &&
3838  "Node has unexpected Opcode");
3839  SDValue LHS = Node->getOperand(0);
3840  SDValue RHS = Node->getOperand(1);
3841  SDLoc dl(Node);
3842 
3843  SDValue Ovf;
3844 
3845  bool IsAdd = Node->getOpcode() == ISD::SADDO;
3846  unsigned CarryOp = IsAdd ? ISD::SADDO_CARRY : ISD::SSUBO_CARRY;
3847 
3848  bool HasCarryOp = TLI.isOperationLegalOrCustom(
3849  CarryOp, TLI.getTypeToExpandTo(*DAG.getContext(), LHS.getValueType()));
3850 
3851  if (HasCarryOp) {
3852  // Expand the subcomponents.
3853  SDValue LHSL, LHSH, RHSL, RHSH;
3854  GetExpandedInteger(LHS, LHSL, LHSH);
3855  GetExpandedInteger(RHS, RHSL, RHSH);
3856  SDVTList VTList = DAG.getVTList(LHSL.getValueType(), Node->getValueType(1));
3857 
3858  Lo = DAG.getNode(IsAdd ? ISD::UADDO : ISD::USUBO, dl, VTList, {LHSL, RHSL});
3859  Hi = DAG.getNode(CarryOp, dl, VTList, { LHSH, RHSH, Lo.getValue(1) });
3860 
3861  Ovf = Hi.getValue(1);
3862  } else {
3863  // Expand the result by simply replacing it with the equivalent
3864  // non-overflow-checking operation.
3865  SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3866  ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3867  LHS, RHS);
3868  SplitInteger(Sum, Lo, Hi);
3869 
3870  // Compute the overflow.
3871  //
3872  // LHSSign -> LHS < 0
3873  // RHSSign -> RHS < 0
3874  // SumSign -> Sum < 0
3875  //
3876  // Add:
3877  // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3878  // Sub:
3879  // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3880  //
3881  // To get better codegen we can rewrite this by doing bitwise math on
3882  // the integers and extract the final sign bit at the end. So the
3883  // above becomes:
3884  //
3885  // Add:
3886  // Overflow -> (~(LHS ^ RHS) & (LHS ^ Sum)) < 0
3887  // Sub:
3888  // Overflow -> ((LHS ^ RHS) & (LHS ^ Sum)) < 0
3889  //
3890  // NOTE: This is different than the expansion we do in expandSADDSUBO
3891  // because it is more costly to determine the RHS is > 0 for SSUBO with the
3892  // integers split.
3893  EVT VT = LHS.getValueType();
3894  SDValue SignsMatch = DAG.getNode(ISD::XOR, dl, VT, LHS, RHS);
3895  if (IsAdd)
3896  SignsMatch = DAG.getNOT(dl, SignsMatch, VT);
3897 
3898  SDValue SumSignNE = DAG.getNode(ISD::XOR, dl, VT, LHS, Sum);
3899  Ovf = DAG.getNode(ISD::AND, dl, VT, SignsMatch, SumSignNE);
3900  EVT OType = Node->getValueType(1);
3901  Ovf = DAG.getSetCC(dl, OType, Ovf, DAG.getConstant(0, dl, VT), ISD::SETLT);
3902  }
3903 
3904  // Use the calculated overflow everywhere.
3905  ReplaceValueWith(SDValue(Node, 1), Ovf);
3906 }
3907 
3908 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
3909  SDValue &Lo, SDValue &Hi) {
3910  EVT VT = N->getValueType(0);
3911  SDLoc dl(N);
3912  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3913 
3915  SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3916  SplitInteger(Res.getValue(0), Lo, Hi);
3917  return;
3918  }
3919 
3920  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3921  if (VT == MVT::i16)
3922  LC = RTLIB::SDIV_I16;
3923  else if (VT == MVT::i32)
3924  LC = RTLIB::SDIV_I32;
3925  else if (VT == MVT::i64)
3926  LC = RTLIB::SDIV_I64;
3927  else if (VT == MVT::i128)
3928  LC = RTLIB::SDIV_I128;
3929  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
3930 
3932  CallOptions.setSExt(true);
3933  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3934 }
3935 
3936 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
3937  SDValue &Lo, SDValue &Hi) {
3938  EVT VT = N->getValueType(0);
3939  SDLoc dl(N);
3940 
3941  // If we can emit an efficient shift operation, do so now. Check to see if
3942  // the RHS is a constant.
3943  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
3944  return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
3945 
3946  // If we can determine that the high bit of the shift is zero or one, even if
3947  // the low bits are variable, emit this shift in an optimized form.
3948  if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
3949  return;
3950 
3951  // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
3952  unsigned PartsOpc;
3953  if (N->getOpcode() == ISD::SHL) {
3954  PartsOpc = ISD::SHL_PARTS;
3955  } else if (N->getOpcode() == ISD::SRL) {
3956  PartsOpc = ISD::SRL_PARTS;
3957  } else {
3958  assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
3959  PartsOpc = ISD::SRA_PARTS;
3960  }
3961 
3962  // Next check to see if the target supports this SHL_PARTS operation or if it
3963  // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
3964  // size, but create a libcall instead.
3965  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3966  TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
3967  const bool LegalOrCustom =
3968  (Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
3969  Action == TargetLowering::Custom;
3970 
3971  if (LegalOrCustom && TLI.shouldExpandShift(DAG, N)) {
3972  // Expand the subcomponents.
3973  SDValue LHSL, LHSH;
3974  GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
3975  EVT VT = LHSL.getValueType();
3976 
3977  // If the shift amount operand is coming from a vector legalization it may
3978  // have an illegal type. Fix that first by casting the operand, otherwise
3979  // the new SHL_PARTS operation would need further legalization.
3980  SDValue ShiftOp = N->getOperand(1);
3981  EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
3982  if (ShiftOp.getValueType() != ShiftTy)
3983  ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
3984 
3985  SDValue Ops[] = { LHSL, LHSH, ShiftOp };
3986  Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
3987  Hi = Lo.getValue(1);
3988  return;
3989  }
3990 
3991  // Otherwise, emit a libcall.
3992  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3993  bool isSigned;
3994  if (N->getOpcode() == ISD::SHL) {
3995  isSigned = false; /*sign irrelevant*/
3996  if (VT == MVT::i16)
3997  LC = RTLIB::SHL_I16;
3998  else if (VT == MVT::i32)
3999  LC = RTLIB::SHL_I32;
4000  else if (VT == MVT::i64)
4001  LC = RTLIB::SHL_I64;
4002  else if (VT == MVT::i128)
4003  LC = RTLIB::SHL_I128;
4004  } else if (N->getOpcode() == ISD::SRL) {
4005  isSigned = false;
4006  if (VT == MVT::i16)
4007  LC = RTLIB::SRL_I16;
4008  else if (VT == MVT::i32)
4009  LC = RTLIB::SRL_I32;
4010  else if (VT == MVT::i64)
4011  LC = RTLIB::SRL_I64;
4012  else if (VT == MVT::i128)
4013  LC = RTLIB::SRL_I128;
4014  } else {
4015  assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
4016  isSigned = true;
4017  if (VT == MVT::i16)
4018  LC = RTLIB::SRA_I16;
4019  else if (VT == MVT::i32)
4020  LC = RTLIB::SRA_I32;
4021  else if (VT == MVT::i64)
4022  LC = RTLIB::SRA_I64;
4023  else if (VT == MVT::i128)
4024  LC = RTLIB::SRA_I128;
4025  }
4026 
4027  if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
4028  EVT ShAmtTy =
4030  SDValue ShAmt = DAG.getZExtOrTrunc(N->getOperand(1), dl, ShAmtTy);
4031  SDValue Ops[2] = {N->getOperand(0), ShAmt};
4033  CallOptions.setSExt(isSigned);
4034  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
4035  return;
4036  }
4037 
4038  if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
4039  llvm_unreachable("Unsupported shift!");
4040 }
4041 
4042 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
4043  SDValue &Lo, SDValue &Hi) {
4044  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4045  SDLoc dl(N);
4046  SDValue Op = N->getOperand(0);
4047  if (Op.getValueType().bitsLE(NVT)) {
4048  // The low part is sign extension of the input (degenerates to a copy).
4049  Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
4050  // The high part is obtained by SRA'ing all but one of the bits of low part.
4051  unsigned LoSize = NVT.getSizeInBits();
4052  Hi = DAG.getNode(
4053  ISD::SRA, dl, NVT, Lo,
4054  DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
4055  } else {
4056  // For example, extension of an i48 to an i64. The operand type necessarily
4057  // promotes to the result type, so will end up being expanded too.
4058  assert(getTypeAction(Op.getValueType()) ==
4060  "Only know how to promote this result!");
4061  SDValue Res = GetPromotedInteger(Op);
4062  assert(Res.getValueType() == N->getValueType(0) &&
4063  "Operand over promoted?");
4064  // Split the promoted operand. This will simplify when it is expanded.
4065  SplitInteger(Res, Lo, Hi);
4066  unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
4067  Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
4069  ExcessBits)));
4070  }
4071 }
4072 
4073 void DAGTypeLegalizer::
4074 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
4075  SDLoc dl(N);
4076  GetExpandedInteger(N->getOperand(0), Lo, Hi);
4077  EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4078 
4079  if (EVT.bitsLE(Lo.getValueType())) {
4080  // sext_inreg the low part if needed.
4081  Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
4082  N->getOperand(1));
4083 
4084  // The high part gets the sign extension from the lo-part. This handles
4085  // things like sextinreg V:i64 from i8.
4086  Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
4087  DAG.getConstant(Hi.getValueSizeInBits() - 1, dl,
4088  TLI.getPointerTy(DAG.getDataLayout())));
4089  } else {
4090  // For example, extension of an i48 to an i64. Leave the low part alone,
4091  // sext_inreg the high part.
4092  unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
4093  Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
4095  ExcessBits)));
4096  }
4097 }
4098 
4099 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
4100  SDValue &Lo, SDValue &Hi) {
4101  EVT VT = N->getValueType(0);
4102  SDLoc dl(N);
4103  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
4104 
4106  SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
4107  SplitInteger(Res.getValue(1), Lo, Hi);
4108  return;
4109  }
4110 
4111  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4112  if (VT == MVT::i16)
4113  LC = RTLIB::SREM_I16;
4114  else if (VT == MVT::i32)
4115  LC = RTLIB::SREM_I32;
4116  else if (VT == MVT::i64)
4117  LC = RTLIB::SREM_I64;
4118  else if (VT == MVT::i128)
4119  LC = RTLIB::SREM_I128;
4120  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
4121 
4123  CallOptions.setSExt(true);
4124  SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
4125 }
4126 
4127 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
4128  SDValue &Lo, SDValue &Hi) {
4129  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4130  SDLoc dl(N);
4131  Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
4132  Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
4133  N->getOperand(0),
4134  DAG.getConstant(NVT.getSizeInBits(), dl,
4135  TLI.getPointerTy(DAG.getDataLayout())));
4136  Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
4137 }
4138 
4139 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
4140  SDValue &Lo, SDValue &Hi) {
4141  EVT VT = N->getValueType(0);
4142  SDLoc dl(N);
4143 
4144  if (N->getOpcode() == ISD::UMULO) {
4145  // This section expands the operation into the following sequence of
4146  // instructions. `iNh` here refers to a t