LLVM  9.0.0svn
InstrEmitter.cpp
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1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the Emit routines for the SelectionDAG class, which creates
10 // MachineInstrs based on the decisions of the SelectionDAG instruction
11 // selection.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "InstrEmitter.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/StackMaps.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/Support/Debug.h"
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "instr-emitter"
34 
35 /// MinRCSize - Smallest register class we allow when constraining virtual
36 /// registers. If satisfying all register class constraints would require
37 /// using a smaller register class, emit a COPY to a new virtual register
38 /// instead.
39 const unsigned MinRCSize = 4;
40 
41 /// CountResults - The results of target nodes have register or immediate
42 /// operands first, then an optional chain, and optional glue operands (which do
43 /// not go into the resulting MachineInstr).
45  unsigned N = Node->getNumValues();
46  while (N && Node->getValueType(N - 1) == MVT::Glue)
47  --N;
48  if (N && Node->getValueType(N - 1) == MVT::Other)
49  --N; // Skip over chain result.
50  return N;
51 }
52 
53 /// countOperands - The inputs to target nodes have any actual inputs first,
54 /// followed by an optional chain operand, then an optional glue operand.
55 /// Compute the number of actual operands that will go into the resulting
56 /// MachineInstr.
57 ///
58 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
59 /// the chain and glue. These operands may be implicit on the machine instr.
60 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
61  unsigned &NumImpUses) {
62  unsigned N = Node->getNumOperands();
63  while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
64  --N;
65  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
66  --N; // Ignore chain if it exists.
67 
68  // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
69  NumImpUses = N - NumExpUses;
70  for (unsigned I = N; I > NumExpUses; --I) {
71  if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
72  continue;
73  if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
75  continue;
76  NumImpUses = N - I;
77  break;
78  }
79 
80  return N;
81 }
82 
83 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
84 /// implicit physical register output.
85 void InstrEmitter::
86 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
87  unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
88  unsigned VRBase = 0;
90  // Just use the input register directly!
91  SDValue Op(Node, ResNo);
92  if (IsClone)
93  VRBaseMap.erase(Op);
94  bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
95  (void)isNew; // Silence compiler warning.
96  assert(isNew && "Node emitted out of order - early");
97  return;
98  }
99 
100  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
101  // the CopyToReg'd destination register instead of creating a new vreg.
102  bool MatchReg = true;
103  const TargetRegisterClass *UseRC = nullptr;
104  MVT VT = Node->getSimpleValueType(ResNo);
105 
106  // Stick to the preferred register classes for legal types.
107  if (TLI->isTypeLegal(VT))
108  UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
109 
110  if (!IsClone && !IsCloned)
111  for (SDNode *User : Node->uses()) {
112  bool Match = true;
113  if (User->getOpcode() == ISD::CopyToReg &&
114  User->getOperand(2).getNode() == Node &&
115  User->getOperand(2).getResNo() == ResNo) {
116  unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
118  VRBase = DestReg;
119  Match = false;
120  } else if (DestReg != SrcReg)
121  Match = false;
122  } else {
123  for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
124  SDValue Op = User->getOperand(i);
125  if (Op.getNode() != Node || Op.getResNo() != ResNo)
126  continue;
127  MVT VT = Node->getSimpleValueType(Op.getResNo());
128  if (VT == MVT::Other || VT == MVT::Glue)
129  continue;
130  Match = false;
131  if (User->isMachineOpcode()) {
132  const MCInstrDesc &II = TII->get(User->getMachineOpcode());
133  const TargetRegisterClass *RC = nullptr;
134  if (i+II.getNumDefs() < II.getNumOperands()) {
135  RC = TRI->getAllocatableClass(
136  TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
137  }
138  if (!UseRC)
139  UseRC = RC;
140  else if (RC) {
141  const TargetRegisterClass *ComRC =
142  TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
143  // If multiple uses expect disjoint register classes, we emit
144  // copies in AddRegisterOperand.
145  if (ComRC)
146  UseRC = ComRC;
147  }
148  }
149  }
150  }
151  MatchReg &= Match;
152  if (VRBase)
153  break;
154  }
155 
156  const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
157  SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
158 
159  // Figure out the register class to create for the destreg.
160  if (VRBase) {
161  DstRC = MRI->getRegClass(VRBase);
162  } else if (UseRC) {
163  assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
164  "Incompatible phys register def and uses!");
165  DstRC = UseRC;
166  } else {
167  DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
168  }
169 
170  // If all uses are reading from the src physical register and copying the
171  // register is either impossible or very expensive, then don't create a copy.
172  if (MatchReg && SrcRC->getCopyCost() < 0) {
173  VRBase = SrcReg;
174  } else {
175  // Create the reg, emit the copy.
176  VRBase = MRI->createVirtualRegister(DstRC);
177  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
178  VRBase).addReg(SrcReg);
179  }
180 
181  SDValue Op(Node, ResNo);
182  if (IsClone)
183  VRBaseMap.erase(Op);
184  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
185  (void)isNew; // Silence compiler warning.
186  assert(isNew && "Node emitted out of order - early");
187 }
188 
189 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
190  MachineInstrBuilder &MIB,
191  const MCInstrDesc &II,
192  bool IsClone, bool IsCloned,
193  DenseMap<SDValue, unsigned> &VRBaseMap) {
194  assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
195  "IMPLICIT_DEF should have been handled as a special case elsewhere!");
196 
197  unsigned NumResults = CountResults(Node);
198  for (unsigned i = 0; i < II.getNumDefs(); ++i) {
199  // If the specific node value is only used by a CopyToReg and the dest reg
200  // is a vreg in the same register class, use the CopyToReg'd destination
201  // register instead of creating a new vreg.
202  unsigned VRBase = 0;
203  const TargetRegisterClass *RC =
204  TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
205  // Always let the value type influence the used register class. The
206  // constraints on the instruction may be too lax to represent the value
207  // type correctly. For example, a 64-bit float (X86::FR64) can't live in
208  // the 32-bit float super-class (X86::FR32).
209  if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
210  const TargetRegisterClass *VTRC = TLI->getRegClassFor(
211  Node->getSimpleValueType(i),
212  (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
213  if (RC)
214  VTRC = TRI->getCommonSubClass(RC, VTRC);
215  if (VTRC)
216  RC = VTRC;
217  }
218 
219  if (II.OpInfo[i].isOptionalDef()) {
220  // Optional def must be a physical register.
221  VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
223  MIB.addReg(VRBase, RegState::Define);
224  }
225 
226  if (!VRBase && !IsClone && !IsCloned)
227  for (SDNode *User : Node->uses()) {
228  if (User->getOpcode() == ISD::CopyToReg &&
229  User->getOperand(2).getNode() == Node &&
230  User->getOperand(2).getResNo() == i) {
231  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
233  const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
234  if (RegRC == RC) {
235  VRBase = Reg;
236  MIB.addReg(VRBase, RegState::Define);
237  break;
238  }
239  }
240  }
241  }
242 
243  // Create the result registers for this node and add the result regs to
244  // the machine instruction.
245  if (VRBase == 0) {
246  assert(RC && "Isn't a register operand!");
247  VRBase = MRI->createVirtualRegister(RC);
248  MIB.addReg(VRBase, RegState::Define);
249  }
250 
251  // If this def corresponds to a result of the SDNode insert the VRBase into
252  // the lookup map.
253  if (i < NumResults) {
254  SDValue Op(Node, i);
255  if (IsClone)
256  VRBaseMap.erase(Op);
257  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
258  (void)isNew; // Silence compiler warning.
259  assert(isNew && "Node emitted out of order - early");
260  }
261  }
262 }
263 
264 /// getVR - Return the virtual register corresponding to the specified result
265 /// of the specified node.
266 unsigned InstrEmitter::getVR(SDValue Op,
267  DenseMap<SDValue, unsigned> &VRBaseMap) {
268  if (Op.isMachineOpcode() &&
269  Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
270  // Add an IMPLICIT_DEF instruction before every use.
271  // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
272  // does not include operand register class info.
273  const TargetRegisterClass *RC = TLI->getRegClassFor(
274  Op.getSimpleValueType(), Op.getNode()->isDivergent());
275  unsigned VReg = MRI->createVirtualRegister(RC);
276  BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
277  TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
278  return VReg;
279  }
280 
282  assert(I != VRBaseMap.end() && "Node emitted out of order - late");
283  return I->second;
284 }
285 
286 
287 /// AddRegisterOperand - Add the specified register as an operand to the
288 /// specified machine instr. Insert register copies if the register is
289 /// not in the required register class.
290 void
291 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
292  SDValue Op,
293  unsigned IIOpNum,
294  const MCInstrDesc *II,
295  DenseMap<SDValue, unsigned> &VRBaseMap,
296  bool IsDebug, bool IsClone, bool IsCloned) {
297  assert(Op.getValueType() != MVT::Other &&
298  Op.getValueType() != MVT::Glue &&
299  "Chain and glue operands should occur at end of operand list!");
300  // Get/emit the operand.
301  unsigned VReg = getVR(Op, VRBaseMap);
302 
303  const MCInstrDesc &MCID = MIB->getDesc();
304  bool isOptDef = IIOpNum < MCID.getNumOperands() &&
305  MCID.OpInfo[IIOpNum].isOptionalDef();
306 
307  // If the instruction requires a register in a different class, create
308  // a new virtual register and copy the value into it, but first attempt to
309  // shrink VReg's register class within reason. For example, if VReg == GR32
310  // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
311  if (II) {
312  const TargetRegisterClass *OpRC = nullptr;
313  if (IIOpNum < II->getNumOperands())
314  OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
315 
316  if (OpRC) {
317  const TargetRegisterClass *ConstrainedRC
318  = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
319  if (!ConstrainedRC) {
320  OpRC = TRI->getAllocatableClass(OpRC);
321  assert(OpRC && "Constraints cannot be fulfilled for allocation");
322  unsigned NewVReg = MRI->createVirtualRegister(OpRC);
323  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
324  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
325  VReg = NewVReg;
326  } else {
327  assert(ConstrainedRC->isAllocatable() &&
328  "Constraining an allocatable VReg produced an unallocatable class?");
329  }
330  }
331  }
332 
333  // If this value has only one use, that use is a kill. This is a
334  // conservative approximation. InstrEmitter does trivial coalescing
335  // with CopyFromReg nodes, so don't emit kill flags for them.
336  // Avoid kill flags on Schedule cloned nodes, since there will be
337  // multiple uses.
338  // Tied operands are never killed, so we need to check that. And that
339  // means we need to determine the index of the operand.
340  bool isKill = Op.hasOneUse() &&
341  Op.getNode()->getOpcode() != ISD::CopyFromReg &&
342  !IsDebug &&
343  !(IsClone || IsCloned);
344  if (isKill) {
345  unsigned Idx = MIB->getNumOperands();
346  while (Idx > 0 &&
347  MIB->getOperand(Idx-1).isReg() &&
348  MIB->getOperand(Idx-1).isImplicit())
349  --Idx;
350  bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
351  if (isTied)
352  isKill = false;
353  }
354 
355  MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
356  getDebugRegState(IsDebug));
357 }
358 
359 /// AddOperand - Add the specified operand to the specified machine instr. II
360 /// specifies the instruction information for the node, and IIOpNum is the
361 /// operand number (in the II) that we are adding.
362 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
363  SDValue Op,
364  unsigned IIOpNum,
365  const MCInstrDesc *II,
366  DenseMap<SDValue, unsigned> &VRBaseMap,
367  bool IsDebug, bool IsClone, bool IsCloned) {
368  if (Op.isMachineOpcode()) {
369  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
370  IsDebug, IsClone, IsCloned);
371  } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
372  MIB.addImm(C->getSExtValue());
373  } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
374  MIB.addFPImm(F->getConstantFPValue());
375  } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
376  unsigned VReg = R->getReg();
377  MVT OpVT = Op.getSimpleValueType();
378  const TargetRegisterClass *IIRC =
379  II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
380  : nullptr;
381  const TargetRegisterClass *OpRC =
382  TLI->isTypeLegal(OpVT)
383  ? TLI->getRegClassFor(OpVT,
384  Op.getNode()->isDivergent() ||
385  (IIRC && TRI->isDivergentRegClass(IIRC)))
386  : nullptr;
387 
388  if (OpRC && IIRC && OpRC != IIRC &&
390  unsigned NewVReg = MRI->createVirtualRegister(IIRC);
391  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
392  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
393  VReg = NewVReg;
394  }
395  // Turn additional physreg operands into implicit uses on non-variadic
396  // instructions. This is used by call and return instructions passing
397  // arguments in registers.
398  bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
399  MIB.addReg(VReg, getImplRegState(Imp));
400  } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
401  MIB.addRegMask(RM->getRegMask());
402  } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
403  MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
404  TGA->getTargetFlags());
405  } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
406  MIB.addMBB(BBNode->getBasicBlock());
407  } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
408  MIB.addFrameIndex(FI->getIndex());
409  } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
410  MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
411  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
412  int Offset = CP->getOffset();
413  unsigned Align = CP->getAlignment();
414  Type *Type = CP->getType();
415  // MachineConstantPool wants an explicit alignment.
416  if (Align == 0) {
417  Align = MF->getDataLayout().getPrefTypeAlignment(Type);
418  if (Align == 0) {
419  // Alignment of vector types. FIXME!
420  Align = MF->getDataLayout().getTypeAllocSize(Type);
421  }
422  }
423 
424  unsigned Idx;
426  if (CP->isMachineConstantPoolEntry())
427  Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
428  else
429  Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
430  MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
431  } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
432  MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
433  } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
434  MIB.addSym(SymNode->getMCSymbol());
435  } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
436  MIB.addBlockAddress(BA->getBlockAddress(),
437  BA->getOffset(),
438  BA->getTargetFlags());
439  } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
440  MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
441  } else {
442  assert(Op.getValueType() != MVT::Other &&
443  Op.getValueType() != MVT::Glue &&
444  "Chain and glue operands should occur at end of operand list!");
445  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
446  IsDebug, IsClone, IsCloned);
447  }
448 }
449 
450 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
451  MVT VT, bool isDivergent, const DebugLoc &DL) {
452  const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
453  const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
454 
455  // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
456  // within reason.
457  if (RC && RC != VRC)
458  RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
459 
460  // VReg has been adjusted. It can be used with SubIdx operands now.
461  if (RC)
462  return VReg;
463 
464  // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
465  // register instead.
466  RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
467  assert(RC && "No legal register class for VT supports that SubIdx");
468  unsigned NewReg = MRI->createVirtualRegister(RC);
469  BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
470  .addReg(VReg);
471  return NewReg;
472 }
473 
474 /// EmitSubregNode - Generate machine code for subreg nodes.
475 ///
476 void InstrEmitter::EmitSubregNode(SDNode *Node,
477  DenseMap<SDValue, unsigned> &VRBaseMap,
478  bool IsClone, bool IsCloned) {
479  unsigned VRBase = 0;
480  unsigned Opc = Node->getMachineOpcode();
481 
482  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
483  // the CopyToReg'd destination register instead of creating a new vreg.
484  for (SDNode *User : Node->uses()) {
485  if (User->getOpcode() == ISD::CopyToReg &&
486  User->getOperand(2).getNode() == Node) {
487  unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
489  VRBase = DestReg;
490  break;
491  }
492  }
493  }
494 
495  if (Opc == TargetOpcode::EXTRACT_SUBREG) {
496  // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
497  // constraints on the %dst register, COPY can target all legal register
498  // classes.
499  unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
500  const TargetRegisterClass *TRC =
501  TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
502 
503  unsigned Reg;
507  Reg = R->getReg();
508  DefMI = nullptr;
509  } else {
510  Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
511  DefMI = MRI->getVRegDef(Reg);
512  }
513 
514  unsigned SrcReg, DstReg, DefSubIdx;
515  if (DefMI &&
516  TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
517  SubIdx == DefSubIdx &&
518  TRC == MRI->getRegClass(SrcReg)) {
519  // Optimize these:
520  // r1025 = s/zext r1024, 4
521  // r1026 = extract_subreg r1025, 4
522  // to a copy
523  // r1026 = copy r1024
524  VRBase = MRI->createVirtualRegister(TRC);
525  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
526  TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
527  MRI->clearKillFlags(SrcReg);
528  } else {
529  // Reg may not support a SubIdx sub-register, and we may need to
530  // constrain its register class or issue a COPY to a compatible register
531  // class.
533  Reg = ConstrainForSubReg(Reg, SubIdx,
534  Node->getOperand(0).getSimpleValueType(),
535  Node->isDivergent(), Node->getDebugLoc());
536  // Create the destreg if it is missing.
537  if (VRBase == 0)
538  VRBase = MRI->createVirtualRegister(TRC);
539 
540  // Create the extract_subreg machine instruction.
541  MachineInstrBuilder CopyMI =
542  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
543  TII->get(TargetOpcode::COPY), VRBase);
545  CopyMI.addReg(Reg, 0, SubIdx);
546  else
547  CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
548  }
549  } else if (Opc == TargetOpcode::INSERT_SUBREG ||
550  Opc == TargetOpcode::SUBREG_TO_REG) {
551  SDValue N0 = Node->getOperand(0);
552  SDValue N1 = Node->getOperand(1);
553  SDValue N2 = Node->getOperand(2);
554  unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
555 
556  // Figure out the register class to create for the destreg. It should be
557  // the largest legal register class supporting SubIdx sub-registers.
558  // RegisterCoalescer will constrain it further if it decides to eliminate
559  // the INSERT_SUBREG instruction.
560  //
561  // %dst = INSERT_SUBREG %src, %sub, SubIdx
562  //
563  // is lowered by TwoAddressInstructionPass to:
564  //
565  // %dst = COPY %src
566  // %dst:SubIdx = COPY %sub
567  //
568  // There is no constraint on the %src register class.
569  //
570  const TargetRegisterClass *SRC =
571  TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
572  SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
573  assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
574 
575  if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
576  VRBase = MRI->createVirtualRegister(SRC);
577 
578  // Create the insert_subreg or subreg_to_reg machine instruction.
579  MachineInstrBuilder MIB =
580  BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
581 
582  // If creating a subreg_to_reg, then the first input operand
583  // is an implicit value immediate, otherwise it's a register
584  if (Opc == TargetOpcode::SUBREG_TO_REG) {
585  const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
586  MIB.addImm(SD->getZExtValue());
587  } else
588  AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
589  IsClone, IsCloned);
590  // Add the subregister being inserted
591  AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
592  IsClone, IsCloned);
593  MIB.addImm(SubIdx);
594  MBB->insert(InsertPos, MIB);
595  } else
596  llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
597 
598  SDValue Op(Node, 0);
599  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
600  (void)isNew; // Silence compiler warning.
601  assert(isNew && "Node emitted out of order - early");
602 }
603 
604 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
605 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
606 /// register is constrained to be in a particular register class.
607 ///
608 void
609 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
610  DenseMap<SDValue, unsigned> &VRBaseMap) {
611  unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
612 
613  // Create the new VReg in the destination class and emit a copy.
614  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
615  const TargetRegisterClass *DstRC =
616  TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
617  unsigned NewVReg = MRI->createVirtualRegister(DstRC);
618  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
619  NewVReg).addReg(VReg);
620 
621  SDValue Op(Node, 0);
622  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
623  (void)isNew; // Silence compiler warning.
624  assert(isNew && "Node emitted out of order - early");
625 }
626 
627 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
628 ///
629 void InstrEmitter::EmitRegSequence(SDNode *Node,
630  DenseMap<SDValue, unsigned> &VRBaseMap,
631  bool IsClone, bool IsCloned) {
632  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
633  const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
634  unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
635  const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
636  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
637  unsigned NumOps = Node->getNumOperands();
638  // If the input pattern has a chain, then the root of the corresponding
639  // output pattern will get a chain as well. This can happen to be a
640  // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
641  if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
642  --NumOps; // Ignore chain if it exists.
643 
644  assert((NumOps & 1) == 1 &&
645  "REG_SEQUENCE must have an odd number of operands!");
646  for (unsigned i = 1; i != NumOps; ++i) {
647  SDValue Op = Node->getOperand(i);
648  if ((i & 1) == 0) {
650  // Skip physical registers as they don't have a vreg to get and we'll
651  // insert copies for them in TwoAddressInstructionPass anyway.
653  unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
654  unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
655  const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
656  const TargetRegisterClass *SRC =
657  TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
658  if (SRC && SRC != RC) {
659  MRI->setRegClass(NewVReg, SRC);
660  RC = SRC;
661  }
662  }
663  }
664  AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
665  IsClone, IsCloned);
666  }
667 
668  MBB->insert(InsertPos, MIB);
669  SDValue Op(Node, 0);
670  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
671  (void)isNew; // Silence compiler warning.
672  assert(isNew && "Node emitted out of order - early");
673 }
674 
675 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
676 ///
677 MachineInstr *
679  DenseMap<SDValue, unsigned> &VRBaseMap) {
680  MDNode *Var = SD->getVariable();
681  MDNode *Expr = SD->getExpression();
682  DebugLoc DL = SD->getDebugLoc();
683  assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
684  "Expected inlined-at fields to agree");
685 
686  SD->setIsEmitted();
687 
688  if (SD->isInvalidated()) {
689  // An invalidated SDNode must generate an undef DBG_VALUE: although the
690  // original value is no longer computed, earlier DBG_VALUEs live ranges
691  // must not leak into later code.
692  auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
693  MIB.addReg(0U);
694  MIB.addReg(0U, RegState::Debug);
695  MIB.addMetadata(Var);
696  MIB.addMetadata(Expr);
697  return &*MIB;
698  }
699 
700  if (SD->getKind() == SDDbgValue::FRAMEIX) {
701  // Stack address; this needs to be lowered in target-dependent fashion.
702  // EmitTargetCodeForFrameDebugValue is responsible for allocation.
703  auto FrameMI = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
704  .addFrameIndex(SD->getFrameIx());
705  if (SD->isIndirect())
706  // Push [fi + 0] onto the DIExpression stack.
707  FrameMI.addImm(0);
708  else
709  // Push fi onto the DIExpression stack.
710  FrameMI.addReg(0);
711  return FrameMI.addMetadata(Var).addMetadata(Expr);
712  }
713  // Otherwise, we're going to create an instruction here.
714  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
715  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
716  if (SD->getKind() == SDDbgValue::SDNODE) {
717  SDNode *Node = SD->getSDNode();
718  SDValue Op = SDValue(Node, SD->getResNo());
719  // It's possible we replaced this SDNode with other(s) and therefore
720  // didn't generate code for it. It's better to catch these cases where
721  // they happen and transfer the debug info, but trying to guarantee that
722  // in all cases would be very fragile; this is a safeguard for any
723  // that were missed.
725  if (I==VRBaseMap.end())
726  MIB.addReg(0U); // undef
727  else
728  AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
729  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
730  } else if (SD->getKind() == SDDbgValue::VREG) {
731  MIB.addReg(SD->getVReg(), RegState::Debug);
732  } else if (SD->getKind() == SDDbgValue::CONST) {
733  const Value *V = SD->getConst();
734  if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
735  if (CI->getBitWidth() > 64)
736  MIB.addCImm(CI);
737  else
738  MIB.addImm(CI->getSExtValue());
739  } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
740  MIB.addFPImm(CF);
741  } else if (isa<ConstantPointerNull>(V)) {
742  // Note: This assumes that all nullptr constants are zero-valued.
743  MIB.addImm(0);
744  } else {
745  // Could be an Undef. In any case insert an Undef so we can see what we
746  // dropped.
747  MIB.addReg(0U);
748  }
749  } else {
750  // Insert an Undef so we can see what we dropped.
751  MIB.addReg(0U);
752  }
753 
754  // Indirect addressing is indicated by an Imm as the second parameter.
755  if (SD->isIndirect())
756  MIB.addImm(0U);
757  else
758  MIB.addReg(0U, RegState::Debug);
759 
760  MIB.addMetadata(Var);
761  MIB.addMetadata(Expr);
762 
763  return &*MIB;
764 }
765 
766 MachineInstr *
768  MDNode *Label = SD->getLabel();
769  DebugLoc DL = SD->getDebugLoc();
770  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
771  "Expected inlined-at fields to agree");
772 
773  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
774  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
775  MIB.addMetadata(Label);
776 
777  return &*MIB;
778 }
779 
780 /// EmitMachineNode - Generate machine code for a target-specific node and
781 /// needed dependencies.
782 ///
783 void InstrEmitter::
784 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
785  DenseMap<SDValue, unsigned> &VRBaseMap) {
786  unsigned Opc = Node->getMachineOpcode();
787 
788  // Handle subreg insert/extract specially
789  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
790  Opc == TargetOpcode::INSERT_SUBREG ||
791  Opc == TargetOpcode::SUBREG_TO_REG) {
792  EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
793  return;
794  }
795 
796  // Handle COPY_TO_REGCLASS specially.
797  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
798  EmitCopyToRegClassNode(Node, VRBaseMap);
799  return;
800  }
801 
802  // Handle REG_SEQUENCE specially.
803  if (Opc == TargetOpcode::REG_SEQUENCE) {
804  EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
805  return;
806  }
807 
808  if (Opc == TargetOpcode::IMPLICIT_DEF)
809  // We want a unique VR for each IMPLICIT_DEF use.
810  return;
811 
812  const MCInstrDesc &II = TII->get(Opc);
813  unsigned NumResults = CountResults(Node);
814  unsigned NumDefs = II.getNumDefs();
815  const MCPhysReg *ScratchRegs = nullptr;
816 
817  // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
818  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
819  // Stackmaps do not have arguments and do not preserve their calling
820  // convention. However, to simplify runtime support, they clobber the same
821  // scratch registers as AnyRegCC.
822  unsigned CC = CallingConv::AnyReg;
823  if (Opc == TargetOpcode::PATCHPOINT) {
825  NumDefs = NumResults;
826  }
827  ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
828  }
829 
830  unsigned NumImpUses = 0;
831  unsigned NodeOperands =
832  countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
833  bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
834 #ifndef NDEBUG
835  unsigned NumMIOperands = NodeOperands + NumResults;
836  if (II.isVariadic())
837  assert(NumMIOperands >= II.getNumOperands() &&
838  "Too few operands for a variadic node!");
839  else
840  assert(NumMIOperands >= II.getNumOperands() &&
841  NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
842  NumImpUses &&
843  "#operands for dag node doesn't match .td file!");
844 #endif
845 
846  // Create the new machine instruction.
847  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
848 
849  // Add result register values for things that are defined by this
850  // instruction.
851  if (NumResults) {
852  CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
853 
854  // Transfer any IR flags from the SDNode to the MachineInstr
855  MachineInstr *MI = MIB.getInstr();
856  const SDNodeFlags Flags = Node->getFlags();
857  if (Flags.hasNoSignedZeros())
858  MI->setFlag(MachineInstr::MIFlag::FmNsz);
859 
860  if (Flags.hasAllowReciprocal())
861  MI->setFlag(MachineInstr::MIFlag::FmArcp);
862 
863  if (Flags.hasNoNaNs())
864  MI->setFlag(MachineInstr::MIFlag::FmNoNans);
865 
866  if (Flags.hasNoInfs())
867  MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
868 
869  if (Flags.hasAllowContract())
870  MI->setFlag(MachineInstr::MIFlag::FmContract);
871 
872  if (Flags.hasApproximateFuncs())
873  MI->setFlag(MachineInstr::MIFlag::FmAfn);
874 
875  if (Flags.hasAllowReassociation())
876  MI->setFlag(MachineInstr::MIFlag::FmReassoc);
877 
878  if (Flags.hasNoUnsignedWrap())
879  MI->setFlag(MachineInstr::MIFlag::NoUWrap);
880 
881  if (Flags.hasNoSignedWrap())
882  MI->setFlag(MachineInstr::MIFlag::NoSWrap);
883 
884  if (Flags.hasExact())
885  MI->setFlag(MachineInstr::MIFlag::IsExact);
886 
887  if (Flags.hasFPExcept())
888  MI->setFlag(MachineInstr::MIFlag::FPExcept);
889  }
890 
891  // Emit all of the actual operands of this instruction, adding them to the
892  // instruction as appropriate.
893  bool HasOptPRefs = NumDefs > NumResults;
894  assert((!HasOptPRefs || !HasPhysRegOuts) &&
895  "Unable to cope with optional defs and phys regs defs!");
896  unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
897  for (unsigned i = NumSkip; i != NodeOperands; ++i)
898  AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
899  VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
900 
901  // Add scratch registers as implicit def and early clobber
902  if (ScratchRegs)
903  for (unsigned i = 0; ScratchRegs[i]; ++i)
904  MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
906 
907  // Set the memory reference descriptions of this instruction now that it is
908  // part of the function.
909  MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
910 
911  // Insert the instruction into position in the block. This needs to
912  // happen before any custom inserter hook is called so that the
913  // hook knows where in the block to insert the replacement code.
914  MBB->insert(InsertPos, MIB);
915 
916  // The MachineInstr may also define physregs instead of virtregs. These
917  // physreg values can reach other instructions in different ways:
918  //
919  // 1. When there is a use of a Node value beyond the explicitly defined
920  // virtual registers, we emit a CopyFromReg for one of the implicitly
921  // defined physregs. This only happens when HasPhysRegOuts is true.
922  //
923  // 2. A CopyFromReg reading a physreg may be glued to this instruction.
924  //
925  // 3. A glued instruction may implicitly use a physreg.
926  //
927  // 4. A glued instruction may use a RegisterSDNode operand.
928  //
929  // Collect all the used physreg defs, and make sure that any unused physreg
930  // defs are marked as dead.
931  SmallVector<unsigned, 8> UsedRegs;
932 
933  // Additional results must be physical register defs.
934  if (HasPhysRegOuts) {
935  for (unsigned i = NumDefs; i < NumResults; ++i) {
936  unsigned Reg = II.getImplicitDefs()[i - NumDefs];
937  if (!Node->hasAnyUseOfValue(i))
938  continue;
939  // This implicitly defined physreg has a use.
940  UsedRegs.push_back(Reg);
941  EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
942  }
943  }
944 
945  // Scan the glue chain for any used physregs.
946  if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
947  for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
948  if (F->getOpcode() == ISD::CopyFromReg) {
949  UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
950  continue;
951  } else if (F->getOpcode() == ISD::CopyToReg) {
952  // Skip CopyToReg nodes that are internal to the glue chain.
953  continue;
954  }
955  // Collect declared implicit uses.
956  const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
957  UsedRegs.append(MCID.getImplicitUses(),
958  MCID.getImplicitUses() + MCID.getNumImplicitUses());
959  // In addition to declared implicit uses, we must also check for
960  // direct RegisterSDNode operands.
961  for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
962  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
963  unsigned Reg = R->getReg();
965  UsedRegs.push_back(Reg);
966  }
967  }
968  }
969 
970  // Finally mark unused registers as dead.
971  if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
972  MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
973 
974  // Run post-isel target hook to adjust this instruction if needed.
975  if (II.hasPostISelHook())
976  TLI->AdjustInstrPostInstrSelection(*MIB, Node);
977 }
978 
979 /// EmitSpecialNode - Generate machine code for a target-independent node and
980 /// needed dependencies.
981 void InstrEmitter::
982 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
983  DenseMap<SDValue, unsigned> &VRBaseMap) {
984  switch (Node->getOpcode()) {
985  default:
986 #ifndef NDEBUG
987  Node->dump();
988 #endif
989  llvm_unreachable("This target-independent node should have been selected!");
990  case ISD::EntryToken:
991  llvm_unreachable("EntryToken should have been excluded from the schedule!");
992  case ISD::MERGE_VALUES:
993  case ISD::TokenFactor: // fall thru
994  break;
995  case ISD::CopyToReg: {
996  unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
997  SDValue SrcVal = Node->getOperand(2);
999  SrcVal.isMachineOpcode() &&
1000  SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
1001  // Instead building a COPY to that vreg destination, build an
1002  // IMPLICIT_DEF instruction instead.
1003  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1004  TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1005  break;
1006  }
1007  unsigned SrcReg;
1008  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
1009  SrcReg = R->getReg();
1010  else
1011  SrcReg = getVR(SrcVal, VRBaseMap);
1012 
1013  if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1014  break;
1015 
1016  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1017  DestReg).addReg(SrcReg);
1018  break;
1019  }
1020  case ISD::CopyFromReg: {
1021  unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1022  EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1023  break;
1024  }
1025  case ISD::EH_LABEL:
1026  case ISD::ANNOTATION_LABEL: {
1027  unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1030  MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1031  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1032  TII->get(Opc)).addSym(S);
1033  break;
1034  }
1035 
1036  case ISD::LIFETIME_START:
1037  case ISD::LIFETIME_END: {
1038  unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
1040 
1042  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1043  .addFrameIndex(FI->getIndex());
1044  break;
1045  }
1046 
1047  case ISD::INLINEASM:
1048  case ISD::INLINEASM_BR: {
1049  unsigned NumOps = Node->getNumOperands();
1050  if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1051  --NumOps; // Ignore the glue operand.
1052 
1053  // Create the inline asm machine instruction.
1054  unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1057  MachineInstrBuilder MIB =
1058  BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1059 
1060  // Add the asm string as an external symbol operand.
1061  SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1062  const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1063  MIB.addExternalSymbol(AsmStr);
1064 
1065  // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1066  // bits.
1067  int64_t ExtraInfo =
1068  cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1069  getZExtValue();
1070  MIB.addImm(ExtraInfo);
1071 
1072  // Remember to operand index of the group flags.
1073  SmallVector<unsigned, 8> GroupIdx;
1074 
1075  // Remember registers that are part of early-clobber defs.
1076  SmallVector<unsigned, 8> ECRegs;
1077 
1078  // Add all of the operand registers to the instruction.
1079  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1080  unsigned Flags =
1081  cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1082  const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1083 
1084  GroupIdx.push_back(MIB->getNumOperands());
1085  MIB.addImm(Flags);
1086  ++i; // Skip the ID value.
1087 
1088  switch (InlineAsm::getKind(Flags)) {
1089  default: llvm_unreachable("Bad flags!");
1091  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1092  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1093  // FIXME: Add dead flags for physical and virtual registers defined.
1094  // For now, mark physical register defs as implicit to help fast
1095  // regalloc. This makes inline asm look a lot like calls.
1096  MIB.addReg(Reg, RegState::Define |
1098  }
1099  break;
1102  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1103  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1106  ECRegs.push_back(Reg);
1107  }
1108  break;
1109  case InlineAsm::Kind_RegUse: // Use of register.
1110  case InlineAsm::Kind_Imm: // Immediate.
1111  case InlineAsm::Kind_Mem: // Addressing mode.
1112  // The addressing mode has been selected, just add all of the
1113  // operands to the machine instruction.
1114  for (unsigned j = 0; j != NumVals; ++j, ++i)
1115  AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1116  /*IsDebug=*/false, IsClone, IsCloned);
1117 
1118  // Manually set isTied bits.
1120  unsigned DefGroup = 0;
1121  if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1122  unsigned DefIdx = GroupIdx[DefGroup] + 1;
1123  unsigned UseIdx = GroupIdx.back() + 1;
1124  for (unsigned j = 0; j != NumVals; ++j)
1125  MIB->tieOperands(DefIdx + j, UseIdx + j);
1126  }
1127  }
1128  break;
1129  }
1130  }
1131 
1132  // GCC inline assembly allows input operands to also be early-clobber
1133  // output operands (so long as the operand is written only after it's
1134  // used), but this does not match the semantics of our early-clobber flag.
1135  // If an early-clobber operand register is also an input operand register,
1136  // then remove the early-clobber flag.
1137  for (unsigned Reg : ECRegs) {
1138  if (MIB->readsRegister(Reg, TRI)) {
1139  MachineOperand *MO =
1140  MIB->findRegisterDefOperand(Reg, false, false, TRI);
1141  assert(MO && "No def operand for clobbered register?");
1142  MO->setIsEarlyClobber(false);
1143  }
1144  }
1145 
1146  // Get the mdnode from the asm if it exists and add it to the instruction.
1148  const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1149  if (MD)
1150  MIB.addMetadata(MD);
1151 
1152  MBB->insert(InsertPos, MIB);
1153  break;
1154  }
1155  }
1156 }
1157 
1158 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1159 /// at the given position in the given block.
1161  MachineBasicBlock::iterator insertpos)
1162  : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1163  TII(MF->getSubtarget().getInstrInfo()),
1164  TRI(MF->getSubtarget().getRegisterInfo()),
1165  TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1166  InsertPos(insertpos) {}
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:709
uint64_t CallInst * C
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:532
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
EVT getValueType() const
Return the ValueType of the referenced return value.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool hasNoSignedZeros() const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:554
This class represents lattice values for constants.
Definition: AllocatorList.h:23
SDNode * getSDNode() const
Returns the SDNode* for a register ref.
bool isInvalidated() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void push_back(const T &Elt)
Definition: SmallVector.h:211
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:529
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
void setIsEmitted()
setIsEmitted / isEmitted - Getter/Setter for flag indicating that this SDDbgValue has been emitted to...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
Completely target-dependent object reference.
const Value * getConst() const
Returns the Value* for a constant.
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first, then an optional chain, and optional flag operands (which do not go into the machine instrs.)
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
F(f)
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned char TargetFlags=0) const
const DebugLoc & getDebugLoc() const
Return the source location info.
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:44
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:341
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
Value is a virtual register.
const DebugLoc & getDebugLoc() const
unsigned getResNo() const
Returns the ResNo for a register ref.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
bool hasApproximateFuncs() const
unsigned getVReg() const
Returns the Virtual Register for a VReg.
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers. ...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:221
unsigned getFrameIx() const
Returns the FrameIx for a stack object.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:211
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
CopyToReg - This node has three operands: a chain, a register number to set to this value...
Definition: ISDOpcodes.h:169
unsigned SubReg
SimpleValueType SimpleTy
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:695
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
void setIsEarlyClobber(bool Val=true)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
Value is contents of a stack location.
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
DIVariable * getVariable() const
Returns the DIVariable pointer for the variable.
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
DbgValueKind getKind() const
Returns the kind.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: ELF.h:334
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Value * getOperand(unsigned i) const
Definition: User.h:169
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getKillRegState(bool B)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getDebugRegState(bool B)
bool hasAllowReciprocal() const
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:877
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
bool hasAllowContract() const
unsigned getDefRegState(bool B)
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:551
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned char TargetFlags=0) const
Machine Value Type.
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:95
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:235
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
bool isMachineOpcode() const
SDNode * getGluedUser() const
If this node has a glue value with a user, return the user (there is at most one).
const SDValue & getOperand(unsigned Num) const
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
unsigned getPrefTypeAlignment(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
Definition: DataLayout.cpp:756
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:301
unsigned getMachineOpcode() const
bool hasNoNaNs() const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:324
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const MachineInstrBuilder & addFrameIndex(int Idx) const
DebugLoc getDebugLoc() const
Returns the DebugLoc.
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:703
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:188
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:49
void dump() const
Dump this node, for debugging.
DIExpression * getExpression() const
Returns the DIExpression pointer for the expression.
unsigned getNumOperands() const
Definition: User.h:191
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
DebugLoc getDebugLoc() const
Returns the DebugLoc.
Value is a constant.
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
bool isDivergent() const
bool hasFPExcept() const
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:226
Represents one node in the SelectionDAG.
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the &#39;hasPostISelHook&#39; flag...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
iterator_range< use_iterator > uses()
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:387
bool hasNoSignedWrap() const
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:469
Representation of each machine instruction.
Definition: MachineInstr.h:63
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
These are IR-level optimization flags that may be propagated to SDNodes.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Value is the result of an expression.
Holds the information from a dbg_label node through SDISel.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
unsigned getImplRegState(bool B)
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
MachineInstr * EmitDbgLabel(SDDbgLabel *SD)
Generate machine instruction for a dbg_label node.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
MDNode * getLabel() const
Returns the MDNode pointer for the label.
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:174
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned char TargetFlags=0) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getReg() const
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, unsigned > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:698
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
LLVM Value Representation.
Definition: Value.h:72
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
unsigned getResNo() const
get the index which selects a specific result in the SDNode
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
bool hasNoUnsignedWrap() const
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:175
static const Function * getParent(const Value *V)
bool hasAllowReassociation() const
IRTranslator LLVM IR MI
bool hasNoInfs() const
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
unsigned getNumOperands() const
bool isIndirect() const
Returns whether this is an indirect value.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
uint64_t getZExtValue() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Holds the information from a dbg_value node through SDISel.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
This file describes how to lower LLVM code to machine code.
bool isImplicit() const
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.