LLVM  17.0.0git
InstrEmitter.cpp
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1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the Emit routines for the SelectionDAG class, which creates
10 // MachineInstrs based on the decisions of the SelectionDAG instruction
11 // selection.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "InstrEmitter.h"
16 #include "SDNodeDbgValue.h"
22 #include "llvm/CodeGen/StackMaps.h"
27 #include "llvm/IR/PseudoProbe.h"
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "instr-emitter"
33 
34 /// MinRCSize - Smallest register class we allow when constraining virtual
35 /// registers. If satisfying all register class constraints would require
36 /// using a smaller register class, emit a COPY to a new virtual register
37 /// instead.
38 const unsigned MinRCSize = 4;
39 
40 /// CountResults - The results of target nodes have register or immediate
41 /// operands first, then an optional chain, and optional glue operands (which do
42 /// not go into the resulting MachineInstr).
44  unsigned N = Node->getNumValues();
45  while (N && Node->getValueType(N - 1) == MVT::Glue)
46  --N;
47  if (N && Node->getValueType(N - 1) == MVT::Other)
48  --N; // Skip over chain result.
49  return N;
50 }
51 
52 /// countOperands - The inputs to target nodes have any actual inputs first,
53 /// followed by an optional chain operand, then an optional glue operand.
54 /// Compute the number of actual operands that will go into the resulting
55 /// MachineInstr.
56 ///
57 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
58 /// the chain and glue. These operands may be implicit on the machine instr.
59 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
60  unsigned &NumImpUses) {
61  unsigned N = Node->getNumOperands();
62  while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
63  --N;
64  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
65  --N; // Ignore chain if it exists.
66 
67  // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
68  NumImpUses = N - NumExpUses;
69  for (unsigned I = N; I > NumExpUses; --I) {
70  if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
71  continue;
72  if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
73  if (RN->getReg().isPhysical())
74  continue;
75  NumImpUses = N - I;
76  break;
77  }
78 
79  return N;
80 }
81 
82 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
83 /// implicit physical register output.
84 void InstrEmitter::EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
85  Register SrcReg,
86  DenseMap<SDValue, Register> &VRBaseMap) {
87  Register VRBase;
88  if (SrcReg.isVirtual()) {
89  // Just use the input register directly!
90  SDValue Op(Node, ResNo);
91  if (IsClone)
92  VRBaseMap.erase(Op);
93  bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
94  (void)isNew; // Silence compiler warning.
95  assert(isNew && "Node emitted out of order - early");
96  return;
97  }
98 
99  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
100  // the CopyToReg'd destination register instead of creating a new vreg.
101  bool MatchReg = true;
102  const TargetRegisterClass *UseRC = nullptr;
103  MVT VT = Node->getSimpleValueType(ResNo);
104 
105  // Stick to the preferred register classes for legal types.
106  if (TLI->isTypeLegal(VT))
107  UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
108 
109  for (SDNode *User : Node->uses()) {
110  bool Match = true;
111  if (User->getOpcode() == ISD::CopyToReg &&
112  User->getOperand(2).getNode() == Node &&
113  User->getOperand(2).getResNo() == ResNo) {
114  Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
115  if (DestReg.isVirtual()) {
116  VRBase = DestReg;
117  Match = false;
118  } else if (DestReg != SrcReg)
119  Match = false;
120  } else {
121  for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
122  SDValue Op = User->getOperand(i);
123  if (Op.getNode() != Node || Op.getResNo() != ResNo)
124  continue;
125  MVT VT = Node->getSimpleValueType(Op.getResNo());
126  if (VT == MVT::Other || VT == MVT::Glue)
127  continue;
128  Match = false;
129  if (User->isMachineOpcode()) {
130  const MCInstrDesc &II = TII->get(User->getMachineOpcode());
131  const TargetRegisterClass *RC = nullptr;
132  if (i + II.getNumDefs() < II.getNumOperands()) {
133  RC = TRI->getAllocatableClass(
134  TII->getRegClass(II, i + II.getNumDefs(), TRI, *MF));
135  }
136  if (!UseRC)
137  UseRC = RC;
138  else if (RC) {
139  const TargetRegisterClass *ComRC =
140  TRI->getCommonSubClass(UseRC, RC);
141  // If multiple uses expect disjoint register classes, we emit
142  // copies in AddRegisterOperand.
143  if (ComRC)
144  UseRC = ComRC;
145  }
146  }
147  }
148  }
149  MatchReg &= Match;
150  if (VRBase)
151  break;
152  }
153 
154  const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
155  SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
156 
157  // Figure out the register class to create for the destreg.
158  if (VRBase) {
159  DstRC = MRI->getRegClass(VRBase);
160  } else if (UseRC) {
161  assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
162  "Incompatible phys register def and uses!");
163  DstRC = UseRC;
164  } else
165  DstRC = SrcRC;
166 
167  // If all uses are reading from the src physical register and copying the
168  // register is either impossible or very expensive, then don't create a copy.
169  if (MatchReg && SrcRC->getCopyCost() < 0) {
170  VRBase = SrcReg;
171  } else {
172  // Create the reg, emit the copy.
173  VRBase = MRI->createVirtualRegister(DstRC);
174  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
175  VRBase).addReg(SrcReg);
176  }
177 
178  SDValue Op(Node, ResNo);
179  if (IsClone)
180  VRBaseMap.erase(Op);
181  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
182  (void)isNew; // Silence compiler warning.
183  assert(isNew && "Node emitted out of order - early");
184 }
185 
186 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
187  MachineInstrBuilder &MIB,
188  const MCInstrDesc &II,
189  bool IsClone, bool IsCloned,
190  DenseMap<SDValue, Register> &VRBaseMap) {
191  assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
192  "IMPLICIT_DEF should have been handled as a special case elsewhere!");
193 
194  unsigned NumResults = CountResults(Node);
195  bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
196  II.isVariadic() && II.variadicOpsAreDefs();
197  unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.getNumDefs();
198  if (Node->getMachineOpcode() == TargetOpcode::STATEPOINT)
199  NumVRegs = NumResults;
200  for (unsigned i = 0; i < NumVRegs; ++i) {
201  // If the specific node value is only used by a CopyToReg and the dest reg
202  // is a vreg in the same register class, use the CopyToReg'd destination
203  // register instead of creating a new vreg.
204  Register VRBase;
205  const TargetRegisterClass *RC =
206  TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
207  // Always let the value type influence the used register class. The
208  // constraints on the instruction may be too lax to represent the value
209  // type correctly. For example, a 64-bit float (X86::FR64) can't live in
210  // the 32-bit float super-class (X86::FR32).
211  if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
212  const TargetRegisterClass *VTRC = TLI->getRegClassFor(
213  Node->getSimpleValueType(i),
214  (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
215  if (RC)
216  VTRC = TRI->getCommonSubClass(RC, VTRC);
217  if (VTRC)
218  RC = VTRC;
219  }
220 
221  if (!II.operands().empty() && II.operands()[i].isOptionalDef()) {
222  // Optional def must be a physical register.
223  VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
224  assert(VRBase.isPhysical());
225  MIB.addReg(VRBase, RegState::Define);
226  }
227 
228  if (!VRBase && !IsClone && !IsCloned)
229  for (SDNode *User : Node->uses()) {
230  if (User->getOpcode() == ISD::CopyToReg &&
231  User->getOperand(2).getNode() == Node &&
232  User->getOperand(2).getResNo() == i) {
233  Register Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
234  if (Reg.isVirtual()) {
235  const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
236  if (RegRC == RC) {
237  VRBase = Reg;
238  MIB.addReg(VRBase, RegState::Define);
239  break;
240  }
241  }
242  }
243  }
244 
245  // Create the result registers for this node and add the result regs to
246  // the machine instruction.
247  if (VRBase == 0) {
248  assert(RC && "Isn't a register operand!");
249  VRBase = MRI->createVirtualRegister(RC);
250  MIB.addReg(VRBase, RegState::Define);
251  }
252 
253  // If this def corresponds to a result of the SDNode insert the VRBase into
254  // the lookup map.
255  if (i < NumResults) {
256  SDValue Op(Node, i);
257  if (IsClone)
258  VRBaseMap.erase(Op);
259  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
260  (void)isNew; // Silence compiler warning.
261  assert(isNew && "Node emitted out of order - early");
262  }
263  }
264 }
265 
266 /// getVR - Return the virtual register corresponding to the specified result
267 /// of the specified node.
268 Register InstrEmitter::getVR(SDValue Op,
269  DenseMap<SDValue, Register> &VRBaseMap) {
270  if (Op.isMachineOpcode() &&
271  Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
272  // Add an IMPLICIT_DEF instruction before every use.
273  // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
274  // does not include operand register class info.
275  const TargetRegisterClass *RC = TLI->getRegClassFor(
276  Op.getSimpleValueType(), Op.getNode()->isDivergent());
277  Register VReg = MRI->createVirtualRegister(RC);
278  BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
279  TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
280  return VReg;
281  }
282 
284  assert(I != VRBaseMap.end() && "Node emitted out of order - late");
285  return I->second;
286 }
287 
288 
289 /// AddRegisterOperand - Add the specified register as an operand to the
290 /// specified machine instr. Insert register copies if the register is
291 /// not in the required register class.
292 void
293 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
294  SDValue Op,
295  unsigned IIOpNum,
296  const MCInstrDesc *II,
297  DenseMap<SDValue, Register> &VRBaseMap,
298  bool IsDebug, bool IsClone, bool IsCloned) {
299  assert(Op.getValueType() != MVT::Other &&
300  Op.getValueType() != MVT::Glue &&
301  "Chain and glue operands should occur at end of operand list!");
302  // Get/emit the operand.
303  Register VReg = getVR(Op, VRBaseMap);
304 
305  const MCInstrDesc &MCID = MIB->getDesc();
306  bool isOptDef = IIOpNum < MCID.getNumOperands() &&
307  MCID.operands()[IIOpNum].isOptionalDef();
308 
309  // If the instruction requires a register in a different class, create
310  // a new virtual register and copy the value into it, but first attempt to
311  // shrink VReg's register class within reason. For example, if VReg == GR32
312  // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
313  if (II) {
314  const TargetRegisterClass *OpRC = nullptr;
315  if (IIOpNum < II->getNumOperands())
316  OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
317 
318  if (OpRC) {
319  unsigned MinNumRegs = MinRCSize;
320  // Don't apply any RC size limit for IMPLICIT_DEF. Each use has a unique
321  // virtual register.
322  if (Op.isMachineOpcode() &&
323  Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)
324  MinNumRegs = 0;
325 
326  const TargetRegisterClass *ConstrainedRC
327  = MRI->constrainRegClass(VReg, OpRC, MinNumRegs);
328  if (!ConstrainedRC) {
329  OpRC = TRI->getAllocatableClass(OpRC);
330  assert(OpRC && "Constraints cannot be fulfilled for allocation");
331  Register NewVReg = MRI->createVirtualRegister(OpRC);
332  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
333  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
334  VReg = NewVReg;
335  } else {
336  assert(ConstrainedRC->isAllocatable() &&
337  "Constraining an allocatable VReg produced an unallocatable class?");
338  }
339  }
340  }
341 
342  // If this value has only one use, that use is a kill. This is a
343  // conservative approximation. InstrEmitter does trivial coalescing
344  // with CopyFromReg nodes, so don't emit kill flags for them.
345  // Avoid kill flags on Schedule cloned nodes, since there will be
346  // multiple uses.
347  // Tied operands are never killed, so we need to check that. And that
348  // means we need to determine the index of the operand.
349  bool isKill = Op.hasOneUse() &&
350  Op.getNode()->getOpcode() != ISD::CopyFromReg &&
351  !IsDebug &&
352  !(IsClone || IsCloned);
353  if (isKill) {
354  unsigned Idx = MIB->getNumOperands();
355  while (Idx > 0 &&
356  MIB->getOperand(Idx-1).isReg() &&
357  MIB->getOperand(Idx-1).isImplicit())
358  --Idx;
359  bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
360  if (isTied)
361  isKill = false;
362  }
363 
364  MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
365  getDebugRegState(IsDebug));
366 }
367 
368 /// AddOperand - Add the specified operand to the specified machine instr. II
369 /// specifies the instruction information for the node, and IIOpNum is the
370 /// operand number (in the II) that we are adding.
371 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
372  SDValue Op,
373  unsigned IIOpNum,
374  const MCInstrDesc *II,
375  DenseMap<SDValue, Register> &VRBaseMap,
376  bool IsDebug, bool IsClone, bool IsCloned) {
377  if (Op.isMachineOpcode()) {
378  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
379  IsDebug, IsClone, IsCloned);
380  } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
381  MIB.addImm(C->getSExtValue());
382  } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
383  MIB.addFPImm(F->getConstantFPValue());
384  } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
385  Register VReg = R->getReg();
386  MVT OpVT = Op.getSimpleValueType();
387  const TargetRegisterClass *IIRC =
388  II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
389  : nullptr;
390  const TargetRegisterClass *OpRC =
391  TLI->isTypeLegal(OpVT)
392  ? TLI->getRegClassFor(OpVT,
393  Op.getNode()->isDivergent() ||
394  (IIRC && TRI->isDivergentRegClass(IIRC)))
395  : nullptr;
396 
397  if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) {
398  Register NewVReg = MRI->createVirtualRegister(IIRC);
399  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
400  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
401  VReg = NewVReg;
402  }
403  // Turn additional physreg operands into implicit uses on non-variadic
404  // instructions. This is used by call and return instructions passing
405  // arguments in registers.
406  bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
407  MIB.addReg(VReg, getImplRegState(Imp));
408  } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
409  MIB.addRegMask(RM->getRegMask());
410  } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
411  MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
412  TGA->getTargetFlags());
413  } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
414  MIB.addMBB(BBNode->getBasicBlock());
415  } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
416  MIB.addFrameIndex(FI->getIndex());
417  } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
418  MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
419  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
420  int Offset = CP->getOffset();
421  Align Alignment = CP->getAlign();
422 
423  unsigned Idx;
425  if (CP->isMachineConstantPoolEntry())
426  Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Alignment);
427  else
428  Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Alignment);
429  MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
430  } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
431  MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
432  } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
433  MIB.addSym(SymNode->getMCSymbol());
434  } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
435  MIB.addBlockAddress(BA->getBlockAddress(),
436  BA->getOffset(),
437  BA->getTargetFlags());
438  } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
439  MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
440  } else {
441  assert(Op.getValueType() != MVT::Other &&
442  Op.getValueType() != MVT::Glue &&
443  "Chain and glue operands should occur at end of operand list!");
444  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
445  IsDebug, IsClone, IsCloned);
446  }
447 }
448 
449 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
450  MVT VT, bool isDivergent, const DebugLoc &DL) {
451  const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
452  const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
453 
454  // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
455  // within reason.
456  if (RC && RC != VRC)
457  RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
458 
459  // VReg has been adjusted. It can be used with SubIdx operands now.
460  if (RC)
461  return VReg;
462 
463  // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
464  // register instead.
465  RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
466  assert(RC && "No legal register class for VT supports that SubIdx");
467  Register NewReg = MRI->createVirtualRegister(RC);
468  BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
469  .addReg(VReg);
470  return NewReg;
471 }
472 
473 /// EmitSubregNode - Generate machine code for subreg nodes.
474 ///
475 void InstrEmitter::EmitSubregNode(SDNode *Node,
476  DenseMap<SDValue, Register> &VRBaseMap,
477  bool IsClone, bool IsCloned) {
478  Register VRBase;
479  unsigned Opc = Node->getMachineOpcode();
480 
481  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
482  // the CopyToReg'd destination register instead of creating a new vreg.
483  for (SDNode *User : Node->uses()) {
484  if (User->getOpcode() == ISD::CopyToReg &&
485  User->getOperand(2).getNode() == Node) {
486  Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
487  if (DestReg.isVirtual()) {
488  VRBase = DestReg;
489  break;
490  }
491  }
492  }
493 
494  if (Opc == TargetOpcode::EXTRACT_SUBREG) {
495  // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
496  // constraints on the %dst register, COPY can target all legal register
497  // classes.
498  unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
499  const TargetRegisterClass *TRC =
500  TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
501 
502  Register Reg;
504  RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
505  if (R && R->getReg().isPhysical()) {
506  Reg = R->getReg();
507  DefMI = nullptr;
508  } else {
509  Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
510  DefMI = MRI->getVRegDef(Reg);
511  }
512 
513  Register SrcReg, DstReg;
514  unsigned DefSubIdx;
515  if (DefMI &&
516  TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
517  SubIdx == DefSubIdx &&
518  TRC == MRI->getRegClass(SrcReg)) {
519  // Optimize these:
520  // r1025 = s/zext r1024, 4
521  // r1026 = extract_subreg r1025, 4
522  // to a copy
523  // r1026 = copy r1024
524  VRBase = MRI->createVirtualRegister(TRC);
525  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
526  TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
527  MRI->clearKillFlags(SrcReg);
528  } else {
529  // Reg may not support a SubIdx sub-register, and we may need to
530  // constrain its register class or issue a COPY to a compatible register
531  // class.
532  if (Reg.isVirtual())
533  Reg = ConstrainForSubReg(Reg, SubIdx,
534  Node->getOperand(0).getSimpleValueType(),
535  Node->isDivergent(), Node->getDebugLoc());
536  // Create the destreg if it is missing.
537  if (!VRBase)
538  VRBase = MRI->createVirtualRegister(TRC);
539 
540  // Create the extract_subreg machine instruction.
541  MachineInstrBuilder CopyMI =
542  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
543  TII->get(TargetOpcode::COPY), VRBase);
544  if (Reg.isVirtual())
545  CopyMI.addReg(Reg, 0, SubIdx);
546  else
547  CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
548  }
549  } else if (Opc == TargetOpcode::INSERT_SUBREG ||
550  Opc == TargetOpcode::SUBREG_TO_REG) {
551  SDValue N0 = Node->getOperand(0);
552  SDValue N1 = Node->getOperand(1);
553  SDValue N2 = Node->getOperand(2);
554  unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
555 
556  // Figure out the register class to create for the destreg. It should be
557  // the largest legal register class supporting SubIdx sub-registers.
558  // RegisterCoalescer will constrain it further if it decides to eliminate
559  // the INSERT_SUBREG instruction.
560  //
561  // %dst = INSERT_SUBREG %src, %sub, SubIdx
562  //
563  // is lowered by TwoAddressInstructionPass to:
564  //
565  // %dst = COPY %src
566  // %dst:SubIdx = COPY %sub
567  //
568  // There is no constraint on the %src register class.
569  //
570  const TargetRegisterClass *SRC =
571  TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
572  SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
573  assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
574 
575  if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
576  VRBase = MRI->createVirtualRegister(SRC);
577 
578  // Create the insert_subreg or subreg_to_reg machine instruction.
579  MachineInstrBuilder MIB =
580  BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
581 
582  // If creating a subreg_to_reg, then the first input operand
583  // is an implicit value immediate, otherwise it's a register
584  if (Opc == TargetOpcode::SUBREG_TO_REG) {
585  const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
586  MIB.addImm(SD->getZExtValue());
587  } else
588  AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
589  IsClone, IsCloned);
590  // Add the subregister being inserted
591  AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
592  IsClone, IsCloned);
593  MIB.addImm(SubIdx);
594  MBB->insert(InsertPos, MIB);
595  } else
596  llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
597 
598  SDValue Op(Node, 0);
599  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
600  (void)isNew; // Silence compiler warning.
601  assert(isNew && "Node emitted out of order - early");
602 }
603 
604 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
605 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
606 /// register is constrained to be in a particular register class.
607 ///
608 void
609 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
610  DenseMap<SDValue, Register> &VRBaseMap) {
611  unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
612 
613  // Create the new VReg in the destination class and emit a copy.
614  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
615  const TargetRegisterClass *DstRC =
616  TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
617  Register NewVReg = MRI->createVirtualRegister(DstRC);
618  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
619  NewVReg).addReg(VReg);
620 
621  SDValue Op(Node, 0);
622  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
623  (void)isNew; // Silence compiler warning.
624  assert(isNew && "Node emitted out of order - early");
625 }
626 
627 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
628 ///
629 void InstrEmitter::EmitRegSequence(SDNode *Node,
630  DenseMap<SDValue, Register> &VRBaseMap,
631  bool IsClone, bool IsCloned) {
632  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
633  const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
634  Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
635  const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
636  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
637  unsigned NumOps = Node->getNumOperands();
638  // If the input pattern has a chain, then the root of the corresponding
639  // output pattern will get a chain as well. This can happen to be a
640  // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
641  if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
642  --NumOps; // Ignore chain if it exists.
643 
644  assert((NumOps & 1) == 1 &&
645  "REG_SEQUENCE must have an odd number of operands!");
646  for (unsigned i = 1; i != NumOps; ++i) {
647  SDValue Op = Node->getOperand(i);
648  if ((i & 1) == 0) {
649  RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
650  // Skip physical registers as they don't have a vreg to get and we'll
651  // insert copies for them in TwoAddressInstructionPass anyway.
652  if (!R || !R->getReg().isPhysical()) {
653  unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
654  unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
655  const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
656  const TargetRegisterClass *SRC =
657  TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
658  if (SRC && SRC != RC) {
659  MRI->setRegClass(NewVReg, SRC);
660  RC = SRC;
661  }
662  }
663  }
664  AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
665  IsClone, IsCloned);
666  }
667 
668  MBB->insert(InsertPos, MIB);
669  SDValue Op(Node, 0);
670  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
671  (void)isNew; // Silence compiler warning.
672  assert(isNew && "Node emitted out of order - early");
673 }
674 
675 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
676 ///
677 MachineInstr *
679  DenseMap<SDValue, Register> &VRBaseMap) {
680  DebugLoc DL = SD->getDebugLoc();
681  assert(cast<DILocalVariable>(SD->getVariable())
682  ->isValidLocationForIntrinsic(DL) &&
683  "Expected inlined-at fields to agree");
684 
685  SD->setIsEmitted();
686 
687  assert(!SD->getLocationOps().empty() &&
688  "dbg_value with no location operands?");
689 
690  if (SD->isInvalidated())
691  return EmitDbgNoLocation(SD);
692 
693  // Attempt to produce a DBG_INSTR_REF if we've been asked to.
694  if (EmitDebugInstrRefs)
695  if (auto *InstrRef = EmitDbgInstrRef(SD, VRBaseMap))
696  return InstrRef;
697 
698  // Emit variadic dbg_value nodes as DBG_VALUE_LIST if they have not been
699  // emitted as instruction references.
700  if (SD->isVariadic())
701  return EmitDbgValueList(SD, VRBaseMap);
702 
703  // Emit single-location dbg_value nodes as DBG_VALUE if they have not been
704  // emitted as instruction references.
705  return EmitDbgValueFromSingleOp(SD, VRBaseMap);
706 }
707 
709  const Value *V = Op.getConst();
710  if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
711  if (CI->getBitWidth() > 64)
712  return MachineOperand::CreateCImm(CI);
713  return MachineOperand::CreateImm(CI->getSExtValue());
714  }
715  if (const ConstantFP *CF = dyn_cast<ConstantFP>(V))
716  return MachineOperand::CreateFPImm(CF);
717  // Note: This assumes that all nullptr constants are zero-valued.
718  if (isa<ConstantPointerNull>(V))
719  return MachineOperand::CreateImm(0);
720  // Undef or unhandled value type, so return an undef operand.
722  /* Reg */ 0U, /* isDef */ false, /* isImp */ false,
723  /* isKill */ false, /* isDead */ false,
724  /* isUndef */ false, /* isEarlyClobber */ false,
725  /* SubReg */ 0, /* isDebug */ true);
726 }
727 
729  MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc,
730  ArrayRef<SDDbgOperand> LocationOps,
731  DenseMap<SDValue, Register> &VRBaseMap) {
732  for (const SDDbgOperand &Op : LocationOps) {
733  switch (Op.getKind()) {
735  MIB.addFrameIndex(Op.getFrameIx());
736  break;
737  case SDDbgOperand::VREG:
738  MIB.addReg(Op.getVReg());
739  break;
740  case SDDbgOperand::SDNODE: {
741  SDValue V = SDValue(Op.getSDNode(), Op.getResNo());
742  // It's possible we replaced this SDNode with other(s) and therefore
743  // didn't generate code for it. It's better to catch these cases where
744  // they happen and transfer the debug info, but trying to guarantee that
745  // in all cases would be very fragile; this is a safeguard for any
746  // that were missed.
747  if (VRBaseMap.count(V) == 0)
748  MIB.addReg(0U); // undef
749  else
750  AddOperand(MIB, V, (*MIB).getNumOperands(), &DbgValDesc, VRBaseMap,
751  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
752  } break;
753  case SDDbgOperand::CONST:
754  MIB.add(GetMOForConstDbgOp(Op));
755  break;
756  }
757  }
758 }
759 
760 MachineInstr *
762  DenseMap<SDValue, Register> &VRBaseMap) {
763  MDNode *Var = SD->getVariable();
764  const DIExpression *Expr = (DIExpression *)SD->getExpression();
765  DebugLoc DL = SD->getDebugLoc();
766  const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF);
767 
768  // Returns true if the given operand is not a legal debug operand for a
769  // DBG_INSTR_REF.
770  auto IsInvalidOp = [](SDDbgOperand DbgOp) {
771  return DbgOp.getKind() == SDDbgOperand::FRAMEIX;
772  };
773  // Returns true if the given operand is not itself an instruction reference
774  // but is a legal debug operand for a DBG_INSTR_REF.
775  auto IsNonInstrRefOp = [](SDDbgOperand DbgOp) {
776  return DbgOp.getKind() == SDDbgOperand::CONST;
777  };
778 
779  // If this variable location does not depend on any instructions or contains
780  // any stack locations, produce it as a standard debug value instead.
781  if (any_of(SD->getLocationOps(), IsInvalidOp) ||
782  all_of(SD->getLocationOps(), IsNonInstrRefOp)) {
783  if (SD->isVariadic())
784  return EmitDbgValueList(SD, VRBaseMap);
785  return EmitDbgValueFromSingleOp(SD, VRBaseMap);
786  }
787 
788  // Immediately fold any indirectness from the LLVM-IR intrinsic into the
789  // expression:
790  if (SD->isIndirect())
791  Expr = DIExpression::append(Expr, dwarf::DW_OP_deref);
792  // If this is not already a variadic expression, it must be modified to become
793  // one.
794  if (!SD->isVariadic())
796 
798 
799  // It may not be immediately possible to identify the MachineInstr that
800  // defines a VReg, it can depend for example on the order blocks are
801  // emitted in. When this happens, or when further analysis is needed later,
802  // produce an instruction like this:
803  //
804  // DBG_INSTR_REF !123, !456, %0:gr64
805  //
806  // i.e., point the instruction at the vreg, and patch it up later in
807  // MachineFunction::finalizeDebugInstrRefs.
808  auto AddVRegOp = [&](unsigned VReg) {
809  MOs.push_back(MachineOperand::CreateReg(
810  /* Reg */ VReg, /* isDef */ false, /* isImp */ false,
811  /* isKill */ false, /* isDead */ false,
812  /* isUndef */ false, /* isEarlyClobber */ false,
813  /* SubReg */ 0, /* isDebug */ true));
814  };
815  unsigned OpCount = SD->getLocationOps().size();
816  for (unsigned OpIdx = 0; OpIdx < OpCount; ++OpIdx) {
817  SDDbgOperand DbgOperand = SD->getLocationOps()[OpIdx];
818 
819  // Try to find both the defined register and the instruction defining it.
820  MachineInstr *DefMI = nullptr;
821  unsigned VReg;
822 
823  if (DbgOperand.getKind() == SDDbgOperand::VREG) {
824  VReg = DbgOperand.getVReg();
825 
826  // No definition means that block hasn't been emitted yet. Leave a vreg
827  // reference to be fixed later.
828  if (!MRI->hasOneDef(VReg)) {
829  AddVRegOp(VReg);
830  continue;
831  }
832 
833  DefMI = &*MRI->def_instr_begin(VReg);
834  } else if (DbgOperand.getKind() == SDDbgOperand::SDNODE) {
835  // Look up the corresponding VReg for the given SDNode, if any.
836  SDNode *Node = DbgOperand.getSDNode();
837  SDValue Op = SDValue(Node, DbgOperand.getResNo());
839  // No VReg -> produce a DBG_VALUE $noreg instead.
840  if (I == VRBaseMap.end())
841  break;
842 
843  // Try to pick out a defining instruction at this point.
844  VReg = getVR(Op, VRBaseMap);
845 
846  // Again, if there's no instruction defining the VReg right now, fix it up
847  // later.
848  if (!MRI->hasOneDef(VReg)) {
849  AddVRegOp(VReg);
850  continue;
851  }
852 
853  DefMI = &*MRI->def_instr_begin(VReg);
854  } else {
855  assert(DbgOperand.getKind() == SDDbgOperand::CONST);
856  MOs.push_back(GetMOForConstDbgOp(DbgOperand));
857  continue;
858  }
859 
860  // Avoid copy like instructions: they don't define values, only move them.
861  // Leave a virtual-register reference until it can be fixed up later, to
862  // find the underlying value definition.
863  if (DefMI->isCopyLike() || TII->isCopyInstr(*DefMI)) {
864  AddVRegOp(VReg);
865  continue;
866  }
867 
868  // Find the operand number which defines the specified VReg.
869  unsigned OperandIdx = 0;
870  for (const auto &MO : DefMI->operands()) {
871  if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)
872  break;
873  ++OperandIdx;
874  }
875  assert(OperandIdx < DefMI->getNumOperands());
876 
877  // Make the DBG_INSTR_REF refer to that instruction, and that operand.
878  unsigned InstrNum = DefMI->getDebugInstrNum();
879  MOs.push_back(MachineOperand::CreateDbgInstrRef(InstrNum, OperandIdx));
880  }
881 
882  // If we haven't created a valid MachineOperand for every DbgOp, abort and
883  // produce an undef DBG_VALUE.
884  if (MOs.size() != OpCount)
885  return EmitDbgNoLocation(SD);
886 
887  return BuildMI(*MF, DL, RefII, false, MOs, Var, Expr);
888 }
889 
891  // An invalidated SDNode must generate an undef DBG_VALUE: although the
892  // original value is no longer computed, earlier DBG_VALUEs live ranges
893  // must not leak into later code.
894  DIVariable *Var = SD->getVariable();
895  const DIExpression *Expr =
897  DebugLoc DL = SD->getDebugLoc();
898  const MCInstrDesc &Desc = TII->get(TargetOpcode::DBG_VALUE);
899  return BuildMI(*MF, DL, Desc, false, 0U, Var, Expr);
900 }
901 
902 MachineInstr *
904  DenseMap<SDValue, Register> &VRBaseMap) {
905  MDNode *Var = SD->getVariable();
906  DIExpression *Expr = SD->getExpression();
907  DebugLoc DL = SD->getDebugLoc();
908  // DBG_VALUE_LIST := "DBG_VALUE_LIST" var, expression, loc (, loc)*
909  const MCInstrDesc &DbgValDesc = TII->get(TargetOpcode::DBG_VALUE_LIST);
910  // Build the DBG_VALUE_LIST instruction base.
911  auto MIB = BuildMI(*MF, DL, DbgValDesc);
912  MIB.addMetadata(Var);
913  MIB.addMetadata(Expr);
914  AddDbgValueLocationOps(MIB, DbgValDesc, SD->getLocationOps(), VRBaseMap);
915  return &*MIB;
916 }
917 
918 MachineInstr *
920  DenseMap<SDValue, Register> &VRBaseMap) {
921  MDNode *Var = SD->getVariable();
922  DIExpression *Expr = SD->getExpression();
923  DebugLoc DL = SD->getDebugLoc();
924  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
925 
926  assert(SD->getLocationOps().size() == 1 &&
927  "Non variadic dbg_value should have only one location op");
928 
929  // See about constant-folding the expression.
930  // Copy the location operand in case we replace it.
931  SmallVector<SDDbgOperand, 1> LocationOps(1, SD->getLocationOps()[0]);
932  if (Expr && LocationOps[0].getKind() == SDDbgOperand::CONST) {
933  const Value *V = LocationOps[0].getConst();
934  if (auto *C = dyn_cast<ConstantInt>(V)) {
935  std::tie(Expr, C) = Expr->constantFold(C);
936  LocationOps[0] = SDDbgOperand::fromConst(C);
937  }
938  }
939 
940  // Emit non-variadic dbg_value nodes as DBG_VALUE.
941  // DBG_VALUE := "DBG_VALUE" loc, isIndirect, var, expr
942  auto MIB = BuildMI(*MF, DL, II);
943  AddDbgValueLocationOps(MIB, II, LocationOps, VRBaseMap);
944 
945  if (SD->isIndirect())
946  MIB.addImm(0U);
947  else
948  MIB.addReg(0U);
949 
950  return MIB.addMetadata(Var).addMetadata(Expr);
951 }
952 
953 MachineInstr *
955  MDNode *Label = SD->getLabel();
956  DebugLoc DL = SD->getDebugLoc();
957  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
958  "Expected inlined-at fields to agree");
959 
960  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
961  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
962  MIB.addMetadata(Label);
963 
964  return &*MIB;
965 }
966 
967 /// EmitMachineNode - Generate machine code for a target-specific node and
968 /// needed dependencies.
969 ///
970 void InstrEmitter::
971 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
972  DenseMap<SDValue, Register> &VRBaseMap) {
973  unsigned Opc = Node->getMachineOpcode();
974 
975  // Handle subreg insert/extract specially
976  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
977  Opc == TargetOpcode::INSERT_SUBREG ||
978  Opc == TargetOpcode::SUBREG_TO_REG) {
979  EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
980  return;
981  }
982 
983  // Handle COPY_TO_REGCLASS specially.
984  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
985  EmitCopyToRegClassNode(Node, VRBaseMap);
986  return;
987  }
988 
989  // Handle REG_SEQUENCE specially.
990  if (Opc == TargetOpcode::REG_SEQUENCE) {
991  EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
992  return;
993  }
994 
995  if (Opc == TargetOpcode::IMPLICIT_DEF)
996  // We want a unique VR for each IMPLICIT_DEF use.
997  return;
998 
999  const MCInstrDesc &II = TII->get(Opc);
1000  unsigned NumResults = CountResults(Node);
1001  unsigned NumDefs = II.getNumDefs();
1002  const MCPhysReg *ScratchRegs = nullptr;
1003 
1004  // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
1005  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
1006  // Stackmaps do not have arguments and do not preserve their calling
1007  // convention. However, to simplify runtime support, they clobber the same
1008  // scratch registers as AnyRegCC.
1009  unsigned CC = CallingConv::AnyReg;
1010  if (Opc == TargetOpcode::PATCHPOINT) {
1011  CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
1012  NumDefs = NumResults;
1013  }
1014  ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
1015  } else if (Opc == TargetOpcode::STATEPOINT) {
1016  NumDefs = NumResults;
1017  }
1018 
1019  unsigned NumImpUses = 0;
1020  unsigned NodeOperands =
1021  countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
1022  bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
1023  II.isVariadic() && II.variadicOpsAreDefs();
1024  bool HasPhysRegOuts = NumResults > NumDefs && !II.implicit_defs().empty() &&
1025  !HasVRegVariadicDefs;
1026 #ifndef NDEBUG
1027  unsigned NumMIOperands = NodeOperands + NumResults;
1028  if (II.isVariadic())
1029  assert(NumMIOperands >= II.getNumOperands() &&
1030  "Too few operands for a variadic node!");
1031  else
1032  assert(NumMIOperands >= II.getNumOperands() &&
1033  NumMIOperands <=
1034  II.getNumOperands() + II.implicit_defs().size() + NumImpUses &&
1035  "#operands for dag node doesn't match .td file!");
1036 #endif
1037 
1038  // Create the new machine instruction.
1039  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
1040 
1041  // Add result register values for things that are defined by this
1042  // instruction.
1043  if (NumResults) {
1044  CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
1045 
1046  // Transfer any IR flags from the SDNode to the MachineInstr
1047  MachineInstr *MI = MIB.getInstr();
1048  const SDNodeFlags Flags = Node->getFlags();
1049  if (Flags.hasNoSignedZeros())
1050  MI->setFlag(MachineInstr::MIFlag::FmNsz);
1051 
1052  if (Flags.hasAllowReciprocal())
1053  MI->setFlag(MachineInstr::MIFlag::FmArcp);
1054 
1055  if (Flags.hasNoNaNs())
1056  MI->setFlag(MachineInstr::MIFlag::FmNoNans);
1057 
1058  if (Flags.hasNoInfs())
1059  MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
1060 
1061  if (Flags.hasAllowContract())
1062  MI->setFlag(MachineInstr::MIFlag::FmContract);
1063 
1064  if (Flags.hasApproximateFuncs())
1065  MI->setFlag(MachineInstr::MIFlag::FmAfn);
1066 
1067  if (Flags.hasAllowReassociation())
1068  MI->setFlag(MachineInstr::MIFlag::FmReassoc);
1069 
1070  if (Flags.hasNoUnsignedWrap())
1071  MI->setFlag(MachineInstr::MIFlag::NoUWrap);
1072 
1073  if (Flags.hasNoSignedWrap())
1074  MI->setFlag(MachineInstr::MIFlag::NoSWrap);
1075 
1076  if (Flags.hasExact())
1077  MI->setFlag(MachineInstr::MIFlag::IsExact);
1078 
1079  if (Flags.hasNoFPExcept())
1080  MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
1081  }
1082 
1083  // Emit all of the actual operands of this instruction, adding them to the
1084  // instruction as appropriate.
1085  bool HasOptPRefs = NumDefs > NumResults;
1086  assert((!HasOptPRefs || !HasPhysRegOuts) &&
1087  "Unable to cope with optional defs and phys regs defs!");
1088  unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
1089  for (unsigned i = NumSkip; i != NodeOperands; ++i)
1090  AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
1091  VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
1092 
1093  // Add scratch registers as implicit def and early clobber
1094  if (ScratchRegs)
1095  for (unsigned i = 0; ScratchRegs[i]; ++i)
1096  MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
1098 
1099  // Set the memory reference descriptions of this instruction now that it is
1100  // part of the function.
1101  MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
1102 
1103  // Set the CFI type.
1104  MIB->setCFIType(*MF, Node->getCFIType());
1105 
1106  // Insert the instruction into position in the block. This needs to
1107  // happen before any custom inserter hook is called so that the
1108  // hook knows where in the block to insert the replacement code.
1109  MBB->insert(InsertPos, MIB);
1110 
1111  // The MachineInstr may also define physregs instead of virtregs. These
1112  // physreg values can reach other instructions in different ways:
1113  //
1114  // 1. When there is a use of a Node value beyond the explicitly defined
1115  // virtual registers, we emit a CopyFromReg for one of the implicitly
1116  // defined physregs. This only happens when HasPhysRegOuts is true.
1117  //
1118  // 2. A CopyFromReg reading a physreg may be glued to this instruction.
1119  //
1120  // 3. A glued instruction may implicitly use a physreg.
1121  //
1122  // 4. A glued instruction may use a RegisterSDNode operand.
1123  //
1124  // Collect all the used physreg defs, and make sure that any unused physreg
1125  // defs are marked as dead.
1126  SmallVector<Register, 8> UsedRegs;
1127 
1128  // Additional results must be physical register defs.
1129  if (HasPhysRegOuts) {
1130  for (unsigned i = NumDefs; i < NumResults; ++i) {
1131  Register Reg = II.implicit_defs()[i - NumDefs];
1132  if (!Node->hasAnyUseOfValue(i))
1133  continue;
1134  // This implicitly defined physreg has a use.
1135  UsedRegs.push_back(Reg);
1136  EmitCopyFromReg(Node, i, IsClone, Reg, VRBaseMap);
1137  }
1138  }
1139 
1140  // Scan the glue chain for any used physregs.
1141  if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
1142  for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
1143  if (F->getOpcode() == ISD::CopyFromReg) {
1144  UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
1145  continue;
1146  } else if (F->getOpcode() == ISD::CopyToReg) {
1147  // Skip CopyToReg nodes that are internal to the glue chain.
1148  continue;
1149  }
1150  // Collect declared implicit uses.
1151  const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
1152  append_range(UsedRegs, MCID.implicit_uses());
1153  // In addition to declared implicit uses, we must also check for
1154  // direct RegisterSDNode operands.
1155  for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
1156  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
1157  Register Reg = R->getReg();
1158  if (Reg.isPhysical())
1159  UsedRegs.push_back(Reg);
1160  }
1161  }
1162  }
1163 
1164  // Add rounding control registers as implicit def for function call.
1165  if (II.isCall() && MF->getFunction().hasFnAttribute(Attribute::StrictFP)) {
1166  const MCPhysReg *RCRegs = TLI->getRoundingControlRegisters();
1167  if (RCRegs)
1168  for (; *RCRegs; ++RCRegs)
1169  UsedRegs.push_back(*RCRegs);
1170  }
1171 
1172  // Finally mark unused registers as dead.
1173  if (!UsedRegs.empty() || !II.implicit_defs().empty() || II.hasOptionalDef())
1174  MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
1175 
1176  // STATEPOINT is too 'dynamic' to have meaningful machine description.
1177  // We have to manually tie operands.
1178  if (Opc == TargetOpcode::STATEPOINT && NumDefs > 0) {
1179  assert(!HasPhysRegOuts && "STATEPOINT mishandled");
1180  MachineInstr *MI = MIB;
1181  unsigned Def = 0;
1183  assert(First > 0 && "Statepoint has Defs but no GC ptr list");
1184  unsigned Use = (unsigned)First;
1185  while (Def < NumDefs) {
1186  if (MI->getOperand(Use).isReg())
1187  MI->tieOperands(Def++, Use);
1189  }
1190  }
1191 
1192  // Run post-isel target hook to adjust this instruction if needed.
1193  if (II.hasPostISelHook())
1194  TLI->AdjustInstrPostInstrSelection(*MIB, Node);
1195 }
1196 
1197 /// EmitSpecialNode - Generate machine code for a target-independent node and
1198 /// needed dependencies.
1199 void InstrEmitter::
1200 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
1201  DenseMap<SDValue, Register> &VRBaseMap) {
1202  switch (Node->getOpcode()) {
1203  default:
1204 #ifndef NDEBUG
1205  Node->dump();
1206 #endif
1207  llvm_unreachable("This target-independent node should have been selected!");
1208  case ISD::EntryToken:
1209  case ISD::MERGE_VALUES:
1210  case ISD::TokenFactor: // fall thru
1211  break;
1212  case ISD::CopyToReg: {
1213  Register DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1214  SDValue SrcVal = Node->getOperand(2);
1215  if (DestReg.isVirtual() && SrcVal.isMachineOpcode() &&
1216  SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
1217  // Instead building a COPY to that vreg destination, build an
1218  // IMPLICIT_DEF instruction instead.
1219  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1220  TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1221  break;
1222  }
1223  Register SrcReg;
1224  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
1225  SrcReg = R->getReg();
1226  else
1227  SrcReg = getVR(SrcVal, VRBaseMap);
1228 
1229  if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1230  break;
1231 
1232  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1233  DestReg).addReg(SrcReg);
1234  break;
1235  }
1236  case ISD::CopyFromReg: {
1237  unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1238  EmitCopyFromReg(Node, 0, IsClone, SrcReg, VRBaseMap);
1239  break;
1240  }
1241  case ISD::EH_LABEL:
1242  case ISD::ANNOTATION_LABEL: {
1243  unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1246  MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1247  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1248  TII->get(Opc)).addSym(S);
1249  break;
1250  }
1251 
1252  case ISD::LIFETIME_START:
1253  case ISD::LIFETIME_END: {
1254  unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START)
1257  auto *FI = cast<FrameIndexSDNode>(Node->getOperand(1));
1258  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1259  .addFrameIndex(FI->getIndex());
1260  break;
1261  }
1262 
1263  case ISD::PSEUDO_PROBE: {
1264  unsigned TarOp = TargetOpcode::PSEUDO_PROBE;
1265  auto Guid = cast<PseudoProbeSDNode>(Node)->getGuid();
1266  auto Index = cast<PseudoProbeSDNode>(Node)->getIndex();
1267  auto Attr = cast<PseudoProbeSDNode>(Node)->getAttributes();
1268 
1269  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1270  .addImm(Guid)
1271  .addImm(Index)
1272  .addImm((uint8_t)PseudoProbeType::Block)
1273  .addImm(Attr);
1274  break;
1275  }
1276 
1277  case ISD::INLINEASM:
1278  case ISD::INLINEASM_BR: {
1279  unsigned NumOps = Node->getNumOperands();
1280  if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1281  --NumOps; // Ignore the glue operand.
1282 
1283  // Create the inline asm machine instruction.
1284  unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1287  MachineInstrBuilder MIB =
1288  BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1289 
1290  // Add the asm string as an external symbol operand.
1291  SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1292  const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1293  MIB.addExternalSymbol(AsmStr);
1294 
1295  // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1296  // bits.
1297  int64_t ExtraInfo =
1298  cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1299  getZExtValue();
1300  MIB.addImm(ExtraInfo);
1301 
1302  // Remember to operand index of the group flags.
1303  SmallVector<unsigned, 8> GroupIdx;
1304 
1305  // Remember registers that are part of early-clobber defs.
1306  SmallVector<unsigned, 8> ECRegs;
1307 
1308  // Add all of the operand registers to the instruction.
1309  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1310  unsigned Flags =
1311  cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1312  const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1313 
1314  GroupIdx.push_back(MIB->getNumOperands());
1315  MIB.addImm(Flags);
1316  ++i; // Skip the ID value.
1317 
1318  switch (InlineAsm::getKind(Flags)) {
1319  default: llvm_unreachable("Bad flags!");
1321  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1322  Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1323  // FIXME: Add dead flags for physical and virtual registers defined.
1324  // For now, mark physical register defs as implicit to help fast
1325  // regalloc. This makes inline asm look a lot like calls.
1326  MIB.addReg(Reg, RegState::Define | getImplRegState(Reg.isPhysical()));
1327  }
1328  break;
1331  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1332  Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1334  getImplRegState(Reg.isPhysical()));
1335  ECRegs.push_back(Reg);
1336  }
1337  break;
1338  case InlineAsm::Kind_RegUse: // Use of register.
1339  case InlineAsm::Kind_Imm: // Immediate.
1340  case InlineAsm::Kind_Mem: // Non-function addressing mode.
1341  // The addressing mode has been selected, just add all of the
1342  // operands to the machine instruction.
1343  for (unsigned j = 0; j != NumVals; ++j, ++i)
1344  AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1345  /*IsDebug=*/false, IsClone, IsCloned);
1346 
1347  // Manually set isTied bits.
1349  unsigned DefGroup = 0;
1350  if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1351  unsigned DefIdx = GroupIdx[DefGroup] + 1;
1352  unsigned UseIdx = GroupIdx.back() + 1;
1353  for (unsigned j = 0; j != NumVals; ++j)
1354  MIB->tieOperands(DefIdx + j, UseIdx + j);
1355  }
1356  }
1357  break;
1358  case InlineAsm::Kind_Func: // Function addressing mode.
1359  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1360  SDValue Op = Node->getOperand(i);
1361  AddOperand(MIB, Op, 0, nullptr, VRBaseMap,
1362  /*IsDebug=*/false, IsClone, IsCloned);
1363 
1364  // Adjust Target Flags for function reference.
1365  if (auto *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
1366  unsigned NewFlags =
1368  TGA->getGlobal());
1369  unsigned LastIdx = MIB.getInstr()->getNumOperands() - 1;
1370  MIB.getInstr()->getOperand(LastIdx).setTargetFlags(NewFlags);
1371  }
1372  }
1373  }
1374  }
1375 
1376  // GCC inline assembly allows input operands to also be early-clobber
1377  // output operands (so long as the operand is written only after it's
1378  // used), but this does not match the semantics of our early-clobber flag.
1379  // If an early-clobber operand register is also an input operand register,
1380  // then remove the early-clobber flag.
1381  for (unsigned Reg : ECRegs) {
1382  if (MIB->readsRegister(Reg, TRI)) {
1383  MachineOperand *MO =
1384  MIB->findRegisterDefOperand(Reg, false, false, TRI);
1385  assert(MO && "No def operand for clobbered register?");
1386  MO->setIsEarlyClobber(false);
1387  }
1388  }
1389 
1390  // Get the mdnode from the asm if it exists and add it to the instruction.
1391  SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1392  const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1393  if (MD)
1394  MIB.addMetadata(MD);
1395 
1396  MBB->insert(InsertPos, MIB);
1397  break;
1398  }
1399  }
1400 }
1401 
1402 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1403 /// at the given position in the given block.
1405  MachineBasicBlock::iterator insertpos)
1406  : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1407  TII(MF->getSubtarget().getInstrInfo()),
1408  TRI(MF->getSubtarget().getRegisterInfo()),
1409  TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1410  InsertPos(insertpos) {
1411  EmitDebugInstrRefs = mbb->getParent()->useDebugInstrRef();
1412 }
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:636
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:247
llvm::SDDbgValue::getExpression
DIExpression * getExpression() const
Returns the DIExpression pointer for the expression.
Definition: SDNodeDbgValue.h:183
llvm::InlineAsm::Kind_Imm
@ Kind_Imm
Definition: InlineAsm.h:244
llvm::SDDbgValue
Holds the information from a dbg_value node through SDISel.
Definition: SDNodeDbgValue.h:133
llvm::SDDbgOperand::fromConst
static SDDbgOperand fromConst(const Value *Const)
Definition: SDNodeDbgValue.h:80
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1586
llvm::RegisterSDNode
Definition: SelectionDAGNodes.h:2165
llvm::TargetLowering::getRoundingControlRegisters
virtual const MCPhysReg * getRoundingControlRegisters() const
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
Definition: TargetLowering.h:4493
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:2055
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2370
llvm::TargetInstrInfo::isCopyInstr
std::optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: TargetInstrInfo.h:1035
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::MachineConstantPool::getConstantPoolIndex
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
Definition: MachineFunction.cpp:1442
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::TargetLowering::getScratchRegisters
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Definition: TargetLowering.h:4487
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::ISD::PATCHPOINT
@ PATCHPOINT
Definition: ISDOpcodes.h:1303
llvm::MachineInstrBuilder::addFPImm
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Definition: MachineInstrBuilder.h:141
llvm::DIExpression::convertToVariadicExpression
static const DIExpression * convertToVariadicExpression(const DIExpression *Expr)
If Expr is a non-variadic expression (i.e.
Definition: DebugInfoMetadata.cpp:1476
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:830
llvm::ISD::LIFETIME_END
@ LIFETIME_END
Definition: ISDOpcodes.h:1229
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:157
llvm::MachineOperand::CreateDbgInstrRef
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
Definition: MachineOperand.h:952
DebugInfoMetadata.h
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:120
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::ISD::LIFETIME_START
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1228
llvm::LLVMTargetMachine::usesPhysRegsForValues
virtual bool usesPhysRegsForValues() const
True if the target uses physical regs (as nearly all targets do).
Definition: TargetMachine.h:492
llvm::InlineAsm::Op_MDNode
@ Op_MDNode
Definition: InlineAsm.h:220
llvm::MachineRegisterInfo::def_instr_begin
def_instr_iterator def_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:419
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::MachineFunction::useDebugInstrRef
bool useDebugInstrRef() const
Returns true if the function's variable locations are tracked with instruction referencing.
Definition: MachineFunction.cpp:1216
llvm::SDDbgOperand::getResNo
unsigned getResNo() const
Returns the ResNo for a register ref.
Definition: SDNodeDbgValue.h:48
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:1032
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::MCInstrDesc::operands
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
llvm::InlineAsm::Op_ExtraInfo
@ Op_ExtraInfo
Definition: InlineAsm.h:221
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:282
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::erase
bool erase(const KeyT &Val)
Definition: DenseMap.h:302
llvm::TargetRegisterClass::getCopyCost
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
Definition: TargetRegisterInfo.h:116
llvm::DenseMapIterator
Definition: DenseMap.h:57
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:513
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:369
llvm::InstrEmitter::InstrEmitter
InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
Definition: InstrEmitter.cpp:1404
LiveDebugValues::DbgOp
TODO: Might pack better if we changed this to a Struct of Arrays, since MachineOperand is width 32,...
Definition: InstrRefBasedImpl.h:282
TargetInstrInfo.h
llvm::InlineAsm::Kind_RegDef
@ Kind_RegDef
Definition: InlineAsm.h:241
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
llvm::InstrEmitter::CountResults
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first,...
Definition: InstrEmitter.cpp:43
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
llvm::SDDbgOperand
Holds the information for a single machine location through SDISel; either an SDNode,...
Definition: SDNodeDbgValue.h:31
llvm::DiagnosticPredicateTy::Match
@ Match
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2611
SDNodeDbgValue.h
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2199
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
GetMOForConstDbgOp
MachineOperand GetMOForConstDbgOp(const SDDbgOperand &Op)
Definition: InstrEmitter.cpp:708
llvm::InlineAsm::Kind_RegDefEarlyClobber
@ Kind_RegDefEarlyClobber
Definition: InlineAsm.h:242
llvm::SDDbgValue::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
Definition: SDNodeDbgValue.h:215
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:275
llvm::MCInstrDesc::hasPostISelHook
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MCInstrDesc.h:516
MachineRegisterInfo.h
llvm::InstrEmitter::AddDbgValueLocationOps
void AddDbgValueLocationOps(MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, ArrayRef< SDDbgOperand > Locations, DenseMap< SDValue, Register > &VRBaseMap)
Definition: InstrEmitter.cpp:728
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1024
llvm::ISD::PSEUDO_PROBE
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
Definition: ISDOpcodes.h:1248
llvm::SDDbgOperand::getVReg
unsigned getVReg() const
Returns the Virtual Register for a VReg.
Definition: SDNodeDbgValue.h:66
llvm::TargetLowering::AdjustInstrPostInstrSelection
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition: SelectionDAGISel.cpp:305
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
TargetLowering.h
llvm::TargetInstrInfo::getRegClass
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Definition: TargetInstrInfo.cpp:46
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:525
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1735
llvm::InstrEmitter::EmitDbgNoLocation
MachineInstr * EmitDbgNoLocation(SDDbgValue *SD)
Emit a DBG_VALUE $noreg, indicating a variable has no location.
Definition: InstrEmitter.cpp:890
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:386
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2241
TargetMachine.h
llvm::SDDbgLabel
Holds the information from a dbg_label node through SDISel.
Definition: SDNodeDbgValue.h:242
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
countOperands
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
Definition: InstrEmitter.cpp:59
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:812
llvm::User
Definition: User.h:44
llvm::ISD::CopyToReg
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Definition: ISDOpcodes.h:203
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1866
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::SDDbgValue::isIndirect
bool isIndirect() const
Returns whether this is an indirect value.
Definition: SDNodeDbgValue.h:210
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::dwarf::Index
Index
Definition: Dwarf.h:550
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::SDDbgOperand::VREG
@ VREG
Value is a virtual register.
Definition: SDNodeDbgValue.h:37
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:256
llvm::FrameIndexSDNode
Definition: SelectionDAGNodes.h:1789
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:303
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition: MachineOperand.h:229
llvm::ISD::EntryToken
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:47
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:398
llvm::ISD::CopyFromReg
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:208
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:351
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RegisterMaskSDNode
Definition: SelectionDAGNodes.h:2181
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::TargetInstrInfo::isCoalescableExtInstr
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Definition: TargetInstrInfo.h:255
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:661
llvm::CallingConv::AnyReg
@ AnyReg
Used for dynamic register based calls (e.g.
Definition: CallingConv.h:60
llvm::DIExpression::append
static DIExpression * append(const DIExpression *Expr, ArrayRef< uint64_t > Ops)
Append the opcodes Ops to DIExpr.
Definition: DebugInfoMetadata.cpp:1738
llvm::InlineAsm::Op_AsmString
@ Op_AsmString
Definition: InlineAsm.h:219
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineRegisterInfo::clearKillFlags
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Definition: MachineRegisterInfo.cpp:435
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:672
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:640
llvm::SDValue::getNumOperands
unsigned getNumOperands() const
Definition: SelectionDAGNodes.h:1145
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:778
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:326
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::SDDbgLabel::getLabel
MDNode * getLabel() const
Returns the MDNode pointer for the label.
Definition: SDNodeDbgValue.h:252
llvm::ConstantFPSDNode
Definition: SelectionDAGNodes.h:1635
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:936
llvm::RegState::EarlyClobber
@ EarlyClobber
Register definition happens before uses.
Definition: MachineInstrBuilder.h:54
llvm::MCInstrDesc::isCall
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:287
llvm::InstrEmitter::EmitDbgLabel
MachineInstr * EmitDbgLabel(SDDbgLabel *SD)
Generate machine instruction for a dbg_label node.
Definition: InstrEmitter.cpp:954
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:31
llvm::MCInstrDesc::implicit_uses
ArrayRef< MCPhysReg > implicit_uses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:565
llvm::DenseMap
Definition: DenseMap.h:714
llvm::MachineConstantPool
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
Definition: MachineConstantPool.h:117
llvm::SDDbgOperand::getKind
Kind getKind() const
Definition: SDNodeDbgValue.h:39
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::InlineAsm::Op_FirstOperand
@ Op_FirstOperand
Definition: InlineAsm.h:222
llvm::PatchPointOpers::CCPos
@ CCPos
Definition: StackMaps.h:79
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:240
MachineConstantPool.h
llvm::BasicBlockSDNode
Definition: SelectionDAGNodes.h:1971
llvm::SDDbgValue::isInvalidated
bool isInvalidated() const
Definition: SDNodeDbgValue.h:225
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
llvm::TargetSubtargetInfo::classifyGlobalFunctionReference
virtual unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const
Classify a global function reference.
Definition: TargetSubtargetInfo.h:318
llvm::MachineFunction::getConstantPool
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
Definition: MachineFunction.h:704
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::ConstantSDNode::getZExtValue
uint64_t getZExtValue() const
Definition: SelectionDAGNodes.h:1601
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:265
llvm::ISD::STACKMAP
@ STACKMAP
Definition: ISDOpcodes.h:1297
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:289
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineRegisterInfo::hasOneDef
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
Definition: MachineRegisterInfo.h:466
llvm::StackMaps::getNextMetaArgIdx
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:171
llvm::MDNode
Metadata node.
Definition: Metadata.h:943
llvm::MachineInstr::readsRegister
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1398
llvm::ISD::ANNOTATION_LABEL
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:1038
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:499
llvm::MCInstrDesc::implicit_defs
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:577
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1887
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1742
Dwarf.h
llvm::InstrEmitter::EmitDbgInstrRef
MachineInstr * EmitDbgInstrRef(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a dbg_value as a DBG_INSTR_REF.
Definition: InstrEmitter.cpp:761
llvm::MachineInstrBuilder::addJumpTableIndex
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:171
llvm::MachineOperand::setIsEarlyClobber
void setIsEarlyClobber(bool Val=true)
Definition: MachineOperand.h:539
llvm::Offset
@ Offset
Definition: DWP.cpp:406
llvm::SDValue::getMachineOpcode
unsigned getMachineOpcode() const
Definition: SelectionDAGNodes.h:1173
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::SDDbgOperand::getSDNode
SDNode * getSDNode() const
Returns the SDNode* for a register ref.
Definition: SDNodeDbgValue.h:42
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition: TargetRegisterInfo.h:296
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:806
llvm::append_range
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
Definition: STLExtras.h:2014
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
InstrEmitter.h
llvm::DIExpression::convertToUndefExpression
static const DIExpression * convertToUndefExpression(const DIExpression *Expr)
Removes all elements from Expr that do not apply to an undef debug value, which includes every operat...
Definition: DebugInfoMetadata.cpp:1466
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::MachineInstrBuilder::addBlockAddress
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:190
llvm::MachineOperand::CreateCImm
static MachineOperand CreateCImm(const ConstantInt *CI)
Definition: MachineOperand.h:818
llvm::MCInstrDesc::variadicOpsAreDefs
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Definition: MCInstrDesc.h:417
llvm::DIVariable
Base class for variables.
Definition: DebugInfoMetadata.h:2545
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::insert
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:207
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::StatepointOpers::getFirstGCPtrIdx
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:125
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
j
return j(j<< 16)
llvm::SDDbgValue::isVariadic
bool isVariadic() const
Definition: SDNodeDbgValue.h:212
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::SDDbgLabel::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
Definition: SDNodeDbgValue.h:255
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1763
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:638
llvm::getDebugRegState
unsigned getDebugRegState(bool B)
Definition: MachineInstrBuilder.h:543
llvm::MachineInstr::isCopyLike
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:1358
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:668
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end
iterator end()
Definition: DenseMap.h:84
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:354
llvm::MCInstrDesc::hasOptionalDef
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:264
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1336
llvm::MachineInstrBuilder::addConstantPoolIndex
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:158
llvm::TargetIndexSDNode
Completely target-dependent object reference.
Definition: SelectionDAGNodes.h:1950
llvm::TargetRegisterInfo::isDivergentRegClass
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
Definition: TargetRegisterInfo.h:556
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1027
llvm::DIExpression::constantFold
std::pair< DIExpression *, const ConstantInt * > constantFold(const ConstantInt *CI)
Try to shorten an expression with an initial constant operand.
Definition: DebugInfoMetadata.cpp:1858
llvm::SDDbgOperand::SDNODE
@ SDNODE
Value is the result of an expression.
Definition: SDNodeDbgValue.h:34
llvm::MCInstrDesc::isVariadic
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:260
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
StackMaps.h
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition: MachineInstrBuilder.h:208
PseudoProbe.h
MinRCSize
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers.
Definition: InstrEmitter.cpp:38
llvm::SDNodeFlags
These are IR-level optimization flags that may be propagated to SDNodes.
Definition: SelectionDAGNodes.h:379
llvm::InstrEmitter::EmitDbgValueList
MachineInstr * EmitDbgValueList(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a DBG_VALUE_LIST from the operands to SDDbgValue.
Definition: InstrEmitter.cpp:903
llvm::MachineInstrBuilder::addTargetIndex
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:164
llvm::SDDbgValue::getVariable
DIVariable * getVariable() const
Returns the DIVariable pointer for the variable.
Definition: SDNodeDbgValue.h:180
llvm::SDDbgValue::getLocationOps
ArrayRef< SDDbgOperand > getLocationOps() const
Definition: SDNodeDbgValue.h:185
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:177
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:531
llvm::PseudoProbeType::Block
@ Block
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:267
llvm::User::getNumOperands
unsigned getNumOperands() const
Definition: User.h:191
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
MachineInstrBuilder.h
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:363
N
#define N
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:108
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:519
llvm::SDDbgOperand::FRAMEIX
@ FRAMEIX
Value is contents of a stack location.
Definition: SDNodeDbgValue.h:36
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:885
llvm::TargetRegisterInfo::getAllocatableClass
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
Definition: TargetRegisterInfo.cpp:195
llvm::MachineInstr::setCFIType
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
Definition: MachineInstr.cpp:505
llvm::SDDbgOperand::CONST
@ CONST
Value is a constant.
Definition: SDNodeDbgValue.h:35
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:83
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1149
llvm::InlineAsm::Kind_Func
@ Kind_Func
Definition: InlineAsm.h:246
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:129
llvm::omp::RTLDependInfoFields::Flags
@ Flags
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:36
RN
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR RN
Definition: README_P9.txt:262
llvm::InstrEmitter::EmitDbgValueFromSingleOp
MachineInstr * EmitDbgValueFromSingleOp(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a DBG_VALUE from the operands to SDDbgValue.
Definition: InstrEmitter.cpp:919
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SDDbgValue::setIsEmitted
void setIsEmitted()
setIsEmitted / isEmitted - Getter/Setter for flag indicating that this SDDbgValue has been emitted to...
Definition: SDNodeDbgValue.h:229
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::InlineAsm::Kind_Clobber
@ Kind_Clobber
Definition: InlineAsm.h:243
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
MachineFunction.h
llvm::MachineInstr::tieOperands
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
Definition: MachineInstr.cpp:1107
llvm::SDValue::isMachineOpcode
bool isMachineOpcode() const
Definition: SelectionDAGNodes.h:1169
llvm::MachineInstr::findRegisterDefOperand
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:1487
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCInstrDesc::getOperandConstraint
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:219
llvm::getImplRegState
unsigned getImplRegState(bool B)
Definition: MachineInstrBuilder.h:528
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:641
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::MachineOperand::CreateFPImm
static MachineOperand CreateFPImm(const ConstantFP *CFP)
Definition: MachineOperand.h:824
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:57
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::InlineAsm::Kind_Mem
@ Kind_Mem
Definition: InlineAsm.h:245
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::InstrEmitter::EmitDbgValue
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
Definition: InstrEmitter.cpp:678