LLVM 20.0.0git
InstrEmitter.cpp
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1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the Emit routines for the SelectionDAG class, which creates
10// MachineInstrs based on the decisions of the SelectionDAG instruction
11// selection.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrEmitter.h"
16#include "SDNodeDbgValue.h"
27#include "llvm/IR/PseudoProbe.h"
30using namespace llvm;
31
32#define DEBUG_TYPE "instr-emitter"
33
34/// MinRCSize - Smallest register class we allow when constraining virtual
35/// registers. If satisfying all register class constraints would require
36/// using a smaller register class, emit a COPY to a new virtual register
37/// instead.
38const unsigned MinRCSize = 4;
39
40/// CountResults - The results of target nodes have register or immediate
41/// operands first, then an optional chain, and optional glue operands (which do
42/// not go into the resulting MachineInstr).
44 unsigned N = Node->getNumValues();
45 while (N && Node->getValueType(N - 1) == MVT::Glue)
46 --N;
47 if (N && Node->getValueType(N - 1) == MVT::Other)
48 --N; // Skip over chain result.
49 return N;
50}
51
52/// countOperands - The inputs to target nodes have any actual inputs first,
53/// followed by an optional chain operand, then an optional glue operand.
54/// Compute the number of actual operands that will go into the resulting
55/// MachineInstr.
56///
57/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
58/// the chain and glue. These operands may be implicit on the machine instr.
59static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
60 unsigned &NumImpUses) {
61 unsigned N = Node->getNumOperands();
62 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
63 --N;
64 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
65 --N; // Ignore chain if it exists.
66
67 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
68 NumImpUses = N - NumExpUses;
69 for (unsigned I = N; I > NumExpUses; --I) {
70 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
71 continue;
72 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
73 if (RN->getReg().isPhysical())
74 continue;
75 NumImpUses = N - I;
76 break;
77 }
78
79 return N;
80}
81
82/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
83/// implicit physical register output.
84void InstrEmitter::EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
85 Register SrcReg, VRBaseMapType &VRBaseMap) {
86 Register VRBase;
87 if (SrcReg.isVirtual()) {
88 // Just use the input register directly!
89 SDValue Op(Node, ResNo);
90 if (IsClone)
91 VRBaseMap.erase(Op);
92 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
93 (void)isNew; // Silence compiler warning.
94 assert(isNew && "Node emitted out of order - early");
95 return;
96 }
97
98 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
99 // the CopyToReg'd destination register instead of creating a new vreg.
100 bool MatchReg = true;
101 const TargetRegisterClass *UseRC = nullptr;
102 MVT VT = Node->getSimpleValueType(ResNo);
103
104 // Stick to the preferred register classes for legal types.
105 if (TLI->isTypeLegal(VT))
106 UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
107
108 for (SDNode *User : Node->users()) {
109 bool Match = true;
110 if (User->getOpcode() == ISD::CopyToReg &&
111 User->getOperand(2).getNode() == Node &&
112 User->getOperand(2).getResNo() == ResNo) {
113 Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
114 if (DestReg.isVirtual()) {
115 VRBase = DestReg;
116 Match = false;
117 } else if (DestReg != SrcReg)
118 Match = false;
119 } else {
120 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
122 if (Op.getNode() != Node || Op.getResNo() != ResNo)
123 continue;
124 MVT VT = Node->getSimpleValueType(Op.getResNo());
125 if (VT == MVT::Other || VT == MVT::Glue)
126 continue;
127 Match = false;
128 if (User->isMachineOpcode()) {
129 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
130 const TargetRegisterClass *RC = nullptr;
131 if (i + II.getNumDefs() < II.getNumOperands()) {
132 RC = TRI->getAllocatableClass(
133 TII->getRegClass(II, i + II.getNumDefs(), TRI, *MF));
134 }
135 if (!UseRC)
136 UseRC = RC;
137 else if (RC) {
138 const TargetRegisterClass *ComRC =
139 TRI->getCommonSubClass(UseRC, RC);
140 // If multiple uses expect disjoint register classes, we emit
141 // copies in AddRegisterOperand.
142 if (ComRC)
143 UseRC = ComRC;
144 }
145 }
146 }
147 }
148 MatchReg &= Match;
149 if (VRBase)
150 break;
151 }
152
153 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
154 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
155
156 // Figure out the register class to create for the destreg.
157 if (VRBase) {
158 DstRC = MRI->getRegClass(VRBase);
159 } else if (UseRC) {
160 assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
161 "Incompatible phys register def and uses!");
162 DstRC = UseRC;
163 } else
164 DstRC = SrcRC;
165
166 // If all uses are reading from the src physical register and copying the
167 // register is either impossible or very expensive, then don't create a copy.
168 if (MatchReg && SrcRC->getCopyCost() < 0) {
169 VRBase = SrcReg;
170 } else {
171 // Create the reg, emit the copy.
172 VRBase = MRI->createVirtualRegister(DstRC);
173 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
174 VRBase).addReg(SrcReg);
175 }
176
177 SDValue Op(Node, ResNo);
178 if (IsClone)
179 VRBaseMap.erase(Op);
180 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
181 (void)isNew; // Silence compiler warning.
182 assert(isNew && "Node emitted out of order - early");
183}
184
185void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
187 const MCInstrDesc &II,
188 bool IsClone, bool IsCloned,
189 VRBaseMapType &VRBaseMap) {
190 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
191 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
192
193 unsigned NumResults = CountResults(Node);
194 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
195 II.isVariadic() && II.variadicOpsAreDefs();
196 unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.getNumDefs();
197 if (Node->getMachineOpcode() == TargetOpcode::STATEPOINT)
198 NumVRegs = NumResults;
199 for (unsigned i = 0; i < NumVRegs; ++i) {
200 // If the specific node value is only used by a CopyToReg and the dest reg
201 // is a vreg in the same register class, use the CopyToReg'd destination
202 // register instead of creating a new vreg.
203 Register VRBase;
204 const TargetRegisterClass *RC =
205 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
206 // Always let the value type influence the used register class. The
207 // constraints on the instruction may be too lax to represent the value
208 // type correctly. For example, a 64-bit float (X86::FR64) can't live in
209 // the 32-bit float super-class (X86::FR32).
210 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
211 const TargetRegisterClass *VTRC = TLI->getRegClassFor(
212 Node->getSimpleValueType(i),
213 (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
214 if (RC)
215 VTRC = TRI->getCommonSubClass(RC, VTRC);
216 if (VTRC)
217 RC = VTRC;
218 }
219
220 if (!II.operands().empty() && II.operands()[i].isOptionalDef()) {
221 // Optional def must be a physical register.
222 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
223 assert(VRBase.isPhysical());
224 MIB.addReg(VRBase, RegState::Define);
225 }
226
227 if (!VRBase && !IsClone && !IsCloned)
228 for (SDNode *User : Node->users()) {
229 if (User->getOpcode() == ISD::CopyToReg &&
230 User->getOperand(2).getNode() == Node &&
231 User->getOperand(2).getResNo() == i) {
232 Register Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
233 if (Reg.isVirtual()) {
234 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
235 if (RegRC == RC) {
236 VRBase = Reg;
237 MIB.addReg(VRBase, RegState::Define);
238 break;
239 }
240 }
241 }
242 }
243
244 // Create the result registers for this node and add the result regs to
245 // the machine instruction.
246 if (VRBase == 0) {
247 assert(RC && "Isn't a register operand!");
248 VRBase = MRI->createVirtualRegister(RC);
249 MIB.addReg(VRBase, RegState::Define);
250 }
251
252 // If this def corresponds to a result of the SDNode insert the VRBase into
253 // the lookup map.
254 if (i < NumResults) {
255 SDValue Op(Node, i);
256 if (IsClone)
257 VRBaseMap.erase(Op);
258 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
259 (void)isNew; // Silence compiler warning.
260 assert(isNew && "Node emitted out of order - early");
261 }
262 }
263}
264
265/// getVR - Return the virtual register corresponding to the specified result
266/// of the specified node.
267Register InstrEmitter::getVR(SDValue Op, VRBaseMapType &VRBaseMap) {
268 if (Op.isMachineOpcode() &&
269 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
270 // Add an IMPLICIT_DEF instruction before every use.
271 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
272 // does not include operand register class info.
273 const TargetRegisterClass *RC = TLI->getRegClassFor(
274 Op.getSimpleValueType(), Op.getNode()->isDivergent());
275 Register VReg = MRI->createVirtualRegister(RC);
276 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
277 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
278 return VReg;
279 }
280
281 VRBaseMapType::iterator I = VRBaseMap.find(Op);
282 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
283 return I->second;
284}
285
287 if (Op->isMachineOpcode()) {
288 switch (Op->getMachineOpcode()) {
289 case TargetOpcode::CONVERGENCECTRL_ANCHOR:
290 case TargetOpcode::CONVERGENCECTRL_ENTRY:
291 case TargetOpcode::CONVERGENCECTRL_LOOP:
292 case TargetOpcode::CONVERGENCECTRL_GLUE:
293 return true;
294 }
295 return false;
296 }
297
298 // We can reach here when CopyFromReg is encountered. But rather than making a
299 // special case for that, we just make sure we don't reach here in some
300 // surprising way.
301 switch (Op->getOpcode()) {
306 llvm_unreachable("Convergence control should have been selected by now.");
307 }
308 return false;
309}
310
311/// AddRegisterOperand - Add the specified register as an operand to the
312/// specified machine instr. Insert register copies if the register is
313/// not in the required register class.
314void
315InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
316 SDValue Op,
317 unsigned IIOpNum,
318 const MCInstrDesc *II,
319 VRBaseMapType &VRBaseMap,
320 bool IsDebug, bool IsClone, bool IsCloned) {
321 assert(Op.getValueType() != MVT::Other &&
322 Op.getValueType() != MVT::Glue &&
323 "Chain and glue operands should occur at end of operand list!");
324 // Get/emit the operand.
325 Register VReg = getVR(Op, VRBaseMap);
326
327 const MCInstrDesc &MCID = MIB->getDesc();
328 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
329 MCID.operands()[IIOpNum].isOptionalDef();
330
331 // If the instruction requires a register in a different class, create
332 // a new virtual register and copy the value into it, but first attempt to
333 // shrink VReg's register class within reason. For example, if VReg == GR32
334 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
335 if (II) {
336 const TargetRegisterClass *OpRC = nullptr;
337 if (IIOpNum < II->getNumOperands())
338 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
339
340 if (OpRC) {
341 unsigned MinNumRegs = MinRCSize;
342 // Don't apply any RC size limit for IMPLICIT_DEF. Each use has a unique
343 // virtual register.
344 if (Op.isMachineOpcode() &&
345 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)
346 MinNumRegs = 0;
347
348 const TargetRegisterClass *ConstrainedRC
349 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs);
350 if (!ConstrainedRC) {
351 OpRC = TRI->getAllocatableClass(OpRC);
352 assert(OpRC && "Constraints cannot be fulfilled for allocation");
353 Register NewVReg = MRI->createVirtualRegister(OpRC);
354 BuildMI(*MBB, InsertPos, MIB->getDebugLoc(),
355 TII->get(TargetOpcode::COPY), NewVReg)
356 .addReg(VReg);
357 VReg = NewVReg;
358 } else {
359 assert(ConstrainedRC->isAllocatable() &&
360 "Constraining an allocatable VReg produced an unallocatable class?");
361 }
362 }
363 }
364
365 // If this value has only one use, that use is a kill. This is a
366 // conservative approximation. InstrEmitter does trivial coalescing
367 // with CopyFromReg nodes, so don't emit kill flags for them.
368 // Avoid kill flags on Schedule cloned nodes, since there will be
369 // multiple uses.
370 // Tied operands are never killed, so we need to check that. And that
371 // means we need to determine the index of the operand.
372 // Don't kill convergence control tokens. Initially they are only used in glue
373 // nodes, and the InstrEmitter later adds implicit uses on the users of the
374 // glue node. This can sometimes make it seem like there is only one use,
375 // which is the glue node itself.
376 bool isKill = Op.hasOneUse() && !isConvergenceCtrlMachineOp(Op) &&
377 Op.getNode()->getOpcode() != ISD::CopyFromReg && !IsDebug &&
378 !(IsClone || IsCloned);
379 if (isKill) {
380 unsigned Idx = MIB->getNumOperands();
381 while (Idx > 0 &&
382 MIB->getOperand(Idx-1).isReg() &&
383 MIB->getOperand(Idx-1).isImplicit())
384 --Idx;
385 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
386 if (isTied)
387 isKill = false;
388 }
389
390 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
391 getDebugRegState(IsDebug));
392}
393
394/// AddOperand - Add the specified operand to the specified machine instr. II
395/// specifies the instruction information for the node, and IIOpNum is the
396/// operand number (in the II) that we are adding.
397void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, SDValue Op,
398 unsigned IIOpNum, const MCInstrDesc *II,
399 VRBaseMapType &VRBaseMap, bool IsDebug,
400 bool IsClone, bool IsCloned) {
401 if (Op.isMachineOpcode()) {
402 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
403 IsDebug, IsClone, IsCloned);
404 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
405 MIB.addImm(C->getSExtValue());
406 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
407 MIB.addFPImm(F->getConstantFPValue());
408 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
409 Register VReg = R->getReg();
410 MVT OpVT = Op.getSimpleValueType();
411 const TargetRegisterClass *IIRC =
412 II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
413 : nullptr;
414 const TargetRegisterClass *OpRC =
415 TLI->isTypeLegal(OpVT)
416 ? TLI->getRegClassFor(OpVT,
417 Op.getNode()->isDivergent() ||
418 (IIRC && TRI->isDivergentRegClass(IIRC)))
419 : nullptr;
420
421 if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) {
422 Register NewVReg = MRI->createVirtualRegister(IIRC);
423 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
424 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
425 VReg = NewVReg;
426 }
427 // Turn additional physreg operands into implicit uses on non-variadic
428 // instructions. This is used by call and return instructions passing
429 // arguments in registers.
430 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
431 MIB.addReg(VReg, getImplRegState(Imp));
432 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
433 MIB.addRegMask(RM->getRegMask());
434 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
435 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
436 TGA->getTargetFlags());
437 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
438 MIB.addMBB(BBNode->getBasicBlock());
439 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
440 MIB.addFrameIndex(FI->getIndex());
441 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
442 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
443 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
444 int Offset = CP->getOffset();
445 Align Alignment = CP->getAlign();
446
447 unsigned Idx;
449 if (CP->isMachineConstantPoolEntry())
450 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Alignment);
451 else
452 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Alignment);
453 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
454 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
455 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
456 } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
457 MIB.addSym(SymNode->getMCSymbol());
458 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
459 MIB.addBlockAddress(BA->getBlockAddress(),
460 BA->getOffset(),
461 BA->getTargetFlags());
462 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
463 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
464 } else {
465 assert(Op.getValueType() != MVT::Other &&
466 Op.getValueType() != MVT::Glue &&
467 "Chain and glue operands should occur at end of operand list!");
468 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
469 IsDebug, IsClone, IsCloned);
470 }
471}
472
473Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
474 MVT VT, bool isDivergent, const DebugLoc &DL) {
475 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
476 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
477
478 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
479 // within reason.
480 if (RC && RC != VRC)
481 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
482
483 // VReg has been adjusted. It can be used with SubIdx operands now.
484 if (RC)
485 return VReg;
486
487 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
488 // register instead.
489 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
490 assert(RC && "No legal register class for VT supports that SubIdx");
491 Register NewReg = MRI->createVirtualRegister(RC);
492 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
493 .addReg(VReg);
494 return NewReg;
495}
496
497/// EmitSubregNode - Generate machine code for subreg nodes.
498///
499void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
500 bool IsClone, bool IsCloned) {
501 Register VRBase;
502 unsigned Opc = Node->getMachineOpcode();
503
504 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
505 // the CopyToReg'd destination register instead of creating a new vreg.
506 for (SDNode *User : Node->users()) {
507 if (User->getOpcode() == ISD::CopyToReg &&
508 User->getOperand(2).getNode() == Node) {
509 Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
510 if (DestReg.isVirtual()) {
511 VRBase = DestReg;
512 break;
513 }
514 }
515 }
516
517 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
518 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
519 // constraints on the %dst register, COPY can target all legal register
520 // classes.
521 unsigned SubIdx = Node->getConstantOperandVal(1);
522 const TargetRegisterClass *TRC =
523 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
524
527 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
528 if (R && R->getReg().isPhysical()) {
529 Reg = R->getReg();
530 DefMI = nullptr;
531 } else {
532 Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
533 DefMI = MRI->getVRegDef(Reg);
534 }
535
536 Register SrcReg, DstReg;
537 unsigned DefSubIdx;
538 if (DefMI &&
539 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
540 SubIdx == DefSubIdx &&
541 TRC == MRI->getRegClass(SrcReg)) {
542 // Optimize these:
543 // r1025 = s/zext r1024, 4
544 // r1026 = extract_subreg r1025, 4
545 // to a copy
546 // r1026 = copy r1024
547 VRBase = MRI->createVirtualRegister(TRC);
548 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
549 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
550 MRI->clearKillFlags(SrcReg);
551 } else {
552 // Reg may not support a SubIdx sub-register, and we may need to
553 // constrain its register class or issue a COPY to a compatible register
554 // class.
555 if (Reg.isVirtual())
556 Reg = ConstrainForSubReg(Reg, SubIdx,
557 Node->getOperand(0).getSimpleValueType(),
558 Node->isDivergent(), Node->getDebugLoc());
559 // Create the destreg if it is missing.
560 if (!VRBase)
561 VRBase = MRI->createVirtualRegister(TRC);
562
563 // Create the extract_subreg machine instruction.
564 MachineInstrBuilder CopyMI =
565 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
566 TII->get(TargetOpcode::COPY), VRBase);
567 if (Reg.isVirtual())
568 CopyMI.addReg(Reg, 0, SubIdx);
569 else
570 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
571 }
572 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
573 Opc == TargetOpcode::SUBREG_TO_REG) {
574 SDValue N0 = Node->getOperand(0);
575 SDValue N1 = Node->getOperand(1);
576 SDValue N2 = Node->getOperand(2);
577 unsigned SubIdx = N2->getAsZExtVal();
578
579 // Figure out the register class to create for the destreg. It should be
580 // the largest legal register class supporting SubIdx sub-registers.
581 // RegisterCoalescer will constrain it further if it decides to eliminate
582 // the INSERT_SUBREG instruction.
583 //
584 // %dst = INSERT_SUBREG %src, %sub, SubIdx
585 //
586 // is lowered by TwoAddressInstructionPass to:
587 //
588 // %dst = COPY %src
589 // %dst:SubIdx = COPY %sub
590 //
591 // There is no constraint on the %src register class.
592 //
593 const TargetRegisterClass *SRC =
594 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
595 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
596 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
597
598 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
599 VRBase = MRI->createVirtualRegister(SRC);
600
601 // Create the insert_subreg or subreg_to_reg machine instruction.
603 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
604
605 // If creating a subreg_to_reg, then the first input operand
606 // is an implicit value immediate, otherwise it's a register
607 if (Opc == TargetOpcode::SUBREG_TO_REG) {
608 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
609 MIB.addImm(SD->getZExtValue());
610 } else
611 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
612 IsClone, IsCloned);
613 // Add the subregister being inserted
614 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
615 IsClone, IsCloned);
616 MIB.addImm(SubIdx);
617 MBB->insert(InsertPos, MIB);
618 } else
619 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
620
621 SDValue Op(Node, 0);
622 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
623 (void)isNew; // Silence compiler warning.
624 assert(isNew && "Node emitted out of order - early");
625}
626
627/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
628/// COPY_TO_REGCLASS is just a normal copy, except that the destination
629/// register is constrained to be in a particular register class.
630///
631void
632InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
633 VRBaseMapType &VRBaseMap) {
634 Register VReg = getVR(Node->getOperand(0), VRBaseMap);
635
636 // Create the new VReg in the destination class and emit a copy.
637 unsigned DstRCIdx = Node->getConstantOperandVal(1);
638 const TargetRegisterClass *DstRC =
639 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
640 Register NewVReg = MRI->createVirtualRegister(DstRC);
641 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
642 NewVReg).addReg(VReg);
643
644 SDValue Op(Node, 0);
645 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
646 (void)isNew; // Silence compiler warning.
647 assert(isNew && "Node emitted out of order - early");
648}
649
650/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
651///
652void InstrEmitter::EmitRegSequence(SDNode *Node, VRBaseMapType &VRBaseMap,
653 bool IsClone, bool IsCloned) {
654 unsigned DstRCIdx = Node->getConstantOperandVal(0);
655 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
656 Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
657 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
658 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
659 unsigned NumOps = Node->getNumOperands();
660 // If the input pattern has a chain, then the root of the corresponding
661 // output pattern will get a chain as well. This can happen to be a
662 // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
663 if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
664 --NumOps; // Ignore chain if it exists.
665
666 assert((NumOps & 1) == 1 &&
667 "REG_SEQUENCE must have an odd number of operands!");
668 for (unsigned i = 1; i != NumOps; ++i) {
669 SDValue Op = Node->getOperand(i);
670 if ((i & 1) == 0) {
671 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
672 // Skip physical registers as they don't have a vreg to get and we'll
673 // insert copies for them in TwoAddressInstructionPass anyway.
674 if (!R || !R->getReg().isPhysical()) {
675 unsigned SubIdx = Op->getAsZExtVal();
676 Register SubReg = getVR(Node->getOperand(i - 1), VRBaseMap);
677 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
678 const TargetRegisterClass *SRC =
679 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
680 if (SRC && SRC != RC) {
681 MRI->setRegClass(NewVReg, SRC);
682 RC = SRC;
683 }
684 }
685 }
686 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
687 IsClone, IsCloned);
688 }
689
690 MBB->insert(InsertPos, MIB);
691 SDValue Op(Node, 0);
692 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
693 (void)isNew; // Silence compiler warning.
694 assert(isNew && "Node emitted out of order - early");
695}
696
697/// EmitDbgValue - Generate machine instruction for a dbg_value node.
698///
701 VRBaseMapType &VRBaseMap) {
702 DebugLoc DL = SD->getDebugLoc();
703 assert(cast<DILocalVariable>(SD->getVariable())
704 ->isValidLocationForIntrinsic(DL) &&
705 "Expected inlined-at fields to agree");
706
707 SD->setIsEmitted();
708
709 assert(!SD->getLocationOps().empty() &&
710 "dbg_value with no location operands?");
711
712 if (SD->isInvalidated())
713 return EmitDbgNoLocation(SD);
714
715 // Attempt to produce a DBG_INSTR_REF if we've been asked to.
716 if (EmitDebugInstrRefs)
717 if (auto *InstrRef = EmitDbgInstrRef(SD, VRBaseMap))
718 return InstrRef;
719
720 // Emit variadic dbg_value nodes as DBG_VALUE_LIST if they have not been
721 // emitted as instruction references.
722 if (SD->isVariadic())
723 return EmitDbgValueList(SD, VRBaseMap);
724
725 // Emit single-location dbg_value nodes as DBG_VALUE if they have not been
726 // emitted as instruction references.
727 return EmitDbgValueFromSingleOp(SD, VRBaseMap);
728}
729
731 const Value *V = Op.getConst();
732 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
733 if (CI->getBitWidth() > 64)
735 return MachineOperand::CreateImm(CI->getSExtValue());
736 }
737 if (const ConstantFP *CF = dyn_cast<ConstantFP>(V))
739 // Note: This assumes that all nullptr constants are zero-valued.
740 if (isa<ConstantPointerNull>(V))
742 // Undef or unhandled value type, so return an undef operand.
744 /* Reg */ 0U, /* isDef */ false, /* isImp */ false,
745 /* isKill */ false, /* isDead */ false,
746 /* isUndef */ false, /* isEarlyClobber */ false,
747 /* SubReg */ 0, /* isDebug */ true);
748}
749
751 MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc,
752 ArrayRef<SDDbgOperand> LocationOps,
753 VRBaseMapType &VRBaseMap) {
754 for (const SDDbgOperand &Op : LocationOps) {
755 switch (Op.getKind()) {
757 MIB.addFrameIndex(Op.getFrameIx());
758 break;
760 MIB.addReg(Op.getVReg());
761 break;
763 SDValue V = SDValue(Op.getSDNode(), Op.getResNo());
764 // It's possible we replaced this SDNode with other(s) and therefore
765 // didn't generate code for it. It's better to catch these cases where
766 // they happen and transfer the debug info, but trying to guarantee that
767 // in all cases would be very fragile; this is a safeguard for any
768 // that were missed.
769 if (VRBaseMap.count(V) == 0)
770 MIB.addReg(0U); // undef
771 else
772 AddOperand(MIB, V, (*MIB).getNumOperands(), &DbgValDesc, VRBaseMap,
773 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
774 } break;
777 break;
778 }
779 }
780}
781
784 VRBaseMapType &VRBaseMap) {
785 MDNode *Var = SD->getVariable();
786 const DIExpression *Expr = (DIExpression *)SD->getExpression();
787 DebugLoc DL = SD->getDebugLoc();
788 const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF);
789
790 // Returns true if the given operand is not a legal debug operand for a
791 // DBG_INSTR_REF.
792 auto IsInvalidOp = [](SDDbgOperand DbgOp) {
793 return DbgOp.getKind() == SDDbgOperand::FRAMEIX;
794 };
795 // Returns true if the given operand is not itself an instruction reference
796 // but is a legal debug operand for a DBG_INSTR_REF.
797 auto IsNonInstrRefOp = [](SDDbgOperand DbgOp) {
798 return DbgOp.getKind() == SDDbgOperand::CONST;
799 };
800
801 // If this variable location does not depend on any instructions or contains
802 // any stack locations, produce it as a standard debug value instead.
803 if (any_of(SD->getLocationOps(), IsInvalidOp) ||
804 all_of(SD->getLocationOps(), IsNonInstrRefOp)) {
805 if (SD->isVariadic())
806 return EmitDbgValueList(SD, VRBaseMap);
807 return EmitDbgValueFromSingleOp(SD, VRBaseMap);
808 }
809
810 // Immediately fold any indirectness from the LLVM-IR intrinsic into the
811 // expression:
812 if (SD->isIndirect())
813 Expr = DIExpression::append(Expr, dwarf::DW_OP_deref);
814 // If this is not already a variadic expression, it must be modified to become
815 // one.
816 if (!SD->isVariadic())
818
820
821 // It may not be immediately possible to identify the MachineInstr that
822 // defines a VReg, it can depend for example on the order blocks are
823 // emitted in. When this happens, or when further analysis is needed later,
824 // produce an instruction like this:
825 //
826 // DBG_INSTR_REF !123, !456, %0:gr64
827 //
828 // i.e., point the instruction at the vreg, and patch it up later in
829 // MachineFunction::finalizeDebugInstrRefs.
830 auto AddVRegOp = [&](unsigned VReg) {
832 /* Reg */ VReg, /* isDef */ false, /* isImp */ false,
833 /* isKill */ false, /* isDead */ false,
834 /* isUndef */ false, /* isEarlyClobber */ false,
835 /* SubReg */ 0, /* isDebug */ true));
836 };
837 unsigned OpCount = SD->getLocationOps().size();
838 for (unsigned OpIdx = 0; OpIdx < OpCount; ++OpIdx) {
839 SDDbgOperand DbgOperand = SD->getLocationOps()[OpIdx];
840
841 // Try to find both the defined register and the instruction defining it.
842 MachineInstr *DefMI = nullptr;
843 unsigned VReg;
844
845 if (DbgOperand.getKind() == SDDbgOperand::VREG) {
846 VReg = DbgOperand.getVReg();
847
848 // No definition means that block hasn't been emitted yet. Leave a vreg
849 // reference to be fixed later.
850 if (!MRI->hasOneDef(VReg)) {
851 AddVRegOp(VReg);
852 continue;
853 }
854
855 DefMI = &*MRI->def_instr_begin(VReg);
856 } else if (DbgOperand.getKind() == SDDbgOperand::SDNODE) {
857 // Look up the corresponding VReg for the given SDNode, if any.
858 SDNode *Node = DbgOperand.getSDNode();
859 SDValue Op = SDValue(Node, DbgOperand.getResNo());
860 VRBaseMapType::iterator I = VRBaseMap.find(Op);
861 // No VReg -> produce a DBG_VALUE $noreg instead.
862 if (I == VRBaseMap.end())
863 break;
864
865 // Try to pick out a defining instruction at this point.
866 VReg = getVR(Op, VRBaseMap);
867
868 // Again, if there's no instruction defining the VReg right now, fix it up
869 // later.
870 if (!MRI->hasOneDef(VReg)) {
871 AddVRegOp(VReg);
872 continue;
873 }
874
875 DefMI = &*MRI->def_instr_begin(VReg);
876 } else {
877 assert(DbgOperand.getKind() == SDDbgOperand::CONST);
878 MOs.push_back(GetMOForConstDbgOp(DbgOperand));
879 continue;
880 }
881
882 // Avoid copy like instructions: they don't define values, only move them.
883 // Leave a virtual-register reference until it can be fixed up later, to
884 // find the underlying value definition.
885 if (DefMI->isCopyLike() || TII->isCopyInstr(*DefMI)) {
886 AddVRegOp(VReg);
887 continue;
888 }
889
890 // Find the operand number which defines the specified VReg.
891 unsigned OperandIdx = 0;
892 for (const auto &MO : DefMI->operands()) {
893 if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)
894 break;
895 ++OperandIdx;
896 }
897 assert(OperandIdx < DefMI->getNumOperands());
898
899 // Make the DBG_INSTR_REF refer to that instruction, and that operand.
900 unsigned InstrNum = DefMI->getDebugInstrNum();
901 MOs.push_back(MachineOperand::CreateDbgInstrRef(InstrNum, OperandIdx));
902 }
903
904 // If we haven't created a valid MachineOperand for every DbgOp, abort and
905 // produce an undef DBG_VALUE.
906 if (MOs.size() != OpCount)
907 return EmitDbgNoLocation(SD);
908
909 return BuildMI(*MF, DL, RefII, false, MOs, Var, Expr);
910}
911
913 // An invalidated SDNode must generate an undef DBG_VALUE: although the
914 // original value is no longer computed, earlier DBG_VALUEs live ranges
915 // must not leak into later code.
916 DIVariable *Var = SD->getVariable();
917 const DIExpression *Expr =
919 DebugLoc DL = SD->getDebugLoc();
920 const MCInstrDesc &Desc = TII->get(TargetOpcode::DBG_VALUE);
921 return BuildMI(*MF, DL, Desc, false, 0U, Var, Expr);
922}
923
926 VRBaseMapType &VRBaseMap) {
927 MDNode *Var = SD->getVariable();
928 DIExpression *Expr = SD->getExpression();
929 DebugLoc DL = SD->getDebugLoc();
930 // DBG_VALUE_LIST := "DBG_VALUE_LIST" var, expression, loc (, loc)*
931 const MCInstrDesc &DbgValDesc = TII->get(TargetOpcode::DBG_VALUE_LIST);
932 // Build the DBG_VALUE_LIST instruction base.
933 auto MIB = BuildMI(*MF, DL, DbgValDesc);
934 MIB.addMetadata(Var);
935 MIB.addMetadata(Expr);
936 AddDbgValueLocationOps(MIB, DbgValDesc, SD->getLocationOps(), VRBaseMap);
937 return &*MIB;
938}
939
942 VRBaseMapType &VRBaseMap) {
943 MDNode *Var = SD->getVariable();
944 DIExpression *Expr = SD->getExpression();
945 DebugLoc DL = SD->getDebugLoc();
946 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
947
948 assert(SD->getLocationOps().size() == 1 &&
949 "Non variadic dbg_value should have only one location op");
950
951 // See about constant-folding the expression.
952 // Copy the location operand in case we replace it.
953 SmallVector<SDDbgOperand, 1> LocationOps(1, SD->getLocationOps()[0]);
954 if (Expr && LocationOps[0].getKind() == SDDbgOperand::CONST) {
955 const Value *V = LocationOps[0].getConst();
956 if (auto *C = dyn_cast<ConstantInt>(V)) {
957 std::tie(Expr, C) = Expr->constantFold(C);
958 LocationOps[0] = SDDbgOperand::fromConst(C);
959 }
960 }
961
962 // Emit non-variadic dbg_value nodes as DBG_VALUE.
963 // DBG_VALUE := "DBG_VALUE" loc, isIndirect, var, expr
964 auto MIB = BuildMI(*MF, DL, II);
965 AddDbgValueLocationOps(MIB, II, LocationOps, VRBaseMap);
966
967 if (SD->isIndirect())
968 MIB.addImm(0U);
969 else
970 MIB.addReg(0U);
971
972 return MIB.addMetadata(Var).addMetadata(Expr);
973}
974
977 MDNode *Label = SD->getLabel();
978 DebugLoc DL = SD->getDebugLoc();
979 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
980 "Expected inlined-at fields to agree");
981
982 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
983 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
984 MIB.addMetadata(Label);
985
986 return &*MIB;
987}
988
989/// EmitMachineNode - Generate machine code for a target-specific node and
990/// needed dependencies.
991///
992void InstrEmitter::
993EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
994 VRBaseMapType &VRBaseMap) {
995 unsigned Opc = Node->getMachineOpcode();
996
997 // Handle subreg insert/extract specially
998 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
999 Opc == TargetOpcode::INSERT_SUBREG ||
1000 Opc == TargetOpcode::SUBREG_TO_REG) {
1001 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
1002 return;
1003 }
1004
1005 // Handle COPY_TO_REGCLASS specially.
1006 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
1007 EmitCopyToRegClassNode(Node, VRBaseMap);
1008 return;
1009 }
1010
1011 // Handle REG_SEQUENCE specially.
1012 if (Opc == TargetOpcode::REG_SEQUENCE) {
1013 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
1014 return;
1015 }
1016
1017 if (Opc == TargetOpcode::IMPLICIT_DEF)
1018 // We want a unique VR for each IMPLICIT_DEF use.
1019 return;
1020
1021 const MCInstrDesc &II = TII->get(Opc);
1022 unsigned NumResults = CountResults(Node);
1023 unsigned NumDefs = II.getNumDefs();
1024 const MCPhysReg *ScratchRegs = nullptr;
1025
1026 // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
1027 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
1028 // Stackmaps do not have arguments and do not preserve their calling
1029 // convention. However, to simplify runtime support, they clobber the same
1030 // scratch registers as AnyRegCC.
1031 unsigned CC = CallingConv::AnyReg;
1032 if (Opc == TargetOpcode::PATCHPOINT) {
1033 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
1034 NumDefs = NumResults;
1035 }
1036 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
1037 } else if (Opc == TargetOpcode::STATEPOINT) {
1038 NumDefs = NumResults;
1039 }
1040
1041 unsigned NumImpUses = 0;
1042 unsigned NodeOperands =
1043 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
1044 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
1045 II.isVariadic() && II.variadicOpsAreDefs();
1046 bool HasPhysRegOuts = NumResults > NumDefs && !II.implicit_defs().empty() &&
1047 !HasVRegVariadicDefs;
1048#ifndef NDEBUG
1049 unsigned NumMIOperands = NodeOperands + NumResults;
1050 if (II.isVariadic())
1051 assert(NumMIOperands >= II.getNumOperands() &&
1052 "Too few operands for a variadic node!");
1053 else
1054 assert(NumMIOperands >= II.getNumOperands() &&
1055 NumMIOperands <=
1056 II.getNumOperands() + II.implicit_defs().size() + NumImpUses &&
1057 "#operands for dag node doesn't match .td file!");
1058#endif
1059
1060 // Create the new machine instruction.
1061 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
1062
1063 // Transfer IR flags from the SDNode to the MachineInstr
1064 MachineInstr *MI = MIB.getInstr();
1065 const SDNodeFlags Flags = Node->getFlags();
1066 if (Flags.hasUnpredictable())
1068
1069 // Add result register values for things that are defined by this
1070 // instruction.
1071 if (NumResults) {
1072 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
1073
1074 if (Flags.hasNoSignedZeros())
1076
1077 if (Flags.hasAllowReciprocal())
1079
1080 if (Flags.hasNoNaNs())
1082
1083 if (Flags.hasNoInfs())
1085
1086 if (Flags.hasAllowContract())
1088
1089 if (Flags.hasApproximateFuncs())
1091
1092 if (Flags.hasAllowReassociation())
1094
1095 if (Flags.hasNoUnsignedWrap())
1097
1098 if (Flags.hasNoSignedWrap())
1100
1101 if (Flags.hasExact())
1103
1104 if (Flags.hasNoFPExcept())
1106
1107 if (Flags.hasDisjoint())
1109
1110 if (Flags.hasSameSign())
1112 }
1113
1114 // Emit all of the actual operands of this instruction, adding them to the
1115 // instruction as appropriate.
1116 bool HasOptPRefs = NumDefs > NumResults;
1117 assert((!HasOptPRefs || !HasPhysRegOuts) &&
1118 "Unable to cope with optional defs and phys regs defs!");
1119 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
1120 for (unsigned i = NumSkip; i != NodeOperands; ++i)
1121 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
1122 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
1123
1124 // Add scratch registers as implicit def and early clobber
1125 if (ScratchRegs)
1126 for (unsigned i = 0; ScratchRegs[i]; ++i)
1127 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
1129
1130 // Set the memory reference descriptions of this instruction now that it is
1131 // part of the function.
1132 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
1133
1134 // Set the CFI type.
1135 MIB->setCFIType(*MF, Node->getCFIType());
1136
1137 // Insert the instruction into position in the block. This needs to
1138 // happen before any custom inserter hook is called so that the
1139 // hook knows where in the block to insert the replacement code.
1140 MBB->insert(InsertPos, MIB);
1141
1142 // The MachineInstr may also define physregs instead of virtregs. These
1143 // physreg values can reach other instructions in different ways:
1144 //
1145 // 1. When there is a use of a Node value beyond the explicitly defined
1146 // virtual registers, we emit a CopyFromReg for one of the implicitly
1147 // defined physregs. This only happens when HasPhysRegOuts is true.
1148 //
1149 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
1150 //
1151 // 3. A glued instruction may implicitly use a physreg.
1152 //
1153 // 4. A glued instruction may use a RegisterSDNode operand.
1154 //
1155 // Collect all the used physreg defs, and make sure that any unused physreg
1156 // defs are marked as dead.
1157 SmallVector<Register, 8> UsedRegs;
1158
1159 // Additional results must be physical register defs.
1160 if (HasPhysRegOuts) {
1161 for (unsigned i = NumDefs; i < NumResults; ++i) {
1162 Register Reg = II.implicit_defs()[i - NumDefs];
1163 if (!Node->hasAnyUseOfValue(i))
1164 continue;
1165 // This implicitly defined physreg has a use.
1166 UsedRegs.push_back(Reg);
1167 EmitCopyFromReg(Node, i, IsClone, Reg, VRBaseMap);
1168 }
1169 }
1170
1171 // Scan the glue chain for any used physregs.
1172 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
1173 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
1174 if (F->getOpcode() == ISD::CopyFromReg) {
1175 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
1176 continue;
1177 } else if (F->getOpcode() == ISD::CopyToReg) {
1178 // Skip CopyToReg nodes that are internal to the glue chain.
1179 continue;
1180 }
1181 // Collect declared implicit uses.
1182 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
1183 append_range(UsedRegs, MCID.implicit_uses());
1184 // In addition to declared implicit uses, we must also check for
1185 // direct RegisterSDNode operands.
1186 for (const SDValue &Op : F->op_values())
1187 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
1188 Register Reg = R->getReg();
1189 if (Reg.isPhysical())
1190 UsedRegs.push_back(Reg);
1191 }
1192 }
1193 }
1194
1195 // Add rounding control registers as implicit def for function call.
1196 if (II.isCall() && MF->getFunction().hasFnAttribute(Attribute::StrictFP)) {
1198 for (MCPhysReg Reg : RCRegs)
1199 UsedRegs.push_back(Reg);
1200 }
1201
1202 // Finally mark unused registers as dead.
1203 if (!UsedRegs.empty() || !II.implicit_defs().empty() || II.hasOptionalDef())
1204 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
1205
1206 // STATEPOINT is too 'dynamic' to have meaningful machine description.
1207 // We have to manually tie operands.
1208 if (Opc == TargetOpcode::STATEPOINT && NumDefs > 0) {
1209 assert(!HasPhysRegOuts && "STATEPOINT mishandled");
1210 MachineInstr *MI = MIB;
1211 unsigned Def = 0;
1213 assert(First > 0 && "Statepoint has Defs but no GC ptr list");
1214 unsigned Use = (unsigned)First;
1215 while (Def < NumDefs) {
1216 if (MI->getOperand(Use).isReg())
1217 MI->tieOperands(Def++, Use);
1219 }
1220 }
1221
1222 if (SDNode *GluedNode = Node->getGluedNode()) {
1223 // FIXME: Possibly iterate over multiple glue nodes?
1224 if (GluedNode->getOpcode() ==
1225 ~(unsigned)TargetOpcode::CONVERGENCECTRL_GLUE) {
1226 Register VReg = getVR(GluedNode->getOperand(0), VRBaseMap);
1227 MachineOperand MO = MachineOperand::CreateReg(VReg, /*isDef=*/false,
1228 /*isImp=*/true);
1229 MIB->addOperand(MO);
1230 }
1231 }
1232
1233 // Run post-isel target hook to adjust this instruction if needed.
1234 if (II.hasPostISelHook())
1236}
1237
1238/// EmitSpecialNode - Generate machine code for a target-independent node and
1239/// needed dependencies.
1240void InstrEmitter::
1241EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
1242 VRBaseMapType &VRBaseMap) {
1243 switch (Node->getOpcode()) {
1244 default:
1245#ifndef NDEBUG
1246 Node->dump();
1247#endif
1248 llvm_unreachable("This target-independent node should have been selected!");
1249 case ISD::EntryToken:
1250 case ISD::MERGE_VALUES:
1251 case ISD::TokenFactor: // fall thru
1252 break;
1253 case ISD::CopyToReg: {
1254 Register DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1255 SDValue SrcVal = Node->getOperand(2);
1256 if (DestReg.isVirtual() && SrcVal.isMachineOpcode() &&
1257 SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
1258 // Instead building a COPY to that vreg destination, build an
1259 // IMPLICIT_DEF instruction instead.
1260 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1261 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1262 break;
1263 }
1264 Register SrcReg;
1265 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
1266 SrcReg = R->getReg();
1267 else
1268 SrcReg = getVR(SrcVal, VRBaseMap);
1269
1270 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1271 break;
1272
1273 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1274 DestReg).addReg(SrcReg);
1275 break;
1276 }
1277 case ISD::CopyFromReg: {
1278 Register SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1279 EmitCopyFromReg(Node, 0, IsClone, SrcReg, VRBaseMap);
1280 break;
1281 }
1282 case ISD::EH_LABEL:
1283 case ISD::ANNOTATION_LABEL: {
1284 unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1285 ? TargetOpcode::EH_LABEL
1286 : TargetOpcode::ANNOTATION_LABEL;
1287 MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1288 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1289 TII->get(Opc)).addSym(S);
1290 break;
1291 }
1292
1294 case ISD::LIFETIME_END: {
1295 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START)
1296 ? TargetOpcode::LIFETIME_START
1297 : TargetOpcode::LIFETIME_END;
1298 auto *FI = cast<FrameIndexSDNode>(Node->getOperand(1));
1299 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1300 .addFrameIndex(FI->getIndex());
1301 break;
1302 }
1303
1304 case ISD::PSEUDO_PROBE: {
1305 unsigned TarOp = TargetOpcode::PSEUDO_PROBE;
1306 auto Guid = cast<PseudoProbeSDNode>(Node)->getGuid();
1307 auto Index = cast<PseudoProbeSDNode>(Node)->getIndex();
1308 auto Attr = cast<PseudoProbeSDNode>(Node)->getAttributes();
1309
1310 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1311 .addImm(Guid)
1312 .addImm(Index)
1314 .addImm(Attr);
1315 break;
1316 }
1317
1318 case ISD::INLINEASM:
1319 case ISD::INLINEASM_BR: {
1320 unsigned NumOps = Node->getNumOperands();
1321 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1322 --NumOps; // Ignore the glue operand.
1323
1324 // Create the inline asm machine instruction.
1325 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1326 ? TargetOpcode::INLINEASM_BR
1327 : TargetOpcode::INLINEASM;
1329 BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1330
1331 // Add the asm string as an external symbol operand.
1332 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1333 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1334 MIB.addExternalSymbol(AsmStr);
1335
1336 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1337 // bits.
1338 int64_t ExtraInfo =
1339 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1340 getZExtValue();
1341 MIB.addImm(ExtraInfo);
1342
1343 // Remember to operand index of the group flags.
1344 SmallVector<unsigned, 8> GroupIdx;
1345
1346 // Remember registers that are part of early-clobber defs.
1348
1349 // Add all of the operand registers to the instruction.
1350 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1351 unsigned Flags = Node->getConstantOperandVal(i);
1352 const InlineAsm::Flag F(Flags);
1353 const unsigned NumVals = F.getNumOperandRegisters();
1354
1355 GroupIdx.push_back(MIB->getNumOperands());
1356 MIB.addImm(Flags);
1357 ++i; // Skip the ID value.
1358
1359 switch (F.getKind()) {
1361 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1362 Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1363 // FIXME: Add dead flags for physical and virtual registers defined.
1364 // For now, mark physical register defs as implicit to help fast
1365 // regalloc. This makes inline asm look a lot like calls.
1366 MIB.addReg(Reg, RegState::Define | getImplRegState(Reg.isPhysical()));
1367 }
1368 break;
1371 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1372 Register Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1374 getImplRegState(Reg.isPhysical()));
1375 ECRegs.push_back(Reg);
1376 }
1377 break;
1378 case InlineAsm::Kind::RegUse: // Use of register.
1379 case InlineAsm::Kind::Imm: // Immediate.
1380 case InlineAsm::Kind::Mem: // Non-function addressing mode.
1381 // The addressing mode has been selected, just add all of the
1382 // operands to the machine instruction.
1383 for (unsigned j = 0; j != NumVals; ++j, ++i)
1384 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1385 /*IsDebug=*/false, IsClone, IsCloned);
1386
1387 // Manually set isTied bits.
1388 if (F.isRegUseKind()) {
1389 unsigned DefGroup;
1390 if (F.isUseOperandTiedToDef(DefGroup)) {
1391 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1392 unsigned UseIdx = GroupIdx.back() + 1;
1393 for (unsigned j = 0; j != NumVals; ++j)
1394 MIB->tieOperands(DefIdx + j, UseIdx + j);
1395 }
1396 }
1397 break;
1398 case InlineAsm::Kind::Func: // Function addressing mode.
1399 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1400 SDValue Op = Node->getOperand(i);
1401 AddOperand(MIB, Op, 0, nullptr, VRBaseMap,
1402 /*IsDebug=*/false, IsClone, IsCloned);
1403
1404 // Adjust Target Flags for function reference.
1405 if (auto *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
1406 unsigned NewFlags =
1408 TGA->getGlobal());
1409 unsigned LastIdx = MIB.getInstr()->getNumOperands() - 1;
1410 MIB.getInstr()->getOperand(LastIdx).setTargetFlags(NewFlags);
1411 }
1412 }
1413 }
1414 }
1415
1416 // Add rounding control registers as implicit def for inline asm.
1417 if (MF->getFunction().hasFnAttribute(Attribute::StrictFP)) {
1419 for (MCPhysReg Reg : RCRegs)
1421 }
1422
1423 // GCC inline assembly allows input operands to also be early-clobber
1424 // output operands (so long as the operand is written only after it's
1425 // used), but this does not match the semantics of our early-clobber flag.
1426 // If an early-clobber operand register is also an input operand register,
1427 // then remove the early-clobber flag.
1428 for (Register Reg : ECRegs) {
1429 if (MIB->readsRegister(Reg, TRI)) {
1430 MachineOperand *MO =
1431 MIB->findRegisterDefOperand(Reg, TRI, false, false);
1432 assert(MO && "No def operand for clobbered register?");
1433 MO->setIsEarlyClobber(false);
1434 }
1435 }
1436
1437 // Get the mdnode from the asm if it exists and add it to the instruction.
1438 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1439 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1440 if (MD)
1441 MIB.addMetadata(MD);
1442
1443 MBB->insert(InsertPos, MIB);
1444 break;
1445 }
1446 }
1447}
1448
1449/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1450/// at the given position in the given block.
1453 : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1454 TII(MF->getSubtarget().getInstrInfo()),
1455 TRI(MF->getSubtarget().getRegisterInfo()),
1456 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1457 InsertPos(insertpos) {
1458 EmitDebugInstrRefs = mbb->getParent()->useDebugInstrRef();
1459}
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static const Function * getParent(const Value *V)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static bool isConvergenceCtrlMachineOp(SDValue Op)
MachineOperand GetMOForConstDbgOp(const SDDbgOperand &Op)
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers.
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
DEMANGLE_DUMP_METHOD void dump() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:271
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
uint64_t getZExtValue() const
DWARF expression.
static DIExpression * append(const DIExpression *Expr, ArrayRef< uint64_t > Ops)
Append the opcodes Ops to DIExpr.
std::pair< DIExpression *, const ConstantInt * > constantFold(const ConstantInt *CI)
Try to shorten an expression with an initial constant operand.
static const DIExpression * convertToVariadicExpression(const DIExpression *Expr)
If Expr is a non-variadic expression (i.e.
static const DIExpression * convertToUndefExpression(const DIExpression *Expr)
Removes all elements from Expr that do not apply to an undef debug value, which includes every operat...
Base class for variables.
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:156
DenseMapIterator< KeyT, ValueT, KeyInfoT, BucketT > iterator
Definition: DenseMap.h:71
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:152
iterator end()
Definition: DenseMap.h:84
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:731
MachineInstr * EmitDbgValue(SDDbgValue *SD, VRBaseMapType &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
MachineInstr * EmitDbgInstrRef(SDDbgValue *SD, VRBaseMapType &VRBaseMap)
Emit a dbg_value as a DBG_INSTR_REF.
MachineInstr * EmitDbgLabel(SDDbgLabel *SD)
Generate machine instruction for a dbg_label node.
MachineInstr * EmitDbgNoLocation(SDDbgValue *SD)
Emit a DBG_VALUE $noreg, indicating a variable has no location.
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first,...
MachineInstr * EmitDbgValueList(SDDbgValue *SD, VRBaseMapType &VRBaseMap)
Emit a DBG_VALUE_LIST from the operands to SDDbgValue.
InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
void AddDbgValueLocationOps(MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, ArrayRef< SDDbgOperand > Locations, VRBaseMapType &VRBaseMap)
MachineInstr * EmitDbgValueFromSingleOp(SDDbgValue *SD, VRBaseMapType &VRBaseMap)
Emit a DBG_VALUE from the operands to SDDbgValue.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:219
ArrayRef< MCPhysReg > implicit_uses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:565
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
Metadata node.
Definition: Metadata.h:1073
Machine Value Type.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
bool useDebugInstrRef() const
Returns true if the function's variable locations are tracked with instruction referencing.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
Definition: MachineInstr.h:71
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr reads the specified register.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:580
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:574
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:693
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:501
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:587
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateFPImm(const ConstantFP *CFP)
bool isImplicit() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static MachineOperand CreateCImm(const ConstantInt *CI)
void setIsEarlyClobber(bool Val=true)
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
void setTargetFlags(unsigned F)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
def_instr_iterator def_instr_begin(Register RegNo) const
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
Holds the information from a dbg_label node through SDISel.
MDNode * getLabel() const
Returns the MDNode pointer for the label.
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
Holds the information for a single machine location through SDISel; either an SDNode,...
unsigned getResNo() const
Returns the ResNo for a register ref.
unsigned getVReg() const
Returns the Virtual Register for a VReg.
static SDDbgOperand fromConst(const Value *Const)
SDNode * getSDNode() const
Returns the SDNode* for a register ref.
@ VREG
Value is a virtual register.
@ FRAMEIX
Value is contents of a stack location.
@ SDNODE
Value is the result of an expression.
@ CONST
Value is a constant.
Kind getKind() const
Holds the information from a dbg_value node through SDISel.
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
DIVariable * getVariable() const
Returns the DIVariable pointer for the variable.
bool isInvalidated() const
ArrayRef< SDDbgOperand > getLocationOps() const
DIExpression * getExpression() const
Returns the DIExpression pointer for the expression.
bool isIndirect() const
Returns whether this is an indirect value.
void setIsEmitted()
setIsEmitted / isEmitted - Getter/Setter for flag indicating that this SDDbgValue has been emitted to...
bool isVariadic() const
Represents one node in the SelectionDAG.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool isMachineOpcode() const
unsigned getMachineOpcode() const
bool empty() const
Definition: SmallVector.h:81
size_t size() const
Definition: SmallVector.h:78
void push_back(const T &Elt)
Definition: SmallVector.h:413
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1196
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:170
MI-level Statepoint operands.
Definition: StackMaps.h:158
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:124
Completely target-dependent object reference.
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
std::optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
virtual ArrayRef< MCPhysReg > getRoundingControlRegisters() const
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
virtual bool usesPhysRegsForValues() const
True if the target uses physical regs (as nearly all targets do).
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
virtual unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const
Classify a global function reference.
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
Value * getOperand(unsigned i) const
Definition: User.h:228
unsigned getNumOperands() const
Definition: User.h:250
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ AnyReg
OBSOLETED - Used for stack based JavaScript calls.
Definition: CallingConv.h:60
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:243
@ CONVERGENCECTRL_ANCHOR
Definition: ISDOpcodes.h:1470
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:1173
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
Definition: ISDOpcodes.h:1179
@ CONVERGENCECTRL_GLUE
Definition: ISDOpcodes.h:1476
@ CONVERGENCECTRL_ENTRY
Definition: ISDOpcodes.h:1471
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:215
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:47
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Definition: ISDOpcodes.h:209
@ LIFETIME_START
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:1377
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1168
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
Definition: ISDOpcodes.h:1402
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
@ CONVERGENCECTRL_LOOP
Definition: ISDOpcodes.h:1472
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1165
@ Define
Register definition.
@ EarlyClobber
Register definition happens before uses.
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< DefNode * > Def
Definition: RDFGraph.h:384
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1739
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
Definition: STLExtras.h:2115
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1746
unsigned getImplRegState(bool B)
unsigned getDebugRegState(bool B)
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
unsigned getDefRegState(bool B)
unsigned getKillRegState(bool B)
DWARFExpression::Operation Op
#define N
TODO: Might pack better if we changed this to a Struct of Arrays, since MachineOperand is width 32,...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Description of the encoding of one expression Op.
These are IR-level optimization flags that may be propagated to SDNodes.