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32 #define DEBUG_TYPE "instr-emitter"
44 unsigned N = Node->getNumValues();
60 unsigned &NumImpUses) {
61 unsigned N = Node->getNumOperands();
62 while (
N && Node->getOperand(
N - 1).getValueType() ==
MVT::Glue)
64 if (
N && Node->getOperand(
N - 1).getValueType() ==
MVT::Other)
68 NumImpUses =
N - NumExpUses;
69 for (
unsigned I =
N;
I > NumExpUses; --
I) {
70 if (isa<RegisterMaskSDNode>(Node->getOperand(
I - 1)))
73 if (
RN->getReg().isPhysical())
84 void InstrEmitter::EmitCopyFromReg(
SDNode *Node,
unsigned ResNo,
bool IsClone,
93 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, SrcReg)).second;
95 assert(isNew &&
"Node emitted out of order - early");
101 bool MatchReg =
true;
103 MVT VT = Node->getSimpleValueType(ResNo);
118 }
else if (DestReg != SrcReg)
123 if (
Op.getNode() != Node ||
Op.getResNo() != ResNo)
125 MVT VT = Node->getSimpleValueType(
Op.getResNo());
129 if (
User->isMachineOpcode()) {
162 "Incompatible phys register def and uses!");
174 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->
get(TargetOpcode::COPY),
181 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, VRBase)).second;
183 assert(isNew &&
"Node emitted out of order - early");
186 void InstrEmitter::CreateVirtualRegisters(
SDNode *Node,
189 bool IsClone,
bool IsCloned,
191 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
192 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
197 unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.
getNumDefs();
198 if (Node->getMachineOpcode() == TargetOpcode::STATEPOINT)
199 NumVRegs = NumResults;
200 for (
unsigned i = 0;
i < NumVRegs; ++
i) {
211 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(
i))) {
213 Node->getSimpleValueType(
i),
223 VRBase = cast<RegisterSDNode>(Node->getOperand(
i-NumResults))->getReg();
228 if (!VRBase && !IsClone && !IsCloned)
234 if (
Reg.isVirtual()) {
248 assert(RC &&
"Isn't a register operand!");
255 if (
i < NumResults) {
259 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, VRBase)).second;
261 assert(isNew &&
"Node emitted out of order - early");
270 if (
Op.isMachineOpcode() &&
271 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
276 Op.getSimpleValueType(),
Op.getNode()->isDivergent());
278 BuildMI(*MBB, InsertPos,
Op.getDebugLoc(),
279 TII->
get(TargetOpcode::IMPLICIT_DEF), VReg);
284 assert(
I != VRBaseMap.
end() &&
"Node emitted out of order - late");
298 bool IsDebug,
bool IsClone,
bool IsCloned) {
301 "Chain and glue operands should occur at end of operand list!");
307 MCID.
operands()[IIOpNum].isOptionalDef();
315 if (IIOpNum < II->getNumOperands())
322 if (
Op.isMachineOpcode() &&
323 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)
328 if (!ConstrainedRC) {
330 assert(OpRC &&
"Constraints cannot be fulfilled for allocation");
332 BuildMI(*MBB, InsertPos,
Op.getNode()->getDebugLoc(),
333 TII->
get(TargetOpcode::COPY), NewVReg).
addReg(VReg);
337 "Constraining an allocatable VReg produced an unallocatable class?");
349 bool isKill =
Op.hasOneUse() &&
352 !(IsClone || IsCloned);
376 bool IsDebug,
bool IsClone,
bool IsCloned) {
377 if (
Op.isMachineOpcode()) {
378 AddRegisterOperand(MIB,
Op, IIOpNum, II, VRBaseMap,
379 IsDebug, IsClone, IsCloned);
386 MVT OpVT =
Op.getSimpleValueType();
393 Op.getNode()->isDivergent() ||
397 if (OpRC && IIRC && OpRC != IIRC && VReg.
isVirtual()) {
399 BuildMI(*MBB, InsertPos,
Op.getNode()->getDebugLoc(),
400 TII->
get(TargetOpcode::COPY), NewVReg).
addReg(VReg);
412 TGA->getTargetFlags());
414 MIB.
addMBB(BBNode->getBasicBlock());
421 Align Alignment =
CP->getAlign();
425 if (
CP->isMachineConstantPoolEntry())
432 }
else if (
auto *SymNode = dyn_cast<MCSymbolSDNode>(
Op)) {
433 MIB.
addSym(SymNode->getMCSymbol());
437 BA->getTargetFlags());
439 MIB.
addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
443 "Chain and glue operands should occur at end of operand list!");
444 AddRegisterOperand(MIB,
Op, IIOpNum, II, VRBaseMap,
445 IsDebug, IsClone, IsCloned);
466 assert(RC &&
"No legal register class for VT supports that SubIdx");
468 BuildMI(*MBB, InsertPos,
DL, TII->
get(TargetOpcode::COPY), NewReg)
475 void InstrEmitter::EmitSubregNode(
SDNode *Node,
477 bool IsClone,
bool IsCloned) {
479 unsigned Opc = Node->getMachineOpcode();
494 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
498 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
500 TLI->
getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
505 if (R &&
R->getReg().isPhysical()) {
509 Reg =
R ?
R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
517 SubIdx == DefSubIdx &&
525 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
526 TII->
get(TargetOpcode::COPY), VRBase).
addReg(SrcReg);
533 Reg = ConstrainForSubReg(
Reg, SubIdx,
534 Node->getOperand(0).getSimpleValueType(),
535 Node->isDivergent(), Node->getDebugLoc());
542 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
543 TII->
get(TargetOpcode::COPY), VRBase);
549 }
else if (Opc == TargetOpcode::INSERT_SUBREG ||
550 Opc == TargetOpcode::SUBREG_TO_REG) {
551 SDValue N0 = Node->getOperand(0);
552 SDValue N1 = Node->getOperand(1);
553 SDValue N2 = Node->getOperand(2);
554 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
571 TLI->
getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
573 assert(SRC &&
"No register class supports VT and SubIdx for INSERT_SUBREG");
580 BuildMI(*MF, Node->getDebugLoc(), TII->
get(Opc), VRBase);
584 if (Opc == TargetOpcode::SUBREG_TO_REG) {
588 AddOperand(MIB, N0, 0,
nullptr, VRBaseMap,
false,
591 AddOperand(MIB, N1, 0,
nullptr, VRBaseMap,
false,
594 MBB->
insert(InsertPos, MIB);
596 llvm_unreachable(
"Node is not insert_subreg, extract_subreg, or subreg_to_reg");
599 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, VRBase)).second;
601 assert(isNew &&
"Node emitted out of order - early");
609 InstrEmitter::EmitCopyToRegClassNode(
SDNode *Node,
611 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
614 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
618 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->
get(TargetOpcode::COPY),
622 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, NewVReg)).second;
624 assert(isNew &&
"Node emitted out of order - early");
629 void InstrEmitter::EmitRegSequence(
SDNode *Node,
631 bool IsClone,
bool IsCloned) {
632 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
637 unsigned NumOps = Node->getNumOperands();
641 if (NumOps && Node->getOperand(NumOps-1).getValueType() ==
MVT::Other)
644 assert((NumOps & 1) == 1 &&
645 "REG_SEQUENCE must have an odd number of operands!");
646 for (
unsigned i = 1;
i != NumOps; ++
i) {
652 if (!R || !
R->getReg().isPhysical()) {
653 unsigned SubIdx = cast<ConstantSDNode>(
Op)->getZExtValue();
654 unsigned SubReg = getVR(Node->getOperand(
i-1), VRBaseMap);
658 if (SRC && SRC != RC) {
664 AddOperand(MIB,
Op,
i+1, &II, VRBaseMap,
false,
668 MBB->
insert(InsertPos, MIB);
670 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, NewVReg)).second;
672 assert(isNew &&
"Node emitted out of order - early");
682 ->isValidLocationForIntrinsic(
DL) &&
683 "Expected inlined-at fields to agree");
688 "dbg_value with no location operands?");
694 if (EmitDebugInstrRefs)
709 const Value *V =
Op.getConst();
710 if (
const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
711 if (CI->getBitWidth() > 64)
715 if (
const ConstantFP *CF = dyn_cast<ConstantFP>(V))
718 if (isa<ConstantPointerNull>(V))
733 switch (
Op.getKind()) {
747 if (VRBaseMap.
count(V) == 0)
750 AddOperand(MIB, V, (*MIB).
getNumOperands(), &DbgValDesc, VRBaseMap,
808 auto AddVRegOp = [&](
unsigned VReg) {
816 for (
unsigned OpIdx = 0; OpIdx < OpCount; ++OpIdx) {
840 if (
I == VRBaseMap.
end())
844 VReg = getVR(
Op, VRBaseMap);
869 unsigned OperandIdx = 0;
871 if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)
875 assert(OperandIdx < DefMI->getNumOperands());
884 if (MOs.size() != OpCount)
887 return BuildMI(*MF,
DL, RefII,
false, MOs, Var, Expr);
899 return BuildMI(*MF,
DL, Desc,
false, 0U, Var, Expr);
909 const MCInstrDesc &DbgValDesc = TII->
get(TargetOpcode::DBG_VALUE_LIST);
927 "Non variadic dbg_value should have only one location op");
933 const Value *V = LocationOps[0].getConst();
934 if (
auto *
C = dyn_cast<ConstantInt>(V)) {
957 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) &&
958 "Expected inlined-at fields to agree");
971 EmitMachineNode(
SDNode *Node,
bool IsClone,
bool IsCloned,
973 unsigned Opc = Node->getMachineOpcode();
976 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
977 Opc == TargetOpcode::INSERT_SUBREG ||
978 Opc == TargetOpcode::SUBREG_TO_REG) {
979 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
984 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
985 EmitCopyToRegClassNode(Node, VRBaseMap);
990 if (Opc == TargetOpcode::REG_SEQUENCE) {
991 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
995 if (Opc == TargetOpcode::IMPLICIT_DEF)
1012 NumDefs = NumResults;
1015 }
else if (Opc == TargetOpcode::STATEPOINT) {
1016 NumDefs = NumResults;
1019 unsigned NumImpUses = 0;
1020 unsigned NodeOperands =
1024 bool HasPhysRegOuts = NumResults > NumDefs && !II.
implicit_defs().empty() &&
1025 !HasVRegVariadicDefs;
1027 unsigned NumMIOperands = NodeOperands + NumResults;
1030 "Too few operands for a variadic node!");
1035 "#operands for dag node doesn't match .td file!");
1044 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
1049 if (
Flags.hasNoSignedZeros())
1050 MI->setFlag(MachineInstr::MIFlag::FmNsz);
1052 if (
Flags.hasAllowReciprocal())
1053 MI->setFlag(MachineInstr::MIFlag::FmArcp);
1055 if (
Flags.hasNoNaNs())
1056 MI->setFlag(MachineInstr::MIFlag::FmNoNans);
1058 if (
Flags.hasNoInfs())
1059 MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
1061 if (
Flags.hasAllowContract())
1062 MI->setFlag(MachineInstr::MIFlag::FmContract);
1064 if (
Flags.hasApproximateFuncs())
1065 MI->setFlag(MachineInstr::MIFlag::FmAfn);
1067 if (
Flags.hasAllowReassociation())
1068 MI->setFlag(MachineInstr::MIFlag::FmReassoc);
1070 if (
Flags.hasNoUnsignedWrap())
1071 MI->setFlag(MachineInstr::MIFlag::NoUWrap);
1073 if (
Flags.hasNoSignedWrap())
1074 MI->setFlag(MachineInstr::MIFlag::NoSWrap);
1076 if (
Flags.hasExact())
1077 MI->setFlag(MachineInstr::MIFlag::IsExact);
1079 if (
Flags.hasNoFPExcept())
1080 MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
1085 bool HasOptPRefs = NumDefs > NumResults;
1086 assert((!HasOptPRefs || !HasPhysRegOuts) &&
1087 "Unable to cope with optional defs and phys regs defs!");
1088 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
1089 for (
unsigned i = NumSkip;
i != NodeOperands; ++
i)
1090 AddOperand(MIB, Node->getOperand(
i),
i-NumSkip+NumDefs, &II,
1091 VRBaseMap,
false, IsClone, IsCloned);
1095 for (
unsigned i = 0; ScratchRegs[
i]; ++
i)
1101 MIB.
setMemRefs(cast<MachineSDNode>(Node)->memoperands());
1109 MBB->
insert(InsertPos, MIB);
1129 if (HasPhysRegOuts) {
1130 for (
unsigned i = NumDefs;
i < NumResults; ++
i) {
1132 if (!Node->hasAnyUseOfValue(
i))
1135 UsedRegs.push_back(
Reg);
1136 EmitCopyFromReg(Node,
i, IsClone,
Reg, VRBaseMap);
1141 if (Node->getValueType(Node->getNumValues()-1) ==
MVT::Glue) {
1142 for (
SDNode *
F = Node->getGluedUser();
F;
F =
F->getGluedUser()) {
1144 UsedRegs.push_back(cast<RegisterSDNode>(
F->getOperand(1))->getReg());
1155 for (
unsigned i = 0,
e =
F->getNumOperands();
i !=
e; ++
i)
1158 if (
Reg.isPhysical())
1159 UsedRegs.push_back(
Reg);
1168 for (; *RCRegs; ++RCRegs)
1169 UsedRegs.push_back(*RCRegs);
1178 if (Opc == TargetOpcode::STATEPOINT && NumDefs > 0) {
1179 assert(!HasPhysRegOuts &&
"STATEPOINT mishandled");
1183 assert(First > 0 &&
"Statepoint has Defs but no GC ptr list");
1184 unsigned Use = (unsigned)First;
1185 while (
Def < NumDefs) {
1186 if (
MI->getOperand(
Use).isReg())
1200 EmitSpecialNode(
SDNode *Node,
bool IsClone,
bool IsCloned,
1202 switch (Node->getOpcode()) {
1207 llvm_unreachable(
"This target-independent node should have been selected!");
1213 Register DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1214 SDValue SrcVal = Node->getOperand(2);
1219 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1220 TII->
get(TargetOpcode::IMPLICIT_DEF), DestReg);
1225 SrcReg =
R->getReg();
1227 SrcReg = getVR(SrcVal, VRBaseMap);
1229 if (SrcReg == DestReg)
1232 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->
get(TargetOpcode::COPY),
1237 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1238 EmitCopyFromReg(Node, 0, IsClone, SrcReg, VRBaseMap);
1246 MCSymbol *
S = cast<LabelSDNode>(Node)->getLabel();
1247 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1257 auto *FI = cast<FrameIndexSDNode>(Node->getOperand(1));
1258 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->
get(TarOp))
1265 auto Guid = cast<PseudoProbeSDNode>(Node)->getGuid();
1266 auto Index = cast<PseudoProbeSDNode>(Node)->getIndex();
1267 auto Attr = cast<PseudoProbeSDNode>(Node)->getAttributes();
1269 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->
get(TarOp))
1279 unsigned NumOps = Node->getNumOperands();
1280 if (Node->getOperand(NumOps-1).getValueType() ==
MVT::Glue)
1288 BuildMI(*MF, Node->getDebugLoc(), TII->
get(TgtOpc));
1292 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1311 cast<ConstantSDNode>(Node->getOperand(
i))->getZExtValue();
1321 for (
unsigned j = 0;
j != NumVals; ++
j, ++
i) {
1322 Register Reg = cast<RegisterSDNode>(Node->getOperand(
i))->getReg();
1331 for (
unsigned j = 0;
j != NumVals; ++
j, ++
i) {
1332 Register Reg = cast<RegisterSDNode>(Node->getOperand(
i))->getReg();
1335 ECRegs.push_back(
Reg);
1343 for (
unsigned j = 0;
j != NumVals; ++
j, ++
i)
1344 AddOperand(MIB, Node->getOperand(
i), 0,
nullptr, VRBaseMap,
1345 false, IsClone, IsCloned);
1349 unsigned DefGroup = 0;
1351 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1352 unsigned UseIdx = GroupIdx.back() + 1;
1353 for (
unsigned j = 0;
j != NumVals; ++
j)
1359 for (
unsigned j = 0;
j != NumVals; ++
j, ++
i) {
1361 AddOperand(MIB,
Op, 0,
nullptr, VRBaseMap,
1362 false, IsClone, IsCloned);
1365 if (
auto *TGA = dyn_cast<GlobalAddressSDNode>(
Op)) {
1381 for (
unsigned Reg : ECRegs) {
1385 assert(MO &&
"No def operand for clobbered register?");
1392 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1396 MBB->
insert(InsertPos, MIB);
1407 TII(MF->getSubtarget().getInstrInfo()),
1408 TRI(MF->getSubtarget().getRegisterInfo()),
1409 TLI(MF->getSubtarget().getTargetLowering()),
MBB(mbb),
1410 InsertPos(insertpos) {
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
DIExpression * getExpression() const
Returns the DIExpression pointer for the expression.
Holds the information from a dbg_value node through SDISel.
static SDDbgOperand fromConst(const Value *Const)
virtual const MCPhysReg * getRoundingControlRegisters() const
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
std::optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
This is an optimization pass for GlobalISel generic memory operations.
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
static const DIExpression * convertToVariadicExpression(const DIExpression *Expr)
If Expr is a non-variadic expression (i.e.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
const MachineInstrBuilder & add(const MachineOperand &MO) const
@ LIFETIME_START
This corresponds to the llvm.lifetime.
virtual bool usesPhysRegsForValues() const
True if the target uses physical regs (as nearly all targets do).
def_instr_iterator def_instr_begin(Register RegNo) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool useDebugInstrRef() const
Returns true if the function's variable locations are tracked with instruction referencing.
unsigned getResNo() const
Returns the ResNo for a register ref.
Reg
All possible values of the reg field in the ModR/M byte.
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Represents one node in the SelectionDAG.
ArrayRef< MCOperandInfo > operands() const
bool erase(const KeyT &Val)
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
TODO: Might pack better if we changed this to a Struct of Arrays, since MachineOperand is width 32,...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first,...
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Holds the information for a single machine location through SDISel; either an SDNode,...
unsigned const TargetRegisterInfo * TRI
MachineOperand GetMOForConstDbgOp(const SDDbgOperand &Op)
@ Kind_RegDefEarlyClobber
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
bool hasPostISelHook() const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
void AddDbgValueLocationOps(MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, ArrayRef< SDDbgOperand > Locations, DenseMap< SDValue, Register > &VRBaseMap)
@ INLINEASM
INLINEASM - Represents an inline asm block.
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
unsigned getVReg() const
Returns the Virtual Register for a VReg.
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
This is the shared class of boolean and integer constants.
unsigned getDefRegState(bool B)
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineInstr * EmitDbgNoLocation(SDDbgValue *SD)
Emit a DBG_VALUE $noreg, indicating a variable has no location.
Holds the information from a dbg_label node through SDISel.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
static MachineOperand CreateImm(int64_t Val)
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
(vector float) vec_cmpeq(*A, *B) C
const MachineOperand & getOperand(unsigned i) const
bool isIndirect() const
Returns whether this is an indirect value.
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
into llvm powi allowing the code generator to produce balanced multiplication trees First
MachineOperand class - Representation of each machine instruction operand.
@ VREG
Value is a virtual register.
ConstantFP - Floating Point Values [float, double].
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
void setTargetFlags(unsigned F)
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
This struct is a compact representation of a valid (non-zero power of two) alignment.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
static unsigned getKind(unsigned Flags)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
@ AnyReg
Used for dynamic register based calls (e.g.
static DIExpression * append(const DIExpression *Expr, ArrayRef< uint64_t > Ops)
Append the opcodes Ops to DIExpr.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
unsigned getNumOperands() const
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
MDNode * getLabel() const
Returns the MDNode pointer for the label.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
@ EarlyClobber
Register definition happens before uses.
bool isCall() const
Return true if the instruction is a call.
MachineInstr * EmitDbgLabel(SDDbgLabel *SD)
Generate machine instruction for a dbg_label node.
ArrayRef< MCPhysReg > implicit_uses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isInvalidated() const
iterator find(const_arg_type_t< KeyT > Val)
virtual unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const
Classify a global function reference.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
uint64_t getZExtValue() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
MachineInstr * EmitDbgInstrRef(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a dbg_value as a DBG_INSTR_REF.
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
void setIsEarlyClobber(bool Val=true)
unsigned getMachineOpcode() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDNode * getSDNode() const
Returns the SDNode* for a register ref.
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
static const Function * getParent(const Value *V)
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static const DIExpression * convertToUndefExpression(const DIExpression *Expr)
Removes all elements from Expr that do not apply to an undef debug value, which includes every operat...
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
static MachineOperand CreateCImm(const ConstantInt *CI)
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
Base class for variables.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
MI-level Statepoint operands.
const DebugLoc & getDebugLoc() const
Returns the DebugLoc.
Function & getFunction()
Return the LLVM function that this machine code represents.
unsigned getDebugRegState(bool B)
bool isCopyLike() const
Return true if the instruction behaves like a copy.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Completely target-dependent object reference.
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
std::pair< DIExpression *, const ConstantInt * > constantFold(const ConstantInt *CI)
Try to shorten an expression with an initial constant operand.
@ SDNODE
Value is the result of an expression.
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers.
These are IR-level optimization flags that may be propagated to SDNodes.
MachineInstr * EmitDbgValueList(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a DBG_VALUE_LIST from the operands to SDDbgValue.
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const
DIVariable * getVariable() const
Returns the DIVariable pointer for the variable.
ArrayRef< SDDbgOperand > getLocationOps() const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
unsigned getKillRegState(bool B)
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
unsigned getNumOperands() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned getNumOperands() const
Retuns the total number of operands.
@ FRAMEIX
Value is contents of a stack location.
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
@ CONST
Value is a constant.
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
const char LLVMTargetMachineRef TM
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR RN
MachineInstr * EmitDbgValueFromSingleOp(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
Emit a DBG_VALUE from the operands to SDDbgValue.
void setIsEmitted()
setIsEmitted / isEmitted - Getter/Setter for flag indicating that this SDDbgValue has been emitted to...
Value * getOperand(unsigned i) const
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
bool isMachineOpcode() const
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getImplRegState(bool B)
@ Define
Register definition.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
iterator_range< mop_iterator > operands()
LLVM Value Representation.
static MachineOperand CreateFPImm(const ConstantFP *CFP)
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
A Use represents the edge between a Value definition and its users.
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, Register > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.