LLVM  16.0.0git
InstructionSelect.cpp
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the InstructionSelect class.
10 //===----------------------------------------------------------------------===//
11 
14 #include "llvm/ADT/ScopeExit.h"
27 #include "llvm/Config/config.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/TargetRegistry.h"
32 #include "llvm/Support/Debug.h"
34 
35 #define DEBUG_TYPE "instruction-select"
36 
37 using namespace llvm;
38 
39 #ifdef LLVM_GISEL_COV_PREFIX
41  CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
42  cl::desc("Record GlobalISel rule coverage files of this "
43  "prefix if instrumentation was generated"));
44 #else
45 static const std::string CoveragePrefix;
46 #endif
47 
48 char InstructionSelect::ID = 0;
50  "Select target instructions out of generic instructions",
51  false, false)
57  "Select target instructions out of generic instructions",
59 
61  : MachineFunctionPass(ID), OptLevel(OL) {}
62 
63 // In order not to crash when calling getAnalysis during testing with -run-pass
64 // we use the default opt level here instead of None, so that the addRequired()
65 // calls are made in getAnalysisUsage().
67  : MachineFunctionPass(ID), OptLevel(CodeGenOpt::Default) {}
68 
73 
74  if (OptLevel != CodeGenOpt::None) {
77  }
80 }
81 
83  // If the ISel pipeline failed, do not bother running that pass.
84  if (MF.getProperties().hasProperty(
86  return false;
87 
88  LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
89 
90  const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
92 
93  CodeGenOpt::Level OldOptLevel = OptLevel;
94  auto RestoreOptLevel = make_scope_exit([=]() { OptLevel = OldOptLevel; });
96  : MF.getTarget().getOptLevel();
97 
98  GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
99  if (OptLevel != CodeGenOpt::None) {
100  PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
101  if (PSI && PSI->hasProfileSummary())
102  BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
103  }
104 
105  CodeGenCoverage CoverageInfo;
106  assert(ISel && "Cannot work without InstructionSelector");
107  ISel->setupMF(MF, KB, CoverageInfo, PSI, BFI);
108 
109  // An optimization remark emitter. Used to report failures.
110  MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
111 
112  // FIXME: There are many other MF/MFI fields we need to initialize.
113 
115 #ifndef NDEBUG
116  // Check that our input is fully legal: we require the function to have the
117  // Legalized property, so it should be.
118  // FIXME: This should be in the MachineVerifier, as the RegBankSelected
119  // property check already is.
121  if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
122  reportGISelFailure(MF, TPC, MORE, "gisel-select",
123  "instruction is not legal", *MI);
124  return false;
125  }
126  // FIXME: We could introduce new blocks and will need to fix the outer loop.
127  // Until then, keep track of the number of blocks to assert that we don't.
128  const size_t NumBlocks = MF.size();
129 #endif
130  // Keep track of selected blocks, so we can delete unreachable ones later.
131  DenseSet<MachineBasicBlock *> SelectedBlocks;
132 
133  for (MachineBasicBlock *MBB : post_order(&MF)) {
134  ISel->CurMBB = MBB;
135  SelectedBlocks.insert(MBB);
136  if (MBB->empty())
137  continue;
138 
139  // Select instructions in reverse block order. We permit erasing so have
140  // to resort to manually iterating and recognizing the begin (rend) case.
141  bool ReachedBegin = false;
142  for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
143  !ReachedBegin;) {
144 #ifndef NDEBUG
145  // Keep track of the insertion range for debug printing.
146  const auto AfterIt = std::next(MII);
147 #endif
148  // Select this instruction.
149  MachineInstr &MI = *MII;
150 
151  // And have our iterator point to the next instruction, if there is one.
152  if (MII == Begin)
153  ReachedBegin = true;
154  else
155  --MII;
156 
157  LLVM_DEBUG(dbgs() << "Selecting: \n " << MI);
158 
159  // We could have folded this instruction away already, making it dead.
160  // If so, erase it.
161  if (isTriviallyDead(MI, MRI)) {
162  LLVM_DEBUG(dbgs() << "Is dead; erasing.\n");
164  MI.eraseFromParent();
165  continue;
166  }
167 
168  // Eliminate hints.
169  if (isPreISelGenericOptimizationHint(MI.getOpcode())) {
170  Register DstReg = MI.getOperand(0).getReg();
171  Register SrcReg = MI.getOperand(1).getReg();
172 
173  // At this point, the destination register class of the hint may have
174  // been decided.
175  //
176  // Propagate that through to the source register.
177  const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
178  if (DstRC)
179  MRI.setRegClass(SrcReg, DstRC);
180  assert(canReplaceReg(DstReg, SrcReg, MRI) &&
181  "Must be able to replace dst with src!");
182  MI.eraseFromParent();
183  MRI.replaceRegWith(DstReg, SrcReg);
184  continue;
185  }
186 
187  if (!ISel->select(MI)) {
188  // FIXME: It would be nice to dump all inserted instructions. It's
189  // not obvious how, esp. considering select() can insert after MI.
190  reportGISelFailure(MF, TPC, MORE, "gisel-select", "cannot select", MI);
191  return false;
192  }
193 
194  // Dump the range of instructions that MI expanded into.
195  LLVM_DEBUG({
196  auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII);
197  dbgs() << "Into:\n";
198  for (auto &InsertedMI : make_range(InsertedBegin, AfterIt))
199  dbgs() << " " << InsertedMI;
200  dbgs() << '\n';
201  });
202  }
203  }
204 
205  for (MachineBasicBlock &MBB : MF) {
206  if (MBB.empty())
207  continue;
208 
209  if (!SelectedBlocks.contains(&MBB)) {
210  // This is an unreachable block and therefore hasn't been selected, since
211  // the main selection loop above uses a postorder block traversal.
212  // We delete all the instructions in this block since it's unreachable.
213  MBB.clear();
214  // Don't delete the block in case the block has it's address taken or is
215  // still being referenced by a phi somewhere.
216  continue;
217  }
218  // Try to find redundant copies b/w vregs of the same register class.
219  bool ReachedBegin = false;
220  for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
221  // Select this instruction.
222  MachineInstr &MI = *MII;
223 
224  // And have our iterator point to the next instruction, if there is one.
225  if (MII == Begin)
226  ReachedBegin = true;
227  else
228  --MII;
229  if (MI.getOpcode() != TargetOpcode::COPY)
230  continue;
231  Register SrcReg = MI.getOperand(1).getReg();
232  Register DstReg = MI.getOperand(0).getReg();
233  if (Register::isVirtualRegister(SrcReg) &&
234  Register::isVirtualRegister(DstReg)) {
235  auto SrcRC = MRI.getRegClass(SrcReg);
236  auto DstRC = MRI.getRegClass(DstReg);
237  if (SrcRC == DstRC) {
238  MRI.replaceRegWith(DstReg, SrcReg);
239  MI.eraseFromParent();
240  }
241  }
242  }
243  }
244 
245 #ifndef NDEBUG
246  const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
247  // Now that selection is complete, there are no more generic vregs. Verify
248  // that the size of the now-constrained vreg is unchanged and that it has a
249  // register class.
250  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
251  unsigned VReg = Register::index2VirtReg(I);
252 
253  MachineInstr *MI = nullptr;
254  if (!MRI.def_empty(VReg))
255  MI = &*MRI.def_instr_begin(VReg);
256  else if (!MRI.use_empty(VReg)) {
257  MI = &*MRI.use_instr_begin(VReg);
258  // Debug value instruction is permitted to use undefined vregs.
259  if (MI->isDebugValue())
260  continue;
261  }
262  if (!MI)
263  continue;
264 
265  const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
266  if (!RC) {
267  reportGISelFailure(MF, TPC, MORE, "gisel-select",
268  "VReg has no regclass after selection", *MI);
269  return false;
270  }
271 
272  const LLT Ty = MRI.getType(VReg);
273  if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
275  MF, TPC, MORE, "gisel-select",
276  "VReg's low-level type and register class have different sizes", *MI);
277  return false;
278  }
279  }
280 
281  if (MF.size() != NumBlocks) {
282  MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
283  MF.getFunction().getSubprogram(),
284  /*MBB=*/nullptr);
285  R << "inserting blocks is not supported yet";
286  reportGISelFailure(MF, TPC, MORE, R);
287  return false;
288  }
289 #endif
290  // Determine if there are any calls in this machine function. Ported from
291  // SelectionDAG.
292  MachineFrameInfo &MFI = MF.getFrameInfo();
293  for (const auto &MBB : MF) {
294  if (MFI.hasCalls() && MF.hasInlineAsm())
295  break;
296 
297  for (const auto &MI : MBB) {
298  if ((MI.isCall() && !MI.isReturn()) || MI.isStackAligningInlineAsm())
299  MFI.setHasCalls(true);
300  if (MI.isInlineAsm())
301  MF.setHasInlineAsm(true);
302  }
303  }
304 
305  // FIXME: FinalizeISel pass calls finalizeLowering, so it's called twice.
306  auto &TLI = *MF.getSubtarget().getTargetLowering();
307  TLI.finalizeLowering(MF);
308 
309  LLVM_DEBUG({
310  dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
311  for (auto RuleID : CoverageInfo.covered())
312  dbgs() << " id" << RuleID;
313  dbgs() << "\n\n";
314  });
315  CoverageInfo.emit(CoveragePrefix,
316  TLI.getTargetMachine().getTarget().getBackendName());
317 
318  // If we successfully selected the function nothing is going to use the vreg
319  // types after us (otherwise MIRPrinter would need them). Make sure the types
320  // disappear.
322 
323  // FIXME: Should we accurately track changes?
324  return true;
325 }
llvm::InstructionSelect::InstructionSelect
InstructionSelect()
Definition: InstructionSelect.cpp:66
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:182
llvm::MachineFunctionProperties::hasProperty
bool hasProperty(Property P) const
Definition: MachineFunction.h:192
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::InstructionSelect::OptLevel
CodeGenOpt::Level OptLevel
Definition: InstructionSelect.h:61
llvm::Function::hasOptNone
bool hasOptNone() const
Do not optimize this function (-O0).
Definition: Function.h:658
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::isPreISelGenericOptimizationHint
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
llvm::MachineBasicBlock::clear
void clear()
Definition: MachineBasicBlock.h:1001
llvm::ProfileSummaryInfo::hasProfileSummary
bool hasProfileSummary() const
Returns true if profile summary is available.
Definition: ProfileSummaryInfo.h:68
llvm::MachineRegisterInfo::def_instr_begin
def_instr_iterator def_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:405
llvm::InstructionSelect::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: InstructionSelect.cpp:82
GISelKnownBits.h
LazyBlockFrequencyInfo.h
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The optimization diagnostic interface.
Definition: MachineOptimizationRemarkEmitter.h:151
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MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::InstructionSelector::setupMF
virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB, CodeGenCoverage &covinfo, ProfileSummaryInfo *psi, BlockFrequencyInfo *bfi)
Setup per-MF selector state.
Definition: InstructionSelector.h:457
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cl::opt< bool > DisableGISelLegalityCheck
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
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static void getLazyBFIAnalysisUsage(AnalysisUsage &AU)
Helper for client passes to set up the analysis usage on behalf of this pass.
Definition: LazyBlockFrequencyInfo.cpp:62
InstructionSelect.h
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:770
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void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:880
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static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::detail::DenseSetImpl< ValueT, DenseMap< ValueT, detail::DenseSetEmpty, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::insert
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Definition: DenseSet.h:206
LegalizerInfo.h
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unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
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iterator_range< const_covered_iterator > covered() const
Definition: CodeGenCoverage.cpp:41
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bool emit(StringRef FilePrefix, StringRef BackendName) const
Definition: CodeGenCoverage.cpp:78
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void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:167
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE, "Select target instructions out of generic instructions", false, false) INITIALIZE_PASS_END(InstructionSelect
MachineRegisterInfo.h
llvm::LazyBlockFrequencyInfoPass
This is an alternative analysis pass to BlockFrequencyInfoWrapperPass.
Definition: LazyBlockFrequencyInfo.h:98
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virtual InstructionSelector * getInstructionSelector() const
Definition: TargetSubtargetInfo.h:111
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
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TargetLowering.h
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MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
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Definition: GISelKnownBits.h:113
TargetMachine.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
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TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
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Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
Utils.h
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const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:747
false
Definition: StackSlotColoring.cpp:141
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unsigned size() const
Definition: MachineFunction.h:863
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
llvm::machineFunctionIsIllegal
const MachineInstr * machineFunctionIsIllegal(const MachineFunction &MF)
Checks that MIR is fully legal, returns an illegal instruction if it's not, nullptr otherwise.
Definition: LegalizerInfo.cpp:424
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Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Definition: Utils.cpp:1334
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void clearVirtRegTypes()
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Definition: MachineRegisterInfo.cpp:197
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bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:514
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unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
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Definition: MachineBasicBlock.h:94
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#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
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def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:434
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const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:647
MachineOptimizationRemarkEmitter.h
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
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Definition: TargetPassConfig.h:84
InstructionSelector.h
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Implements a dense probed hash-table based set.
Definition: DenseSet.h:268
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const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
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Definition: CommandLine.h:1399
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Definition: InstIterator.h:133
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Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:428
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Definition: CodeGenCoverage.h:19
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
ProfileSummaryInfo.h
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Diagnostic information for missed-optimization remarks.
Definition: MachineOptimizationRemarkEmitter.h:83
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use_instr_iterator use_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:485
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static const std::string CoveragePrefix
Definition: InstructionSelect.cpp:45
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Definition: InstructionSelect.h:58
I
#define I(x, y, z)
Definition: MD5.cpp:58
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Definition: CommandLine.h:439
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Definition: ProfileSummaryInfo.h:193
TargetPassConfig.h
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Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
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const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:664
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StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:567
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bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:212
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Definition: MachineFunction.h:257
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@ None
Definition: CodeGen.h:53
DEBUG_TYPE
#define DEBUG_TYPE
Definition: InstructionSelect.cpp:35
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void setHasCalls(bool V)
Definition: MachineFrameInfo.h:606
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AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
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Definition: DenseSet.h:185
TargetSubtargetInfo.h
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static char ID
Definition: InstructionSelect.h:35
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Definition: CodeGen.h:33
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Definition: CodeGen.h:52
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Definition: InstructionSelect.h:59
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#define MORE()
Definition: regcomp.c:252
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unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
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Wrapper class representing virtual and physical registers.
Definition: Register.h:19
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detail::scope_exit< std::decay_t< Callable > > make_scope_exit(Callable &&F)
Definition: ScopeExit.h:59
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bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:605
llvm::MachineRegisterInfo::replaceRegWith
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
Definition: MachineRegisterInfo.cpp:378
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@ Select
Definition: MCInstrDesc.h:164
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
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@ FailedISel
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Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
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unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:280
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:652
MachineFrameInfo.h
llvm::canReplaceReg
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:198
llvm::post_order
iterator_range< po_iterator< T > > post_order(const T &G)
Definition: PostOrderIterator.h:189
Function.h
llvm::reportGISelFailure
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:268
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
PostOrderIterator.h
llvm::InstructionSelect::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Definition: InstructionSelect.cpp:69
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iterator begin()
Definition: MachineBasicBlock.h:305
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:745
llvm::InstructionSelector::CurMBB
MachineBasicBlock * CurMBB
Definition: InstructionSelector.h:450
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:277
ScopeExit.h
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AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::cl::desc
Definition: CommandLine.h:412
TargetRegistry.h
Debug.h
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iterator end()
Definition: MachineBasicBlock.h:307
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:56
of
Add support for conditional and other related patterns Instead of
Definition: README.txt:134
llvm::InstructionSelector::select
virtual bool select(MachineInstr &I)=0
Select the (possibly generic) instruction I to only use target-specific opcodes.
llvm::LLT
Definition: LowLevelTypeImpl.h:39