LLVM  10.0.0svn
InstructionSelect.cpp
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the InstructionSelect class.
10 //===----------------------------------------------------------------------===//
11 
14 #include "llvm/ADT/Twine.h"
23 #include "llvm/Config/config.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
27 #include "llvm/Support/Debug.h"
29 
30 #define DEBUG_TYPE "instruction-select"
31 
32 using namespace llvm;
33 
34 #ifdef LLVM_GISEL_COV_PREFIX
36  CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
37  cl::desc("Record GlobalISel rule coverage files of this "
38  "prefix if instrumentation was generated"));
39 #else
40 static const std::string CoveragePrefix = "";
41 #endif
42 
43 char InstructionSelect::ID = 0;
45  "Select target instructions out of generic instructions",
46  false, false)
49  "Select target instructions out of generic instructions",
50  false, false)
51 
52 InstructionSelect::InstructionSelect() : MachineFunctionPass(ID) { }
53 
58 }
59 
61  // If the ISel pipeline failed, do not bother running that pass.
62  if (MF.getProperties().hasProperty(
64  return false;
65 
66  LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
67 
68  const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
70  CodeGenCoverage CoverageInfo;
71  assert(ISel && "Cannot work without InstructionSelector");
72  ISel->setupMF(MF, CoverageInfo);
73 
74  // An optimization remark emitter. Used to report failures.
75  MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
76 
77  // FIXME: There are many other MF/MFI fields we need to initialize.
78 
80 #ifndef NDEBUG
81  // Check that our input is fully legal: we require the function to have the
82  // Legalized property, so it should be.
83  // FIXME: This should be in the MachineVerifier, as the RegBankSelected
84  // property check already is.
86  if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
87  reportGISelFailure(MF, TPC, MORE, "gisel-select",
88  "instruction is not legal", *MI);
89  return false;
90  }
91  // FIXME: We could introduce new blocks and will need to fix the outer loop.
92  // Until then, keep track of the number of blocks to assert that we don't.
93  const size_t NumBlocks = MF.size();
94 #endif
95 
96  for (MachineBasicBlock *MBB : post_order(&MF)) {
97  if (MBB->empty())
98  continue;
99 
100  // Select instructions in reverse block order. We permit erasing so have
101  // to resort to manually iterating and recognizing the begin (rend) case.
102  bool ReachedBegin = false;
103  for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
104  !ReachedBegin;) {
105 #ifndef NDEBUG
106  // Keep track of the insertion range for debug printing.
107  const auto AfterIt = std::next(MII);
108 #endif
109  // Select this instruction.
110  MachineInstr &MI = *MII;
111 
112  // And have our iterator point to the next instruction, if there is one.
113  if (MII == Begin)
114  ReachedBegin = true;
115  else
116  --MII;
117 
118  LLVM_DEBUG(dbgs() << "Selecting: \n " << MI);
119 
120  // We could have folded this instruction away already, making it dead.
121  // If so, erase it.
122  if (isTriviallyDead(MI, MRI)) {
123  LLVM_DEBUG(dbgs() << "Is dead; erasing.\n");
125  continue;
126  }
127 
128  if (!ISel->select(MI)) {
129  // FIXME: It would be nice to dump all inserted instructions. It's
130  // not obvious how, esp. considering select() can insert after MI.
131  reportGISelFailure(MF, TPC, MORE, "gisel-select", "cannot select", MI);
132  return false;
133  }
134 
135  // Dump the range of instructions that MI expanded into.
136  LLVM_DEBUG({
137  auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII);
138  dbgs() << "Into:\n";
139  for (auto &InsertedMI : make_range(InsertedBegin, AfterIt))
140  dbgs() << " " << InsertedMI;
141  dbgs() << '\n';
142  });
143  }
144  }
145 
146  for (MachineBasicBlock &MBB : MF) {
147  if (MBB.empty())
148  continue;
149 
150  // Try to find redundant copies b/w vregs of the same register class.
151  bool ReachedBegin = false;
152  for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
153  // Select this instruction.
154  MachineInstr &MI = *MII;
155 
156  // And have our iterator point to the next instruction, if there is one.
157  if (MII == Begin)
158  ReachedBegin = true;
159  else
160  --MII;
161  if (MI.getOpcode() != TargetOpcode::COPY)
162  continue;
163  Register SrcReg = MI.getOperand(1).getReg();
164  Register DstReg = MI.getOperand(0).getReg();
165  if (Register::isVirtualRegister(SrcReg) &&
166  Register::isVirtualRegister(DstReg)) {
167  auto SrcRC = MRI.getRegClass(SrcReg);
168  auto DstRC = MRI.getRegClass(DstReg);
169  if (SrcRC == DstRC) {
170  MRI.replaceRegWith(DstReg, SrcReg);
172  }
173  }
174  }
175  }
176 
177 #ifndef NDEBUG
178  const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
179  // Now that selection is complete, there are no more generic vregs. Verify
180  // that the size of the now-constrained vreg is unchanged and that it has a
181  // register class.
182  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
183  unsigned VReg = Register::index2VirtReg(I);
184 
185  MachineInstr *MI = nullptr;
186  if (!MRI.def_empty(VReg))
187  MI = &*MRI.def_instr_begin(VReg);
188  else if (!MRI.use_empty(VReg))
189  MI = &*MRI.use_instr_begin(VReg);
190  if (!MI)
191  continue;
192 
193  const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
194  if (!RC) {
195  reportGISelFailure(MF, TPC, MORE, "gisel-select",
196  "VReg has no regclass after selection", *MI);
197  return false;
198  }
199 
200  const LLT Ty = MRI.getType(VReg);
201  if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
203  MF, TPC, MORE, "gisel-select",
204  "VReg's low-level type and register class have different sizes", *MI);
205  return false;
206  }
207  }
208 
209  if (MF.size() != NumBlocks) {
210  MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
211  MF.getFunction().getSubprogram(),
212  /*MBB=*/nullptr);
213  R << "inserting blocks is not supported yet";
214  reportGISelFailure(MF, TPC, MORE, R);
215  return false;
216  }
217 #endif
218  auto &TLI = *MF.getSubtarget().getTargetLowering();
219  TLI.finalizeLowering(MF);
220 
221  LLVM_DEBUG({
222  dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
223  for (auto RuleID : CoverageInfo.covered())
224  dbgs() << " id" << RuleID;
225  dbgs() << "\n\n";
226  });
227  CoverageInfo.emit(CoveragePrefix,
228  MF.getSubtarget()
229  .getTargetLowering()
230  ->getTargetMachine()
231  .getTarget()
232  .getBackendName());
233 
234  // If we successfully selected the function nothing is going to use the vreg
235  // types after us (otherwise MIRPrinter would need them). Make sure the types
236  // disappear.
237  MRI.clearVirtRegTypes();
238 
239  // FIXME: Should we accurately track changes?
240  return true;
241 }
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:412
const MachineFunctionProperties & getProperties() const
Get the function properties.
unsigned size() const
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
unsigned const TargetRegisterInfo * TRI
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:83
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
bool emit(StringRef FilePrefix, StringRef BackendName) const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
Target-Independent Code Generator Pass Configuration Options.
INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE, "Select target instructions out of generic instructions", false, false) INITIALIZE_PASS_END(InstructionSelect
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink &#39;this&#39; from the containing basic block and delete it.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Represent the analysis usage information of a pass.
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool isValid() const
virtual InstructionSelector * getInstructionSelector() const
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
iterator_range< po_iterator< T > > post_order(const T &G)
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static const std::string CoveragePrefix
cl::opt< bool > DisableGISelLegalityCheck
#define DEBUG_TYPE
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
const MachineInstr * machineFunctionIsIllegal(const MachineFunction &MF)
Checks that MIR is fully legal, returns an illegal instruction if it&#39;s not, nullptr otherwise...
The optimization diagnostic interface.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
#define MORE()
Definition: regcomp.c:251
This pass is responsible for selecting generic machine instructions to target-specific instructions...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
def_instr_iterator def_instr_begin(unsigned RegNo) const
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Provides the logic to select generic machine instructions.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:158
Representation of each machine instruction.
Definition: MachineInstr.h:64
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
iterator_range< const_covered_iterator > covered() const
#define I(x, y, z)
Definition: MD5.cpp:58
Diagnostic information for missed-optimization remarks.
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasProperty(Property P) const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
IRTranslator LLVM IR MI
inst_range instructions(Function *F)
Definition: InstIterator.h:133
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:178
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This file describes how to lower LLVM code to machine code.