27#include "llvm/Config/config.h"
35#define DEBUG_TYPE "instruction-select"
39#ifdef LLVM_GISEL_COV_PREFIX
42 cl::desc(
"Record GlobalISel rule coverage files of this "
43 "prefix if instrumentation was generated"));
50 "Select target instructions out of generic instructions",
98 GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
100 PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
102 BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
106 assert(ISel &&
"Cannot work without InstructionSelector");
123 "instruction is not legal", *
MI);
128 const size_t NumBlocks = MF.
size();
141 bool ReachedBegin =
false;
146 const auto AfterIt = std::next(MII);
164 MI.eraseFromParent();
179 MRI.setRegClass(SrcReg, DstRC);
181 "Must be able to replace dst with src!");
182 MI.eraseFromParent();
183 MRI.replaceRegWith(DstReg, SrcReg);
187 if (
MI.getOpcode() == TargetOpcode::G_INVOKE_REGION_START) {
188 MI.eraseFromParent();
201 auto InsertedBegin = ReachedBegin ?
MBB->
begin() : std::next(MII);
203 for (
auto &InsertedMI :
make_range(InsertedBegin, AfterIt))
204 dbgs() <<
" " << InsertedMI;
224 bool ReachedBegin =
false;
225 for (
auto MII = std::prev(
MBB.
end()), Begin =
MBB.
begin(); !ReachedBegin;) {
234 if (
MI.getOpcode() != TargetOpcode::COPY)
239 auto SrcRC =
MRI.getRegClass(SrcReg);
240 auto DstRC =
MRI.getRegClass(DstReg);
241 if (SrcRC == DstRC) {
242 MRI.replaceRegWith(DstReg, SrcReg);
243 MI.eraseFromParent();
254 for (
unsigned I = 0,
E =
MRI.getNumVirtRegs();
I !=
E; ++
I) {
258 if (!
MRI.def_empty(VReg))
259 MI = &*
MRI.def_instr_begin(VReg);
260 else if (!
MRI.use_empty(VReg)) {
261 MI = &*
MRI.use_instr_begin(VReg);
263 if (
MI->isDebugValue())
272 "VReg has no regclass after selection", *
MI);
276 const LLT Ty =
MRI.getType(VReg);
279 MF, TPC,
MORE,
"gisel-select",
280 "VReg's low-level type and register class have different sizes", *
MI);
285 if (MF.
size() != NumBlocks) {
289 R <<
"inserting blocks is not supported yet";
297 for (
const auto &
MBB : MF) {
301 for (
const auto &
MI :
MBB) {
302 if ((
MI.isCall() && !
MI.isReturn()) ||
MI.isStackAligningInlineAsm())
304 if (
MI.isInlineAsm())
314 dbgs() <<
"Rules covered by selecting function: " << MF.
getName() <<
":";
315 for (
auto RuleID : CoverageInfo.
covered())
316 dbgs() <<
" id" << RuleID;
320 TLI.getTargetMachine().getTarget().getBackendName());
325 MRI.clearVirtRegTypes();
unsigned const MachineRegisterInfo * MRI
amdgpu AMDGPU Register Bank Select
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Provides analysis for querying information about KnownBits during GISel passes.
Select target instructions out of generic instructions
static const std::string CoveragePrefix
Interface for Targets to specify which operations they can successfully select and how the others sho...
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the make_scope_exit function, which executes user-defined cleanup logic at scope ex...
This file describes how to lower LLVM code to machine code.
Target-Independent Code Generator Pass Configuration Options pass.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
iterator_range< const_covered_iterator > covered() const
bool emit(StringRef FilePrefix, StringRef BackendName) const
Implements a dense probed hash-table based set.
DISubprogram * getSubprogram() const
Get the attached subprogram.
bool hasOptNone() const
Do not optimize this function (-O0).
To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelKnownBitsInfoAnalysis...
This pass is responsible for selecting generic machine instructions to target-specific instructions.
CodeGenOpt::Level OptLevel
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Provides the logic to select generic machine instructions.
virtual bool select(MachineInstr &I)=0
Select the (possibly generic) instruction I to only use target-specific opcodes.
virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB, CodeGenCoverage &covinfo, ProfileSummaryInfo *psi, BlockFrequencyInfo *bfi)
Setup per-MF selector state.
MachineBasicBlock * CurMBB
constexpr bool isValid() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
This is an alternative analysis pass to BlockFrequencyInfoWrapperPass.
static void getLazyBFIAnalysisUsage(AnalysisUsage &AU)
Helper for client passes to set up the analysis usage on behalf of this pass.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasCalls() const
Return true if the current function has any function calls.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool hasProperty(Property P) const
void setHasInlineAsm(bool B)
Set a flag that indicates that the function contains inline assembly.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
An analysis pass based on legacy pass manager to deliver ProfileSummaryInfo.
bool hasProfileSummary() const
Returns true if profile summary is available.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Target-Independent Code Generator Pass Configuration Options.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual InstructionSelector * getInstructionSelector() const
virtual const TargetLowering * getTargetLowering() const
std::pair< iterator, bool > insert(const ValueT &V)
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
Level
Code generation optimization level.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
detail::scope_exit< std::decay_t< Callable > > make_scope_exit(Callable &&F)
void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
iterator_range< po_iterator< T > > post_order(const T &G)
bool isPreISelGenericOptimizationHint(unsigned Opcode)
cl::opt< bool > DisableGISelLegalityCheck
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const MachineInstr * machineFunctionIsIllegal(const MachineFunction &MF)
Checks that MIR is fully legal, returns an illegal instruction if it's not, nullptr otherwise.
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...