LLVM 17.0.0git
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1//===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9/// \file
10/// R600 DAG Lowering interface definition
17#include "AMDGPUISelLowering.h"
20namespace llvm {
22class R600Subtarget;
26 const R600Subtarget *Subtarget;
34 MachineBasicBlock *BB) const override;
35 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
36 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
39 SelectionDAG &DAG) const override;
40 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
42 bool isVarArg,
44 const SDLoc &DL, SelectionDAG &DAG,
45 SmallVectorImpl<SDValue> &InVals) const override;
47 EVT VT) const override;
49 bool canMergeStoresTo(unsigned AS, EVT MemVT,
50 const MachineFunction &MF) const override;
53 EVT VT, unsigned AS, Align Alignment,
55 unsigned *IsFast = nullptr) const override;
57 bool canCombineTruncStore(EVT ValVT, EVT MemVT,
58 bool LegalOperations) const override {
59 // R600 has "custom" lowering for truncating stores despite not supporting
60 // those instructions. If we allow that custom lowering in the DAG combiner
61 // then all truncates are merged into truncating stores, giving worse code
62 // generation. This hook prevents the DAG combiner performing that combine.
63 return isTruncStoreLegal(ValVT, MemVT);
64 }
67 unsigned Gen;
68 /// Each OpenCL kernel has nine implicit parameters that are stored in the
69 /// first nine dwords of a Vertex Buffer. These implicit parameters are
70 /// lowered to load instructions which retrieve the values from the Vertex
71 /// Buffer.
72 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
73 unsigned DwordOffset) const;
75 void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
76 MachineRegisterInfo & MRI, unsigned dword_offset) const;
77 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[],
78 SelectionDAG &DAG, const SDLoc &DL) const;
79 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
81 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
85 SelectionDAG &DAG) const override;
86 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
88 SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
89 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
90 SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
91 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
93 SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
95 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
96 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
97 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
98 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
99 SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
100 unsigned mainop, unsigned ovf) const;
102 SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
103 SelectionDAG &DAG) const;
104 void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
105 unsigned &Channel, unsigned &PtrIncr) const;
106 bool isZero(SDValue Op) const;
107 bool isHWTrueValue(SDValue Op) const;
108 bool isHWFalseValue(SDValue Op) const;
110 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
111 SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
112 SelectionDAG &DAG) const;
113 SDValue constBufferLoad(LoadSDNode *LoadNode, int Block,
114 SelectionDAG &DAG) const;
116 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
119 shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const override;
122} // End namespace llvm;
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Interface definition of the TargetLowering class that is common to all AMD GPUs.
Function Alias Analysis Results
IRTranslator LLVM IR MI
const char LLVMTargetMachineRef TM
@ Flags
Definition: TextStubV5.cpp:93
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
This class is used to represent ISD::LOAD nodes.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags values. These may be or'd together.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
An SDNode that represents everything that will be needed to construct a MachineInstr.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
const R600Subtarget * getSubtarget() const
bool canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const override
Return the ValueType of the result of SETCC operations.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *IsFast=nullptr) const override
Determine if the target supports unaligned memory accesses.
bool canCombineTruncStore(EVT ValVT, EVT MemVT, bool LegalOperations) const override
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
XXX Only kernel functions are supported, so we can assume for now that every function is a kernel fun...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This class is used to represent ISD::STORE nodes.
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34