LLVM  14.0.0git
AMDGPUMCInstLower.cpp
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1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14 
15 #include "AMDGPUMCInstLower.h"
16 #include "AMDGPUAsmPrinter.h"
17 #include "AMDGPUTargetMachine.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/MC/MCCodeEmitter.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/Support/Format.h"
33 #include <algorithm>
34 
35 using namespace llvm;
36 
37 #include "AMDGPUGenMCPseudoLowering.inc"
38 
40  const TargetSubtargetInfo &st,
41  const AsmPrinter &ap):
42  Ctx(ctx), ST(st), AP(ap) { }
43 
44 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
45  switch (MOFlags) {
46  default:
47  return MCSymbolRefExpr::VK_None;
49  return MCSymbolRefExpr::VK_GOTPCREL;
50  case SIInstrInfo::MO_GOTPCREL32_LO:
51  return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO;
52  case SIInstrInfo::MO_GOTPCREL32_HI:
53  return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI;
54  case SIInstrInfo::MO_REL32_LO:
55  return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
56  case SIInstrInfo::MO_REL32_HI:
57  return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
58  case SIInstrInfo::MO_ABS32_LO:
59  return MCSymbolRefExpr::VK_AMDGPU_ABS32_LO;
60  case SIInstrInfo::MO_ABS32_HI:
61  return MCSymbolRefExpr::VK_AMDGPU_ABS32_HI;
62  }
63 }
64 
66  MCOperand &MCOp) const {
67  switch (MO.getType()) {
68  default:
69  break;
70  case MachineOperand::MO_Immediate:
71  MCOp = MCOperand::createImm(MO.getImm());
72  return true;
73  case MachineOperand::MO_Register:
74  MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
75  return true;
76  case MachineOperand::MO_MachineBasicBlock:
77  MCOp = MCOperand::createExpr(
78  MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx));
79  return true;
80  case MachineOperand::MO_GlobalAddress: {
81  const GlobalValue *GV = MO.getGlobal();
85  const MCExpr *Expr =
86  MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
87  int64_t Offset = MO.getOffset();
88  if (Offset != 0) {
89  Expr = MCBinaryExpr::createAdd(Expr,
90  MCConstantExpr::create(Offset, Ctx), Ctx);
91  }
92  MCOp = MCOperand::createExpr(Expr);
93  return true;
94  }
95  case MachineOperand::MO_ExternalSymbol: {
97  Sym->setExternal(true);
98  const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
99  MCOp = MCOperand::createExpr(Expr);
100  return true;
101  }
102  case MachineOperand::MO_RegisterMask:
103  // Regmasks are like implicit defs.
104  return false;
105  case MachineOperand::MO_MCSymbol:
106  if (MO.getTargetFlags() == SIInstrInfo::MO_FAR_BRANCH_OFFSET) {
107  MCSymbol *Sym = MO.getMCSymbol();
108  MCOp = MCOperand::createExpr(Sym->getVariableValue());
109  return true;
110  }
111  break;
112  }
113  llvm_unreachable("unknown operand type");
114 }
115 
116 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
117  unsigned Opcode = MI->getOpcode();
118  const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
119 
120  // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
121  // need to select it to the subtarget specific version, and there's no way to
122  // do that with a single pseudo source operation.
123  if (Opcode == AMDGPU::S_SETPC_B64_return)
124  Opcode = AMDGPU::S_SETPC_B64;
125  else if (Opcode == AMDGPU::SI_CALL) {
126  // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
127  // called function (which we need to remove here).
128  OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
129  MCOperand Dest, Src;
130  lowerOperand(MI->getOperand(0), Dest);
131  lowerOperand(MI->getOperand(1), Src);
132  OutMI.addOperand(Dest);
133  OutMI.addOperand(Src);
134  return;
135  } else if (Opcode == AMDGPU::SI_TCRETURN) {
136  // TODO: How to use branch immediate and avoid register+add?
137  Opcode = AMDGPU::S_SETPC_B64;
138  }
139 
140  int MCOpcode = TII->pseudoToMCOpcode(Opcode);
141  if (MCOpcode == -1) {
142  LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
143  C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
144  "a target-specific version: " + Twine(MI->getOpcode()));
145  }
146 
147  OutMI.setOpcode(MCOpcode);
148 
149  for (const MachineOperand &MO : MI->explicit_operands()) {
150  MCOperand MCOp;
151  lowerOperand(MO, MCOp);
152  OutMI.addOperand(MCOp);
153  }
154 
155  int FIIdx = AMDGPU::getNamedOperandIdx(MCOpcode, AMDGPU::OpName::fi);
156  if (FIIdx >= (int)OutMI.getNumOperands())
157  OutMI.addOperand(MCOperand::createImm(0));
158 }
159 
160 bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
161  MCOperand &MCOp) const {
162  const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
163  AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
164  return MCInstLowering.lowerOperand(MO, MCOp);
165 }
166 
168  if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
169  return E;
170  return AsmPrinter::lowerConstant(CV);
171 }
172 
175  return;
176 
177  const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
178  AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
179 
180  StringRef Err;
181  if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
182  LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
183  C.emitError("Illegal instruction detected: " + Err);
184  MI->print(errs());
185  }
186 
187  if (MI->isBundle()) {
188  const MachineBasicBlock *MBB = MI->getParent();
189  MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
190  while (I != MBB->instr_end() && I->isInsideBundle()) {
191  emitInstruction(&*I);
192  ++I;
193  }
194  } else {
195  // We don't want these pseudo instructions encoded. They are
196  // placeholder terminator instructions and should only be printed as
197  // comments.
198  if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
199  if (isVerbose())
200  OutStreamer->emitRawComment(" return to shader part epilog");
201  return;
202  }
203 
204  if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
205  if (isVerbose())
206  OutStreamer->emitRawComment(" wave barrier");
207  return;
208  }
209 
210  if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
211  if (isVerbose())
212  OutStreamer->emitRawComment(" divergent unreachable");
213  return;
214  }
215 
216  if (MI->isMetaInstruction()) {
217  if (isVerbose())
218  OutStreamer->emitRawComment(" meta instruction");
219  return;
220  }
221 
222  MCInst TmpInst;
223  MCInstLowering.lower(MI, TmpInst);
224  EmitToStreamer(*OutStreamer, TmpInst);
225 
226 #ifdef EXPENSIVE_CHECKS
227  // Sanity-check getInstSizeInBytes on explicitly specified CPUs (it cannot
228  // work correctly for the generic CPU).
229  //
230  // The isPseudo check really shouldn't be here, but unfortunately there are
231  // some negative lit tests that depend on being able to continue through
232  // here even when pseudo instructions haven't been lowered.
233  //
234  // We also overestimate branch sizes with the offset bug.
235  if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU()) &&
236  (!STI.hasOffset3fBug() || !MI->isBranch())) {
238  SmallVector<char, 16> CodeBytes;
239  raw_svector_ostream CodeStream(CodeBytes);
240 
241  std::unique_ptr<MCCodeEmitter> InstEmitter(createSIMCCodeEmitter(
243  InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI);
244 
245  assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI));
246  }
247 #endif
248 
249  if (DumpCodeInstEmitter) {
250  // Disassemble instruction/operands to text
251  DisasmLines.resize(DisasmLines.size() + 1);
252  std::string &DisasmLine = DisasmLines.back();
253  raw_string_ostream DisasmStream(DisasmLine);
254 
255  AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *STI.getInstrInfo(),
256  *STI.getRegisterInfo());
257  InstPrinter.printInst(&TmpInst, 0, StringRef(), STI, DisasmStream);
258 
259  // Disassemble instruction/operands to hex representation.
261  SmallVector<char, 16> CodeBytes;
262  raw_svector_ostream CodeStream(CodeBytes);
263 
264  DumpCodeInstEmitter->encodeInstruction(
265  TmpInst, CodeStream, Fixups, MF->getSubtarget<MCSubtargetInfo>());
266  HexLines.resize(HexLines.size() + 1);
267  std::string &HexLine = HexLines.back();
268  raw_string_ostream HexStream(HexLine);
269 
270  for (size_t i = 0; i < CodeBytes.size(); i += 4) {
271  unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
272  HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
273  }
274 
275  DisasmStream.flush();
276  DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
277  }
278  }
279 }
i
i
Definition: README.txt:29
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:1545
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::AsmPrinter::lowerConstant
virtual const MCExpr * lowerConstant(const Constant *CV)
Lower the specified LLVM Constant to an MCExpr.
Definition: AsmPrinter.cpp:2472
AMDGPUMCInstLower::lowerOperand
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const
Definition: AMDGPUMCInstLower.cpp:65
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:563
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
AMDGPUMCInstLower
Definition: AMDGPUMCInstLower.h:29
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:425
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virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
MCCodeEmitter.h
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A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:625
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Definition: SmallVector.h:1168
ErrorHandling.h
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Definition: AsmPrinter.cpp:481
MachineBasicBlock.h
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Definition: SIMCCodeEmitter.cpp:81
Offset
uint64_t Offset
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Definition: GCNSubtarget.h:31
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Definition: raw_ostream.cpp:893
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Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
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LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
Format.h
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int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:600
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unsigned getNumOperands() const
Definition: MCInst.h:208
llvm::GCNSubtarget::getRegisterInfo
const SIRegisterInfo * getRegisterInfo() const override
Definition: GCNSubtarget.h:219
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition: MachineOperand.h:573
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Definition: AsmPrinter.cpp:243
llvm::GCNSubtarget::getInstrInfo
const SIInstrInfo * getInstrInfo() const override
Definition: GCNSubtarget.h:207
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Definition: MCInst.h:197
MCObjectStreamer.h
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Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:60
llvm::AMDGPUAsmPrinter::emitInstruction
void emitInstruction(const MachineInstr *MI) override
Implemented in AMDGPUMCInstLower.cpp.
Definition: AMDGPUMCInstLower.cpp:173
llvm::MCContext::getOrCreateSymbol
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Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:191
llvm::AMDGPUInstPrinter
Definition: AMDGPUInstPrinter.h:19
Constants.h
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Definition: SIInstrInfo.cpp:7285
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int64_t getImm() const
Definition: MachineOperand.h:537
llvm::AsmPrinter::OutStreamer
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:97
C
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Definition: README_ALTIVEC.txt:86
MCContext.h
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const MCExpr * getVariableValue(bool SetUsed=true) const
getVariableValue - Get the value for variable symbols.
Definition: MCSymbol.h:298
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
llvm::raw_ostream::flush
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Definition: raw_ostream.h:186
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Definition: MachineBasicBlock.h:95
llvm::MCInst::addOperand
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Definition: MCInst.h:210
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Definition: GCNSubtarget.h:857
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print - Print out the internal state of the pass.
Definition: Pass.cpp:125
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const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:630
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Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
AMDGPUMCTargetDesc.h
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VariantKind
Definition: MCExpr.h:194
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:221
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
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This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
I
#define I(x, y, z)
Definition: MD5.cpp:59
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getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:219
assert
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Definition: AMDGPUAsmPrinter.h:136
llvm::AsmPrinter::MF
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The current machine function.
Definition: AsmPrinter.h:100
llvm::AsmPrinter::OutContext
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This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:92
AMDGPUMCInstLower::lower
void lower(const MachineInstr *MI, MCInst &OutMI) const
Lower a MachineInstr to an MCInst.
Definition: AMDGPUMCInstLower.cpp:116
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
AMDGPUMCInstLower.h
llvm::MCSymbolRefExpr
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
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Definition: MachineBasicBlock.h:254
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const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:207
llvm::AMDGPUAsmPrinter::lowerConstant
const MCExpr * lowerConstant(const Constant *CV) override
Lower the specified LLVM Constant to an MCExpr.
Definition: AMDGPUMCInstLower.cpp:167
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
getVariantKind
static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags)
Definition: AMDGPUMCInstLower.cpp:44
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
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bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Definition: SIInstrInfo.cpp:3773
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#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
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These are helper functions used to produce formatted output.
Definition: Format.h:124
llvm::AMDGPUAsmPrinter::DisasmLineMaxLen
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Definition: AMDGPUAsmPrinter.h:137
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Definition: TargetSubtargetInfo.h:59
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Definition: AArch64SLSHardening.cpp:74
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Key for Kernel::Metadata::mSymbolName.
Definition: AMDGPUMetadata.h:381
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Definition: Twine.h:83
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void setExternal(bool Value) const
Definition: MCSymbol.h:402
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Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
GlobalVariable.h
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This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:82
llvm::AMDGPUInstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition: AMDGPUInstPrinter.cpp:49
llvm::SIInstrInfo
Definition: SIInstrInfo.h:38
llvm::AMDGPUAsmPrinter::emitPseudoExpansionLowering
bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, const MachineInstr *MI)
tblgen'erated driver function for lowering simple MI->MC pseudo instructions.
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TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:85
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:608
MCStreamer.h
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Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
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A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:658
llvm::M68kII::MO_GOTPCREL
@ MO_GOTPCREL
On a symbol operand this indicates that the immediate is offset to the GOT entry for the symbol name ...
Definition: M68kBaseInfo.h:108
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::AsmPrinter::isVerbose
bool isVerbose() const
Return true if assembly output should contain comments.
Definition: AsmPrinter.h:238
llvm::AMDGPUAsmPrinter::HexLines
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Definition: AMDGPUAsmPrinter.h:136
MCExpr.h
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Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
AMDGPUMCInstLower::AMDGPUMCInstLower
AMDGPUMCInstLower(MCContext &ctx, const TargetSubtargetInfo &ST, const AsmPrinter &AP)
Definition: AMDGPUMCInstLower.cpp:39
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
AMDGPUTargetMachine.h
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virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.