LLVM  15.0.0git
AMDGPUMCInstLower.cpp
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1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14 
15 #include "AMDGPUMCInstLower.h"
16 #include "AMDGPUAsmPrinter.h"
17 #include "AMDGPUTargetMachine.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/MC/MCCodeEmitter.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/Support/Format.h"
33 #include <algorithm>
34 
35 using namespace llvm;
36 
37 #include "AMDGPUGenMCPseudoLowering.inc"
38 
40  const TargetSubtargetInfo &st,
41  const AsmPrinter &ap):
42  Ctx(ctx), ST(st), AP(ap) { }
43 
44 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
45  switch (MOFlags) {
46  default:
47  return MCSymbolRefExpr::VK_None;
49  return MCSymbolRefExpr::VK_GOTPCREL;
50  case SIInstrInfo::MO_GOTPCREL32_LO:
51  return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO;
52  case SIInstrInfo::MO_GOTPCREL32_HI:
53  return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI;
54  case SIInstrInfo::MO_REL32_LO:
55  return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
56  case SIInstrInfo::MO_REL32_HI:
57  return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
58  case SIInstrInfo::MO_ABS32_LO:
59  return MCSymbolRefExpr::VK_AMDGPU_ABS32_LO;
60  case SIInstrInfo::MO_ABS32_HI:
61  return MCSymbolRefExpr::VK_AMDGPU_ABS32_HI;
62  }
63 }
64 
66  MCOperand &MCOp) const {
67  switch (MO.getType()) {
68  default:
69  break;
70  case MachineOperand::MO_Immediate:
71  MCOp = MCOperand::createImm(MO.getImm());
72  return true;
73  case MachineOperand::MO_Register:
74  MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
75  return true;
76  case MachineOperand::MO_MachineBasicBlock:
77  MCOp = MCOperand::createExpr(
78  MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx));
79  return true;
80  case MachineOperand::MO_GlobalAddress: {
81  const GlobalValue *GV = MO.getGlobal();
85  const MCExpr *Expr =
86  MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx);
87  int64_t Offset = MO.getOffset();
88  if (Offset != 0) {
89  Expr = MCBinaryExpr::createAdd(Expr,
90  MCConstantExpr::create(Offset, Ctx), Ctx);
91  }
92  MCOp = MCOperand::createExpr(Expr);
93  return true;
94  }
95  case MachineOperand::MO_ExternalSymbol: {
97  Sym->setExternal(true);
98  const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
99  MCOp = MCOperand::createExpr(Expr);
100  return true;
101  }
102  case MachineOperand::MO_RegisterMask:
103  // Regmasks are like implicit defs.
104  return false;
105  case MachineOperand::MO_MCSymbol:
106  if (MO.getTargetFlags() == SIInstrInfo::MO_FAR_BRANCH_OFFSET) {
107  MCSymbol *Sym = MO.getMCSymbol();
108  MCOp = MCOperand::createExpr(Sym->getVariableValue());
109  return true;
110  }
111  break;
112  }
113  llvm_unreachable("unknown operand type");
114 }
115 
116 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
117  unsigned Opcode = MI->getOpcode();
118  const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
119 
120  // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
121  // need to select it to the subtarget specific version, and there's no way to
122  // do that with a single pseudo source operation.
123  if (Opcode == AMDGPU::S_SETPC_B64_return)
124  Opcode = AMDGPU::S_SETPC_B64;
125  else if (Opcode == AMDGPU::SI_CALL) {
126  // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
127  // called function (which we need to remove here).
128  OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
129  MCOperand Dest, Src;
130  lowerOperand(MI->getOperand(0), Dest);
131  lowerOperand(MI->getOperand(1), Src);
132  OutMI.addOperand(Dest);
133  OutMI.addOperand(Src);
134  return;
135  } else if (Opcode == AMDGPU::SI_TCRETURN) {
136  // TODO: How to use branch immediate and avoid register+add?
137  Opcode = AMDGPU::S_SETPC_B64;
138  }
139 
140  int MCOpcode = TII->pseudoToMCOpcode(Opcode);
141  if (MCOpcode == -1) {
142  LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
143  C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
144  "a target-specific version: " + Twine(MI->getOpcode()));
145  }
146 
147  OutMI.setOpcode(MCOpcode);
148 
149  for (const MachineOperand &MO : MI->explicit_operands()) {
150  MCOperand MCOp;
151  lowerOperand(MO, MCOp);
152  OutMI.addOperand(MCOp);
153  }
154 
155  int FIIdx = AMDGPU::getNamedOperandIdx(MCOpcode, AMDGPU::OpName::fi);
156  if (FIIdx >= (int)OutMI.getNumOperands())
157  OutMI.addOperand(MCOperand::createImm(0));
158 }
159 
160 bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
161  MCOperand &MCOp) const {
162  const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
163  AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
164  return MCInstLowering.lowerOperand(MO, MCOp);
165 }
166 
168  if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
169  return E;
170  return AsmPrinter::lowerConstant(CV);
171 }
172 
175  return;
176 
177  const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
178  AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
179 
180  StringRef Err;
181  if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
182  LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
183  C.emitError("Illegal instruction detected: " + Err);
184  MI->print(errs());
185  }
186 
187  if (MI->isBundle()) {
188  const MachineBasicBlock *MBB = MI->getParent();
189  MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
190  while (I != MBB->instr_end() && I->isInsideBundle()) {
191  emitInstruction(&*I);
192  ++I;
193  }
194  } else {
195  // We don't want these pseudo instructions encoded. They are
196  // placeholder terminator instructions and should only be printed as
197  // comments.
198  if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
199  if (isVerbose())
200  OutStreamer->emitRawComment(" return to shader part epilog");
201  return;
202  }
203 
204  if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
205  if (isVerbose())
206  OutStreamer->emitRawComment(" wave barrier");
207  return;
208  }
209 
210  if (MI->getOpcode() == AMDGPU::SCHED_BARRIER) {
211  if (isVerbose()) {
212  std::string HexString;
213  raw_string_ostream HexStream(HexString);
214  HexStream << format_hex(MI->getOperand(0).getImm(), 10, true);
215  OutStreamer->emitRawComment(" sched_barrier mask(" + HexString + ")");
216  }
217  return;
218  }
219 
220  if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
221  if (isVerbose())
222  OutStreamer->emitRawComment(" divergent unreachable");
223  return;
224  }
225 
226  if (MI->isMetaInstruction()) {
227  if (isVerbose())
228  OutStreamer->emitRawComment(" meta instruction");
229  return;
230  }
231 
232  MCInst TmpInst;
233  MCInstLowering.lower(MI, TmpInst);
234  EmitToStreamer(*OutStreamer, TmpInst);
235 
236 #ifdef EXPENSIVE_CHECKS
237  // Check getInstSizeInBytes on explicitly specified CPUs (it cannot
238  // work correctly for the generic CPU).
239  //
240  // The isPseudo check really shouldn't be here, but unfortunately there are
241  // some negative lit tests that depend on being able to continue through
242  // here even when pseudo instructions haven't been lowered.
243  //
244  // We also overestimate branch sizes with the offset bug.
245  if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU()) &&
246  (!STI.hasOffset3fBug() || !MI->isBranch())) {
248  SmallVector<char, 16> CodeBytes;
249  raw_svector_ostream CodeStream(CodeBytes);
250 
251  std::unique_ptr<MCCodeEmitter> InstEmitter(createSIMCCodeEmitter(
252  *STI.getInstrInfo(), OutContext));
253  InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI);
254 
255  assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI));
256  }
257 #endif
258 
259  if (DumpCodeInstEmitter) {
260  // Disassemble instruction/operands to text
261  DisasmLines.resize(DisasmLines.size() + 1);
262  std::string &DisasmLine = DisasmLines.back();
263  raw_string_ostream DisasmStream(DisasmLine);
264 
265  AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *STI.getInstrInfo(),
266  *STI.getRegisterInfo());
267  InstPrinter.printInst(&TmpInst, 0, StringRef(), STI, DisasmStream);
268 
269  // Disassemble instruction/operands to hex representation.
271  SmallVector<char, 16> CodeBytes;
272  raw_svector_ostream CodeStream(CodeBytes);
273 
274  DumpCodeInstEmitter->encodeInstruction(
275  TmpInst, CodeStream, Fixups, MF->getSubtarget<MCSubtargetInfo>());
276  HexLines.resize(HexLines.size() + 1);
277  std::string &HexLine = HexLines.back();
278  raw_string_ostream HexStream(HexLine);
279 
280  for (size_t i = 0; i < CodeBytes.size(); i += 4) {
281  unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
282  HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
283  }
284 
285  DisasmStream.flush();
286  DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
287  }
288  }
289 }
i
i
Definition: README.txt:29
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:1861
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Definition: SIMCCodeEmitter.cpp:89
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Definition: IRTranslator.cpp:104
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Definition: AddressRanges.h:17
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Definition: MCSymbol.h:41
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virtual const MCExpr * lowerConstant(const Constant *CV)
Lower the specified LLVM Constant to an MCExpr.
Definition: AsmPrinter.cpp:2673
AMDGPUMCInstLower::lowerOperand
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const
Definition: AMDGPUMCInstLower.cpp:65
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const GlobalValue * getGlobal() const
Definition: MachineOperand.h:572
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Definition: MCContext.h:76
AMDGPUMCInstLower
Definition: AMDGPUMCInstLower.h:29
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virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
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Format.h
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Definition: MCInst.h:208
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Definition: GCNSubtarget.h:223
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Definition: MachineBasicBlock.cpp:57
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Implemented in AMDGPUMCInstLower.cpp.
Definition: AMDGPUMCInstLower.cpp:173
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Definition: AsmPrinter.h:96
C
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Definition: README_ALTIVEC.txt:86
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getVariableValue - Get the value for variable symbols.
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MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
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Definition: AArch64FixupKinds.h:17
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Definition: Pass.cpp:129
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Definition: GlobalValue.h:44
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Definition: Constant.h:41
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Definition: MachineOperand.h:220
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Definition: MachineInstr.h:66
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Definition: ARMBaseInfo.h:73
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Definition: LLVMContext.h:68
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Definition: AsmPrinter.h:99
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Definition: AsmPrinter.h:91
AMDGPUMCInstLower::lower
void lower(const MachineInstr *MI, MCInst &OutMI) const
Lower a MachineInstr to an MCInst.
Definition: AMDGPUMCInstLower.cpp:116
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Definition: MachineOperand.h:359
AMDGPUMCInstLower.h
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Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
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Definition: MachineBasicBlock.h:264
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Definition: TargetMachine.h:205
llvm::AMDGPUAsmPrinter::lowerConstant
const MCExpr * lowerConstant(const Constant *CV) override
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Definition: AMDGPUMCInstLower.cpp:167
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Definition: AMDGPUMCInstLower.cpp:44
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Definition: StringRef.h:58
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Definition: SIInstrInfo.cpp:3965
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Definition: ErrorHandling.h:143
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Definition: Format.h:124
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Definition: AMDGPUAsmPrinter.h:136
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Definition: TargetSubtargetInfo.h:60
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Definition: AMDGPUMetadata.h:386
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Definition: Twine.h:83
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Definition: MCSymbol.h:402
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Definition: ilist_iterator.h:57
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Definition: AsmPrinter.h:81
llvm::AMDGPUInstPrinter::printInst
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Print the specified MCInst to the specified raw_ostream.
Definition: AMDGPUInstPrinter.cpp:49
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Definition: SIInstrInfo.h:44
llvm::AMDGPUAsmPrinter::emitPseudoExpansionLowering
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TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:84
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const char * getSymbolName() const
Definition: MachineOperand.h:617
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Definition: raw_ostream.h:662
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@ MO_GOTPCREL
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Definition: M68kBaseInfo.h:108
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Definition: MCInst.h:36
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bool isVerbose() const
Return true if assembly output should contain comments.
Definition: AsmPrinter.h:254
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Definition: AMDGPUAsmPrinter.h:135
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Definition: Format.h:186
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Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
AMDGPUMCInstLower::AMDGPUMCInstLower
AMDGPUMCInstLower(MCContext &ctx, const TargetSubtargetInfo &ST, const AsmPrinter &AP)
Definition: AMDGPUMCInstLower.cpp:39
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Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
AMDGPUTargetMachine.h
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virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
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